From cdabbbd867c08f1a5b81b6d875c637007a2a46cb Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Mon, 12 Aug 2019 12:52:35 -0700 Subject: u-boot: cleanup 2019.07 stratix10 patches Signed-off-by: Dalon Westergreen --- ...cfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch | 30 -------- ...ocfpga-stratix10-Enable-PSCI-system-reset.patch | 4 +- ...ria10-Fix-error-in-fpga-pin-configuration.patch | 38 ---------- ...-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch | 4 +- ...-stratix10-Enable-PSCI-support-for-Strati.patch | 10 +-- ...-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | 4 +- ...-stratix10-Add-SOCFPGA-bridges-reset-supp.patch | 4 +- ...-stratix10-Add-Stratix10-FPGA-configurati.patch | 4 +- ...Enable-small-delay-before-returning-error.patch | 4 +- ...ga-stratix10-Enable-DMA330-DMA-controller.patch | 4 +- ...-Stratix10-Fix-el3_exception_vectors-relo.patch | 4 +- ...cfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch | 30 ++++++++ ...d-target-to-generate-hex-output-for-combi.patch | 79 -------------------- ...-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch | 52 ------------- ...d-target-to-generate-hex-output-for-combi.patch | 87 ++++++++++++++++++++++ ...-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch | 36 +++++++++ ...-stratix10-Temporarily-revert-to-2GB-DRAM.patch | 31 -------- ...-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch | 30 ++++++++ ...ria10-Fix-error-in-fpga-pin-configuration.patch | 38 ++++++++++ recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb | 12 ++- 20 files changed, 247 insertions(+), 258 deletions(-) delete mode 100644 recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch delete mode 100644 recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch create mode 100644 recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch delete mode 100644 recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch delete mode 100644 recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch create mode 100644 recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch create mode 100644 recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch delete mode 100644 recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch create mode 100644 recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch create mode 100644 recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch deleted file mode 100644 index e954ac0..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 45dd1ac82881153c73bd4243cd20f3b13955ad21 Mon Sep 17 00:00:00 2001 -From: Chee Hong Ang -Date: Sat, 11 May 2019 00:09:46 +0800 -Subject: [PATCH] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET - -Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI -function calls are not supported in u-boot running in EL3. - -Signed-off-by: Chee Hong Ang ---- - arch/arm/cpu/armv8/Kconfig | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig -index 7405c3a4a1..409ee7ada0 100644 ---- a/arch/arm/cpu/armv8/Kconfig -+++ b/arch/arm/cpu/armv8/Kconfig -@@ -108,7 +108,8 @@ config PSCI_RESET - !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ -- !ARCH_UNIPHIER && !TARGET_S32V234EVB -+ !ARCH_UNIPHIER && !TARGET_S32V234EVB && \ -+ !TARGET_SOCFPGA_STRATIX10 - help - Most armv8 systems have PSCI support enabled in EL3, either through - ARM Trusted Firmware or other firmware. --- -2.13.0 - diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch index a4b7857..0b4fec1 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch @@ -1,7 +1,7 @@ -From 97f599b2a7b34d17067b4ccf6c468cdcc6805349 Mon Sep 17 00:00:00 2001 +From 5534368e77a2bfcb366eb158c72a751c28e377a7 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Mon, 29 Apr 2019 23:35:30 -0700 -Subject: [PATCH 01/12] ARM: socfpga: stratix10: Enable PSCI system reset +Subject: [PATCH 01/14] ARM: socfpga: stratix10: Enable PSCI system reset Enable psci_system_reset support for Stratix10. This PSCI function will eventually trigger the mailbox HPS_REBOOT to SDM. diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch b/recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch deleted file mode 100644 index 2ea6e18..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 58b4cc1a3d1e4a989b65892b97af119c25d9a511 Mon Sep 17 00:00:00 2001 -From: Dalon Westergreen -Date: Tue, 16 Jul 2019 09:12:53 -0700 -Subject: [PATCH] fpga: arria10: Fix error in fpga pin configuration - -Pin configuration of the FPGA devicetree block should be done -after core configuration in the arria10 fpga driver. This fix -corrects the check of status, and ensures that the fpga pin mux -is configured on correct configuration of the core fpga image. - -Signed-off-by: Dalon Westergreen ---- - drivers/fpga/socfpga_arria10.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - -diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c -index 285280e507..5fb9d6a191 100644 ---- a/drivers/fpga/socfpga_arria10.c -+++ b/drivers/fpga/socfpga_arria10.c -@@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) - fpgamgr_program_write(rbf_data, rbf_size); - - status = fpgamgr_program_finish(); -- if (status) { -- config_pins(gd->fdt_blob, "fpga"); -- puts("FPGA: Enter user mode.\n"); -- } -+ if (status) -+ return status; -+ -+ config_pins(gd->fdt_blob, "fpga"); -+ puts("FPGA: Enter user mode.\n"); - - return status; - } --- -2.21.0 - diff --git a/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch index ebf6fe7..05d1e91 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch @@ -1,7 +1,7 @@ -From 257cff780ec1a50600a77cf361df27746801d684 Mon Sep 17 00:00:00 2001 +From 0d6fb850e5662ade636b0c7aa96de9d6ed653310 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Mon, 14 Jan 2019 01:07:50 -0800 -Subject: [PATCH 02/12] ARM: socfpga: stratix10: Enable PSCI CPU_ON +Subject: [PATCH 02/14] ARM: socfpga: stratix10: Enable PSCI CPU_ON Enable psci_cpu_on support for Stratix10. This PSCI function will pass the cpu release address for CPU1-CPU3. Then send event diff --git a/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch index ed60cc0..9b92117 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch @@ -1,7 +1,7 @@ -From 504f8bd14f703bfb2ffd5dccac7126d5fd22e0d1 Mon Sep 17 00:00:00 2001 +From d58eacb640040fc19b0939f4398829fa43e5601e Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Mon, 29 Apr 2019 23:18:38 -0700 -Subject: [PATCH 03/12] ARM: socfpga: stratix10: Enable PSCI support for +Subject: [PATCH 03/14] ARM: socfpga: stratix10: Enable PSCI support for Stratix 10 The address of PSCI text, data and stack sections start at @@ -13,10 +13,10 @@ Signed-off-by: Ang, Chee Hong 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig -index 48f02f08d4..755bab5dd2 100644 +index 1d914648e3..dc4cba67ab 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig -@@ -12,6 +12,12 @@ config SPL_SYS_MALLOC_F_LEN +@@ -18,6 +18,12 @@ config SPL_SYS_MALLOC_F_LEN config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 @@ -29,7 +29,7 @@ index 48f02f08d4..755bab5dd2 100644 config SYS_MALLOC_F_LEN default 0x2000 if TARGET_SOCFPGA_ARRIA10 default 0x2000 if TARGET_SOCFPGA_GEN5 -@@ -56,8 +62,9 @@ config TARGET_SOCFPGA_GEN5 +@@ -64,8 +70,9 @@ config TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY diff --git a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch index 7d30706..55a9805 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch @@ -1,7 +1,7 @@ -From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001 +From d6ac4f9f2756a14021f9cdc3c3305f950643d45f Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Fri, 20 Apr 2018 18:28:07 +0800 -Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from +Subject: [PATCH 04/14] ARM: socfpga: stratix10: Enable SMC/PSCI calls from slave CPUs Before this patch, only master CPU (CPU0) is able to diff --git a/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch index fd43dd2..a6c2b2a 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch @@ -1,7 +1,7 @@ -From 16460c05fe576050cf485282151fd5623d6e862a Mon Sep 17 00:00:00 2001 +From 97cae73c90b57bbcf2b422ff142a3c9de6e9ea66 Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Wed, 22 May 2019 17:05:12 -0700 -Subject: [PATCH 05/12] ARM: socfpga: stratix10: Add SOCFPGA bridges reset +Subject: [PATCH 05/14] ARM: socfpga: stratix10: Add SOCFPGA bridges reset support for PSCI call Add SOCFPGA bridges reset support for FPGA configuration SMC services diff --git a/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch index cc0be27..5f58e52 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch @@ -1,7 +1,7 @@ -From 04187fba93e6d359ebb4dd8e397dff282f53ec5a Mon Sep 17 00:00:00 2001 +From 97b805b19ed529f389bf5899fbe1d99bd13ffd59 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Mon, 29 Apr 2019 23:42:39 -0700 -Subject: [PATCH 06/12] ARM: socfpga: stratix10: Add Stratix10 FPGA +Subject: [PATCH 06/14] ARM: socfpga: stratix10: Add Stratix10 FPGA configuration PSCI services Allow PSCI layer to handle the S10 FPGA configuration (SiP) service diff --git a/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch index 8da5892..71625cd 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch @@ -1,7 +1,7 @@ -From 17366d3b46cf70a8fa4d807519790ef4b1b03772 Mon Sep 17 00:00:00 2001 +From 5dd98b8e0aec2059863ae73d5c83fa043b0a6170 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Wed, 30 Jan 2019 21:47:36 -0800 -Subject: [PATCH 07/12] mmc: dwmmc: Enable small delay before returning error +Subject: [PATCH 07/14] mmc: dwmmc: Enable small delay before returning error 'SET_BLOCKLEN' may occasionally fail on first attempt. This patch enable a small delay in dwmci_send_cmd() on diff --git a/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch index 91505b7..8e0e907 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch @@ -1,7 +1,7 @@ -From da0bd33c8c8f6a1b77ecaa4c676f8ee14997b9e9 Mon Sep 17 00:00:00 2001 +From f4e6b02369f2a7daed5799f27e29198714bda848 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Wed, 30 Jan 2019 21:29:09 -0800 -Subject: [PATCH 08/12] ARM: socfpga: stratix10: Enable DMA330 DMA controller +Subject: [PATCH 08/14] ARM: socfpga: stratix10: Enable DMA330 DMA controller Signed-off-by: Ang, Chee Hong --- diff --git a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch index 54fa812..fb060bb 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch @@ -1,7 +1,7 @@ -From 8569e08a1a4b3bd810f60083058053a39b27534e Mon Sep 17 00:00:00 2001 +From b4807003314579b069877df69eefbace4c7b6efa Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Sat, 18 May 2019 16:42:10 +0800 -Subject: [PATCH 09/12] ARM: socfpga: Stratix10: Fix el3_exception_vectors +Subject: [PATCH 09/14] ARM: socfpga: Stratix10: Fix el3_exception_vectors relocation issue New toolchain has issue relocating the 32-bit pointer to address of diff --git a/recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch b/recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch new file mode 100644 index 0000000..030c38b --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch @@ -0,0 +1,30 @@ +From 31bb5e5583e87e5bc6d7daa3647891374eec708b Mon Sep 17 00:00:00 2001 +From: Chee Hong Ang +Date: Sat, 11 May 2019 00:09:46 +0800 +Subject: [PATCH 10/14] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET + +Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI +function calls are not supported in u-boot running in EL3. + +Signed-off-by: Chee Hong Ang +--- + arch/arm/cpu/armv8/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig +index 92a2b58ed4..f3683bccb4 100644 +--- a/arch/arm/cpu/armv8/Kconfig ++++ b/arch/arm/cpu/armv8/Kconfig +@@ -110,7 +110,8 @@ config PSCI_RESET + !TARGET_LS1046AFRWY && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ + !TARGET_LX2160AQDS && \ +- !ARCH_UNIPHIER && !TARGET_S32V234EVB ++ !ARCH_UNIPHIER && !TARGET_S32V234EVB && \ ++ !TARGET_SOCFPGA_STRATIX10 + help + Most armv8 systems have PSCI support enabled in EL3, either through + ARM Trusted Firmware or other firmware. +-- +2.21.0 + diff --git a/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch deleted file mode 100644 index 113d767..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 939875d39e56d6d2c965c2b63d5d2f20dff532e0 Mon Sep 17 00:00:00 2001 -From: Dalon Westergreen -Date: Wed, 20 Mar 2019 11:21:20 -0700 -Subject: [PATCH 10/12] Makefile: Add target to generate hex output for - combined spl and dtb - -Some architectures, Stratix10, require a hex formatted spl that combines -the spl image and dtb. This adds a target to create said hex file with -and offset of SPL_TEXT_BASE. - -Signed-off-by: Dalon Westergreen ---- - Makefile | 12 +++++++----- - scripts/Makefile.spl | 8 ++++++++ - 2 files changed, 15 insertions(+), 5 deletions(-) - -diff --git a/Makefile b/Makefile -index 059978bfe6..62d85ff279 100644 ---- a/Makefile -+++ b/Makefile -@@ -1121,11 +1121,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ - $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ - $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) - --OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) -- --spl/u-boot-spl.hex: spl/u-boot-spl FORCE -- $(call if_changed,objcopy) -- - binary_size_check: u-boot-nodtb.bin FORCE - @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ - map_size=$(shell cat u-boot.map | \ -@@ -1704,6 +1699,13 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE - - spl/u-boot-spl.bin: spl/u-boot-spl - @: -+ -+spl/u-boot-spl-dtb.bin: spl/u-boot-spl -+ @: -+ -+spl/u-boot-spl-dtb.hex: spl/u-boot-spl -+ @: -+ - spl/u-boot-spl: tools prepare \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ - $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) -diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl -index 7af6b120b6..3c90e2cd72 100644 ---- a/scripts/Makefile.spl -+++ b/scripts/Makefile.spl -@@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) - ALL-y += $(obj)/$(SPL_BIN).sfp - endif - -+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex -+ - ifdef CONFIG_ARCH_SUNXI - ALL-y += $(obj)/sunxi-spl.bin - -@@ -363,6 +365,11 @@ endif - $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE - $(call if_changed,mkimage) - -+OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) -+ -+$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE -+ $(call if_changed,objcopy) -+ - quiet_cmd_mksunxiboot = MKSUNXI $@ - cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ - --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ -@@ -463,3 +470,4 @@ ifdef CONFIG_ARCH_K3 - tispl.bin: $(obj)/u-boot-spl-nodtb.bin $(SHRUNK_ARCH_DTB) $(SPL_ITS) FORCE - $(call if_changed,mkfitimage) - endif -+ --- -2.21.0 - diff --git a/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch deleted file mode 100644 index 21794d2..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 37814e55403a9ec5f852b58576618ba9a1936a20 Mon Sep 17 00:00:00 2001 -From: Dalon Westergreen -Date: Fri, 10 May 2019 10:30:44 -0700 -Subject: [PATCH 11/12] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED - -CONFIG_OF_EMBED was primarily enabled to support the stratix10 -spl hex file requirements. Since this option now produces a -warning during build, and the spl hex can be created using -alternate methods, CONFIG_OF_EMBED is no longer needed. - -Signed-off-by: Dalon Westergreen ---- - configs/socfpga_stratix10_defconfig | 1 - - include/configs/socfpga_stratix10_socdk.h | 4 ++-- - 2 files changed, 2 insertions(+), 3 deletions(-) - -diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig -index fbab388b43..f27180385d 100644 ---- a/configs/socfpga_stratix10_defconfig -+++ b/configs/socfpga_stratix10_defconfig -@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y - CONFIG_CMD_EXT4=y - CONFIG_CMD_FAT=y - CONFIG_CMD_FS_GENERIC=y --CONFIG_OF_EMBED=y - CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" - CONFIG_ENV_IS_IN_MMC=y - CONFIG_NET_RANDOM_ETHADDR=y -diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h -index 39d757d737..e93c598be9 100644 ---- a/include/configs/socfpga_stratix10_socdk.h -+++ b/include/configs/socfpga_stratix10_socdk.h -@@ -197,7 +197,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) - * - */ --#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" -+#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE - #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -@@ -210,6 +210,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); - - /* SPL SDMMC boot support */ - #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 --#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" - - #endif /* __CONFIG_H */ --- -2.21.0 - diff --git a/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch new file mode 100644 index 0000000..640df20 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch @@ -0,0 +1,87 @@ +From 56332c75a69a9f9ef7928e0f43d1fc509db9c866 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen +Date: Wed, 20 Mar 2019 11:21:20 -0700 +Subject: [PATCH 11/14] Makefile: Add target to generate hex output for + combined spl and dtb + +Stratix10 requires a hex image of the spl plus spl devicetree offset to +the Stratix10 onchip memory located at SPL_TEXT_BASE. This patch adds +a target to generate a hex file from the u-boot-spl binary including the +dtb offset at SPL_TEST_BASE. + +Objcopy is used to convert the $(SPL_BIN).bin, which includes the spl +dtb, to a hex file. the --change-address option is used to offset the +hex to SPL_TEXT_BASE as objcopy on the spl binary will not result in +a hex file appropriately offset at SPL_TEXT_BASE. + +Signed-off-by: Dalon Westergreen + +--- +Changes in v3: + -> Cleanup commit message and better describe the problem being + resolved + -> Remove extraneous hunk + -> use SPL_BIN instead of u-boot-spl +Changes in v2: + -> Move spl hex file generation to SPL Makefile + -> Create hexfile from $(SPL_BIN).bin which will include the dtb + ifneq(build_dtb,) +--- + Makefile | 8 +++----- + scripts/Makefile.spl | 7 +++++++ + 2 files changed, 10 insertions(+), 5 deletions(-) + +diff --git a/Makefile b/Makefile +index 516260f46d..8236f095fc 100644 +--- a/Makefile ++++ b/Makefile +@@ -1136,11 +1136,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ + $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ + $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) + +-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) +- +-spl/u-boot-spl.hex: spl/u-boot-spl FORCE +- $(call if_changed,objcopy) +- + binary_size_check: u-boot-nodtb.bin FORCE + @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ + map_size=$(shell cat u-boot.map | \ +@@ -1721,6 +1716,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl + @: + $(SPL_SIZE_CHECK) + ++spl/u-boot-spl.hex: spl/u-boot-spl ++ @: ++ + spl/u-boot-spl: tools prepare \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) +diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl +index 7af6b120b6..551002194e 100644 +--- a/scripts/Makefile.spl ++++ b/scripts/Makefile.spl +@@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) + ALL-y += $(obj)/$(SPL_BIN).sfp + endif + ++ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex ++ + ifdef CONFIG_ARCH_SUNXI + ALL-y += $(obj)/sunxi-spl.bin + +@@ -363,6 +365,11 @@ endif + $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE + $(call if_changed,mkimage) + ++OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) ++ ++$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE ++ $(call if_changed,objcopy) ++ + quiet_cmd_mksunxiboot = MKSUNXI $@ + cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ + --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ +-- +2.21.0 + diff --git a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch new file mode 100644 index 0000000..40e7704 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch @@ -0,0 +1,36 @@ +From 708a2590681425da62f9027f5ed1144377a001bf Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen +Date: Fri, 10 May 2019 10:30:44 -0700 +Subject: [PATCH 12/14] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED + +CONFIG_OF_EMBED was primarily enabled to support the stratix10 +spl hex file requirements. Since this option now produces a +warning during build, and the spl hex can be created using +alternate methods, CONFIG_OF_EMBED is no longer needed. + +Signed-off-by: Dalon Westergreen + +--- +Changes in v3: + -> Revert to u-boot.img for SPL payload name +Changes in v2: + -> Change CONFIG_SPL_TARGET back to u-boot-spl.hex +--- + configs/socfpga_stratix10_defconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig +index fbab388b43..f27180385d 100644 +--- a/configs/socfpga_stratix10_defconfig ++++ b/configs/socfpga_stratix10_defconfig +@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y + CONFIG_CMD_EXT4=y + CONFIG_CMD_FAT=y + CONFIG_CMD_FS_GENERIC=y +-CONFIG_OF_EMBED=y + CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" + CONFIG_ENV_IS_IN_MMC=y + CONFIG_NET_RANDOM_ETHADDR=y +-- +2.21.0 + diff --git a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch deleted file mode 100644 index c7f73ba..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 97d491bda1dea7d2afe74a7c3fb4ea43a83a79ff Mon Sep 17 00:00:00 2001 -From: Dalon Westergreen -Date: Fri, 10 May 2019 10:31:15 -0700 -Subject: [PATCH 12/12] ARM: socfpga: stratix10: Temporarily revert to 2GB DRAM - -The current shipping GHRD still has the DDR configured as a -2GB DDR. This reverts the devicetree to use 2GB instead of -4GB. - -Signed-off-by: Dalon Westergreen ---- - arch/arm/dts/socfpga_stratix10_socdk.dts | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts -index 2745050810..1caae0ab6f 100755 ---- a/arch/arm/dts/socfpga_stratix10_socdk.dts -+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts -@@ -37,8 +37,7 @@ - memory { - device_type = "memory"; - /* 4GB */ -- reg = <0 0x00000000 0 0x80000000>, -- <1 0x80000000 0 0x80000000>; -+ reg = <0 0x00000000 0 0x80000000>; - u-boot,dm-pre-reloc; - }; - }; --- -2.21.0 - diff --git a/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch b/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch new file mode 100644 index 0000000..3b34325 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch @@ -0,0 +1,30 @@ +From 441ba6f4d508bf77cc543feb00d1d3fca9a80934 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen +Date: Tue, 4 Jun 2019 13:43:59 -0700 +Subject: [PATCH 13/14] ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to + u-boot.img + +Bring cyclone5 / arria5 / arria10 in line with convention and use +u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME. + +Signed-off-by: Dalon Westergreen +--- + include/configs/socfpga_common.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h +index d1034ac280..36b0ed5459 100644 +--- a/include/configs/socfpga_common.h ++++ b/include/configs/socfpga_common.h +@@ -203,7 +203,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); + /* SPL SDMMC boot support */ + #ifdef CONFIG_SPL_MMC_SUPPORT + #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" ++#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + #endif + #else +-- +2.21.0 + diff --git a/recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch b/recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch new file mode 100644 index 0000000..0255efc --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch @@ -0,0 +1,38 @@ +From db2095305c0fb464f57b001464fb811a86f19834 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen +Date: Tue, 16 Jul 2019 09:12:53 -0700 +Subject: [PATCH 14/14] fpga: arria10: Fix error in fpga pin configuration + +Pin configuration of the FPGA devicetree block should be done +after core configuration in the arria10 fpga driver. This fix +corrects the check of status, and ensures that the fpga pin mux +is configured on correct configuration of the core fpga image. + +Signed-off-by: Dalon Westergreen +--- + drivers/fpga/socfpga_arria10.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c +index 285280e507..5fb9d6a191 100644 +--- a/drivers/fpga/socfpga_arria10.c ++++ b/drivers/fpga/socfpga_arria10.c +@@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) + fpgamgr_program_write(rbf_data, rbf_size); + + status = fpgamgr_program_finish(); +- if (status) { +- config_pins(gd->fdt_blob, "fpga"); +- puts("FPGA: Enter user mode.\n"); +- } ++ if (status) ++ return status; ++ ++ config_pins(gd->fdt_blob, "fpga"); ++ puts("FPGA: Enter user mode.\n"); + + return status; + } +-- +2.21.0 + diff --git a/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb index 0229a01..0fd1ff0 100644 --- a/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb +++ b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb @@ -4,8 +4,6 @@ require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc LICENSE = "GPLv2+" LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" -PR = "2" - FILESEXTRAPATHS =. "${THISDIR}/files/v2019.07:" SRCREV = "e5aee22e4be75e75a854ab64503fc80598bc2004" @@ -20,11 +18,11 @@ SRC_URI_append = "\ file://0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch \ file://0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch \ file://0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch \ - file://0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ - file://0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ - file://0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch \ - file://0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ - file://0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch \ + file://0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ + file://0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ + file://0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ + file://0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch \ + file://0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch \ " DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" -- cgit v1.2.3-54-g00ecf