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-rw-r--r--meta-renesas-extras/recipes/linux/linux-renesas/0001-draak-change-lvds-timings-to-match-KOE-1280x480-disp.patch327
-rw-r--r--meta-renesas-extras/recipes/linux/linux-renesas_%.bbappend5
2 files changed, 331 insertions, 1 deletions
diff --git a/meta-renesas-extras/recipes/linux/linux-renesas/0001-draak-change-lvds-timings-to-match-KOE-1280x480-disp.patch b/meta-renesas-extras/recipes/linux/linux-renesas/0001-draak-change-lvds-timings-to-match-KOE-1280x480-disp.patch
new file mode 100644
index 0000000..a3a3624
--- /dev/null
+++ b/meta-renesas-extras/recipes/linux/linux-renesas/0001-draak-change-lvds-timings-to-match-KOE-1280x480-disp.patch
@@ -0,0 +1,327 @@
1From 1115b5113bc31d048441cc138c6d2f45785bd53e Mon Sep 17 00:00:00 2001
2From: Samuli Piippo <samuli.piippo@qt.io>
3Date: Tue, 20 Nov 2018 15:43:47 +0200
4Subject: [PATCH] draak: change lvds timings to match KOE 1280x480 display
5
6Add new dtb for Draak that enables LVDS output and changes
7the panel timings to match KOE tx31d200vm0baa display.
8---
9 arch/arm64/boot/dts/renesas/Makefile | 1 +
10 .../boot/dts/renesas/r8a77995-draak-lvds.dts | 296 ++++++++++++++++++
11 2 files changed, 297 insertions(+)
12 create mode 100644 arch/arm64/boot/dts/renesas/r8a77995-draak-lvds.dts
13
14diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
15index 3daccfdfc5ea..b24e31d6a1ce 100644
16--- a/arch/arm64/boot/dts/renesas/Makefile
17+++ b/arch/arm64/boot/dts/renesas/Makefile
18@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
19 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
20 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
21 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
22+dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak-lvds.dtb
23
24 always := $(dtb-y)
25 clean-files := *.dtb
26diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak-lvds.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak-lvds.dts
27new file mode 100644
28index 000000000000..53df48a99c30
29--- /dev/null
30+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak-lvds.dts
31@@ -0,0 +1,296 @@
32+/*
33+ * Device Tree Source for the Draak board
34+ *
35+ * Copyright (C) 2017 Renesas Electronics Corp.
36+ *
37+ * This file is licensed under the terms of the GNU General Public License
38+ * version 2. This program is licensed "as is" without any warranty of any
39+ * kind, whether express or implied.
40+ */
41+
42+/dts-v1/;
43+#include "r8a77995.dtsi"
44+#include <dt-bindings/gpio/gpio.h>
45+
46+/ {
47+ model = "Renesas Draak board based on r8a77995";
48+ compatible = "renesas,draak", "renesas,r8a77995";
49+
50+ aliases {
51+ serial0 = &scif2;
52+ ethernet0 = &avb;
53+ };
54+
55+ chosen {
56+ bootargs = "ignore_loglevel";
57+ stdout-path = "serial0:115200n8";
58+ };
59+
60+ memory@48000000 {
61+ device_type = "memory";
62+ /* first 128MB is reserved for secure area. */
63+ reg = <0x0 0x48000000 0x0 0x18000000>;
64+ };
65+
66+ reserved-memory {
67+ #address-cells = <2>;
68+ #size-cells = <2>;
69+ ranges;
70+
71+ /* global autoconfigured region for contiguous allocations */
72+ linux,cma {
73+ compatible = "shared-dma-pool";
74+ reusable;
75+ reg = <0x00000000 0x58000000 0x0 0x8000000>;
76+ linux,cma-default;
77+ };
78+ };
79+
80+ reg_1p8v: regulator0 {
81+ compatible = "regulator-fixed";
82+ regulator-name = "fixed-1.8V";
83+ regulator-min-microvolt = <1800000>;
84+ regulator-max-microvolt = <1800000>;
85+ regulator-boot-on;
86+ regulator-always-on;
87+ };
88+
89+ reg_3p3v: regulator1 {
90+ compatible = "regulator-fixed";
91+ regulator-name = "fixed-3.3V";
92+ regulator-min-microvolt = <3300000>;
93+ regulator-max-microvolt = <3300000>;
94+ regulator-boot-on;
95+ regulator-always-on;
96+ };
97+
98+ lvds0 {
99+ compatible = "panel-lvds";
100+
101+ width-mm = <210>;
102+ height-mm = <158>;
103+
104+ data-mapping = "jeida-24";
105+
106+ panel-timing {
107+ /* 1280x480 @60Hz */
108+ clock-frequency = <43248000>;
109+ hactive = <1280>;
110+ vactive = <480>;
111+ hback-porch = <40>;
112+ hfront-porch = <30>;
113+ vback-porch = <30>;
114+ vfront-porch = <10>;
115+ hsync-len = <10>;
116+ vsync-len = <10>;
117+ };
118+ port {
119+ lvds0_in: endpoint {
120+ remote-endpoint = <&du_out_lvds0>;
121+ };
122+ };
123+ };
124+
125+ lvds1 {
126+ compatible = "panel-lvds";
127+
128+ width-mm = <210>;
129+ height-mm = <158>;
130+
131+ data-mapping = "jeida-24";
132+
133+ panel-timing {
134+ /* 1280x480 @60Hz */
135+ clock-frequency = <43248000>;
136+ hactive = <1280>;
137+ vactive = <480>;
138+ hback-porch = <40>;
139+ hfront-porch = <30>;
140+ vback-porch = <30>;
141+ vfront-porch = <10>;
142+ hsync-len = <10>;
143+ vsync-len = <10>;
144+ };
145+ port {
146+ lvds1_in: endpoint {
147+ remote-endpoint = <&du_out_lvds1>;
148+ };
149+ };
150+ };
151+};
152+
153+&pfc {
154+ avb_pins: avb {
155+ groups = "avb0_td", "avb0_tx_ctl", "avb0_txc",
156+ "avb0_rd", "avb0_rx_ctl", "avb0_rxc",
157+ "avb0_txcrefclk", "avb0_mdc", "avb0_mdio";
158+ function = "avb0";
159+ };
160+
161+ sdhi2_pins: sd2 {
162+ groups = "mmc_data8", "mmc_ctrl";
163+ function = "mmc";
164+ power-source = <3300>;
165+ };
166+
167+ sdhi2_pins_uhs: sd2_uhs {
168+ groups = "mmc_data8", "mmc_ctrl";
169+ function = "mmc";
170+ power-source = <1800>;
171+ };
172+
173+ usb0_pins: usb0 {
174+ groups = "usb0";
175+ function = "usb0";
176+ };
177+
178+};
179+
180+&extal_clk {
181+ clock-frequency = <48000000>;
182+};
183+
184+&du_dotclkin0 {
185+ clock-frequency = <74250000>;
186+};
187+
188+&i2c0 {
189+ status = "okay";
190+
191+ clock-frequency = <400000>;
192+
193+ adv7180: adv7180@20 {
194+ compatible = "adi,adv7180";
195+ reg = <0x20>;
196+ remote = <&vin4>;
197+
198+ port {
199+ cvbs_in: endpoint {
200+ bus-width = <8>;
201+ remote-endpoint = <&vin4ep0>;
202+ };
203+ };
204+ };
205+
206+ adv7612: adv7612@4c {
207+ compatible = "adi,adv7612";
208+ reg = <0x4c>;
209+ remote = <&vin4>;
210+
211+ #address-cells = <1>;
212+ #size-cells = <0>;
213+
214+ default-input = <0>;
215+
216+ port@0 {
217+ reg = <0>;
218+ };
219+ port@1 {
220+ reg = <1>;
221+ hdmi_in: endpoint {
222+ remote-endpoint = <&vin4ep0>;
223+ };
224+ };
225+ };
226+};
227+
228+&avb {
229+ pinctrl-0 = <&avb_pins>;
230+ pinctrl-names = "default";
231+ renesas,no-ether-link;
232+ phy-handle = <&phy0>;
233+ status = "okay";
234+ phy-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>;
235+ phy-reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
236+
237+ phy0: ethernet-phy@0 {
238+ rxc-skew-ps = <1500>;
239+ rxdv-skew-ps = <420>; /* default */
240+ rxd0-skew-ps = <420>; /* default */
241+ rxd1-skew-ps = <420>; /* default */
242+ rxd2-skew-ps = <420>; /* default */
243+ rxd3-skew-ps = <420>; /* default */
244+ txc-skew-ps = <900>; /* default */
245+ txen-skew-ps = <420>; /* default */
246+ txd0-skew-ps = <420>; /* default */
247+ txd1-skew-ps = <420>; /* default */
248+ txd2-skew-ps = <420>; /* default */
249+ txd3-skew-ps = <420>; /* default */
250+ reg = <0>;
251+ interrupt-parent = <&gpio5>;
252+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
253+ };
254+};
255+
256+&scif2 {
257+ status = "okay";
258+};
259+
260+&vin4 {
261+ status = "okay";
262+ port {
263+ #address-cells = <1>;
264+ #size-cells = <0>;
265+
266+ vin4ep0: endpoint {
267+ remote-endpoint = <&hdmi_in>;
268+ bus-width = <8>;
269+ };
270+ };
271+};
272+
273+&usb2_phy0 {
274+ pinctrl-0 = <&usb0_pins>;
275+ pinctrl-names = "default";
276+
277+ status = "okay";
278+};
279+
280+&ehci0 {
281+ status = "okay";
282+};
283+
284+&ohci0 {
285+ status = "okay";
286+};
287+
288+&sdhi2 {
289+ /* used for on-board 8bit eMMC */
290+ pinctrl-0 = <&sdhi2_pins>;
291+ pinctrl-1 = <&sdhi2_pins_uhs>;
292+ pinctrl-names = "default", "state_uhs";
293+
294+ vmmc-supply = <&reg_3p3v>;
295+ vqmmc-supply = <&reg_1p8v>;
296+ mmc-hs200-1_8v;
297+ bus-width = <8>;
298+ non-removable;
299+ status = "okay";
300+};
301+
302+&du {
303+ status = "okay";
304+
305+ /* update <du_dotclkin0/1> */
306+ clocks = <&cpg CPG_MOD 724>,
307+ <&cpg CPG_MOD 723>,
308+ <&cpg CPG_MOD 727>,
309+ <&cpg CPG_MOD 727>,
310+ <&du_dotclkin0>;
311+
312+ backlight0-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;/* LVDS0 */
313+ backlight1-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* LVDS1 */
314+
315+ ports {
316+ port@1 {
317+ endpoint {
318+ remote-endpoint = <&lvds0_in>;
319+ };
320+ };
321+ port@2 {
322+ endpoint {
323+ remote-endpoint = <&lvds1_in>;
324+ };
325+ };
326+ };
327+};
diff --git a/meta-renesas-extras/recipes/linux/linux-renesas_%.bbappend b/meta-renesas-extras/recipes/linux/linux-renesas_%.bbappend
index 1a9a9da..edabc4b 100644
--- a/meta-renesas-extras/recipes/linux/linux-renesas_%.bbappend
+++ b/meta-renesas-extras/recipes/linux/linux-renesas_%.bbappend
@@ -29,4 +29,7 @@
29 29
30FILESEXTRAPATHS_prepend_draak := "${THISDIR}/${PN}:" 30FILESEXTRAPATHS_prepend_draak := "${THISDIR}/${PN}:"
31 31
32SRC_URI_append_draak = " file://0001-give-up-on-gcc-ilog2-constant-optimizations.patch" 32SRC_URI_append_draak = " \
33 file://0001-give-up-on-gcc-ilog2-constant-optimizations.patch \
34 file://0001-draak-change-lvds-timings-to-match-KOE-1280x480-disp.patch \
35 "
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-05-13 02:05:19 +0000