From 000581d0ecd3aa3c956640a0e28d845999430f07 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Mon, 5 May 2025 10:23:22 -0700 Subject: fluentbit: Enable vectorizer on riscv64 Signed-off-by: Khem Raj --- conf/nonclangable.conf | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/conf/nonclangable.conf b/conf/nonclangable.conf index 0bf23a7..ddd94a4 100644 --- a/conf/nonclangable.conf +++ b/conf/nonclangable.conf @@ -563,6 +563,10 @@ CFLAGS:append:pn-dav1d:riscv64:toolchain-clang = " -no-integrated-as" TOOLCHAIN_OPTIONS:append:pn-python3-numpy:riscv64:toolchain-clang = " -march=rv64gcv" TOOLCHAIN_OPTIONS:append:pn-python3-numpy:riscv32:toolchain-clang = " -march=rv32gcv" +# git/lib/simdutf-amalgamation-5.5.0/src/simdutf/simdutf.cpp:4941:57: error: RISC-V type 'vuint16m1_t' (aka '__rvv_uint16m1_t') requires the 'zve32x' extension +# return __riscv_vmacc_vx_u16m1(__riscv_vsrl_vx_u16m1(v, 8, vl), 0x100, v, vl); +TOOLCHAIN_OPTIONS:append:pn-fluentbit:riscv64:toolchain-clang = " -march=rv64gcv" + # test_connectx segfaults with this option set to -fstack-protector-strong SECURITY_STACK_PROTECTOR:pn-lksctp-tools:toolchain-clang = "" -- cgit v1.2.3-54-g00ecf