diff -uNr a/events/Makefile.am b/events/Makefile.am --- a/events/Makefile.am 2012-08-27 20:59:13.000000000 +0200 +++ b/events/Makefile.am 2013-02-07 07:06:04.168567619 +0100 @@ -72,6 +72,7 @@ ppc/7450/events ppc/7450/unit_masks \ ppc/e500/events ppc/e500/unit_masks \ ppc/e500v2/events ppc/e500v2/unit_masks \ + ppc/e500mc/events ppc/e500mc/unit_masks \ ppc/e300/events ppc/e300/unit_masks \ tile/tile64/events tile/tile64/unit_masks \ tile/tilepro/events tile/tilepro/unit_masks \ diff -uNr a/events/ppc/e500mc/events b/events/ppc/e500mc/events --- a/events/ppc/e500mc/events 1970-01-01 01:00:00.000000000 +0100 +++ b/events/ppc/e500mc/events 2013-02-07 07:03:57.990063725 +0100 @@ -0,0 +1,83 @@ +# e500 Events +# +event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles +event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle) +event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update) +event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches +event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded +event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed +event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed +event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed +event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects +event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished +event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished +event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished +event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction +event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction +event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken +event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded +event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued +event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued +event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled +event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled +event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled +event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled +event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events +event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated. +event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.) +event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.) +event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.) +event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi) +event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated +event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated +event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated +event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated. +event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB +event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.) +event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.) +event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.) +event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.) +event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.) +event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason. +event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF. +event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full. +event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full. +event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer. +event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full. +event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision. +event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss. +event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy. +event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache. +event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full. +event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full. +event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer. +event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full. +event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision. +event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss. +event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy. +event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache. +event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.) +event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch. +event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch) +event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads +event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads +event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads +event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads +event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt +event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.) +event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.) +event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.) +event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.) +event:0x47 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_RETRIES : Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.) +event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.) +event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared) +event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.) +event:0x4b counters:0,1,2,3 um:zero minimum:500 name:SNOOP_RETRIES : Number of snoop requests retried. (Counts snoop ARTRYs.) +event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0. +event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0. +event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0. +event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0. +event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken +event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken +event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken +event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts diff -uNr a/events/ppc/e500mc/unit_masks b/events/ppc/e500mc/unit_masks --- a/events/ppc/e500mc/unit_masks 1970-01-01 01:00:00.000000000 +0100 +++ b/events/ppc/e500mc/unit_masks 2013-02-07 07:03:57.994063551 +0100 @@ -0,0 +1,4 @@ +# e500 possible unit masks +# +name:zero type:mandatory default:0x0 + 0x0 No unit mask diff -uNr a/libop/op_cpu_type.c b/libop/op_cpu_type.c --- a/libop/op_cpu_type.c 2012-08-27 20:59:14.000000000 +0200 +++ b/libop/op_cpu_type.c 2013-02-07 07:03:57.994063551 +0100 @@ -66,6 +66,7 @@ { "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2 }, { "e500", "ppc/e500", CPU_PPC_E500, 4 }, { "e500v2", "ppc/e500v2", CPU_PPC_E500_2, 4 }, + { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 }, { "Core Solo / Duo", "i386/core", CPU_CORE, 2 }, { "PowerPC G4", "ppc/7450", CPU_PPC_7450, 6 }, { "Core 2", "i386/core_2", CPU_CORE_2, 2 }, diff -uNr a/libop/op_cpu_type.c.orig b/libop/op_cpu_type.c.orig --- a/libop/op_cpu_type.c.orig 1970-01-01 01:00:00.000000000 +0100 +++ b/libop/op_cpu_type.c.orig 2013-02-07 07:01:39.408100801 +0100 @@ -0,0 +1,621 @@ +/** + * @file op_cpu_type.c + * CPU type determination + * + * @remark Copyright 2002 OProfile authors + * @remark Read the file COPYING + * + * @author John Levon + * @author Philippe Elie + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "op_cpu_type.h" +#include "op_hw_specific.h" + +struct cpu_descr { + char const * pretty; + char const * name; + op_cpu cpu; + unsigned int nr_counters; +}; + +static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { + { "Pentium Pro", "i386/ppro", CPU_PPRO, 2 }, + { "PII", "i386/pii", CPU_PII, 2 }, + { "PIII", "i386/piii", CPU_PIII, 2 }, + { "Athlon", "i386/athlon", CPU_ATHLON, 4 }, + { "CPU with timer interrupt", "timer", CPU_TIMER_INT, 1 }, + { "CPU with RTC device", "rtc", CPU_RTC, 1 }, + { "P4 / Xeon", "i386/p4", CPU_P4, 8 }, + { "IA64", "ia64/ia64", CPU_IA64, 4 }, + { "Itanium", "ia64/itanium", CPU_IA64_1, 4 }, + { "Itanium 2", "ia64/itanium2", CPU_IA64_2, 4 }, + { "AMD64 processors", "x86-64/hammer", CPU_HAMMER, 4 }, + { "P4 / Xeon with 2 hyper-threads", "i386/p4-ht", CPU_P4_HT2, 4 }, + { "Alpha EV4", "alpha/ev4", CPU_AXP_EV4, 2 }, + { "Alpha EV5", "alpha/ev5", CPU_AXP_EV5, 3 }, + { "Alpha PCA56", "alpha/pca56", CPU_AXP_PCA56, 3 }, + { "Alpha EV6", "alpha/ev6", CPU_AXP_EV6, 2 }, + { "Alpha EV67", "alpha/ev67", CPU_AXP_EV67, 20 }, + { "Pentium M (P6 core)", "i386/p6_mobile", CPU_P6_MOBILE, 2 }, + { "ARM/XScale PMU1", "arm/xscale1", CPU_ARM_XSCALE1, 3 }, + { "ARM/XScale PMU2", "arm/xscale2", CPU_ARM_XSCALE2, 5 }, + { "ppc64 POWER4", "ppc64/power4", CPU_PPC64_POWER4, 8 }, + { "ppc64 POWER5", "ppc64/power5", CPU_PPC64_POWER5, 6 }, + { "ppc64 POWER5+", "ppc64/power5+", CPU_PPC64_POWER5p, 6 }, + { "ppc64 970", "ppc64/970", CPU_PPC64_970, 8 }, + { "MIPS 20K", "mips/20K", CPU_MIPS_20K, 1}, + { "MIPS 24K", "mips/24K", CPU_MIPS_24K, 2}, + { "MIPS 25K", "mips/25K", CPU_MIPS_25K, 2}, + { "MIPS 34K", "mips/34K", CPU_MIPS_34K, 2}, + { "MIPS 5K", "mips/5K", CPU_MIPS_5K, 2}, + { "MIPS R10000", "mips/r10000", CPU_MIPS_R10000, 2 }, + { "MIPS R12000", "mips/r12000", CPU_MIPS_R12000, 4 }, + { "QED RM7000", "mips/rm7000", CPU_MIPS_RM7000, 1 }, + { "PMC-Sierra RM9000", "mips/rm9000", CPU_MIPS_RM9000, 2 }, + { "Sibyte SB1", "mips/sb1", CPU_MIPS_SB1, 4 }, + { "NEC VR5432", "mips/vr5432", CPU_MIPS_VR5432, 2 }, + { "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2 }, + { "e500", "ppc/e500", CPU_PPC_E500, 4 }, + { "e500v2", "ppc/e500v2", CPU_PPC_E500_2, 4 }, + { "Core Solo / Duo", "i386/core", CPU_CORE, 2 }, + { "PowerPC G4", "ppc/7450", CPU_PPC_7450, 6 }, + { "Core 2", "i386/core_2", CPU_CORE_2, 2 }, + { "ppc64 POWER6", "ppc64/power6", CPU_PPC64_POWER6, 4 }, + { "ppc64 970MP", "ppc64/970MP", CPU_PPC64_970MP, 8 }, + { "ppc64 Cell Broadband Engine", "ppc64/cell-be", CPU_PPC64_CELL, 8 }, + { "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 }, + { "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 }, + { "ARM 11MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 }, + { "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 }, + { "ppc64 POWER5++", "ppc64/power5++", CPU_PPC64_POWER5pp, 6 }, + { "e300", "ppc/e300", CPU_PPC_E300, 4 }, + { "AVR32", "avr32", CPU_AVR32, 3 }, + { "ARM Cortex-A8", "arm/armv7", CPU_ARM_V7, 5 }, + { "Intel Architectural Perfmon", "i386/arch_perfmon", CPU_ARCH_PERFMON, 0}, + { "AMD64 family11h", "x86-64/family11h", CPU_FAMILY11H, 4 }, + { "ppc64 POWER7", "ppc64/power7", CPU_PPC64_POWER7, 6 }, + { "ppc64 compat version 1", "ppc64/ibm-compat-v1", CPU_PPC64_IBM_COMPAT_V1, 4 }, + { "Intel Core/i7", "i386/core_i7", CPU_CORE_I7, 4 }, + { "Intel Atom", "i386/atom", CPU_ATOM, 2 }, + { "Loongson2", "mips/loongson2", CPU_MIPS_LOONGSON2, 2 }, + { "Intel Nehalem microarchitecture", "i386/nehalem", CPU_NEHALEM, 4 }, + { "ARM Cortex-A9", "arm/armv7-ca9", CPU_ARM_V7_CA9, 7 }, + { "MIPS 74K", "mips/74K", CPU_MIPS_74K, 4}, + { "MIPS 1004K", "mips/1004K", CPU_MIPS_1004K, 2}, + { "AMD64 family12h", "x86-64/family12h", CPU_FAMILY12H, 4 }, + { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 }, + { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 }, + { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 }, + { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 }, + { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 }, + { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 }, + { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 }, + { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 }, + { "TILE-GX", "tile/tilegx", CPU_TILE_TILEGX, 4 }, + { "IBM System z10", "s390/z10", CPU_S390_Z10, 1 }, + { "IBM zEnterprise z196", "s390/z196", CPU_S390_Z196, 1 }, + { "Intel Ivy Bridge microarchitecture", "i386/ivybridge", CPU_IVYBRIDGE, 8 }, + { "ARM Cortex-A5", "arm/armv7-ca5", CPU_ARM_V7_CA5, 3 }, + { "ARM Cortex-A7", "arm/armv7-ca7", CPU_ARM_V7_CA7, 5 }, + { "ARM Cortex-A15", "arm/armv7-ca15", CPU_ARM_V7_CA15, 7 }, +}; + +static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); + +static char * _get_cpuinfo_cpu_type_line(char * buf, int len, const char * prefix, int token) +{ + char * ret = NULL; + char * end = NULL; + int prefix_len = strlen(prefix); + FILE * fp = fopen("/proc/cpuinfo", "r"); + + if (!fp) { + perror("Unable to open /proc/cpuinfo\n"); + return ret; + } + + memset(buf, 0, len); + + while (!ret) { + if (fgets(buf, len, fp) == NULL) { + fprintf(stderr, "Did not find processor type in /proc/cpuinfo.\n"); + break; + } + if (!strncmp(buf, prefix, prefix_len)) { + ret = buf + prefix_len; + /* Strip leading whitespace and ':' delimiter */ + while (*ret && (*ret == ':' || isspace(*ret))) + ++ret; + buf = ret; + /* if token param 0 then read the whole line else + * first token only. */ + if (token == 0) { + /* Trim trailing whitespace */ + end = buf + strlen(buf) - 1; + while (isspace(*end)) + --end; + *(++end) = '\0'; + break; + } else { + /* Scan ahead to the end of the token */ + while (*buf && !isspace(*buf)) + ++buf; + /* Trim trailing whitespace */ + *buf = '\0'; + break; + } + } + } + + fclose(fp); + return ret; +} + +static char * _get_cpuinfo_cpu_type(char * buf, int len, const char * prefix) +{ + return _get_cpuinfo_cpu_type_line(buf, len, prefix, 1); +} + +static op_cpu _get_ppc64_cpu_type(void) +{ + int i; + size_t len; + char line[100], cpu_type_str[64], cpu_name_lowercase[64], * cpu_name; + + cpu_name = _get_cpuinfo_cpu_type(line, 100, "cpu"); + if (!cpu_name) + return CPU_NO_GOOD; + + len = strlen(cpu_name); + for (i = 0; i < (int)len ; i++) + cpu_name_lowercase[i] = tolower(cpu_name[i]); + + cpu_type_str[0] = '\0'; + strcat(cpu_type_str, "ppc64/"); + strncat(cpu_type_str, cpu_name_lowercase, len); + return op_get_cpu_number(cpu_type_str); +} + +static op_cpu _get_arm_cpu_type(void) +{ + unsigned long cpuid, vendorid; + char line[100]; + char * cpu_part, * cpu_implementer; + + cpu_implementer = _get_cpuinfo_cpu_type(line, 100, "CPU implementer"); + if (!cpu_implementer) + return CPU_NO_GOOD; + + errno = 0; + vendorid = strtoul(cpu_implementer, NULL, 16); + if (errno) { + fprintf(stderr, "Unable to parse CPU implementer %s\n", cpu_implementer); + return CPU_NO_GOOD; + } + + cpu_part = _get_cpuinfo_cpu_type(line, 100, "CPU part"); + if (!cpu_part) + return CPU_NO_GOOD; + + errno = 0; + cpuid = strtoul(cpu_part, NULL, 16); + if (errno) { + fprintf(stderr, "Unable to parse CPU part %s\n", cpu_part); + return CPU_NO_GOOD; + } + + if (vendorid == 0x41) { /* ARM Ltd. */ + switch (cpuid) { + case 0xb36: + case 0xb56: + case 0xb76: + return op_get_cpu_number("arm/armv6"); + case 0xb02: + return op_get_cpu_number("arm/mpcore"); + case 0xc05: + return op_get_cpu_number("arm/armv7-ca5"); + case 0xc07: + return op_get_cpu_number("arm/armv7-ca7"); + case 0xc08: + return op_get_cpu_number("arm/armv7"); + case 0xc09: + return op_get_cpu_number("arm/armv7-ca9"); + case 0xc0f: + return op_get_cpu_number("arm/armv7-ca15"); + } + } else if (vendorid == 0x69) { /* Intel xscale */ + switch (cpuid >> 9) { + case 1: + return op_get_cpu_number("arm/xscale1"); + case 2: + return op_get_cpu_number("arm/xscale2"); + } + } + + return CPU_NO_GOOD; +} + +static op_cpu _get_tile_cpu_type(void) +{ + int i; + size_t len; + char line[100], cpu_type_str[64], cpu_name_lowercase[64], * cpu_name; + + cpu_name = _get_cpuinfo_cpu_type(line, 100, "model name"); + if (!cpu_name) + return CPU_NO_GOOD; + + len = strlen(cpu_name); + for (i = 0; i < (int)len ; i++) + cpu_name_lowercase[i] = tolower(cpu_name[i]); + + cpu_type_str[0] = '\0'; + strcat(cpu_type_str, "tile/"); + strncat(cpu_type_str, cpu_name_lowercase, len); + return op_get_cpu_number(cpu_type_str); +} + +#if defined(__x86_64__) || defined(__i386__) +int op_is_cpu_vendor(char * vendor) +{ + return cpuid_vendor(vendor); +} + +static unsigned cpuid_eax(unsigned func) +{ + cpuid_data d; + + cpuid(func, &d); + return d.eax; +} + +static inline int perfmon_available(void) +{ + unsigned eax; + if (cpuid_eax(0) < 10) + return 0; + eax = cpuid_eax(10); + if ((eax & 0xff) == 0) + return 0; + return (eax >> 8) & 0xff; +} + +static int cpu_info_number(char *name, unsigned long *number) +{ + char buf[100]; + char *end; + + if (!_get_cpuinfo_cpu_type(buf, sizeof buf, name)) + return 0; + *number = strtoul(buf, &end, 0); + return end > buf; +} + +static op_cpu _get_intel_cpu_type(void) +{ + unsigned eax, family, model; + + if (perfmon_available()) + return op_cpu_specific_type(CPU_ARCH_PERFMON); + + /* Handle old non arch perfmon CPUs */ + eax = cpuid_signature(); + family = cpu_family(eax); + model = cpu_model(eax); + + if (family == 6) { + /* Reproduce kernel p6_init logic. Only for non arch perfmon cpus */ + switch (model) { + case 0 ... 2: + return op_get_cpu_number("i386/ppro"); + case 3 ... 5: + return op_get_cpu_number("i386/pii"); + case 6 ... 8: + case 10 ... 11: + return op_get_cpu_number("i386/piii"); + case 9: + case 13: + return op_get_cpu_number("i386/p6_mobile"); + } + } else if (family == 15) { + unsigned long siblings; + + /* Reproduce kernel p4_init() logic */ + if (model > 6 || model == 5) + return CPU_NO_GOOD; + if (!cpu_info_number("siblings", &siblings) || + siblings == 1) + return op_get_cpu_number("i386/p4"); + if (siblings == 2) + return op_get_cpu_number("i386/p4-ht"); + } + return CPU_NO_GOOD; +} + +static op_cpu _get_amd_cpu_type(void) +{ + unsigned eax, family, model; + op_cpu ret = CPU_NO_GOOD; + + eax = cpuid_signature(); + family = cpu_family(eax); + model = cpu_model(eax); + + switch (family) { + case 0x0f: + ret = op_get_cpu_number("x86-64/hammer"); + break; + case 0x10: + ret = op_get_cpu_number("x86-64/family10"); + break; + case 0x11: + ret = op_get_cpu_number("x86-64/family11h"); + break; + case 0x12: + ret = op_get_cpu_number("x86-64/family12h"); + break; + case 0x14: + ret = op_get_cpu_number("x86-64/family14h"); + break; + case 0x15: + switch (model) { + case 0x00 ... 0x0f: + ret = op_get_cpu_number("x86-64/family15h"); + break; + default: + break; + } + break; + default: + break; + } + + return ret; +} + +static op_cpu _get_x86_64_cpu_type(void) +{ + op_cpu ret = CPU_NO_GOOD; + + if (cpuid_vendor("GenuineIntel")) { + ret = _get_intel_cpu_type(); + } else if (cpuid_vendor("AuthenticAMD")) { + ret = _get_amd_cpu_type(); + } + + return ret; +} + +#else +static op_cpu _get_x86_64_cpu_type(void) +{ + return CPU_NO_GOOD; +} +#endif + +struct mips_cpu_descr +{ + const char * key; + const char * value; +}; + +static struct mips_cpu_descr mips_cpu_descrs[] = { + { .key = "MIPS 5Kc", .value = "mips/5K" }, /* CPU_5KC */ + { .key = "MIPS 20Kc", .value = "mips/20K" }, /* CPU_20KC */ + { .key = "MIPS 24Kc", .value = "mips/24K" }, /* CPU_24K */ + { .key = "MIPS 25Kc", .value = "mips/25K" }, /* CPU_25KF */ + { .key = "MIPS 34Kc", .value = "mips/34K" }, /* CPU_34K */ + { .key = "MIPS 74Kc", .value = "mips/74K" }, /* CPU_74K */ + { .key = "MIPS M14Kc", .value = "mips/M14Kc" }, /* CPU_M14KC */ + { .key = "RM9000", .value = "mips/rm9000" }, /* CPU_RM9000 */ + { .key = "R10000", .value = "mips/r10000" }, /* CPU_R10000 */ + { .key = "R12000", .value = "mips/r12000" }, /* CPU_R12000 */ + { .key = "R14000", .value = "mips/r12000" }, /* CPU_R14000 */ + { .key = "ICT Loongson-2", .value = "mips/loongson2" }, /* CPU_LOONGSON2 */ + { .key = NULL, .value = NULL } +}; + +static const char * _get_mips_op_name(const char * key) +{ + struct mips_cpu_descr * p_it = mips_cpu_descrs; + size_t len; + + + while (p_it->key != NULL) { + len = strlen(p_it->key); + if (0 == strncmp(key, p_it->key, len)) + return p_it->value; + ++p_it; + } + return NULL; +} + +static op_cpu _get_mips_cpu_type(void) +{ + char line[100]; + char * cpu_model; + const char * op_name = NULL; + + cpu_model = _get_cpuinfo_cpu_type_line(line, 100, "cpu model", 0); + if (!cpu_model) + return CPU_NO_GOOD; + + op_name = _get_mips_op_name(cpu_model); + + if (op_name) + return op_get_cpu_number(op_name); + return CPU_NO_GOOD; +} + +static op_cpu __get_cpu_type_alt_method(void) +{ + struct utsname uname_info; + if (uname(&uname_info) < 0) { + perror("uname failed"); + return CPU_NO_GOOD; + } + if (strncmp(uname_info.machine, "x86_64", 6) == 0 || + fnmatch("i?86", uname_info.machine, 0) == 0) { + return _get_x86_64_cpu_type(); + } + if (strncmp(uname_info.machine, "ppc64", 5) == 0) { + return _get_ppc64_cpu_type(); + } + if (strncmp(uname_info.machine, "arm", 3) == 0) { + return _get_arm_cpu_type(); + } + if (strncmp(uname_info.machine, "tile", 4) == 0) { + return _get_tile_cpu_type(); + } + if (strncmp(uname_info.machine, "mips", 4) == 0) { + return _get_mips_cpu_type(); + } + return CPU_NO_GOOD; +} + +int op_cpu_variations(op_cpu cpu_type) +{ + switch (cpu_type) { + case CPU_ARCH_PERFMON: + return 1; + default: + return 0; + } +} + + +op_cpu op_cpu_base_type(op_cpu cpu_type) +{ + /* All the processors that support CPU_ARCH_PERFMON */ + switch (cpu_type) { + case CPU_CORE_2: + case CPU_CORE_I7: + case CPU_ATOM: + case CPU_NEHALEM: + case CPU_WESTMERE: + case CPU_SANDYBRIDGE: + case CPU_IVYBRIDGE: + return CPU_ARCH_PERFMON; + default: + /* assume processor in a class by itself */ + return cpu_type; + } +} + +op_cpu op_get_cpu_type(void) +{ + int cpu_type = CPU_NO_GOOD; + char str[100]; + FILE * fp; + + fp = fopen("/proc/sys/dev/oprofile/cpu_type", "r"); + if (!fp) { + /* Try 2.6's oprofilefs one instead. */ + fp = fopen("/dev/oprofile/cpu_type", "r"); + if (!fp) { + if ((cpu_type = __get_cpu_type_alt_method()) == CPU_NO_GOOD) { + fprintf(stderr, "Unable to open cpu_type file for reading\n"); + fprintf(stderr, "Make sure you have done opcontrol --init\n"); + } + return cpu_type; + } + } + + if (!fgets(str, 99, fp)) { + fprintf(stderr, "Could not read cpu type.\n"); + fclose(fp); + return cpu_type; + } + + cpu_type = op_get_cpu_number(str); + + if (op_cpu_variations(cpu_type)) + cpu_type = op_cpu_specific_type(cpu_type); + + fclose(fp); + + return cpu_type; +} + + +op_cpu op_get_cpu_number(char const * cpu_string) +{ + int cpu_type = CPU_NO_GOOD; + size_t i; + + for (i = 0; i < nr_cpu_descrs; ++i) { + if (!strcmp(cpu_descrs[i].name, cpu_string)) { + cpu_type = cpu_descrs[i].cpu; + break; + } + } + + /* Attempt to convert into a number */ + if (cpu_type == CPU_NO_GOOD) + sscanf(cpu_string, "%d\n", &cpu_type); + + if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE) + cpu_type = CPU_NO_GOOD; + + return cpu_type; +} + + +char const * op_get_cpu_type_str(op_cpu cpu_type) +{ + if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE) + return "invalid cpu type"; + + return cpu_descrs[cpu_type].pretty; +} + + +char const * op_get_cpu_name(op_cpu cpu_type) +{ + if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE) + return "invalid cpu type"; + + return cpu_descrs[cpu_type].name; +} + + +int op_get_nr_counters(op_cpu cpu_type) +{ + int cnt; + + if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE) + return 0; + + cnt = arch_num_counters(cpu_type); + if (cnt >= 0) + return cnt; + + return op_cpu_has_timer_fs() + ? cpu_descrs[cpu_type].nr_counters + 1 + : cpu_descrs[cpu_type].nr_counters; +} + +int op_cpu_has_timer_fs(void) +{ + static int cached_has_timer_fs_p = -1; + FILE * fp; + + if (cached_has_timer_fs_p != -1) + return cached_has_timer_fs_p; + + fp = fopen("/dev/oprofile/timer", "r"); + cached_has_timer_fs_p = !!fp; + if (fp) + fclose(fp); + + return cached_has_timer_fs_p; +} diff -uNr a/libop/op_cpu_type.h b/libop/op_cpu_type.h --- a/libop/op_cpu_type.h 2012-08-27 20:59:14.000000000 +0200 +++ b/libop/op_cpu_type.h 2013-02-07 07:03:57.994063551 +0100 @@ -59,6 +59,7 @@ CPU_MIPS_VR5500, /**< MIPS VR5500, VR5532 and VR7701 */ CPU_PPC_E500, /**< e500 */ CPU_PPC_E500_2, /**< e500v2 */ + CPU_PPC_E500MC, /**< e500mc */ CPU_CORE, /**< Core Solo / Duo series */ CPU_PPC_7450, /**< PowerPC G4 */ CPU_CORE_2, /**< Intel Core 2 */ diff -uNr a/libop/op_events.c b/libop/op_events.c --- a/libop/op_events.c 2012-08-27 20:59:14.000000000 +0200 +++ b/libop/op_events.c 2013-02-07 07:03:57.994063551 +0100 @@ -1182,6 +1182,7 @@ case CPU_PPC_E500: case CPU_PPC_E500_2: + case CPU_PPC_E500MC: case CPU_PPC_E300: descr->name = "CPU_CLK"; break; diff -uNr a/libop/op_events.c.orig b/libop/op_events.c.orig --- a/libop/op_events.c.orig 1970-01-01 01:00:00.000000000 +0100 +++ b/libop/op_events.c.orig 2013-02-07 07:01:39.408100801 +0100 @@ -0,0 +1,1327 @@ +/** + * @file op_events.c + * Details of PMC profiling events + * + * You can have silliness here. + * + * @remark Copyright 2002 OProfile authors + * @remark Read the file COPYING + * + * @author John Levon + * @author Philippe Elie + */ + +#include "op_events.h" +#include "op_libiberty.h" +#include "op_fileio.h" +#include "op_string.h" +#include "op_cpufreq.h" +#include "op_hw_specific.h" +#include "op_parse_event.h" + +#include +#include +#include +#include + +static LIST_HEAD(events_list); +static LIST_HEAD(um_list); + +static char const * filename; +static unsigned int line_nr; + +static void delete_event(struct op_event * event); +static void read_events(char const * file); +static void read_unit_masks(char const * file); +static void free_unit_mask(struct op_unit_mask * um); + +static char *build_fn(const char *cpu_name, const char *fn) +{ + char *s; + static const char *dir; + if (dir == NULL) + dir = getenv("OPROFILE_EVENTS_DIR"); + if (dir == NULL) + dir = OP_DATADIR; + s = xmalloc(strlen(dir) + strlen(cpu_name) + strlen(fn) + 5); + sprintf(s, "%s/%s/%s", dir, cpu_name, fn); + return s; +} + +static void parse_error(char const * context) +{ + fprintf(stderr, "oprofile: parse error in %s, line %u\n", + filename, line_nr); + fprintf(stderr, "%s\n", context); + exit(EXIT_FAILURE); +} + + +static int parse_int(char const * str) +{ + int value; + if (sscanf(str, "%d", &value) != 1) + parse_error("expected decimal value"); + + return value; +} + + +static int parse_hex(char const * str) +{ + int value; + /* 0x/0X to force the use of hexa notation for field intended to + be in hexadecimal */ + if (sscanf(str, "0x%x", &value) != 1 && + sscanf(str, "0X%x", &value) != 1) + parse_error("expected hexadecimal value"); + + return value; +} + + +static u64 parse_long_hex(char const * str) +{ + u64 value; + if (sscanf(str, "%Lx", &value) != 1) + parse_error("expected long hexadecimal value"); + + fflush(stderr); + return value; +} + +static void include_um(const char *start, const char *end) +{ + char *s; + char cpu[end - start + 1]; + int old_line_nr; + const char *old_filename; + + strncpy(cpu, start, end - start); + cpu[end - start] = 0; + s = build_fn(cpu, "unit_masks"); + old_line_nr = line_nr; + old_filename = filename; + read_unit_masks(s); + line_nr = old_line_nr; + filename = old_filename; + free(s); +} + +/* extra:cmask=12,inv,edge */ +unsigned parse_extra(const char *s) +{ + unsigned v, w; + int o; + + v = 0; + while (*s) { + if (isspace(*s)) + break; + if (strisprefix(s, "edge")) { + v |= EXTRA_EDGE; + s += 4; + } else if (strisprefix(s, "inv")) { + v |= EXTRA_INV; + s += 3; + } else if (sscanf(s, "cmask=%x%n", &w, &o) >= 1) { + v |= (w & EXTRA_CMASK_MASK) << EXTRA_CMASK_SHIFT; + s += o; + } else if (strisprefix(s, "any")) { + v |= EXTRA_ANY; + s += 3; + } else { + parse_error("Illegal extra field modifier"); + } + if (*s == ',') + ++s; + } + return v; +} + +/* name:MESI type:bitmask default:0x0f */ +static void parse_um(struct op_unit_mask * um, char const * line) +{ + int seen_name = 0; + int seen_type = 0; + int seen_default = 0; + char const * valueend = line + 1; + char const * tagend = line + 1; + char const * start = line; + + while (*valueend) { + valueend = skip_nonws(valueend); + + while (*tagend != ':' && *tagend) + ++tagend; + + if (valueend == tagend) + break; + + if (!*tagend) + parse_error("parse_um() expected :value"); + + ++tagend; + + if (strisprefix(start, "include")) { + if (seen_name + seen_type + seen_default > 0) + parse_error("include must be on its own"); + free_unit_mask(um); + include_um(tagend, valueend); + return; + } + + if (strisprefix(start, "name")) { + if (seen_name) + parse_error("duplicate name: tag"); + seen_name = 1; + um->name = op_xstrndup(tagend, valueend - tagend); + } else if (strisprefix(start, "type")) { + if (seen_type) + parse_error("duplicate type: tag"); + seen_type = 1; + if (strisprefix(tagend, "mandatory")) { + um->unit_type_mask = utm_mandatory; + } else if (strisprefix(tagend, "bitmask")) { + um->unit_type_mask = utm_bitmask; + } else if (strisprefix(tagend, "exclusive")) { + um->unit_type_mask = utm_exclusive; + } else { + parse_error("invalid unit mask type"); + } + } else if (strisprefix(start, "default")) { + if (seen_default) + parse_error("duplicate default: tag"); + seen_default = 1; + um->default_mask = parse_hex(tagend); + } else { + parse_error("invalid unit mask tag"); + } + + valueend = skip_ws(valueend); + tagend = valueend; + start = valueend; + } + + if (!um->name) + parse_error("Missing name for unit mask"); + if (!seen_type) + parse_error("Missing type for unit mask"); +} + + +/* \t0x08 (M)odified cache state */ +/* \t0x08 extra:inv,cmask=... (M)odified cache state */ +static void parse_um_entry(struct op_described_um * entry, char const * line) +{ + char const * c = line; + + c = skip_ws(c); + entry->value = parse_hex(c); + c = skip_nonws(c); + + c = skip_ws(c); + if (strisprefix(c, "extra:")) { + c += 6; + entry->extra = parse_extra(c); + c = skip_nonws(c); + } else + entry->extra = 0; + + if (!*c) + parse_error("invalid unit mask entry"); + + c = skip_ws(c); + + if (!*c) + parse_error("invalid unit mask entry"); + + entry->desc = xstrdup(c); +} + + +static struct op_unit_mask * new_unit_mask(void) +{ + struct op_unit_mask * um = xmalloc(sizeof(struct op_unit_mask)); + memset(um, '\0', sizeof(struct op_unit_mask)); + list_add_tail(&um->um_next, &um_list); + + return um; +} + +static void free_unit_mask(struct op_unit_mask * um) +{ + list_del(&um->um_next); + free(um); +} + +/* + * name:zero type:mandatory default:0x0 + * \t0x0 No unit mask + */ +static void read_unit_masks(char const * file) +{ + struct op_unit_mask * um = NULL; + char * line; + FILE * fp = fopen(file, "r"); + + if (!fp) { + fprintf(stderr, + "oprofile: could not open unit mask description file %s\n", file); + exit(EXIT_FAILURE); + } + + filename = file; + line_nr = 1; + + line = op_get_line(fp); + + while (line) { + if (empty_line(line) || comment_line(line)) + goto next; + + if (line[0] != '\t') { + um = new_unit_mask(); + parse_um(um, line); + } else { + if (!um) + parse_error("no unit mask name line"); + if (um->num >= MAX_UNIT_MASK) + parse_error("oprofile: maximum unit mask entries exceeded"); + + parse_um_entry(&um->um[um->num], line); + ++(um->num); + } + +next: + free(line); + line = op_get_line(fp); + ++line_nr; + } + + fclose(fp); +} + + +static u32 parse_counter_mask(char const * str) +{ + u32 mask = 0; + char const * numstart = str; + + while (*numstart) { + mask |= 1 << parse_int(numstart); + + while (*numstart && *numstart != ',') + ++numstart; + /* skip , unless we reach eos */ + if (*numstart) + ++numstart; + + numstart = skip_ws(numstart); + } + + return mask; +} + +static struct op_unit_mask * try_find_um(char const * value) +{ + struct list_head * pos; + + list_for_each(pos, &um_list) { + struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next); + if (strcmp(value, um->name) == 0) { + um->used = 1; + return um; + } + } + return NULL; +} + +static struct op_unit_mask * find_um(char const * value) +{ + struct op_unit_mask * um = try_find_um(value); + if (um) + return um; + fprintf(stderr, "oprofile: could not find unit mask %s\n", value); + exit(EXIT_FAILURE); +} + +/* um:a,b,c,d merge multiple unit masks */ +static struct op_unit_mask * merge_um(char * value) +{ + int num; + char *s; + struct op_unit_mask *new, *um; + enum unit_mask_type type = -1U; + + um = try_find_um(value); + if (um) + return um; + + new = new_unit_mask(); + new->name = xstrdup(value); + new->used = 1; + num = 0; + while ((s = strsep(&value, ",")) != NULL) { + unsigned c; + um = find_um(s); + if (type == -1U) + type = um->unit_type_mask; + if (um->unit_type_mask != type) + parse_error("combined unit mask must be all the same types"); + if (type != utm_bitmask && type != utm_exclusive) + parse_error("combined unit mask must be all bitmasks or exclusive"); + new->default_mask |= um->default_mask; + new->num += um->num; + if (new->num > MAX_UNIT_MASK) + parse_error("too many members in combined unit mask"); + for (c = 0; c < um->num; c++, num++) { + new->um[num] = um->um[c]; + new->um[num].desc = xstrdup(new->um[num].desc); + } + } + if (type == -1U) + parse_error("Empty unit mask"); + new->unit_type_mask = type; + return new; +} + +/* parse either a "tag:value" or a ": trailing description string" */ +static int next_token(char const ** cp, char ** name, char ** value) +{ + size_t tag_len; + size_t val_len; + char const * c = *cp; + char const * end; + char const * colon; + + c = skip_ws(c); + end = colon = c; + end = skip_nonws(end); + + colon = strchr(colon, ':'); + + if (!colon) { + if (*c) + parse_error("next_token(): garbage at end of line"); + return 0; + } + + if (colon >= end) + parse_error("next_token() expected ':'"); + + tag_len = colon - c; + val_len = end - (colon + 1); + + if (!tag_len) { + /* : trailing description */ + end = skip_ws(end); + *name = xstrdup("desc"); + *value = xstrdup(end); + end += strlen(end); + } else { + /* tag:value */ + *name = op_xstrndup(c, tag_len); + *value = op_xstrndup(colon + 1, val_len); + end = skip_ws(end); + } + + *cp = end; + return 1; +} + +static void include_events (char *value) +{ + char * event_file; + const char *old_filename; + int old_line_nr; + + event_file = build_fn(value, "events"); + old_line_nr = line_nr; + old_filename = filename; + read_events(event_file); + line_nr = old_line_nr; + filename = old_filename; + free(event_file); +} + +static struct op_event * new_event(void) +{ + struct op_event * event = xmalloc(sizeof(struct op_event)); + memset(event, '\0', sizeof(struct op_event)); + list_add_tail(&event->event_next, &events_list); + + return event; +} + +static void free_event(struct op_event * event) +{ + list_del(&event->event_next); + free(event); +} + +/* event:0x00 counters:0 um:zero minimum:4096 name:ISSUES : Total issues */ +/* event:0x00 ext:xxxxxx um:zero minimum:4096 name:ISSUES : Total issues */ +static void read_events(char const * file) +{ + struct op_event * event = NULL; + char * line; + char * name; + char * value; + char const * c; + int seen_event, seen_counters, seen_um, seen_minimum, seen_name, seen_ext; + FILE * fp = fopen(file, "r"); + int tags; + + if (!fp) { + fprintf(stderr, "oprofile: could not open event description file %s\n", file); + exit(EXIT_FAILURE); + } + + filename = file; + line_nr = 1; + + line = op_get_line(fp); + + while (line) { + if (empty_line(line) || comment_line(line)) + goto next; + + tags = 0; + seen_name = 0; + seen_event = 0; + seen_counters = 0; + seen_ext = 0; + seen_um = 0; + seen_minimum = 0; + event = new_event(); + event->filter = -1; + event->ext = NULL; + + c = line; + while (next_token(&c, &name, &value)) { + if (strcmp(name, "name") == 0) { + if (seen_name) + parse_error("duplicate name: tag"); + seen_name = 1; + if (strchr(value, '/') != NULL) + parse_error("invalid event name"); + if (strchr(value, '.') != NULL) + parse_error("invalid event name"); + event->name = value; + } else if (strcmp(name, "event") == 0) { + if (seen_event) + parse_error("duplicate event: tag"); + seen_event = 1; + event->val = parse_hex(value); + free(value); + } else if (strcmp(name, "counters") == 0) { + if (seen_counters) + parse_error("duplicate counters: tag"); + seen_counters = 1; + if (!strcmp(value, "cpuid")) + event->counter_mask = arch_get_counter_mask(); + else + event->counter_mask = parse_counter_mask(value); + free(value); + } else if (strcmp(name, "ext") == 0) { + if (seen_ext) + parse_error("duplicate ext: tag"); + seen_ext = 1; + event->ext = value; + } else if (strcmp(name, "um") == 0) { + if (seen_um) + parse_error("duplicate um: tag"); + seen_um = 1; + if (strchr(value, ',')) + event->unit = merge_um(value); + else + event->unit = find_um(value); + free(value); + } else if (strcmp(name, "minimum") == 0) { + if (seen_minimum) + parse_error("duplicate minimum: tag"); + seen_minimum = 1; + event->min_count = parse_int(value); + free(value); + } else if (strcmp(name, "desc") == 0) { + event->desc = value; + } else if (strcmp(name, "filter") == 0) { + event->filter = parse_int(value); + free(value); + } else if (strcmp(name, "include") == 0) { + if (tags > 0) + parse_error("tags before include:"); + free_event(event); + include_events(value); + free(value); + c = skip_ws(c); + if (*c != '\0' && *c != '#') + parse_error("non whitespace after include:"); + } else { + parse_error("unknown tag"); + } + tags++; + + free(name); + } +next: + free(line); + line = op_get_line(fp); + ++line_nr; + } + + fclose(fp); +} + + +/* usefull for make check */ +static int check_unit_mask(struct op_unit_mask const * um, + char const * cpu_name) +{ + u32 i; + int err = 0; + + if (!um->used) { + fprintf(stderr, "um %s is not used\n", um->name); + err = EXIT_FAILURE; + } + + if (um->unit_type_mask == utm_mandatory && um->num != 1) { + fprintf(stderr, "mandatory um %s doesn't contain exactly one " + "entry (%s)\n", um->name, cpu_name); + err = EXIT_FAILURE; + } else if (um->unit_type_mask == utm_bitmask) { + u32 default_mask = um->default_mask; + for (i = 0; i < um->num; ++i) + default_mask &= ~um->um[i].value; + + if (default_mask) { + fprintf(stderr, "um %s default mask is not valid " + "(%s)\n", um->name, cpu_name); + err = EXIT_FAILURE; + } + } else { + for (i = 0; i < um->num; ++i) { + if (um->default_mask == um->um[i].value) + break; + } + + if (i == um->num) { + fprintf(stderr, "exclusive um %s default value is not " + "valid (%s)\n", um->name, cpu_name); + err = EXIT_FAILURE; + } + } + return err; +} + +static void arch_filter_events(op_cpu cpu_type) +{ + struct list_head * pos, * pos2; + unsigned filter = arch_get_filter(cpu_type); + if (!filter) + return; + list_for_each_safe (pos, pos2, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + if (event->filter >= 0 && ((1U << event->filter) & filter)) + delete_event(event); + } +} + +static void load_events_name(const char *cpu_name) +{ + char * event_file; + char * um_file; + + event_file = build_fn(cpu_name, "events"); + um_file = build_fn(cpu_name, "unit_masks"); + + read_unit_masks(um_file); + read_events(event_file); + + free(um_file); + free(event_file); +} + +static void load_events(op_cpu cpu_type) +{ + const char * cpu_name = op_get_cpu_name(cpu_type); + struct list_head * pos; + struct op_event *event; + struct op_unit_mask *unit_mask; + int err = 0; + + if (!list_empty(&events_list)) + return; + + load_events_name(cpu_name); + + arch_filter_events(cpu_type); + + /* sanity check: all unit mask must be used */ + list_for_each(pos, &um_list) { + struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next); + err |= check_unit_mask(um, cpu_name); + } + if (err) + exit(err); + + if (!op_cpu_has_timer_fs()) + return; + + /* sanity check: Don't use event `TIMER' since it is predefined. */ + list_for_each(pos, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, + event_next); + + if (strcmp(event->name, TIMER_EVENT_NAME) == 0) { + fprintf(stderr, "Error: " TIMER_EVENT_NAME + " event cannot be redefined.\n"); + exit(EXIT_FAILURE); + } + if (event->val == TIMER_EVENT_VALUE) { + fprintf(stderr, "Error: Event %s uses " TIMER_EVENT_NAME + " which is reserverd for timer based sampling.\n", + event->name); + exit(EXIT_FAILURE); + } + } + + list_for_each(pos, &um_list) { + struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, + um_next); + if (strcmp(um->name, TIMER_EVENT_UNIT_MASK_NAME) == 0) { + fprintf(stderr, "Error: " TIMER_EVENT_UNIT_MASK_NAME + " unit mask cannot be redefined.\n"); + exit(EXIT_FAILURE); + } + } + + unit_mask = new_unit_mask(); + unit_mask->name = xstrdup(TIMER_EVENT_UNIT_MASK_NAME); + unit_mask->num = 1; + unit_mask->unit_type_mask = utm_mandatory; + unit_mask->um[0].extra = 0; + unit_mask->um[0].value = 0; + unit_mask->um[0].desc = xstrdup("No unit mask"); + unit_mask->used = 1; + + event = new_event(); + event->name = xstrdup(TIMER_EVENT_NAME); + event->desc = xstrdup(TIMER_EVENT_DESC); + event->val = TIMER_EVENT_VALUE; + event->unit = unit_mask; + event->min_count = 0; + event->filter = 0; + event->counter_mask = 1 << (op_get_nr_counters(cpu_type) - 1); + event->ext = NULL; + event->filter = -1; +} + +struct list_head * op_events(op_cpu cpu_type) +{ + load_events(cpu_type); + arch_filter_events(cpu_type); + return &events_list; +} + + +static void delete_unit_mask(struct op_unit_mask * unit) +{ + u32 cur; + for (cur = 0 ; cur < unit->num ; ++cur) { + if (unit->um[cur].desc) + free(unit->um[cur].desc); + } + + if (unit->name) + free(unit->name); + + list_del(&unit->um_next); + free(unit); +} + + +static void delete_event(struct op_event * event) +{ + if (event->name) + free(event->name); + if (event->desc) + free(event->desc); + + list_del(&event->event_next); + free(event); +} + + +void op_free_events(void) +{ + struct list_head * pos, * pos2; + list_for_each_safe(pos, pos2, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + delete_event(event); + } + + list_for_each_safe(pos, pos2, &um_list) { + struct op_unit_mask * unit = list_entry(pos, struct op_unit_mask, um_next); + delete_unit_mask(unit); + } +} + +/* There can be actually multiple events here, so this is not quite correct */ +static struct op_event * find_event_any(u32 nr) +{ + struct list_head * pos; + + list_for_each(pos, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + if (event->val == nr) + return event; + } + + return NULL; +} + +static struct op_event * find_event_um(u32 nr, u32 um) +{ + struct list_head * pos; + unsigned int i; + + list_for_each(pos, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + if (event->val == nr) { + for (i = 0; i < event->unit->num; i++) { + if (event->unit->um[i].value == um) + return event; + } + } + } + + return NULL; +} + +static FILE * open_event_mapping_file(char const * cpu_name) +{ + char * ev_map_file; + char * dir; + dir = getenv("OPROFILE_EVENTS_DIR"); + if (dir == NULL) + dir = OP_DATADIR; + + ev_map_file = xmalloc(strlen(dir) + strlen("/") + strlen(cpu_name) + + strlen("/") + + strlen("event_mappings") + 1); + strcpy(ev_map_file, dir); + strcat(ev_map_file, "/"); + + strcat(ev_map_file, cpu_name); + strcat(ev_map_file, "/"); + strcat(ev_map_file, "event_mappings"); + filename = ev_map_file; + return (fopen(ev_map_file, "r")); +} + + +/** + * This function is PPC64-specific. + */ +static char const * get_mapping(u32 nr, FILE * fp) +{ + char * line; + char * name; + char * value; + char const * c; + char * map = NULL; + int seen_event = 0, seen_mmcr0 = 0, seen_mmcr1 = 0, seen_mmcra = 0; + u32 mmcr0 = 0; + u64 mmcr1 = 0; + u32 mmcra = 0; + int event_found = 0; + + line_nr = 1; + line = op_get_line(fp); + while (line && !event_found) { + if (empty_line(line) || comment_line(line)) + goto next; + + seen_event = 0; + seen_mmcr0 = 0; + seen_mmcr1 = 0; + seen_mmcra = 0; + mmcr0 = 0; + mmcr1 = 0; + mmcra = 0; + + c = line; + while (next_token(&c, &name, &value)) { + if (strcmp(name, "event") == 0) { + u32 evt; + if (seen_event) + parse_error("duplicate event tag"); + seen_event = 1; + evt = parse_hex(value); + if (evt == nr) + event_found = 1; + free(value); + } else if (strcmp(name, "mmcr0") == 0) { + if (seen_mmcr0) + parse_error("duplicate mmcr0 tag"); + seen_mmcr0 = 1; + mmcr0 = parse_hex(value); + free(value); + } else if (strcmp(name, "mmcr1") == 0) { + if (seen_mmcr1) + parse_error("duplicate mmcr1: tag"); + seen_mmcr1 = 1; + mmcr1 = parse_long_hex(value); + free(value); + } else if (strcmp(name, "mmcra") == 0) { + if (seen_mmcra) + parse_error("duplicate mmcra: tag"); + seen_mmcra = 1; + mmcra = parse_hex(value); + free(value); + } else { + parse_error("unknown tag"); + } + + free(name); + } +next: + free(line); + line = op_get_line(fp); + ++line_nr; + } + if (event_found) { + if (!seen_mmcr0 || !seen_mmcr1 || !seen_mmcra) { + fprintf(stderr, "Error: Missing information in line %d of event mapping file %s\n", line_nr, filename); + exit(EXIT_FAILURE); + } + map = xmalloc(70); + snprintf(map, 70, "mmcr0:%u mmcr1:%Lu mmcra:%u", + mmcr0, mmcr1, mmcra); + } + + return map; +} + + +char const * find_mapping_for_event(u32 nr, op_cpu cpu_type) +{ + char const * cpu_name = op_get_cpu_name(cpu_type); + FILE * fp = open_event_mapping_file(cpu_name); + char const * map = NULL; + switch (cpu_type) { + case CPU_PPC64_PA6T: + case CPU_PPC64_970: + case CPU_PPC64_970MP: + case CPU_PPC64_POWER4: + case CPU_PPC64_POWER5: + case CPU_PPC64_POWER5p: + case CPU_PPC64_POWER5pp: + case CPU_PPC64_POWER6: + case CPU_PPC64_POWER7: + case CPU_PPC64_IBM_COMPAT_V1: + if (!fp) { + fprintf(stderr, "oprofile: could not open event mapping file %s\n", filename); + exit(EXIT_FAILURE); + } else { + map = get_mapping(nr, fp); + } + break; + default: + break; + } + + if (fp) + fclose(fp); + + return map; +} + +static int match_event(int i, struct op_event *event, unsigned um) +{ + unsigned v = event->unit->um[i].value; + + switch (event->unit->unit_type_mask) { + case utm_exclusive: + case utm_mandatory: + return v == um; + + case utm_bitmask: + return (v & um) || (!v && v == 0); + } + + abort(); +} + +struct op_event * find_event_by_name(char const * name, unsigned um, int um_valid) +{ + struct list_head * pos; + + list_for_each(pos, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + if (strcmp(event->name, name) == 0) { + if (um_valid) { + unsigned i; + + for (i = 0; i < event->unit->num; i++) + if (match_event(i, event, um)) + return event; + continue; + } + return event; + } + } + + return NULL; +} + + +static struct op_event * find_next_event(struct op_event * e) +{ + struct list_head * n; + + for (n = e->event_next.next; n != &events_list; n = n->next) { + struct op_event * ne = list_entry(n, struct op_event, event_next); + if (!strcmp(e->name, ne->name)) + return ne; + } + return NULL; +} + +struct op_event * op_find_event(op_cpu cpu_type, u32 nr, u32 um) +{ + struct op_event * event; + + load_events(cpu_type); + + event = find_event_um(nr, um); + + return event; +} + +struct op_event * op_find_event_any(op_cpu cpu_type, u32 nr) +{ + load_events(cpu_type); + + return find_event_any(nr); +} + +int op_check_events(int ctr, u32 nr, u32 um, op_cpu cpu_type) +{ + int ret = OP_INVALID_EVENT; + size_t i; + u32 ctr_mask = 1 << ctr; + struct list_head * pos; + + load_events(cpu_type); + + list_for_each(pos, &events_list) { + struct op_event * event = list_entry(pos, struct op_event, event_next); + if (event->val != nr) + continue; + + ret = OP_OK_EVENT; + + if ((event->counter_mask & ctr_mask) == 0) + ret |= OP_INVALID_COUNTER; + + if (event->unit->unit_type_mask == utm_bitmask) { + for (i = 0; i < event->unit->num; ++i) + um &= ~(event->unit->um[i].value); + + if (um) + ret |= OP_INVALID_UM; + + } else { + for (i = 0; i < event->unit->num; ++i) { + if (event->unit->um[i].value == um) + break; + } + + if (i == event->unit->num) + ret |= OP_INVALID_UM; + + } + + if (ret == OP_OK_EVENT) + return ret; + } + + return ret; +} + + +void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) +{ + descr->name = ""; + descr->um = 0x0; + /* A fixed value of CPU cycles; this should ensure good + * granulity even on faster CPUs, though it will generate more + * interrupts. + */ + descr->count = 100000; + + switch (cpu_type) { + case CPU_PPRO: + case CPU_PII: + case CPU_PIII: + case CPU_P6_MOBILE: + case CPU_CORE: + case CPU_CORE_2: + case CPU_ATHLON: + case CPU_HAMMER: + case CPU_FAMILY10: + case CPU_ARCH_PERFMON: + case CPU_FAMILY11H: + case CPU_ATOM: + case CPU_CORE_I7: + case CPU_NEHALEM: + case CPU_WESTMERE: + case CPU_SANDYBRIDGE: + case CPU_IVYBRIDGE: + case CPU_MIPS_LOONGSON2: + case CPU_FAMILY12H: + case CPU_FAMILY14H: + case CPU_FAMILY15H: + descr->name = "CPU_CLK_UNHALTED"; + break; + + case CPU_RTC: + descr->name = "RTC_INTERRUPTS"; + descr->count = 1024; + break; + + case CPU_P4: + case CPU_P4_HT2: + descr->name = "GLOBAL_POWER_EVENTS"; + descr->um = 0x1; + break; + + case CPU_IA64: + case CPU_IA64_1: + case CPU_IA64_2: + descr->count = 1000000; + descr->name = "CPU_CYCLES"; + break; + + case CPU_AXP_EV4: + case CPU_AXP_EV5: + case CPU_AXP_PCA56: + case CPU_AXP_EV6: + case CPU_AXP_EV67: + descr->name = "CYCLES"; + break; + + // we could possibly use the CCNT + case CPU_ARM_XSCALE1: + case CPU_ARM_XSCALE2: + case CPU_ARM_MPCORE: + case CPU_ARM_V6: + case CPU_ARM_V7: + case CPU_ARM_V7_CA5: + case CPU_ARM_V7_CA7: + case CPU_ARM_V7_CA9: + case CPU_ARM_V7_CA15: + case CPU_AVR32: + case CPU_ARM_SCORPION: + case CPU_ARM_SCORPIONMP: + descr->name = "CPU_CYCLES"; + break; + + case CPU_PPC64_PA6T: + case CPU_PPC64_970: + case CPU_PPC64_970MP: + case CPU_PPC_7450: + case CPU_PPC64_POWER4: + case CPU_PPC64_POWER5: + case CPU_PPC64_POWER6: + case CPU_PPC64_POWER5p: + case CPU_PPC64_POWER5pp: + case CPU_PPC64_CELL: + case CPU_PPC64_POWER7: + case CPU_PPC64_IBM_COMPAT_V1: + descr->name = "CYCLES"; + break; + + case CPU_MIPS_20K: + descr->name = "CYCLES"; + break; + + case CPU_MIPS_24K: + case CPU_MIPS_34K: + case CPU_MIPS_74K: + case CPU_MIPS_1004K: + descr->name = "INSTRUCTIONS"; + break; + + case CPU_MIPS_5K: + case CPU_MIPS_25K: + descr->name = "CYCLES"; + break; + + case CPU_MIPS_R10000: + case CPU_MIPS_R12000: + descr->name = "INSTRUCTIONS_GRADUATED"; + break; + + case CPU_MIPS_RM7000: + case CPU_MIPS_RM9000: + descr->name = "INSTRUCTIONS_ISSUED"; + break; + + case CPU_MIPS_SB1: + descr->name = "INSN_SURVIVED_STAGE7"; + break; + + case CPU_MIPS_VR5432: + case CPU_MIPS_VR5500: + descr->name = "INSTRUCTIONS_EXECUTED"; + break; + + case CPU_PPC_E500: + case CPU_PPC_E500_2: + case CPU_PPC_E300: + descr->name = "CPU_CLK"; + break; + case CPU_S390_Z10: + case CPU_S390_Z196: + if (op_get_nr_counters(cpu_type) > 1) { + descr->name = "HWSAMPLING"; + descr->count = 4127518; + } else { + descr->name = TIMER_EVENT_NAME; + descr->count = 10000; + } + break; + + case CPU_TILE_TILE64: + case CPU_TILE_TILEPRO: + case CPU_TILE_TILEGX: + descr->name = "ONE"; + break; + + // don't use default, if someone add a cpu he wants a compiler + // warning if he forgets to handle it here. + case CPU_TIMER_INT: + case CPU_NO_GOOD: + case MAX_CPU_TYPE: + break; + } +} + +static void extra_check(struct op_event *e, u32 unit_mask) +{ + unsigned i; + int found = 0; + + for (i = 0; i < e->unit->num; i++) + if (e->unit->um[i].value == unit_mask) + found++; + if (found > 1) { + fprintf(stderr, +"Named unit masks not allowed for events without 'extra:' values.\n" +"Please specify the numerical value for the unit mask. See 'opcontrol'" +" man page for more info.\n"); + exit(EXIT_FAILURE); + } +} + +static void another_extra_check(struct op_event *e, char *name, unsigned w) +{ + int found; + unsigned i; + + if (!e->unit->um[w].extra) { + fprintf(stderr, +"Named unit mask (%s) not allowed for event without 'extra:' values.\n" +"Please specify the numerical value for the unit mask. See 'opcontrol'" +" man page for more info.\n", name); + exit(EXIT_FAILURE); + } + + found = 0; + for (i = 0; i < e->unit->num; i++) { + int len = strcspn(e->unit->um[i].desc, " \t"); + if (!strncmp(name, e->unit->um[i].desc, len) && + name[len] == '\0') + found++; + } + if (found > 1) { + fprintf(stderr, + "Unit mask name `%s' not unique. Sorry please use a numerical unit mask\n", name); + exit(EXIT_FAILURE); + } +} + +static void do_resolve_unit_mask(struct op_event *e, struct parsed_event *pe, + u32 *extra) +{ + unsigned i; + int found; + + for (;;) { + if (pe->unit_mask_name == NULL) { + int had_unit_mask = pe->unit_mask_valid; + + found = 0; + for (i = 0; i < e->unit->num; i++) { + if (!pe->unit_mask_valid && + e->unit->um[i].value == e->unit->default_mask) { + pe->unit_mask_valid = 1; + pe->unit_mask = e->unit->default_mask; + break; + } + } + if (found > 1 && had_unit_mask) { + fprintf(stderr, + "Non unique numerical unit mask.\n" + "Please specify the unit mask using the first word of the description\n"); + exit(EXIT_FAILURE); + } + extra_check(e, pe->unit_mask); + if (i == e->unit->num) { + e = find_next_event(e); + if (e != NULL) + continue; + } else { + if (extra) + *extra = e->unit->um[i].extra; + } + return; + } + for (i = 0; i < e->unit->num; i++) { + int len = strcspn(e->unit->um[i].desc, " \t"); + if (!strncmp(pe->unit_mask_name, e->unit->um[i].desc, + len) && pe->unit_mask_name[len] == '\0') + break; + } + if (i == e->unit->num) { + e = find_next_event(e); + if (e != NULL) + continue; + fprintf(stderr, "Cannot find unit mask %s for %s\n", + pe->unit_mask_name, pe->name); + exit(EXIT_FAILURE); + } + another_extra_check(e, pe->unit_mask_name, i); + pe->unit_mask_valid = 1; + pe->unit_mask = e->unit->um[i].value; + if (extra) + *extra = e->unit->um[i].extra; + return; + } +} + +void op_resolve_unit_mask(struct parsed_event *pe, u32 *extra) +{ + struct op_event *e; + + e = find_event_by_name(pe->name, 0, 0); + if (!e) { + fprintf(stderr, "Cannot find event %s\n", pe->name); + exit(EXIT_FAILURE); + } + return do_resolve_unit_mask(e, pe, extra); +}