u-boot: fix UART clock setting for mx53

Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.

FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.

On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

2 files changed, 59 insertions, 1 deletions

diff --git a/recipes-bsp/u-boot/u-boot/mx53-fix-uart-clock.patch b/recipes-bsp/u-boot/u-boot/mx53-fix-uart-clock.patch
new file mode 100644
index 0000000..7d4f6bc
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/mx53-fix-uart-clock.patch
@@ -0,0 +1,55 @@
+Change the parent UART clock to be PLL2, so that U-boot can also boot
+a Freescale 2.6.35 kernel for mx53.
+
+FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
+conflicts with IPU clocks, so that the video resolution can be changed
+without affecting the UART clock. 
+
+On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
+and this patch fixes this problem.
+
+Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
+
+Upstream-Status: Submitted [under review]
+
+Reported-by: Otavio Salvador <otavio@ossystems.com.br>
+Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
+---
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S |   20 +++++++++++++++++---
+ 1 files changed, 17 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index 01f6d75..90c6ec1 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -284,10 +284,24 @@
+        ldr r1, =0x00C30321
+        str r1, [r0, #CLKCTL_CSCDR1]
+ #elif defined(CONFIG_MX53)
++       /* Switch peripheral to PLL2 */
++       ldr r0, =CCM_BASE_ADDR
++       ldr r1, =0x00808145
++       orr r1, r1, #(2 << 10)
++       orr r1, r1, #(0 << 16)
++       orr r1, r1, #(1 << 19)
++       str r1, [r0, #CLKCTL_CBCDR]
++
++       ldr r1, =0x00016154
++       str r1, [r0, #CLKCTL_CBCMR]
++       /* Change uart clk parent to pll2*/
++       ldr r1, [r0, #CLKCTL_CSCMR1]
++       and r1, r1, #0xfcffffff
++       orr r1, r1, #0x01000000
++       str r1, [r0, #CLKCTL_CSCMR1]
+        ldr r1, [r0, #CLKCTL_CSCDR1]
+-       orr r1, r1, #0x3f
+-       eor r1, r1, #0x3f
+-       orr r1, r1, #0x21
++       and r1, r1, #0xffffffc0
++       orr r1, r1, #0x0a
+        str r1, [r0, #CLKCTL_CSCDR1]
+ #endif
+        /* make sure divider effective */
+-- 
+1.7.1
+
diff --git a/recipes-bsp/u-boot/u-boot_git.bb b/recipes-bsp/u-boot/u-boot_git.bb
index 0255af7..46a3fb3 100644
--- a/recipes-bsp/u-boot/u-boot_git.bb
+++ b/recipes-bsp/u-boot/u-boot_git.bb
@@ -6,11 +6,14 @@ COMPATIBLE_MACHINE = "(imx53qsb|imx53ard|imx51evk)"
 
 DEPENDS_mxs += "elftosb-native"
 
+PR = "r1"
+
 SRCREV = "6751b05f855bbe56005d5b88d4eb58bcd52170d2"
 
 PV = "v2011.12+git"
 
-SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git"
+SRC_URI = "git://git.denx.de/u-boot.git;branch=master;protocol=git \
+           file://mx53-fix-uart-clock.patch"
 
 S = "${WORKDIR}/git"