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-rw-r--r--recipes-kernel/linux/linux-imx-3.10.17/0002-ARM-imx6sl-Disable-imx6sl-specific-code-when-imx6sl-.patch419
-rw-r--r--recipes-kernel/linux/linux-imx_3.10.17.bb3
2 files changed, 1 insertions, 421 deletions
diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0002-ARM-imx6sl-Disable-imx6sl-specific-code-when-imx6sl-.patch b/recipes-kernel/linux/linux-imx-3.10.17/0002-ARM-imx6sl-Disable-imx6sl-specific-code-when-imx6sl-.patch
deleted file mode 100644
index 3255352..0000000
--- a/recipes-kernel/linux/linux-imx-3.10.17/0002-ARM-imx6sl-Disable-imx6sl-specific-code-when-imx6sl-.patch
+++ /dev/null
@@ -1,419 +0,0 @@
1From 351f605f08b7fb808ed3fdcb57f61db478be2c59 Mon Sep 17 00:00:00 2001
2From: Nikolay Dimitrov <picmaster@mail.bg>
3Date: Fri, 6 Feb 2015 14:37:50 +0200
4Subject: [PATCH] ARM: imx6sl: Disable imx6sl-specific code when imx6sl SOC
5 support is disabled
6
7---
8 arch/arm/mach-imx/anatop.c | 13 +++++++++++--
9 arch/arm/mach-imx/busfreq-imx6.c | 35 ++++++++++++++++++++++++++---------
10 arch/arm/mach-imx/gpc.c | 23 ++++++++++++++++++++---
11 arch/arm/mach-imx/mxc.h | 2 ++
12 arch/arm/mach-imx/pm-imx6.c | 18 ++++++++++++++++--
13 arch/arm/mach-imx/system.c | 16 ++++++++++++----
14 6 files changed, 87 insertions(+), 20 deletions(-)
15
16diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
17index 9bdea7e..c58ae28 100644
18--- a/arch/arm/mach-imx/anatop.c
19+++ b/arch/arm/mach-imx/anatop.c
20@@ -77,10 +77,13 @@ static inline void imx_anatop_disconnect_high_snvs(bool enable)
21
22 void imx_anatop_pre_suspend(void)
23 {
24+#ifdef CONFIG_SOC_IMX6SL
25 if (cpu_is_imx6sl()) {
26 imx_anatop_enable_2p5_pulldown(true);
27 imx_anatop_disconnect_high_snvs(true);
28- } else {
29+ } else
30+#endif
31+ {
32 imx_anatop_enable_weak2p5(true);
33 }
34
35@@ -90,10 +93,14 @@ void imx_anatop_pre_suspend(void)
36 void imx_anatop_post_resume(void)
37 {
38 imx_anatop_enable_fet_odrive(false);
39+
40+#ifdef CONFIG_SOC_IMX6SL
41 if (cpu_is_imx6sl()) {
42 imx_anatop_enable_2p5_pulldown(false);
43 imx_anatop_disconnect_high_snvs(false);
44- } else {
45+ } else
46+#endif
47+ {
48 imx_anatop_enable_weak2p5(false);
49 }
50 }
51@@ -141,8 +148,10 @@ void __init imx_init_revision_from_anatop(void)
52 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
53 anatop_base = of_iomap(np, 0);
54 WARN_ON(!anatop_base);
55+#ifdef CONFIG_SOC_IMX6SL
56 if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
57 offset = ANADIG_DIGPROG_IMX6SL;
58+#endif
59 digprog = readl_relaxed(anatop_base + offset);
60 iounmap(anatop_base);
61
62diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
63index 527b042..4b4b342 100644
64--- a/arch/arm/mach-imx/busfreq-imx6.c
65+++ b/arch/arm/mach-imx/busfreq-imx6.c
66@@ -62,7 +62,6 @@ unsigned int ddr_normal_rate;
67 static int bus_freq_scaling_initialized;
68 static struct device *busfreq_dev;
69 static int busfreq_suspended;
70-static u32 org_arm_rate;
71 static int bus_freq_scaling_is_active;
72 static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count;
73 static unsigned int ddr_low_rate;
74@@ -73,7 +72,6 @@ extern int update_ddr_freq(int ddr_rate);
75 extern int update_lpddr2_freq(int ddr_rate);
76
77 DEFINE_MUTEX(bus_freq_mutex);
78-static DEFINE_SPINLOCK(freq_lock);
79
80 static struct clk *pll2_400;
81 static struct clk *periph_clk;
82@@ -85,6 +83,17 @@ static struct clk *cpu_clk;
83 static struct clk *pll3;
84 static struct clk *pll2;
85 static struct clk *pll2_200;
86+static struct clk *axi_sel_clk;
87+static struct clk *pll3_pfd1_540m;
88+
89+static struct delayed_work low_bus_freq_handler;
90+static struct delayed_work bus_freq_daemon;
91+
92+#ifdef CONFIG_SOC_IMX6SL
93+static u32 org_arm_rate;
94+
95+static DEFINE_SPINLOCK(freq_lock);
96+
97 static struct clk *pll1_sys;
98 static struct clk *periph2_clk;
99 static struct clk *ocram_clk;
100@@ -94,12 +103,8 @@ static struct clk *periph2_pre_clk;
101 static struct clk *periph2_clk2_sel;
102 static struct clk *periph2_clk2;
103 static struct clk *step_clk;
104-static struct clk *axi_sel_clk;
105-static struct clk *pll3_pfd1_540m;
106
107 static u32 pll2_org_rate;
108-static struct delayed_work low_bus_freq_handler;
109-static struct delayed_work bus_freq_daemon;
110
111 static void enter_lpm_imx6sl(void)
112 {
113@@ -250,14 +255,19 @@ static void exit_lpm_imx6sl(void)
114 ultra_low_bus_freq_mode = 0;
115 }
116 }
117+#endif // CONFIG_SOC_IMX6SL
118
119 int reduce_bus_freq(void)
120 {
121 int ret = 0;
122 clk_prepare_enable(pll3);
123+
124+#ifdef CONFIG_SOC_IMX6SL
125 if (cpu_is_imx6sl())
126 enter_lpm_imx6sl();
127- else {
128+ else
129+#endif
130+ {
131 if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk)
132 != periph_clk))
133 /* Set axi to periph_clk */
134@@ -393,9 +403,13 @@ int set_high_bus_freq(int high_bus_freq)
135 return 0;
136
137 clk_prepare_enable(pll3);
138+
139+#ifdef CONFIG_SOC_IMX6SL
140 if (cpu_is_imx6sl())
141 exit_lpm_imx6sl();
142- else {
143+ else
144+#endif
145+ {
146 if (high_bus_freq) {
147 update_ddr_freq(ddr_normal_rate);
148 /* Make sure periph clk's parent also got updated */
149@@ -773,6 +787,7 @@ static int busfreq_probe(struct platform_device *pdev)
150 }
151 }
152
153+#ifdef CONFIG_SOC_IMX6SL
154 if (cpu_is_imx6sl()) {
155 pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
156 if (IS_ERR(pll1_sys)) {
157@@ -840,8 +855,8 @@ static int busfreq_probe(struct platform_device *pdev)
158 __func__);
159 return PTR_ERR(periph2_clk2_sel);
160 }
161-
162 }
163+#endif // CONFIG_SOC_IMX6SL
164
165 err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
166 if (err) {
167@@ -880,9 +895,11 @@ static int busfreq_probe(struct platform_device *pdev)
168 register_pm_notifier(&imx_bus_freq_pm_notifier);
169 register_reboot_notifier(&imx_busfreq_reboot_notifier);
170
171+#ifdef CONFIG_SOC_IMX6SL
172 if (cpu_is_imx6sl())
173 err = init_mmdc_lpddr2_settings(pdev);
174 else
175+#endif
176 err = init_mmdc_ddr3_settings(pdev);
177 if (err) {
178 dev_err(busfreq_dev, "Busfreq init of MMDC failed\n");
179diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
180index 25e987c..dfdb1b7 100644
181--- a/arch/arm/mach-imx/gpc.c
182+++ b/arch/arm/mach-imx/gpc.c
183@@ -55,8 +55,10 @@ static void __iomem *gpc_base;
184 static u32 gpc_wake_irqs[IMR_NUM];
185 static u32 gpc_saved_imrs[IMR_NUM];
186 static struct clk *gpu3d_clk, *gpu3d_shader_clk, *gpu2d_clk, *gpu2d_axi_clk;
187+#ifdef CONFIG_SOC_IMX6SL
188 static struct clk *lcd_axi_clk, *lcd_pix_clk, *epdc_axi_clk, *epdc_pix_clk;
189 static struct clk *pxp_axi_clk;
190+#endif
191 static struct clk *openvg_axi_clk, *vpu_clk, *ipg_clk;
192 static struct device *gpc_dev;
193 struct regulator *pu_reg;
194@@ -71,6 +73,7 @@ static struct regulator_init_data pu_dummy_initdata = {
195 };
196 static int pu_dummy_enable;
197
198+#ifdef CONFIG_SOC_IMX6SL
199 static void imx_disp_clk(bool enable)
200 {
201 if (enable) {
202@@ -87,9 +90,11 @@ static void imx_disp_clk(bool enable)
203 clk_disable_unprepare(pxp_axi_clk);
204 }
205 }
206+#endif // CONFIG_SOC_IMX6SL
207
208 static void imx_gpc_dispmix_on(void)
209 {
210+#ifdef CONFIG_SOC_IMX6SL
211 if (cpu_is_imx6sl() &&
212 imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) {
213 imx_disp_clk(true);
214@@ -102,10 +107,12 @@ static void imx_gpc_dispmix_on(void)
215
216 imx_disp_clk(false);
217 }
218+#endif
219 }
220
221 static void imx_gpc_dispmix_off(void)
222 {
223+#ifdef CONFIG_SOC_IMX6SL
224 if (cpu_is_imx6sl() &&
225 imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) {
226 imx_disp_clk(true);
227@@ -121,6 +128,7 @@ static void imx_gpc_dispmix_off(void)
228
229 imx_disp_clk(false);
230 }
231+#endif
232 }
233
234 void imx_gpc_pre_suspend(bool arm_power_off)
235@@ -224,10 +232,13 @@ void imx_gpc_irq_mask(struct irq_data *d)
236 static void imx_pu_clk(bool enable)
237 {
238 if (enable) {
239+#ifdef CONFIG_SOC_IMX6SL
240 if (cpu_is_imx6sl()) {
241 clk_prepare_enable(gpu2d_clk);
242 clk_prepare_enable(openvg_axi_clk);
243- } else {
244+ } else
245+#endif
246+ {
247 clk_prepare_enable(gpu3d_clk);
248 clk_prepare_enable(gpu3d_shader_clk);
249 clk_prepare_enable(vpu_clk);
250@@ -236,10 +247,13 @@ static void imx_pu_clk(bool enable)
251 clk_prepare_enable(openvg_axi_clk);
252 }
253 } else {
254+#ifdef CONFIG_SOC_IMX6SL
255 if (cpu_is_imx6sl()) {
256 clk_disable_unprepare(gpu2d_clk);
257 clk_disable_unprepare(openvg_axi_clk);
258- } else {
259+ } else
260+#endif
261+ {
262 clk_disable_unprepare(gpu3d_clk);
263 clk_disable_unprepare(gpu3d_shader_clk);
264 clk_disable_unprepare(vpu_clk);
265@@ -478,6 +492,7 @@ static int imx_gpc_probe(struct platform_device *pdev)
266 nb.notifier_call = &imx_gpc_regulator_notify;
267
268 /* Get gpu&vpu clk for power up PU by GPC */
269+#ifdef CONFIG_SOC_IMX6SL
270 if (cpu_is_imx6sl()) {
271 gpu2d_clk = devm_clk_get(gpc_dev, "gpu2d_podf");
272 openvg_axi_clk = devm_clk_get(gpc_dev, "gpu2d_ovg");
273@@ -494,7 +509,9 @@ static int imx_gpc_probe(struct platform_device *pdev)
274 dev_err(gpc_dev, "failed to get clk!\n");
275 return -ENOENT;
276 }
277- } else {
278+ } else
279+#endif // CONFIG_SOC_IMX6SL
280+ {
281 gpu3d_clk = devm_clk_get(gpc_dev, "gpu3d_core");
282 gpu3d_shader_clk = devm_clk_get(gpc_dev, "gpu3d_shader");
283 gpu2d_clk = devm_clk_get(gpc_dev, "gpu2d_core");
284diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
285index c78174d..cd81f1e 100644
286--- a/arch/arm/mach-imx/mxc.h
287+++ b/arch/arm/mach-imx/mxc.h
288@@ -155,10 +155,12 @@ extern unsigned int __mxc_cpu_type;
289 #endif
290
291 #ifndef __ASSEMBLY__
292+#ifdef CONFIG_SOC_IMX6SL
293 static inline bool cpu_is_imx6sl(void)
294 {
295 return __mxc_cpu_type == MXC_CPU_IMX6SL;
296 }
297+#endif
298
299 static inline bool cpu_is_imx6dl(void)
300 {
301diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
302index 587cc7e..b0a3264 100644
303--- a/arch/arm/mach-imx/pm-imx6.c
304+++ b/arch/arm/mach-imx/pm-imx6.c
305@@ -221,19 +221,24 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
306 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
307 val &= ~BM_CLPCR_VSTBY;
308 val &= ~BM_CLPCR_SBYOS;
309+#ifdef CONFIG_SOC_IMX6SL
310 if (cpu_is_imx6sl())
311 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
312 else
313+#endif
314 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
315 break;
316 case STOP_POWER_ON:
317 val |= 0x2 << BP_CLPCR_LPM;
318 val &= ~BM_CLPCR_VSTBY;
319 val &= ~BM_CLPCR_SBYOS;
320+#ifdef CONFIG_SOC_IMX6SL
321 if (cpu_is_imx6sl()) {
322 val |= BM_CLPCR_BYPASS_PMIC_READY;
323 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
324- } else {
325+ } else
326+#endif
327+ {
328 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
329 }
330 break;
331@@ -247,10 +252,13 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
332 val |= 0x3 << BP_CLPCR_STBY_COUNT;
333 val |= BM_CLPCR_VSTBY;
334 val |= BM_CLPCR_SBYOS;
335+#ifdef CONFIG_SOC_IMX6SL
336 if (cpu_is_imx6sl()) {
337 val |= BM_CLPCR_BYPASS_PMIC_READY;
338 val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
339- } else {
340+ } else
341+#endif
342+ {
343 val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
344 }
345 break;
346@@ -304,12 +312,16 @@ static int imx6_pm_enter(suspend_state_t state)
347 imx6_set_lpm(STOP_POWER_ON);
348 imx6_set_cache_lpm_in_wait(true);
349 imx_gpc_pre_suspend(false);
350+#ifdef CONFIG_SOC_IMX6SL
351 if (cpu_is_imx6sl())
352 imx6sl_set_wait_clk(true);
353+#endif
354 /* Zzz ... */
355 cpu_do_idle();
356+#ifdef CONFIG_SOC_IMX6SL
357 if (cpu_is_imx6sl())
358 imx6sl_set_wait_clk(false);
359+#endif
360 imx_gpc_post_resume();
361 imx6_set_lpm(WAIT_CLOCKED);
362 break;
363@@ -328,8 +340,10 @@ static int imx6_pm_enter(suspend_state_t state)
364
365 imx6_restore_cpu_arch_regs();
366
367+#ifdef CONFIG_SOC_IMX6SL
368 if (!cpu_is_imx6sl())
369 imx_smp_prepare();
370+#endif
371 imx_anatop_post_resume();
372 imx_gpc_post_resume();
373 imx6_enable_rbc(false);
374diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
375index df3d1ff..86fb602 100644
376--- a/arch/arm/mach-imx/system.c
377+++ b/arch/arm/mach-imx/system.c
378@@ -54,8 +54,11 @@ void mxc_restart(char mode, const char *cmd)
379 * trigger external POR later. Use WDOG1 to reset in ldo-enable
380 * mode. You can set it by "fsl,wdog-reset" in dts.
381 */
382- else if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
383- cpu_is_imx6sl()))
384+ else if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl()
385+#ifdef CONFIG_SOC_IMX6SL
386+ || cpu_is_imx6sl()
387+#endif
388+ ))
389 wcr_enable = 0x14;
390 else
391 wcr_enable = (1 << 2);
392@@ -97,8 +100,10 @@ void __init mxc_arch_reset_init_dt(void)
393
394 if (cpu_is_imx6q() || cpu_is_imx6dl())
395 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
396+#ifdef CONFIG_SOC_IMX6SL
397 else if (cpu_is_imx6sl())
398 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc");
399+#endif
400
401 if (np)
402 of_property_read_u32(np, "fsl,wdog-reset", &wdog_source);
403@@ -109,8 +114,11 @@ void __init mxc_arch_reset_init_dt(void)
404 WARN_ON(!wdog_base);
405
406 /* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */
407- if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
408- cpu_is_imx6sl())) {
409+ if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl()
410+#ifdef CONFIG_SOC_IMX6SL
411+ || cpu_is_imx6sl()
412+#endif
413+ )) {
414 np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt");
415 wdog_base = of_iomap(np, 0);
416 WARN_ON(!wdog_base);
417--
4181.7.10.4
419
diff --git a/recipes-kernel/linux/linux-imx_3.10.17.bb b/recipes-kernel/linux/linux-imx_3.10.17.bb
index d22289b..143eaab 100644
--- a/recipes-kernel/linux/linux-imx_3.10.17.bb
+++ b/recipes-kernel/linux/linux-imx_3.10.17.bb
@@ -15,7 +15,6 @@ SRCBRANCH = "imx_3.10.17_1.0.0_ga"
15SRCREV = "33597e348b2d60dd5c71890ef7b7d3d3fd6e4e97" 15SRCREV = "33597e348b2d60dd5c71890ef7b7d3d3fd6e4e97"
16LOCALVERSION = "-1.0.2_ga" 16LOCALVERSION = "-1.0.2_ga"
17 17
18SRC_URI += "file://0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch \ 18SRC_URI += "file://0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch"
19 file://0002-ARM-imx6sl-Disable-imx6sl-specific-code-when-imx6sl-.patch"
20 19
21COMPATIBLE_MACHINE = "(mx6)" 20COMPATIBLE_MACHINE = "(mx6)"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-05-13 18:33:08 +0000