From daf582c93a7283fb0af3b25fe2ada48f4c9985c4 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Tue, 2 Jul 2013 11:52:51 -0300 Subject: perf: Disable FPU tune for i.MX5 SoCs to workaround GCC ICE GCC 4.8 currently ICE when building perf for i.MX5 SoCs and we can workaround it disabling the FPU tunning for it. This is a temporary solution until GCC fixes this in an upcoming release. GCC bugzilla: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748 Change-Id: I5a23e6b57695a90e9750f0fa28c419b260c83be2 Signed-off-by: Otavio Salvador --- recipes-kernel/perf/perf.bbappend | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 recipes-kernel/perf/perf.bbappend (limited to 'recipes-kernel') diff --git a/recipes-kernel/perf/perf.bbappend b/recipes-kernel/perf/perf.bbappend new file mode 100644 index 0000000..604e2b4 --- /dev/null +++ b/recipes-kernel/perf/perf.bbappend @@ -0,0 +1,3 @@ +# FIXME: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57748 +TUNE_CCARGS_mx5 := "${@oe_filter_out('-mfpu=neon', '${TUNE_CCARGS}', d)}" + -- cgit v1.2.3-54-g00ecf