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-rw-r--r--meta-python/recipes-devtools/python/python3-grpcio/0001-Fix-build-on-riscv32.patch65
-rw-r--r--meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch13
-rw-r--r--meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb1
3 files changed, 75 insertions, 4 deletions
diff --git a/meta-python/recipes-devtools/python/python3-grpcio/0001-Fix-build-on-riscv32.patch b/meta-python/recipes-devtools/python/python3-grpcio/0001-Fix-build-on-riscv32.patch
new file mode 100644
index 0000000000..920fc1169d
--- /dev/null
+++ b/meta-python/recipes-devtools/python/python3-grpcio/0001-Fix-build-on-riscv32.patch
@@ -0,0 +1,65 @@
1From 04e28fdda03b545a0f7b446a784ec2fa7249cbb8 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Wed, 29 Apr 2020 15:37:40 -0700
4Subject: [PATCH] Fix build on riscv32
5
6Define __NR_mmap in terms of __NR_mmap2 and __NR_futex interms of
7__NR_futex_time64 for rv32, since there calls dont exist for rv32
8
9Also recognise rv32 as a new 32bit platform
10
11Upstream-Status: Submitted [https://github.com/abseil/abseil-cpp/pull/675]
12Signed-off-by: Khem Raj <raj.khem@gmail.com>
13---
14 absl/base/internal/direct_mmap.h | 5 +++++
15 absl/base/internal/spinlock_linux.inc | 4 ++++
16 absl/synchronization/internal/waiter.cc | 4 ++++
17 3 files changed, 13 insertions(+)
18
19--- a/third_party/abseil-cpp/absl/base/internal/direct_mmap.h
20+++ b/third_party/abseil-cpp/absl/base/internal/direct_mmap.h
21@@ -26,6 +26,10 @@
22
23 #ifdef __linux__
24
25+#if !defined(__NR_mmap) && defined(__riscv) && __riscv_xlen == 32
26+# define __NR_mmap __NR_mmap2
27+#endif
28+
29 #include <sys/types.h>
30 #ifdef __BIONIC__
31 #include <sys/syscall.h>
32@@ -72,6 +76,7 @@ inline void* DirectMmap(void* start, siz
33 #if defined(__i386__) || defined(__ARM_ARCH_3__) || defined(__ARM_EABI__) || \
34 (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32) || \
35 (defined(__PPC__) && !defined(__PPC64__)) || \
36+ (defined(__riscv) && __riscv_xlen == 32) || \
37 (defined(__s390__) && !defined(__s390x__))
38 // On these architectures, implement mmap with mmap2.
39 static int pagesize = 0;
40--- a/third_party/abseil-cpp/absl/base/internal/spinlock_linux.inc
41+++ b/third_party/abseil-cpp/absl/base/internal/spinlock_linux.inc
42@@ -14,6 +14,10 @@
43 //
44 // This file is a Linux-specific part of spinlock_wait.cc
45
46+#if !defined(__NR_futex) && defined(__riscv) && __riscv_xlen == 32
47+# define __NR_futex __NR_futex_time64
48+#endif
49+
50 #include <linux/futex.h>
51 #include <sys/syscall.h>
52 #include <unistd.h>
53--- a/third_party/abseil-cpp/absl/synchronization/internal/waiter.cc
54+++ b/third_party/abseil-cpp/absl/synchronization/internal/waiter.cc
55@@ -24,6 +24,10 @@
56 #include <unistd.h>
57 #endif
58
59+#if !defined(__NR_futex) && defined(__riscv) && __riscv_xlen == 32
60+# define __NR_futex __NR_futex_time64
61+#endif
62+
63 #ifdef __linux__
64 #include <linux/futex.h>
65 #include <sys/syscall.h>
diff --git a/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch b/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch
index b55d50bde5..8c9ffa21b7 100644
--- a/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch
+++ b/meta-python/recipes-devtools/python/python3-grpcio/riscv64_support.patch
@@ -4,13 +4,18 @@ Upstream-Status: Pending
4Signed-off-by: Khem Raj <raj.khem@gmail.com> 4Signed-off-by: Khem Raj <raj.khem@gmail.com>
5--- a/third_party/boringssl/include/openssl/base.h 5--- a/third_party/boringssl/include/openssl/base.h
6+++ b/third_party/boringssl/include/openssl/base.h 6+++ b/third_party/boringssl/include/openssl/base.h
7@@ -108,6 +108,9 @@ extern "C" { 7@@ -108,6 +108,14 @@ extern "C" {
8 #elif defined(__mips__) && defined(__LP64__) 8 #elif defined(__mips__) && defined(__LP64__)
9 #define OPENSSL_64_BIT 9 #define OPENSSL_64_BIT
10 #define OPENSSL_MIPS64 10 #define OPENSSL_MIPS64
11+#elif defined(__riscv) && defined(__riscv_xlen) 11+#elif defined(__riscv)
12+#define OPENSSL_64_BIT 12+# if (__riscv_xlen == 64)
13+#define OPENSSL_RISCV64 13+# define OPENSSL_64_BIT
14+# define OPENSSL_RISCV64
15+# elif(__riscv_xlen == 32)
16+# define OPENSSL_32_BIT
17+# define OPENSSL_RISCV32
18+# endif
14 #elif defined(__pnacl__) 19 #elif defined(__pnacl__)
15 #define OPENSSL_32_BIT 20 #define OPENSSL_32_BIT
16 #define OPENSSL_PNACL 21 #define OPENSSL_PNACL
diff --git a/meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb b/meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb
index 83d3671016..129bb35bcc 100644
--- a/meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb
+++ b/meta-python/recipes-devtools/python/python3-grpcio_1.27.1.bb
@@ -9,6 +9,7 @@ DEPENDS += "${PYTHON_PN}-protobuf"
9SRC_URI += "file://0001-setup.py-Do-not-mix-C-and-C-compiler-options.patch" 9SRC_URI += "file://0001-setup.py-Do-not-mix-C-and-C-compiler-options.patch"
10SRC_URI_append_class-target = " file://ppc-boringssl-support.patch \ 10SRC_URI_append_class-target = " file://ppc-boringssl-support.patch \
11 file://riscv64_support.patch \ 11 file://riscv64_support.patch \
12 file://0001-Fix-build-on-riscv32.patch \
12" 13"
13SRC_URI[md5sum] = "ccaf4e7eb4f031d926fb80035d193b98" 14SRC_URI[md5sum] = "ccaf4e7eb4f031d926fb80035d193b98"
14SRC_URI[sha256sum] = "a899725d34769a498ecd3be154021c4368dd22bdc69473f6ec46779696f626c4" 15SRC_URI[sha256sum] = "a899725d34769a498ecd3be154021c4368dd22bdc69473f6ec46779696f626c4"