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1 files changed, 244 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch
new file mode 100644
index 0000000000..635d3f8bd5
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch
@@ -0,0 +1,244 @@
12010-07-09 Sandra Loosemore <sandra@codesourcery.com>
2
3 Backport from mainline (originally on Sourcery G++ 4.4):
4
5 2010-07-02 Julian Brown <julian@codesourcery.com>
6 Sandra Loosemore <sandra@codesourcery.com>
7
8 PR target/43703
9
10 gcc/
11 * config/arm/vec-common.md (add<mode>3, sub<mode>3, smin<mode>3)
12 (smax<mode>3): Disable for NEON float modes when
13 flag_unsafe_math_optimizations is false.
14 * config/arm/neon.md (*add<mode>3_neon, *sub<mode>3_neon)
15 (*mul<mode>3_neon)
16 (mul<mode>3add<mode>_neon, mul<mode>3neg<mode>add<mode>_neon)
17 (reduc_splus_<mode>, reduc_smin_<mode>, reduc_smax_<mode>): Disable
18 for NEON float modes when flag_unsafe_math_optimizations is false.
19 (quad_halves_<code>v4sf): Only enable if flag_unsafe_math_optimizations
20 is true.
21 * doc/invoke.texi (ARM Options): Add note about floating point
22 vectorization requiring -funsafe-math-optimizations.
23
24 gcc/testsuite/
25 * gcc.dg/vect/vect.exp: Add -ffast-math for NEON.
26 * gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON.
27
28 2010-07-08 Sandra Loosemore <sandra@codesourcery.com>
29
30 Backport from upstream (originally from Sourcery G++ 4.4):
31
32=== modified file 'gcc/config/arm/neon.md'
33--- old/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000
34+++ new/gcc/config/arm/neon.md 2010-07-29 17:03:20 +0000
35@@ -819,7 +819,7 @@
36 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
37 (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
38 (match_operand:VDQ 2 "s_register_operand" "w")))]
39- "TARGET_NEON"
40+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
41 "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
42 [(set (attr "neon_type")
43 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
44@@ -853,7 +853,7 @@
45 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
46 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
47 (match_operand:VDQ 2 "s_register_operand" "w")))]
48- "TARGET_NEON"
49+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
50 "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
51 [(set (attr "neon_type")
52 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
53@@ -888,7 +888,7 @@
54 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
55 (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
56 (match_operand:VDQ 2 "s_register_operand" "w")))]
57- "TARGET_NEON"
58+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
59 "vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
60 [(set (attr "neon_type")
61 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
62@@ -910,7 +910,7 @@
63 (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
64 (match_operand:VDQ 3 "s_register_operand" "w"))
65 (match_operand:VDQ 1 "s_register_operand" "0")))]
66- "TARGET_NEON"
67+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
68 "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
69 [(set (attr "neon_type")
70 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
71@@ -932,7 +932,7 @@
72 (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
73 (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
74 (match_operand:VDQ 3 "s_register_operand" "w"))))]
75- "TARGET_NEON"
76+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
77 "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
78 [(set (attr "neon_type")
79 (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
80@@ -1361,7 +1361,7 @@
81 (parallel [(const_int 0) (const_int 1)]))
82 (vec_select:V2SF (match_dup 1)
83 (parallel [(const_int 2) (const_int 3)]))))]
84- "TARGET_NEON"
85+ "TARGET_NEON && flag_unsafe_math_optimizations"
86 "<VQH_mnem>.f32\t%P0, %e1, %f1"
87 [(set_attr "vqh_mnem" "<VQH_mnem>")
88 (set (attr "neon_type")
89@@ -1496,7 +1496,7 @@
90 (define_expand "reduc_splus_<mode>"
91 [(match_operand:VD 0 "s_register_operand" "")
92 (match_operand:VD 1 "s_register_operand" "")]
93- "TARGET_NEON"
94+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
95 {
96 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
97 &gen_neon_vpadd_internal<mode>);
98@@ -1506,7 +1506,7 @@
99 (define_expand "reduc_splus_<mode>"
100 [(match_operand:VQ 0 "s_register_operand" "")
101 (match_operand:VQ 1 "s_register_operand" "")]
102- "TARGET_NEON"
103+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
104 {
105 rtx step1 = gen_reg_rtx (<V_HALF>mode);
106 rtx res_d = gen_reg_rtx (<V_HALF>mode);
107@@ -1541,7 +1541,7 @@
108 (define_expand "reduc_smin_<mode>"
109 [(match_operand:VD 0 "s_register_operand" "")
110 (match_operand:VD 1 "s_register_operand" "")]
111- "TARGET_NEON"
112+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
113 {
114 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
115 &gen_neon_vpsmin<mode>);
116@@ -1551,7 +1551,7 @@
117 (define_expand "reduc_smin_<mode>"
118 [(match_operand:VQ 0 "s_register_operand" "")
119 (match_operand:VQ 1 "s_register_operand" "")]
120- "TARGET_NEON"
121+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
122 {
123 rtx step1 = gen_reg_rtx (<V_HALF>mode);
124 rtx res_d = gen_reg_rtx (<V_HALF>mode);
125@@ -1566,7 +1566,7 @@
126 (define_expand "reduc_smax_<mode>"
127 [(match_operand:VD 0 "s_register_operand" "")
128 (match_operand:VD 1 "s_register_operand" "")]
129- "TARGET_NEON"
130+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
131 {
132 neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
133 &gen_neon_vpsmax<mode>);
134@@ -1576,7 +1576,7 @@
135 (define_expand "reduc_smax_<mode>"
136 [(match_operand:VQ 0 "s_register_operand" "")
137 (match_operand:VQ 1 "s_register_operand" "")]
138- "TARGET_NEON"
139+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
140 {
141 rtx step1 = gen_reg_rtx (<V_HALF>mode);
142 rtx res_d = gen_reg_rtx (<V_HALF>mode);
143
144=== modified file 'gcc/config/arm/vec-common.md'
145--- old/gcc/config/arm/vec-common.md 2009-11-11 14:23:03 +0000
146+++ new/gcc/config/arm/vec-common.md 2010-07-29 17:03:20 +0000
147@@ -57,7 +57,8 @@
148 [(set (match_operand:VALL 0 "s_register_operand" "")
149 (plus:VALL (match_operand:VALL 1 "s_register_operand" "")
150 (match_operand:VALL 2 "s_register_operand" "")))]
151- "TARGET_NEON
152+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
153+ || flag_unsafe_math_optimizations))
154 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
155 {
156 })
157@@ -66,7 +67,8 @@
158 [(set (match_operand:VALL 0 "s_register_operand" "")
159 (minus:VALL (match_operand:VALL 1 "s_register_operand" "")
160 (match_operand:VALL 2 "s_register_operand" "")))]
161- "TARGET_NEON
162+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
163+ || flag_unsafe_math_optimizations))
164 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
165 {
166 })
167@@ -75,7 +77,9 @@
168 [(set (match_operand:VALLW 0 "s_register_operand" "")
169 (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
170 (match_operand:VALLW 2 "s_register_operand" "")))]
171- "TARGET_NEON || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
172+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
173+ || flag_unsafe_math_optimizations))
174+ || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
175 {
176 })
177
178@@ -83,7 +87,8 @@
179 [(set (match_operand:VALLW 0 "s_register_operand" "")
180 (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
181 (match_operand:VALLW 2 "s_register_operand" "")))]
182- "TARGET_NEON
183+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
184+ || flag_unsafe_math_optimizations))
185 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
186 {
187 })
188@@ -101,7 +106,8 @@
189 [(set (match_operand:VALLW 0 "s_register_operand" "")
190 (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
191 (match_operand:VALLW 2 "s_register_operand" "")))]
192- "TARGET_NEON
193+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
194+ || flag_unsafe_math_optimizations))
195 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
196 {
197 })
198
199=== modified file 'gcc/doc/invoke.texi'
200--- old/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000
201+++ new/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000
202@@ -9874,6 +9874,14 @@
203 If @option{-msoft-float} is specified this specifies the format of
204 floating point values.
205
206+If the selected floating-point hardware includes the NEON extension
207+(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
208+operations will not be used by GCC's auto-vectorization pass unless
209+@option{-funsafe-math-optimizations} is also specified. This is
210+because NEON hardware does not fully implement the IEEE 754 standard for
211+floating-point arithmetic (in particular denormal values are treated as
212+zero), so the use of NEON instructions may lead to a loss of precision.
213+
214 @item -mfp16-format=@var{name}
215 @opindex mfp16-format
216 Specify the format of the @code{__fp16} half-precision floating-point type.
217
218=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-6.c'
219--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2007-09-04 12:05:19 +0000
220+++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2010-07-29 17:03:20 +0000
221@@ -49,5 +49,6 @@
222 }
223
224 /* need -ffast-math to vectorizer these loops. */
225-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
226+/* ARM NEON passes -ffast-math to these tests, so expect this to fail. */
227+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */
228 /* { dg-final { cleanup-tree-dump "vect" } } */
229
230=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
231--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 15:38:15 +0000
232+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 17:03:20 +0000
233@@ -102,6 +102,10 @@
234 set dg-do-what-default run
235 } elseif [is-effective-target arm_neon_ok] {
236 eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
237+ # NEON does not support denormals, so is not used for vectorization by
238+ # default to avoid loss of precision. We must pass -ffast-math to test
239+ # vectorization of float operations.
240+ lappend DEFAULT_VECTCFLAGS "-ffast-math"
241 if [is-effective-target arm_neon_hw] {
242 set dg-do-what-default run
243 } else {
244
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