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-rw-r--r--recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch369
1 files changed, 369 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch
new file mode 100644
index 0000000000..82a9e93e43
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch
@@ -0,0 +1,369 @@
12010-09-09 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from mainline:
4
5 2010-08-25 Tejas Belagod <tejas.belagod@arm.com>
6 * config/arm/iterators.md (VU, SE, V_widen_l): New.
7 (V_unpack, US): New.
8 * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for
9 vmovl.
10 (vec_unpack<US>_lo_<mode>): Likewise.
11 (neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl.
12 (neon_vec_unpack<US>_lo_<mode>): Likewise.
13 (vec_widen_<US>mult_lo_<mode>): Expansion for vmull.
14 (vec_widen_<US>mult_hi_<mode>): Likewise.
15 (neon_vec_<US>mult_lo_<mode>"): Instruction pattern for vmull.
16 (neon_vec_<US>mult_hi_<mode>"): Likewise.
17 (neon_unpack<US>_<mode>): Widening move intermediate step for
18 vectorizing without -mvectorize-with-neon-quad.
19 (neon_vec_<US>mult_<mode>): Widening multiply intermediate step
20 for vectorizing without -mvectorize-with-neon-quad.
21 * config/arm/predicates.md (vect_par_constant_high): Check for
22 high-half lanes of a vector.
23 (vect_par_constant_low): Check for low-half lanes of a vector.
24
25 2010-08-25 Tejas Belagod <tejas.belagod@arm.com>
26 * lib/target-supports.exp (check_effective_target_vect_unpack):
27 Set vect_unpack supported flag to true for neon.
28
29 2010-09-07 Andrew Stubbs <ams@codesourcery.com>
30
31 Backport from gcc-patches:
32
33=== modified file 'gcc/config/arm/arm.md'
34--- old/gcc/config/arm/arm.md 2010-09-01 13:29:58 +0000
35+++ new/gcc/config/arm/arm.md 2010-09-09 14:11:34 +0000
36@@ -868,6 +868,9 @@
37 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
38 (define_code_attr optab [(ltu "ltu") (geu "geu")])
39
40+;; Assembler mnemonics for signedness of widening operations.
41+(define_code_attr US [(sign_extend "s") (zero_extend "u")])
42+
43 (define_insn "*addsi3_carryin_<optab>"
44 [(set (match_operand:SI 0 "s_register_operand" "=r")
45 (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
46
47=== modified file 'gcc/config/arm/neon.md'
48--- old/gcc/config/arm/neon.md 2010-08-23 14:29:45 +0000
49+++ new/gcc/config/arm/neon.md 2010-09-09 14:11:34 +0000
50@@ -235,6 +235,9 @@
51 ;; Modes with 32-bit elements only.
52 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
53
54+;; Modes with 8-bit, 16-bit and 32-bit elements.
55+(define_mode_iterator VU [V16QI V8HI V4SI])
56+
57 ;; (Opposite) mode to convert to/from for above conversions.
58 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
59 (V4SI "V4SF") (V4SF "V4SI")])
60@@ -388,6 +391,9 @@
61 ;; Same, without unsigned variants (for use with *SFmode pattern).
62 (define_code_iterator vqhs_ops [plus smin smax])
63
64+;; A list of widening operators
65+(define_code_iterator SE [sign_extend zero_extend])
66+
67 ;; Assembler mnemonics for above codes.
68 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
69 (umin "vmin") (umax "vmax")])
70@@ -443,6 +449,12 @@
71 (V2SF "2") (V4SF "4")
72 (DI "1") (V2DI "2")])
73
74+;; Same as V_widen, but lower-case.
75+(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
76+
77+;; Widen. Result is half the number of elements, but widened to double-width.
78+(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
79+
80 (define_insn "*neon_mov<mode>"
81 [(set (match_operand:VD 0 "nonimmediate_operand"
82 "=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
83@@ -5540,3 +5552,205 @@
84 emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2]));
85 DONE;
86 })
87+
88+(define_insn "neon_vec_unpack<US>_lo_<mode>"
89+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
90+ (SE:<V_unpack> (vec_select:<V_HALF>
91+ (match_operand:VU 1 "register_operand" "w")
92+ (match_operand:VU 2 "vect_par_constant_low" ""))))]
93+ "TARGET_NEON"
94+ "vmovl.<US><V_sz_elem> %q0, %e1"
95+ [(set_attr "neon_type" "neon_shift_1")]
96+)
97+
98+(define_insn "neon_vec_unpack<US>_hi_<mode>"
99+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
100+ (SE:<V_unpack> (vec_select:<V_HALF>
101+ (match_operand:VU 1 "register_operand" "w")
102+ (match_operand:VU 2 "vect_par_constant_high" ""))))]
103+ "TARGET_NEON"
104+ "vmovl.<US><V_sz_elem> %q0, %f1"
105+ [(set_attr "neon_type" "neon_shift_1")]
106+)
107+
108+(define_expand "vec_unpack<US>_hi_<mode>"
109+ [(match_operand:<V_unpack> 0 "register_operand" "")
110+ (SE:<V_unpack> (match_operand:VU 1 "register_operand"))]
111+ "TARGET_NEON"
112+ {
113+ rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
114+ rtx t1;
115+ int i;
116+ for (i = 0; i < (<V_mode_nunits>/2); i++)
117+ RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
118+
119+ t1 = gen_rtx_PARALLEL (<MODE>mode, v);
120+ emit_insn (gen_neon_vec_unpack<US>_hi_<mode> (operands[0],
121+ operands[1],
122+ t1));
123+ DONE;
124+ }
125+)
126+
127+(define_expand "vec_unpack<US>_lo_<mode>"
128+ [(match_operand:<V_unpack> 0 "register_operand" "")
129+ (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))]
130+ "TARGET_NEON"
131+ {
132+ rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
133+ rtx t1;
134+ int i;
135+ for (i = 0; i < (<V_mode_nunits>/2) ; i++)
136+ RTVEC_ELT (v, i) = GEN_INT (i);
137+ t1 = gen_rtx_PARALLEL (<MODE>mode, v);
138+ emit_insn (gen_neon_vec_unpack<US>_lo_<mode> (operands[0],
139+ operands[1],
140+ t1));
141+ DONE;
142+ }
143+)
144+
145+(define_insn "neon_vec_<US>mult_lo_<mode>"
146+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
147+ (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
148+ (match_operand:VU 1 "register_operand" "w")
149+ (match_operand:VU 2 "vect_par_constant_low" "")))
150+ (SE:<V_unpack> (vec_select:<V_HALF>
151+ (match_operand:VU 3 "register_operand" "w")
152+ (match_dup 2)))))]
153+ "TARGET_NEON"
154+ "vmull.<US><V_sz_elem> %q0, %e1, %e3"
155+ [(set_attr "neon_type" "neon_shift_1")]
156+)
157+
158+(define_expand "vec_widen_<US>mult_lo_<mode>"
159+ [(match_operand:<V_unpack> 0 "register_operand" "")
160+ (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
161+ (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
162+ "TARGET_NEON"
163+ {
164+ rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
165+ rtx t1;
166+ int i;
167+ for (i = 0; i < (<V_mode_nunits>/2) ; i++)
168+ RTVEC_ELT (v, i) = GEN_INT (i);
169+ t1 = gen_rtx_PARALLEL (<MODE>mode, v);
170+
171+ emit_insn (gen_neon_vec_<US>mult_lo_<mode> (operands[0],
172+ operands[1],
173+ t1,
174+ operands[2]));
175+ DONE;
176+ }
177+)
178+
179+(define_insn "neon_vec_<US>mult_hi_<mode>"
180+ [(set (match_operand:<V_unpack> 0 "register_operand" "=w")
181+ (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF>
182+ (match_operand:VU 1 "register_operand" "w")
183+ (match_operand:VU 2 "vect_par_constant_high" "")))
184+ (SE:<V_unpack> (vec_select:<V_HALF>
185+ (match_operand:VU 3 "register_operand" "w")
186+ (match_dup 2)))))]
187+ "TARGET_NEON"
188+ "vmull.<US><V_sz_elem> %q0, %f1, %f3"
189+ [(set_attr "neon_type" "neon_shift_1")]
190+)
191+
192+(define_expand "vec_widen_<US>mult_hi_<mode>"
193+ [(match_operand:<V_unpack> 0 "register_operand" "")
194+ (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
195+ (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))]
196+ "TARGET_NEON"
197+ {
198+ rtvec v = rtvec_alloc (<V_mode_nunits>/2) ;
199+ rtx t1;
200+ int i;
201+ for (i = 0; i < (<V_mode_nunits>/2) ; i++)
202+ RTVEC_ELT (v, i) = GEN_INT (<V_mode_nunits>/2 + i);
203+ t1 = gen_rtx_PARALLEL (<MODE>mode, v);
204+
205+ emit_insn (gen_neon_vec_<US>mult_hi_<mode> (operands[0],
206+ operands[1],
207+ t1,
208+ operands[2]));
209+ DONE;
210+
211+ }
212+)
213+
214+;; Vectorize for non-neon-quad case
215+(define_insn "neon_unpack<US>_<mode>"
216+ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
217+ (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))]
218+ "TARGET_NEON"
219+ "vmovl.<US><V_sz_elem> %q0, %1"
220+ [(set_attr "neon_type" "neon_shift_1")]
221+)
222+
223+(define_expand "vec_unpack<US>_lo_<mode>"
224+ [(match_operand:<V_double_width> 0 "register_operand" "")
225+ (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
226+ "TARGET_NEON"
227+{
228+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
229+ emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
230+ emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
231+
232+ DONE;
233+}
234+)
235+
236+(define_expand "vec_unpack<US>_hi_<mode>"
237+ [(match_operand:<V_double_width> 0 "register_operand" "")
238+ (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))]
239+ "TARGET_NEON"
240+{
241+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
242+ emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1]));
243+ emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
244+
245+ DONE;
246+}
247+)
248+
249+(define_insn "neon_vec_<US>mult_<mode>"
250+ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
251+ (mult:<V_widen> (SE:<V_widen>
252+ (match_operand:VDI 1 "register_operand" "w"))
253+ (SE:<V_widen>
254+ (match_operand:VDI 2 "register_operand" "w"))))]
255+ "TARGET_NEON"
256+ "vmull.<US><V_sz_elem> %q0, %1, %2"
257+ [(set_attr "neon_type" "neon_shift_1")]
258+)
259+
260+(define_expand "vec_widen_<US>mult_hi_<mode>"
261+ [(match_operand:<V_double_width> 0 "register_operand" "")
262+ (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
263+ (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
264+ "TARGET_NEON"
265+ {
266+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
267+ emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
268+ emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
269+
270+ DONE;
271+
272+ }
273+)
274+
275+(define_expand "vec_widen_<US>mult_lo_<mode>"
276+ [(match_operand:<V_double_width> 0 "register_operand" "")
277+ (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
278+ (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))]
279+ "TARGET_NEON"
280+ {
281+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
282+ emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2]));
283+ emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
284+
285+ DONE;
286+
287+ }
288+)
289
290=== modified file 'gcc/config/arm/predicates.md'
291--- old/gcc/config/arm/predicates.md 2010-08-31 10:00:27 +0000
292+++ new/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000
293@@ -573,3 +573,61 @@
294 (and (match_test "TARGET_32BIT")
295 (match_operand 0 "arm_di_operand"))))
296
297+;; Predicates for parallel expanders based on mode.
298+(define_special_predicate "vect_par_constant_high"
299+ (match_code "parallel")
300+{
301+ HOST_WIDE_INT count = XVECLEN (op, 0);
302+ int i;
303+ int base = GET_MODE_NUNITS (mode);
304+
305+ if ((count < 1)
306+ || (count != base/2))
307+ return false;
308+
309+ if (!VECTOR_MODE_P (mode))
310+ return false;
311+
312+ for (i = 0; i < count; i++)
313+ {
314+ rtx elt = XVECEXP (op, 0, i);
315+ int val;
316+
317+ if (GET_CODE (elt) != CONST_INT)
318+ return false;
319+
320+ val = INTVAL (elt);
321+ if (val != (base/2) + i)
322+ return false;
323+ }
324+ return true;
325+})
326+
327+(define_special_predicate "vect_par_constant_low"
328+ (match_code "parallel")
329+{
330+ HOST_WIDE_INT count = XVECLEN (op, 0);
331+ int i;
332+ int base = GET_MODE_NUNITS (mode);
333+
334+ if ((count < 1)
335+ || (count != base/2))
336+ return false;
337+
338+ if (!VECTOR_MODE_P (mode))
339+ return false;
340+
341+ for (i = 0; i < count; i++)
342+ {
343+ rtx elt = XVECEXP (op, 0, i);
344+ int val;
345+
346+ if (GET_CODE (elt) != CONST_INT)
347+ return false;
348+
349+ val = INTVAL (elt);
350+ if (val != i)
351+ return false;
352+ }
353+ return true;
354+})
355
356=== modified file 'gcc/testsuite/lib/target-supports.exp'
357--- old/gcc/testsuite/lib/target-supports.exp 2010-08-24 13:00:03 +0000
358+++ new/gcc/testsuite/lib/target-supports.exp 2010-09-09 14:11:34 +0000
359@@ -2519,7 +2519,8 @@
360 if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
361 || [istarget i?86-*-*]
362 || [istarget x86_64-*-*]
363- || [istarget spu-*-*] } {
364+ || [istarget spu-*-*]
365+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
366 set et_vect_unpack_saved 1
367 }
368 }
369
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