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Diffstat (limited to 'recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch')
| -rw-r--r-- | recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch new file mode 100644 index 0000000000..b63c9b35e7 --- /dev/null +++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | 2010-11-03 Nathan Froyd <froydnj@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10002 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.c (arm_legitimate_index_p): Split | ||
| 7 | VALID_NEON_QREG_MODE and VALID_NEON_DREG_MODE cases. Permit | ||
| 8 | slightly larger constants in the latter case. | ||
| 9 | (thumb2_legitimate_index_p): Likewise. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.c' | ||
| 12 | --- old/gcc/config/arm/arm.c 2010-11-04 12:49:37 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.c 2010-11-11 11:00:53 +0000 | ||
| 14 | @@ -5611,13 +5611,25 @@ | ||
| 15 | && INTVAL (index) > -1024 | ||
| 16 | && (INTVAL (index) & 3) == 0); | ||
| 17 | |||
| 18 | - if (TARGET_NEON | ||
| 19 | - && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | ||
| 20 | + /* For quad modes, we restrict the constant offset to be slightly less | ||
| 21 | + than what the instruction format permits. We do this because for | ||
| 22 | + quad mode moves, we will actually decompose them into two separate | ||
| 23 | + double-mode reads or writes. INDEX must therefore be a valid | ||
| 24 | + (double-mode) offset and so should INDEX+8. */ | ||
| 25 | + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | ||
| 26 | return (code == CONST_INT | ||
| 27 | && INTVAL (index) < 1016 | ||
| 28 | && INTVAL (index) > -1024 | ||
| 29 | && (INTVAL (index) & 3) == 0); | ||
| 30 | |||
| 31 | + /* We have no such constraint on double mode offsets, so we permit the | ||
| 32 | + full range of the instruction format. */ | ||
| 33 | + if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | ||
| 34 | + return (code == CONST_INT | ||
| 35 | + && INTVAL (index) < 1024 | ||
| 36 | + && INTVAL (index) > -1024 | ||
| 37 | + && (INTVAL (index) & 3) == 0); | ||
| 38 | + | ||
| 39 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | ||
| 40 | return (code == CONST_INT | ||
| 41 | && INTVAL (index) < 1024 | ||
| 42 | @@ -5731,13 +5743,25 @@ | ||
| 43 | && (INTVAL (index) & 3) == 0); | ||
| 44 | } | ||
| 45 | |||
| 46 | - if (TARGET_NEON | ||
| 47 | - && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | ||
| 48 | + /* For quad modes, we restrict the constant offset to be slightly less | ||
| 49 | + than what the instruction format permits. We do this because for | ||
| 50 | + quad mode moves, we will actually decompose them into two separate | ||
| 51 | + double-mode reads or writes. INDEX must therefore be a valid | ||
| 52 | + (double-mode) offset and so should INDEX+8. */ | ||
| 53 | + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | ||
| 54 | return (code == CONST_INT | ||
| 55 | && INTVAL (index) < 1016 | ||
| 56 | && INTVAL (index) > -1024 | ||
| 57 | && (INTVAL (index) & 3) == 0); | ||
| 58 | |||
| 59 | + /* We have no such constraint on double mode offsets, so we permit the | ||
| 60 | + full range of the instruction format. */ | ||
| 61 | + if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | ||
| 62 | + return (code == CONST_INT | ||
| 63 | + && INTVAL (index) < 1024 | ||
| 64 | + && INTVAL (index) > -1024 | ||
| 65 | + && (INTVAL (index) & 3) == 0); | ||
| 66 | + | ||
| 67 | if (arm_address_register_rtx_p (index, strict_p) | ||
| 68 | && (GET_MODE_SIZE (mode) <= 4)) | ||
| 69 | return 1; | ||
| 70 | |||