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diff --git a/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch
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+++ b/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch
@@ -0,0 +1,1500 @@
12010-11-16 Chung-Lin Tang <cltang@codesourcery.com>
2
3 2010-07-21 Richard Henderson <rth@redhat.com>
4
5 gcc/
6 * config/i386/i386.c (setup_incoming_varargs_64): Emit a simple
7 comparison for avoiding xmm register saves. Emit the xmm register
8 saves explicitly.
9 * config/i386/i386.md (UNSPEC_SSE_PROLOGUE_SAVE): Remove.
10 (UNSPEC_SSE_PROLOGUE_SAVE_LOW): Remove.
11 (sse_prologue_save, sse_prologue_save_insn1, sse_prologue_save_insn):
12 Remove patterns and the associated splitters.
13
14 2010-07-22 Richard Henderson <rth@redhat.com>
15
16 gcc/
17 PR target/45027
18 * config/i386/i386.c (setup_incoming_varargs_64): Force the use
19 of V4SFmode for the SSE saves; increase stack alignment if needed.
20
212010-11-16 Chung-Lin Tang <cltang@codesourcery.com>
22
23 Re-merge, backport from mainline:
24
25 2010-07-15 Bernd Schmidt <bernds@codesourcery.com>
26
27 gcc/
28 * postreload.c (last_label_ruid, first_index_reg, last_index_reg):
29 New static variables.
30 (reload_combine_recognize_pattern): New static function, broken out
31 of reload_combine.
32 (reload_combine): Use it. Only initialize first_index_reg and
33 last_index_reg once.
34
35 2010-07-17 Bernd Schmidt <bernds@codesourcery.com>
36
37 PR target/42235
38 gcc/
39 * postreload.c (reload_cse_move2add): Return bool, true if anything.
40 changed. All callers changed.
41 (move2add_use_add2_insn): Likewise.
42 (move2add_use_add3_insn): Likewise.
43 (reload_cse_regs): If reload_cse_move2add changed anything, rerun
44 reload_combine.
45 (RELOAD_COMBINE_MAX_USES): Bump to 16.
46 (last_jump_ruid): New static variable.
47 (struct reg_use): New members CONTAINING_MEM and RUID.
48 (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID.
49 (reload_combine_split_one_ruid, reload_combine_split_ruids,
50 reload_combine_purge_insn_uses, reload_combine_closest_single_use
51 reload_combine_purge_reg_uses_after_ruid,
52 reload_combine_recognize_const_pattern): New static functions.
53 (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH
54 is true for our reg and that we have available index regs.
55 (reload_combine_note_use): New args RUID and CONTAINING_MEM. All
56 callers changed. Use them to initialize fields in struct reg_use.
57 (reload_combine): Initialize last_jump_ruid. Be careful when to
58 take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields.
59 Call reload_combine_recognize_const_pattern.
60 (reload_combine_note_store): Update REAL_STORE_RUID field.
61
62 gcc/testsuite/
63 * gcc.target/arm/pr42235.c: New test.
64
65 2010-07-19 Bernd Schmidt <bernds@codesourcery.com>
66
67 gcc/
68 * postreload.c (reload_combine_closest_single_use): Ignore the
69 number of uses for DEBUG_INSNs.
70 (fixup_debug_insns): New static function.
71 (reload_combine_recognize_const_pattern): Use it. Don't let the
72 main loop be affected by DEBUG_INSNs.
73 Really disallow moving adds past a jump insn.
74 (reload_combine_recognize_pattern): Don't update use_ruid here.
75 (reload_combine_note_use): Do it here.
76 (reload_combine): Use control_flow_insn_p rather than JUMP_P.
77
78 2010-07-20 Bernd Schmidt <bernds@codesourcery.com>
79
80 gcc/
81 * postreload.c (fixup_debug_insns): Remove arg REGNO. New args
82 FROM and TO. All callers changed. Don't look for tracked uses,
83 just scan the RTL for DEBUG_INSNs and substitute.
84 (reload_combine_recognize_pattern): Call fixup_debug_insns.
85 (reload_combine): Ignore DEBUG_INSNs.
86
87 2010-07-22 Bernd Schmidt <bernds@codesourcery.com>
88
89 PR bootstrap/44970
90 PR middle-end/45009
91 gcc/
92 * postreload.c: Include "target.h".
93 (reload_combine_closest_single_use): Don't take DEBUG_INSNs
94 into account.
95 (fixup_debug_insns): Don't copy the rtx.
96 (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses.
97 Don't copy when replacing. Call fixup_debug_insns in the case where
98 we merged one add with another.
99 (reload_combine_recognize_pattern): Fail if there aren't any uses.
100 Try harder to determine whether we're picking a valid index register.
101 Don't set store_ruid for an insn we're going to scan in the
102 next iteration.
103 (reload_combine): Remove unused code.
104 (reload_combine_note_use): When updating use information for
105 an old insn, ignore a use that occurs after store_ruid.
106 * Makefile.in (postreload.o): Update dependencies.
107
108 2010-07-27 Bernd Schmidt <bernds@codesourcery.com>
109
110 gcc/
111 * postreload.c (reload_combine_recognize_const_pattern): Move test
112 for limiting the insn movement to the right scope.
113
114 2010-07-27 Bernd Schmidt <bernds@codesourcery.com>
115
116 gcc/
117 * postreload.c (try_replace_in_use): New static function.
118 (reload_combine_recognize_const_pattern): Use it here. Allow
119 substituting into a final add insn, and substituting into a memory
120 reference in an insn that sets the reg.
121
122=== modified file 'gcc/Makefile.in'
123--- old/gcc/Makefile.in 2010-11-11 11:34:59 +0000
124+++ new/gcc/Makefile.in 2010-11-16 18:05:53 +0000
125@@ -3157,7 +3157,7 @@
126 $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \
127 hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \
128 $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \
129- $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
130+ $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H)
131 postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
132 $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \
133 $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
134
135=== modified file 'gcc/config/i386/i386.c'
136--- old/gcc/config/i386/i386.c 2010-09-30 20:24:54 +0000
137+++ new/gcc/config/i386/i386.c 2010-11-16 18:05:53 +0000
138@@ -6737,12 +6737,8 @@
139 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
140 {
141 rtx save_area, mem;
142- rtx label;
143- rtx label_ref;
144- rtx tmp_reg;
145- rtx nsse_reg;
146 alias_set_type set;
147- int i;
148+ int i, max;
149
150 /* GPR size of varargs save area. */
151 if (cfun->va_list_gpr_size)
152@@ -6752,7 +6748,7 @@
153
154 /* FPR size of varargs save area. We don't need it if we don't pass
155 anything in SSE registers. */
156- if (cum->sse_nregs && cfun->va_list_fpr_size)
157+ if (TARGET_SSE && cfun->va_list_fpr_size)
158 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
159 else
160 ix86_varargs_fpr_size = 0;
161@@ -6763,10 +6759,11 @@
162 save_area = frame_pointer_rtx;
163 set = get_varargs_alias_set ();
164
165- for (i = cum->regno;
166- i < X86_64_REGPARM_MAX
167- && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
168- i++)
169+ max = cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
170+ if (max > X86_64_REGPARM_MAX)
171+ max = X86_64_REGPARM_MAX;
172+
173+ for (i = cum->regno; i < max; i++)
174 {
175 mem = gen_rtx_MEM (Pmode,
176 plus_constant (save_area, i * UNITS_PER_WORD));
177@@ -6778,62 +6775,42 @@
178
179 if (ix86_varargs_fpr_size)
180 {
181- /* Stack must be aligned to 16byte for FP register save area. */
182- if (crtl->stack_alignment_needed < 128)
183- crtl->stack_alignment_needed = 128;
184+ enum machine_mode smode;
185+ rtx label, test;
186
187 /* Now emit code to save SSE registers. The AX parameter contains number
188- of SSE parameter registers used to call this function. We use
189- sse_prologue_save insn template that produces computed jump across
190- SSE saves. We need some preparation work to get this working. */
191+ of SSE parameter registers used to call this function, though all we
192+ actually check here is the zero/non-zero status. */
193
194 label = gen_label_rtx ();
195- label_ref = gen_rtx_LABEL_REF (Pmode, label);
196-
197- /* Compute address to jump to :
198- label - eax*4 + nnamed_sse_arguments*4 Or
199- label - eax*5 + nnamed_sse_arguments*5 for AVX. */
200- tmp_reg = gen_reg_rtx (Pmode);
201- nsse_reg = gen_reg_rtx (Pmode);
202- emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
203- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
204- gen_rtx_MULT (Pmode, nsse_reg,
205- GEN_INT (4))));
206-
207- /* vmovaps is one byte longer than movaps. */
208- if (TARGET_AVX)
209- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
210- gen_rtx_PLUS (Pmode, tmp_reg,
211- nsse_reg)));
212-
213- if (cum->sse_regno)
214- emit_move_insn
215- (nsse_reg,
216- gen_rtx_CONST (DImode,
217- gen_rtx_PLUS (DImode,
218- label_ref,
219- GEN_INT (cum->sse_regno
220- * (TARGET_AVX ? 5 : 4)))));
221- else
222- emit_move_insn (nsse_reg, label_ref);
223- emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
224-
225- /* Compute address of memory block we save into. We always use pointer
226- pointing 127 bytes after first byte to store - this is needed to keep
227- instruction size limited by 4 bytes (5 bytes for AVX) with one
228- byte displacement. */
229- tmp_reg = gen_reg_rtx (Pmode);
230- emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
231- plus_constant (save_area,
232- ix86_varargs_gpr_size + 127)));
233- mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
234- MEM_NOTRAP_P (mem) = 1;
235- set_mem_alias_set (mem, set);
236- set_mem_align (mem, BITS_PER_WORD);
237-
238- /* And finally do the dirty job! */
239- emit_insn (gen_sse_prologue_save (mem, nsse_reg,
240- GEN_INT (cum->sse_regno), label));
241+ test = gen_rtx_EQ (VOIDmode, gen_rtx_REG (QImode, AX_REG), const0_rtx);
242+ emit_jump_insn (gen_cbranchqi4 (test, XEXP (test, 0), XEXP (test, 1),
243+ label));
244+
245+ /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
246+ we used movdqa (i.e. TImode) instead? Perhaps even better would
247+ be if we could determine the real mode of the data, via a hook
248+ into pass_stdarg. Ignore all that for now. */
249+ smode = V4SFmode;
250+ if (crtl->stack_alignment_needed < GET_MODE_ALIGNMENT (smode))
251+ crtl->stack_alignment_needed = GET_MODE_ALIGNMENT (smode);
252+
253+ max = cum->sse_regno + cfun->va_list_fpr_size / 16;
254+ if (max > X86_64_SSE_REGPARM_MAX)
255+ max = X86_64_SSE_REGPARM_MAX;
256+
257+ for (i = cum->sse_regno; i < max; ++i)
258+ {
259+ mem = plus_constant (save_area, i * 16 + ix86_varargs_gpr_size);
260+ mem = gen_rtx_MEM (smode, mem);
261+ MEM_NOTRAP_P (mem) = 1;
262+ set_mem_alias_set (mem, set);
263+ set_mem_align (mem, GET_MODE_ALIGNMENT (smode));
264+
265+ emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i)));
266+ }
267+
268+ emit_label (label);
269 }
270 }
271
272
273=== modified file 'gcc/config/i386/i386.md'
274--- old/gcc/config/i386/i386.md 2010-10-22 04:56:41 +0000
275+++ new/gcc/config/i386/i386.md 2010-11-27 15:24:12 +0000
276@@ -80,7 +80,6 @@
277 ; Prologue support
278 (UNSPEC_STACK_ALLOC 11)
279 (UNSPEC_SET_GOT 12)
280- (UNSPEC_SSE_PROLOGUE_SAVE 13)
281 (UNSPEC_REG_SAVE 14)
282 (UNSPEC_DEF_CFA 15)
283 (UNSPEC_SET_RIP 16)
284@@ -20252,74 +20251,6 @@
285 { return ASM_SHORT "0x0b0f"; }
286 [(set_attr "length" "2")])
287
288-(define_expand "sse_prologue_save"
289- [(parallel [(set (match_operand:BLK 0 "" "")
290- (unspec:BLK [(reg:DI XMM0_REG)
291- (reg:DI XMM1_REG)
292- (reg:DI XMM2_REG)
293- (reg:DI XMM3_REG)
294- (reg:DI XMM4_REG)
295- (reg:DI XMM5_REG)
296- (reg:DI XMM6_REG)
297- (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
298- (use (match_operand:DI 1 "register_operand" ""))
299- (use (match_operand:DI 2 "immediate_operand" ""))
300- (use (label_ref:DI (match_operand 3 "" "")))])]
301- "TARGET_64BIT"
302- "")
303-
304-(define_insn "*sse_prologue_save_insn"
305- [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
306- (match_operand:DI 4 "const_int_operand" "n")))
307- (unspec:BLK [(reg:DI XMM0_REG)
308- (reg:DI XMM1_REG)
309- (reg:DI XMM2_REG)
310- (reg:DI XMM3_REG)
311- (reg:DI XMM4_REG)
312- (reg:DI XMM5_REG)
313- (reg:DI XMM6_REG)
314- (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
315- (use (match_operand:DI 1 "register_operand" "r"))
316- (use (match_operand:DI 2 "const_int_operand" "i"))
317- (use (label_ref:DI (match_operand 3 "" "X")))]
318- "TARGET_64BIT
319- && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
320- && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
321-{
322- int i;
323- operands[0] = gen_rtx_MEM (Pmode,
324- gen_rtx_PLUS (Pmode, operands[0], operands[4]));
325- /* VEX instruction with a REX prefix will #UD. */
326- if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS)
327- gcc_unreachable ();
328-
329- output_asm_insn ("jmp\t%A1", operands);
330- for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
331- {
332- operands[4] = adjust_address (operands[0], DImode, i*16);
333- operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
334- PUT_MODE (operands[4], TImode);
335- if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
336- output_asm_insn ("rex", operands);
337- output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands);
338- }
339- (*targetm.asm_out.internal_label) (asm_out_file, "L",
340- CODE_LABEL_NUMBER (operands[3]));
341- return "";
342-}
343- [(set_attr "type" "other")
344- (set_attr "length_immediate" "0")
345- (set_attr "length_address" "0")
346- (set (attr "length")
347- (if_then_else
348- (eq (symbol_ref "TARGET_AVX") (const_int 0))
349- (const_string "34")
350- (const_string "42")))
351- (set_attr "memory" "store")
352- (set_attr "modrm" "0")
353- (set_attr "prefix" "maybe_vex")
354- (set_attr "mode" "DI")])
355-
356 (define_expand "prefetch"
357 [(prefetch (match_operand 0 "address_operand" "")
358 (match_operand:SI 1 "const_int_operand" "")
359
360=== modified file 'gcc/postreload.c'
361--- old/gcc/postreload.c 2010-11-08 22:08:43 +0000
362+++ new/gcc/postreload.c 2010-11-16 18:05:53 +0000
363@@ -44,6 +44,7 @@
364 #include "toplev.h"
365 #include "except.h"
366 #include "tree.h"
367+#include "target.h"
368 #include "timevar.h"
369 #include "tree-pass.h"
370 #include "df.h"
371@@ -56,10 +57,10 @@
372 static int reload_cse_simplify_operands (rtx, rtx);
373
374 static void reload_combine (void);
375-static void reload_combine_note_use (rtx *, rtx);
376+static void reload_combine_note_use (rtx *, rtx, int, rtx);
377 static void reload_combine_note_store (rtx, const_rtx, void *);
378
379-static void reload_cse_move2add (rtx);
380+static bool reload_cse_move2add (rtx);
381 static void move2add_note_store (rtx, const_rtx, void *);
382
383 /* Call cse / combine like post-reload optimization phases.
384@@ -67,11 +68,16 @@
385 void
386 reload_cse_regs (rtx first ATTRIBUTE_UNUSED)
387 {
388+ bool moves_converted;
389 reload_cse_regs_1 (first);
390 reload_combine ();
391- reload_cse_move2add (first);
392+ moves_converted = reload_cse_move2add (first);
393 if (flag_expensive_optimizations)
394- reload_cse_regs_1 (first);
395+ {
396+ if (moves_converted)
397+ reload_combine ();
398+ reload_cse_regs_1 (first);
399+ }
400 }
401
402 /* See whether a single set SET is a noop. */
403@@ -660,30 +666,43 @@
404
405 /* The maximum number of uses of a register we can keep track of to
406 replace them with reg+reg addressing. */
407-#define RELOAD_COMBINE_MAX_USES 6
408+#define RELOAD_COMBINE_MAX_USES 16
409
410-/* INSN is the insn where a register has been used, and USEP points to the
411- location of the register within the rtl. */
412-struct reg_use { rtx insn, *usep; };
413+/* Describes a recorded use of a register. */
414+struct reg_use
415+{
416+ /* The insn where a register has been used. */
417+ rtx insn;
418+ /* Points to the memory reference enclosing the use, if any, NULL_RTX
419+ otherwise. */
420+ rtx containing_mem;
421+ /* Location of the register withing INSN. */
422+ rtx *usep;
423+ /* The reverse uid of the insn. */
424+ int ruid;
425+};
426
427 /* If the register is used in some unknown fashion, USE_INDEX is negative.
428 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
429- indicates where it becomes live again.
430+ indicates where it is first set or clobbered.
431 Otherwise, USE_INDEX is the index of the last encountered use of the
432- register (which is first among these we have seen since we scan backwards),
433- OFFSET contains the constant offset that is added to the register in
434- all encountered uses, and USE_RUID indicates the first encountered, i.e.
435- last, of these uses.
436+ register (which is first among these we have seen since we scan backwards).
437+ USE_RUID indicates the first encountered, i.e. last, of these uses.
438+ If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
439+ with a constant offset; OFFSET contains this constant in that case.
440 STORE_RUID is always meaningful if we only want to use a value in a
441 register in a different place: it denotes the next insn in the insn
442- stream (i.e. the last encountered) that sets or clobbers the register. */
443+ stream (i.e. the last encountered) that sets or clobbers the register.
444+ REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
445 static struct
446 {
447 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
448+ rtx offset;
449 int use_index;
450- rtx offset;
451 int store_ruid;
452+ int real_store_ruid;
453 int use_ruid;
454+ bool all_offsets_match;
455 } reg_state[FIRST_PSEUDO_REGISTER];
456
457 /* Reverse linear uid. This is increased in reload_combine while scanning
458@@ -691,42 +710,548 @@
459 and the store_ruid / use_ruid fields in reg_state. */
460 static int reload_combine_ruid;
461
462+/* The RUID of the last label we encountered in reload_combine. */
463+static int last_label_ruid;
464+
465+/* The RUID of the last jump we encountered in reload_combine. */
466+static int last_jump_ruid;
467+
468+/* The register numbers of the first and last index register. A value of
469+ -1 in LAST_INDEX_REG indicates that we've previously computed these
470+ values and found no suitable index registers. */
471+static int first_index_reg = -1;
472+static int last_index_reg;
473+
474 #define LABEL_LIVE(LABEL) \
475 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
476
477+/* Subroutine of reload_combine_split_ruids, called to fix up a single
478+ ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
479+
480+static inline void
481+reload_combine_split_one_ruid (int *pruid, int split_ruid)
482+{
483+ if (*pruid > split_ruid)
484+ (*pruid)++;
485+}
486+
487+/* Called when we insert a new insn in a position we've already passed in
488+ the scan. Examine all our state, increasing all ruids that are higher
489+ than SPLIT_RUID by one in order to make room for a new insn. */
490+
491+static void
492+reload_combine_split_ruids (int split_ruid)
493+{
494+ unsigned i;
495+
496+ reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
497+ reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
498+ reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
499+
500+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
501+ {
502+ int j, idx = reg_state[i].use_index;
503+ reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
504+ reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
505+ reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
506+ split_ruid);
507+ if (idx < 0)
508+ continue;
509+ for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
510+ {
511+ reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
512+ split_ruid);
513+ }
514+ }
515+}
516+
517+/* Called when we are about to rescan a previously encountered insn with
518+ reload_combine_note_use after modifying some part of it. This clears all
519+ information about uses in that particular insn. */
520+
521+static void
522+reload_combine_purge_insn_uses (rtx insn)
523+{
524+ unsigned i;
525+
526+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
527+ {
528+ int j, k, idx = reg_state[i].use_index;
529+ if (idx < 0)
530+ continue;
531+ j = k = RELOAD_COMBINE_MAX_USES;
532+ while (j-- > idx)
533+ {
534+ if (reg_state[i].reg_use[j].insn != insn)
535+ {
536+ k--;
537+ if (k != j)
538+ reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
539+ }
540+ }
541+ reg_state[i].use_index = k;
542+ }
543+}
544+
545+/* Called when we need to forget about all uses of REGNO after an insn
546+ which is identified by RUID. */
547+
548+static void
549+reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
550+{
551+ int j, k, idx = reg_state[regno].use_index;
552+ if (idx < 0)
553+ return;
554+ j = k = RELOAD_COMBINE_MAX_USES;
555+ while (j-- > idx)
556+ {
557+ if (reg_state[regno].reg_use[j].ruid >= ruid)
558+ {
559+ k--;
560+ if (k != j)
561+ reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
562+ }
563+ }
564+ reg_state[regno].use_index = k;
565+}
566+
567+/* Find the use of REGNO with the ruid that is highest among those
568+ lower than RUID_LIMIT, and return it if it is the only use of this
569+ reg in the insn. Return NULL otherwise. */
570+
571+static struct reg_use *
572+reload_combine_closest_single_use (unsigned regno, int ruid_limit)
573+{
574+ int i, best_ruid = 0;
575+ int use_idx = reg_state[regno].use_index;
576+ struct reg_use *retval;
577+
578+ if (use_idx < 0)
579+ return NULL;
580+ retval = NULL;
581+ for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
582+ {
583+ struct reg_use *use = reg_state[regno].reg_use + i;
584+ int this_ruid = use->ruid;
585+ if (this_ruid >= ruid_limit)
586+ continue;
587+ if (this_ruid > best_ruid)
588+ {
589+ best_ruid = this_ruid;
590+ retval = use;
591+ }
592+ else if (this_ruid == best_ruid)
593+ retval = NULL;
594+ }
595+ if (last_label_ruid >= best_ruid)
596+ return NULL;
597+ return retval;
598+}
599+
600+/* After we've moved an add insn, fix up any debug insns that occur
601+ between the old location of the add and the new location. REG is
602+ the destination register of the add insn; REPLACEMENT is the
603+ SET_SRC of the add. FROM and TO specify the range in which we
604+ should make this change on debug insns. */
605+
606+static void
607+fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to)
608+{
609+ rtx insn;
610+ for (insn = from; insn != to; insn = NEXT_INSN (insn))
611+ {
612+ rtx t;
613+
614+ if (!DEBUG_INSN_P (insn))
615+ continue;
616+
617+ t = INSN_VAR_LOCATION_LOC (insn);
618+ t = simplify_replace_rtx (t, reg, replacement);
619+ validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
620+ }
621+}
622+
623+/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
624+ with SRC in the insn described by USE, taking costs into account. Return
625+ true if we made the replacement. */
626+
627+static bool
628+try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
629+{
630+ rtx use_insn = use->insn;
631+ rtx mem = use->containing_mem;
632+ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
633+
634+ if (mem != NULL_RTX)
635+ {
636+ addr_space_t as = MEM_ADDR_SPACE (mem);
637+ rtx oldaddr = XEXP (mem, 0);
638+ rtx newaddr = NULL_RTX;
639+ int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
640+ int new_cost;
641+
642+ newaddr = simplify_replace_rtx (oldaddr, reg, src);
643+ if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
644+ {
645+ XEXP (mem, 0) = newaddr;
646+ new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
647+ XEXP (mem, 0) = oldaddr;
648+ if (new_cost <= old_cost
649+ && validate_change (use_insn,
650+ &XEXP (mem, 0), newaddr, 0))
651+ return true;
652+ }
653+ }
654+ else
655+ {
656+ rtx new_set = single_set (use_insn);
657+ if (new_set
658+ && REG_P (SET_DEST (new_set))
659+ && GET_CODE (SET_SRC (new_set)) == PLUS
660+ && REG_P (XEXP (SET_SRC (new_set), 0))
661+ && CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
662+ {
663+ rtx new_src;
664+ int old_cost = rtx_cost (SET_SRC (new_set), SET, speed);
665+
666+ gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
667+ new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
668+
669+ if (rtx_cost (new_src, SET, speed) <= old_cost
670+ && validate_change (use_insn, &SET_SRC (new_set),
671+ new_src, 0))
672+ return true;
673+ }
674+ }
675+ return false;
676+}
677+
678+/* Called by reload_combine when scanning INSN. This function tries to detect
679+ patterns where a constant is added to a register, and the result is used
680+ in an address.
681+ Return true if no further processing is needed on INSN; false if it wasn't
682+ recognized and should be handled normally. */
683+
684+static bool
685+reload_combine_recognize_const_pattern (rtx insn)
686+{
687+ int from_ruid = reload_combine_ruid;
688+ rtx set, pat, reg, src, addreg;
689+ unsigned int regno;
690+ struct reg_use *use;
691+ bool must_move_add;
692+ rtx add_moved_after_insn = NULL_RTX;
693+ int add_moved_after_ruid = 0;
694+ int clobbered_regno = -1;
695+
696+ set = single_set (insn);
697+ if (set == NULL_RTX)
698+ return false;
699+
700+ reg = SET_DEST (set);
701+ src = SET_SRC (set);
702+ if (!REG_P (reg)
703+ || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1
704+ || GET_MODE (reg) != Pmode
705+ || reg == stack_pointer_rtx)
706+ return false;
707+
708+ regno = REGNO (reg);
709+
710+ /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
711+ uses of REG1 inside an address, or inside another add insn. If
712+ possible and profitable, merge the addition into subsequent
713+ uses. */
714+ if (GET_CODE (src) != PLUS
715+ || !REG_P (XEXP (src, 0))
716+ || !CONSTANT_P (XEXP (src, 1)))
717+ return false;
718+
719+ addreg = XEXP (src, 0);
720+ must_move_add = rtx_equal_p (reg, addreg);
721+
722+ pat = PATTERN (insn);
723+ if (must_move_add && set != pat)
724+ {
725+ /* We have to be careful when moving the add; apart from the
726+ single_set there may also be clobbers. Recognize one special
727+ case, that of one clobber alongside the set (likely a clobber
728+ of the CC register). */
729+ gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
730+ if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
731+ || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
732+ || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
733+ return false;
734+ clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
735+ }
736+
737+ do
738+ {
739+ use = reload_combine_closest_single_use (regno, from_ruid);
740+
741+ if (use)
742+ /* Start the search for the next use from here. */
743+ from_ruid = use->ruid;
744+
745+ if (use && GET_MODE (*use->usep) == Pmode)
746+ {
747+ bool delete_add = false;
748+ rtx use_insn = use->insn;
749+ int use_ruid = use->ruid;
750+
751+ /* Avoid moving the add insn past a jump. */
752+ if (must_move_add && use_ruid <= last_jump_ruid)
753+ break;
754+
755+ /* If the add clobbers another hard reg in parallel, don't move
756+ it past a real set of this hard reg. */
757+ if (must_move_add && clobbered_regno >= 0
758+ && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
759+ break;
760+
761+ gcc_assert (reg_state[regno].store_ruid <= use_ruid);
762+ /* Avoid moving a use of ADDREG past a point where it is stored. */
763+ if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
764+ break;
765+
766+ /* We also must not move the addition past an insn that sets
767+ the same register, unless we can combine two add insns. */
768+ if (must_move_add && reg_state[regno].store_ruid == use_ruid)
769+ {
770+ if (use->containing_mem == NULL_RTX)
771+ delete_add = true;
772+ else
773+ break;
774+ }
775+
776+ if (try_replace_in_use (use, reg, src))
777+ {
778+ reload_combine_purge_insn_uses (use_insn);
779+ reload_combine_note_use (&PATTERN (use_insn), use_insn,
780+ use_ruid, NULL_RTX);
781+
782+ if (delete_add)
783+ {
784+ fixup_debug_insns (reg, src, insn, use_insn);
785+ delete_insn (insn);
786+ return true;
787+ }
788+ if (must_move_add)
789+ {
790+ add_moved_after_insn = use_insn;
791+ add_moved_after_ruid = use_ruid;
792+ }
793+ continue;
794+ }
795+ }
796+ /* If we get here, we couldn't handle this use. */
797+ if (must_move_add)
798+ break;
799+ }
800+ while (use);
801+
802+ if (!must_move_add || add_moved_after_insn == NULL_RTX)
803+ /* Process the add normally. */
804+ return false;
805+
806+ fixup_debug_insns (reg, src, insn, add_moved_after_insn);
807+
808+ reorder_insns (insn, insn, add_moved_after_insn);
809+ reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
810+ reload_combine_split_ruids (add_moved_after_ruid - 1);
811+ reload_combine_note_use (&PATTERN (insn), insn,
812+ add_moved_after_ruid, NULL_RTX);
813+ reg_state[regno].store_ruid = add_moved_after_ruid;
814+
815+ return true;
816+}
817+
818+/* Called by reload_combine when scanning INSN. Try to detect a pattern we
819+ can handle and improve. Return true if no further processing is needed on
820+ INSN; false if it wasn't recognized and should be handled normally. */
821+
822+static bool
823+reload_combine_recognize_pattern (rtx insn)
824+{
825+ rtx set, reg, src;
826+ unsigned int regno;
827+
828+ set = single_set (insn);
829+ if (set == NULL_RTX)
830+ return false;
831+
832+ reg = SET_DEST (set);
833+ src = SET_SRC (set);
834+ if (!REG_P (reg)
835+ || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1)
836+ return false;
837+
838+ regno = REGNO (reg);
839+
840+ /* Look for (set (REGX) (CONST_INT))
841+ (set (REGX) (PLUS (REGX) (REGY)))
842+ ...
843+ ... (MEM (REGX)) ...
844+ and convert it to
845+ (set (REGZ) (CONST_INT))
846+ ...
847+ ... (MEM (PLUS (REGZ) (REGY)))... .
848+
849+ First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
850+ and that we know all uses of REGX before it dies.
851+ Also, explicitly check that REGX != REGY; our life information
852+ does not yet show whether REGY changes in this insn. */
853+
854+ if (GET_CODE (src) == PLUS
855+ && reg_state[regno].all_offsets_match
856+ && last_index_reg != -1
857+ && REG_P (XEXP (src, 1))
858+ && rtx_equal_p (XEXP (src, 0), reg)
859+ && !rtx_equal_p (XEXP (src, 1), reg)
860+ && reg_state[regno].use_index >= 0
861+ && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES
862+ && last_label_ruid < reg_state[regno].use_ruid)
863+ {
864+ rtx base = XEXP (src, 1);
865+ rtx prev = prev_nonnote_insn (insn);
866+ rtx prev_set = prev ? single_set (prev) : NULL_RTX;
867+ rtx index_reg = NULL_RTX;
868+ rtx reg_sum = NULL_RTX;
869+ int i;
870+
871+ /* Now we need to set INDEX_REG to an index register (denoted as
872+ REGZ in the illustration above) and REG_SUM to the expression
873+ register+register that we want to use to substitute uses of REG
874+ (typically in MEMs) with. First check REG and BASE for being
875+ index registers; we can use them even if they are not dead. */
876+ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
877+ || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
878+ REGNO (base)))
879+ {
880+ index_reg = reg;
881+ reg_sum = src;
882+ }
883+ else
884+ {
885+ /* Otherwise, look for a free index register. Since we have
886+ checked above that neither REG nor BASE are index registers,
887+ if we find anything at all, it will be different from these
888+ two registers. */
889+ for (i = first_index_reg; i <= last_index_reg; i++)
890+ {
891+ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
892+ && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
893+ && reg_state[i].store_ruid <= reg_state[regno].use_ruid
894+ && (call_used_regs[i] || df_regs_ever_live_p (i))
895+ && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM)
896+ && !fixed_regs[i] && !global_regs[i]
897+ && hard_regno_nregs[i][GET_MODE (reg)] == 1
898+ && targetm.hard_regno_scratch_ok (i))
899+ {
900+ index_reg = gen_rtx_REG (GET_MODE (reg), i);
901+ reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
902+ break;
903+ }
904+ }
905+ }
906+
907+ /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
908+ (REGY), i.e. BASE, is not clobbered before the last use we'll
909+ create. */
910+ if (reg_sum
911+ && prev_set
912+ && CONST_INT_P (SET_SRC (prev_set))
913+ && rtx_equal_p (SET_DEST (prev_set), reg)
914+ && (reg_state[REGNO (base)].store_ruid
915+ <= reg_state[regno].use_ruid))
916+ {
917+ /* Change destination register and, if necessary, the constant
918+ value in PREV, the constant loading instruction. */
919+ validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
920+ if (reg_state[regno].offset != const0_rtx)
921+ validate_change (prev,
922+ &SET_SRC (prev_set),
923+ GEN_INT (INTVAL (SET_SRC (prev_set))
924+ + INTVAL (reg_state[regno].offset)),
925+ 1);
926+
927+ /* Now for every use of REG that we have recorded, replace REG
928+ with REG_SUM. */
929+ for (i = reg_state[regno].use_index;
930+ i < RELOAD_COMBINE_MAX_USES; i++)
931+ validate_unshare_change (reg_state[regno].reg_use[i].insn,
932+ reg_state[regno].reg_use[i].usep,
933+ /* Each change must have its own
934+ replacement. */
935+ reg_sum, 1);
936+
937+ if (apply_change_group ())
938+ {
939+ struct reg_use *lowest_ruid = NULL;
940+
941+ /* For every new use of REG_SUM, we have to record the use
942+ of BASE therein, i.e. operand 1. */
943+ for (i = reg_state[regno].use_index;
944+ i < RELOAD_COMBINE_MAX_USES; i++)
945+ {
946+ struct reg_use *use = reg_state[regno].reg_use + i;
947+ reload_combine_note_use (&XEXP (*use->usep, 1), use->insn,
948+ use->ruid, use->containing_mem);
949+ if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid)
950+ lowest_ruid = use;
951+ }
952+
953+ fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);
954+
955+ /* Delete the reg-reg addition. */
956+ delete_insn (insn);
957+
958+ if (reg_state[regno].offset != const0_rtx)
959+ /* Previous REG_EQUIV / REG_EQUAL notes for PREV
960+ are now invalid. */
961+ remove_reg_equal_equiv_notes (prev);
962+
963+ reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
964+ return true;
965+ }
966+ }
967+ }
968+ return false;
969+}
970+
971 static void
972 reload_combine (void)
973 {
974- rtx insn, set;
975- int first_index_reg = -1;
976- int last_index_reg = 0;
977+ rtx insn, prev;
978 int i;
979 basic_block bb;
980 unsigned int r;
981- int last_label_ruid;
982 int min_labelno, n_labels;
983 HARD_REG_SET ever_live_at_start, *label_live;
984
985- /* If reg+reg can be used in offsetable memory addresses, the main chunk of
986- reload has already used it where appropriate, so there is no use in
987- trying to generate it now. */
988- if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
989- return;
990-
991 /* To avoid wasting too much time later searching for an index register,
992 determine the minimum and maximum index register numbers. */
993- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
994- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
995- {
996- if (first_index_reg == -1)
997- first_index_reg = r;
998-
999- last_index_reg = r;
1000- }
1001-
1002- /* If no index register is available, we can quit now. */
1003- if (first_index_reg == -1)
1004- return;
1005+ if (INDEX_REG_CLASS == NO_REGS)
1006+ last_index_reg = -1;
1007+ else if (first_index_reg == -1 && last_index_reg == 0)
1008+ {
1009+ for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1010+ if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
1011+ {
1012+ if (first_index_reg == -1)
1013+ first_index_reg = r;
1014+
1015+ last_index_reg = r;
1016+ }
1017+
1018+ /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1019+ to -1 so we'll know to quit early the next time we get here. */
1020+ if (first_index_reg == -1)
1021+ {
1022+ last_index_reg = -1;
1023+ return;
1024+ }
1025+ }
1026
1027 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1028 information is a bit fuzzy immediately after reload, but it's
1029@@ -753,20 +1278,23 @@
1030 }
1031
1032 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1033- last_label_ruid = reload_combine_ruid = 0;
1034+ last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
1035 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
1036 {
1037- reg_state[r].store_ruid = reload_combine_ruid;
1038+ reg_state[r].store_ruid = 0;
1039+ reg_state[r].real_store_ruid = 0;
1040 if (fixed_regs[r])
1041 reg_state[r].use_index = -1;
1042 else
1043 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1044 }
1045
1046- for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
1047+ for (insn = get_last_insn (); insn; insn = prev)
1048 {
1049 rtx note;
1050
1051+ prev = PREV_INSN (insn);
1052+
1053 /* We cannot do our optimization across labels. Invalidating all the use
1054 information we have would be costly, so we just note where the label
1055 is and then later disable any optimization that would cross it. */
1056@@ -777,141 +1305,17 @@
1057 if (! fixed_regs[r])
1058 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
1059
1060- if (! INSN_P (insn))
1061+ if (! NONDEBUG_INSN_P (insn))
1062 continue;
1063
1064 reload_combine_ruid++;
1065
1066- /* Look for (set (REGX) (CONST_INT))
1067- (set (REGX) (PLUS (REGX) (REGY)))
1068- ...
1069- ... (MEM (REGX)) ...
1070- and convert it to
1071- (set (REGZ) (CONST_INT))
1072- ...
1073- ... (MEM (PLUS (REGZ) (REGY)))... .
1074-
1075- First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1076- and that we know all uses of REGX before it dies.
1077- Also, explicitly check that REGX != REGY; our life information
1078- does not yet show whether REGY changes in this insn. */
1079- set = single_set (insn);
1080- if (set != NULL_RTX
1081- && REG_P (SET_DEST (set))
1082- && (hard_regno_nregs[REGNO (SET_DEST (set))]
1083- [GET_MODE (SET_DEST (set))]
1084- == 1)
1085- && GET_CODE (SET_SRC (set)) == PLUS
1086- && REG_P (XEXP (SET_SRC (set), 1))
1087- && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
1088- && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set))
1089- && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
1090- {
1091- rtx reg = SET_DEST (set);
1092- rtx plus = SET_SRC (set);
1093- rtx base = XEXP (plus, 1);
1094- rtx prev = prev_nonnote_nondebug_insn (insn);
1095- rtx prev_set = prev ? single_set (prev) : NULL_RTX;
1096- unsigned int regno = REGNO (reg);
1097- rtx index_reg = NULL_RTX;
1098- rtx reg_sum = NULL_RTX;
1099-
1100- /* Now we need to set INDEX_REG to an index register (denoted as
1101- REGZ in the illustration above) and REG_SUM to the expression
1102- register+register that we want to use to substitute uses of REG
1103- (typically in MEMs) with. First check REG and BASE for being
1104- index registers; we can use them even if they are not dead. */
1105- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
1106- || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1107- REGNO (base)))
1108- {
1109- index_reg = reg;
1110- reg_sum = plus;
1111- }
1112- else
1113- {
1114- /* Otherwise, look for a free index register. Since we have
1115- checked above that neither REG nor BASE are index registers,
1116- if we find anything at all, it will be different from these
1117- two registers. */
1118- for (i = first_index_reg; i <= last_index_reg; i++)
1119- {
1120- if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
1121- i)
1122- && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
1123- && reg_state[i].store_ruid <= reg_state[regno].use_ruid
1124- && hard_regno_nregs[i][GET_MODE (reg)] == 1)
1125- {
1126- index_reg = gen_rtx_REG (GET_MODE (reg), i);
1127- reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
1128- break;
1129- }
1130- }
1131- }
1132-
1133- /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1134- (REGY), i.e. BASE, is not clobbered before the last use we'll
1135- create. */
1136- if (reg_sum
1137- && prev_set
1138- && CONST_INT_P (SET_SRC (prev_set))
1139- && rtx_equal_p (SET_DEST (prev_set), reg)
1140- && reg_state[regno].use_index >= 0
1141- && (reg_state[REGNO (base)].store_ruid
1142- <= reg_state[regno].use_ruid))
1143- {
1144- int i;
1145-
1146- /* Change destination register and, if necessary, the constant
1147- value in PREV, the constant loading instruction. */
1148- validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
1149- if (reg_state[regno].offset != const0_rtx)
1150- validate_change (prev,
1151- &SET_SRC (prev_set),
1152- GEN_INT (INTVAL (SET_SRC (prev_set))
1153- + INTVAL (reg_state[regno].offset)),
1154- 1);
1155-
1156- /* Now for every use of REG that we have recorded, replace REG
1157- with REG_SUM. */
1158- for (i = reg_state[regno].use_index;
1159- i < RELOAD_COMBINE_MAX_USES; i++)
1160- validate_unshare_change (reg_state[regno].reg_use[i].insn,
1161- reg_state[regno].reg_use[i].usep,
1162- /* Each change must have its own
1163- replacement. */
1164- reg_sum, 1);
1165-
1166- if (apply_change_group ())
1167- {
1168- /* For every new use of REG_SUM, we have to record the use
1169- of BASE therein, i.e. operand 1. */
1170- for (i = reg_state[regno].use_index;
1171- i < RELOAD_COMBINE_MAX_USES; i++)
1172- reload_combine_note_use
1173- (&XEXP (*reg_state[regno].reg_use[i].usep, 1),
1174- reg_state[regno].reg_use[i].insn);
1175-
1176- if (reg_state[REGNO (base)].use_ruid
1177- > reg_state[regno].use_ruid)
1178- reg_state[REGNO (base)].use_ruid
1179- = reg_state[regno].use_ruid;
1180-
1181- /* Delete the reg-reg addition. */
1182- delete_insn (insn);
1183-
1184- if (reg_state[regno].offset != const0_rtx)
1185- /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1186- are now invalid. */
1187- remove_reg_equal_equiv_notes (prev);
1188-
1189- reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
1190- reg_state[REGNO (index_reg)].store_ruid
1191- = reload_combine_ruid;
1192- continue;
1193- }
1194- }
1195- }
1196+ if (control_flow_insn_p (insn))
1197+ last_jump_ruid = reload_combine_ruid;
1198+
1199+ if (reload_combine_recognize_const_pattern (insn)
1200+ || reload_combine_recognize_pattern (insn))
1201+ continue;
1202
1203 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
1204
1205@@ -967,7 +1371,8 @@
1206 reg_state[i].use_index = -1;
1207 }
1208
1209- reload_combine_note_use (&PATTERN (insn), insn);
1210+ reload_combine_note_use (&PATTERN (insn), insn,
1211+ reload_combine_ruid, NULL_RTX);
1212 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1213 {
1214 if (REG_NOTE_KIND (note) == REG_INC
1215@@ -976,6 +1381,7 @@
1216 int regno = REGNO (XEXP (note, 0));
1217
1218 reg_state[regno].store_ruid = reload_combine_ruid;
1219+ reg_state[regno].real_store_ruid = reload_combine_ruid;
1220 reg_state[regno].use_index = -1;
1221 }
1222 }
1223@@ -985,8 +1391,8 @@
1224 }
1225
1226 /* Check if DST is a register or a subreg of a register; if it is,
1227- update reg_state[regno].store_ruid and reg_state[regno].use_index
1228- accordingly. Called via note_stores from reload_combine. */
1229+ update store_ruid, real_store_ruid and use_index in the reg_state
1230+ structure accordingly. Called via note_stores from reload_combine. */
1231
1232 static void
1233 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
1234@@ -1010,14 +1416,14 @@
1235 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1236 careful with registers / register parts that are not full words.
1237 Similarly for ZERO_EXTRACT. */
1238- if (GET_CODE (set) != SET
1239- || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1240+ if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
1241 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1242 {
1243 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1244 {
1245 reg_state[i].use_index = -1;
1246 reg_state[i].store_ruid = reload_combine_ruid;
1247+ reg_state[i].real_store_ruid = reload_combine_ruid;
1248 }
1249 }
1250 else
1251@@ -1025,6 +1431,8 @@
1252 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--)
1253 {
1254 reg_state[i].store_ruid = reload_combine_ruid;
1255+ if (GET_CODE (set) == SET)
1256+ reg_state[i].real_store_ruid = reload_combine_ruid;
1257 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
1258 }
1259 }
1260@@ -1035,7 +1443,7 @@
1261 *XP is the pattern of INSN, or a part of it.
1262 Called from reload_combine, and recursively by itself. */
1263 static void
1264-reload_combine_note_use (rtx *xp, rtx insn)
1265+reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem)
1266 {
1267 rtx x = *xp;
1268 enum rtx_code code = x->code;
1269@@ -1048,7 +1456,7 @@
1270 case SET:
1271 if (REG_P (SET_DEST (x)))
1272 {
1273- reload_combine_note_use (&SET_SRC (x), insn);
1274+ reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX);
1275 return;
1276 }
1277 break;
1278@@ -1104,6 +1512,11 @@
1279 return;
1280 }
1281
1282+ /* We may be called to update uses in previously seen insns.
1283+ Don't add uses beyond the last store we saw. */
1284+ if (ruid < reg_state[regno].store_ruid)
1285+ return;
1286+
1287 /* If this register is already used in some unknown fashion, we
1288 can't do anything.
1289 If we decrement the index from zero to -1, we can't store more
1290@@ -1112,29 +1525,34 @@
1291 if (use_index < 0)
1292 return;
1293
1294- if (use_index != RELOAD_COMBINE_MAX_USES - 1)
1295- {
1296- /* We have found another use for a register that is already
1297- used later. Check if the offsets match; if not, mark the
1298- register as used in an unknown fashion. */
1299- if (! rtx_equal_p (offset, reg_state[regno].offset))
1300- {
1301- reg_state[regno].use_index = -1;
1302- return;
1303- }
1304- }
1305- else
1306+ if (use_index == RELOAD_COMBINE_MAX_USES - 1)
1307 {
1308 /* This is the first use of this register we have seen since we
1309 marked it as dead. */
1310 reg_state[regno].offset = offset;
1311- reg_state[regno].use_ruid = reload_combine_ruid;
1312- }
1313+ reg_state[regno].all_offsets_match = true;
1314+ reg_state[regno].use_ruid = ruid;
1315+ }
1316+ else
1317+ {
1318+ if (reg_state[regno].use_ruid > ruid)
1319+ reg_state[regno].use_ruid = ruid;
1320+
1321+ if (! rtx_equal_p (offset, reg_state[regno].offset))
1322+ reg_state[regno].all_offsets_match = false;
1323+ }
1324+
1325 reg_state[regno].reg_use[use_index].insn = insn;
1326+ reg_state[regno].reg_use[use_index].ruid = ruid;
1327+ reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
1328 reg_state[regno].reg_use[use_index].usep = xp;
1329 return;
1330 }
1331
1332+ case MEM:
1333+ containing_mem = x;
1334+ break;
1335+
1336 default:
1337 break;
1338 }
1339@@ -1144,11 +1562,12 @@
1340 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1341 {
1342 if (fmt[i] == 'e')
1343- reload_combine_note_use (&XEXP (x, i), insn);
1344+ reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem);
1345 else if (fmt[i] == 'E')
1346 {
1347 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1348- reload_combine_note_use (&XVECEXP (x, i, j), insn);
1349+ reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid,
1350+ containing_mem);
1351 }
1352 }
1353 }
1354@@ -1196,9 +1615,10 @@
1355 while REG is known to already have value (SYM + offset).
1356 This function tries to change INSN into an add instruction
1357 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1358- It also updates the information about REG's known value. */
1359+ It also updates the information about REG's known value.
1360+ Return true if we made a change. */
1361
1362-static void
1363+static bool
1364 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
1365 {
1366 rtx pat = PATTERN (insn);
1367@@ -1207,6 +1627,7 @@
1368 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
1369 GET_MODE (reg));
1370 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1371+ bool changed = false;
1372
1373 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1374 use (set (reg) (reg)) instead.
1375@@ -1221,13 +1642,13 @@
1376 (reg)), would be discarded. Maybe we should
1377 try a truncMN pattern? */
1378 if (INTVAL (off) == reg_offset [regno])
1379- validate_change (insn, &SET_SRC (pat), reg, 0);
1380+ changed = validate_change (insn, &SET_SRC (pat), reg, 0);
1381 }
1382 else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
1383 && have_add2_insn (reg, new_src))
1384 {
1385 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
1386- validate_change (insn, &SET_SRC (pat), tem, 0);
1387+ changed = validate_change (insn, &SET_SRC (pat), tem, 0);
1388 }
1389 else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
1390 {
1391@@ -1252,8 +1673,9 @@
1392 gen_rtx_STRICT_LOW_PART (VOIDmode,
1393 narrow_reg),
1394 narrow_src);
1395- if (validate_change (insn, &PATTERN (insn),
1396- new_set, 0))
1397+ changed = validate_change (insn, &PATTERN (insn),
1398+ new_set, 0);
1399+ if (changed)
1400 break;
1401 }
1402 }
1403@@ -1263,6 +1685,7 @@
1404 reg_mode[regno] = GET_MODE (reg);
1405 reg_symbol_ref[regno] = sym;
1406 reg_offset[regno] = INTVAL (off);
1407+ return changed;
1408 }
1409
1410
1411@@ -1272,9 +1695,10 @@
1412 value (SYM + offset) and change INSN into an add instruction
1413 (set (REG) (plus (the found register) (OFF - offset))) if such
1414 a register is found. It also updates the information about
1415- REG's known value. */
1416+ REG's known value.
1417+ Return true iff we made a change. */
1418
1419-static void
1420+static bool
1421 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
1422 {
1423 rtx pat = PATTERN (insn);
1424@@ -1284,6 +1708,7 @@
1425 int min_regno;
1426 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
1427 int i;
1428+ bool changed = false;
1429
1430 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1431 if (reg_set_luid[i] > move2add_last_label_luid
1432@@ -1328,20 +1753,25 @@
1433 GET_MODE (reg));
1434 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
1435 }
1436- validate_change (insn, &SET_SRC (pat), tem, 0);
1437+ if (validate_change (insn, &SET_SRC (pat), tem, 0))
1438+ changed = true;
1439 }
1440 reg_set_luid[regno] = move2add_luid;
1441 reg_base_reg[regno] = -1;
1442 reg_mode[regno] = GET_MODE (reg);
1443 reg_symbol_ref[regno] = sym;
1444 reg_offset[regno] = INTVAL (off);
1445+ return changed;
1446 }
1447
1448-static void
1449+/* Convert move insns with constant inputs to additions if they are cheaper.
1450+ Return true if any changes were made. */
1451+static bool
1452 reload_cse_move2add (rtx first)
1453 {
1454 int i;
1455 rtx insn;
1456+ bool changed = false;
1457
1458 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1459 {
1460@@ -1402,7 +1832,7 @@
1461 && reg_base_reg[regno] < 0
1462 && reg_symbol_ref[regno] == NULL_RTX)
1463 {
1464- move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1465+ changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn);
1466 continue;
1467 }
1468
1469@@ -1463,6 +1893,7 @@
1470 }
1471 if (success)
1472 delete_insn (insn);
1473+ changed |= success;
1474 insn = next;
1475 reg_mode[regno] = GET_MODE (reg);
1476 reg_offset[regno] =
1477@@ -1508,12 +1939,12 @@
1478 && reg_base_reg[regno] < 0
1479 && reg_symbol_ref[regno] != NULL_RTX
1480 && rtx_equal_p (sym, reg_symbol_ref[regno]))
1481- move2add_use_add2_insn (reg, sym, off, insn);
1482+ changed |= move2add_use_add2_insn (reg, sym, off, insn);
1483
1484 /* Otherwise, we have to find a register whose value is sum
1485 of sym and some constant value. */
1486 else
1487- move2add_use_add3_insn (reg, sym, off, insn);
1488+ changed |= move2add_use_add3_insn (reg, sym, off, insn);
1489
1490 continue;
1491 }
1492@@ -1568,6 +1999,7 @@
1493 }
1494 }
1495 }
1496+ return changed;
1497 }
1498
1499 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
1500
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-10-04 03:33:28 +0000