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| author | Jaewon Lee <jaewon.lee@xilinx.com> | 2020-08-27 08:47:48 -0700 |
|---|---|---|
| committer | Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> | 2020-09-08 11:13:22 -0700 |
| commit | 1e4c4d152c62eca55b513f78e7c1cfb9c0876536 (patch) | |
| tree | 81da90ed3c22002bf28803f4093ae4dac6744810 | |
| parent | c7c4029c7e28d1c1273facf4a10f77ed6f14c292 (diff) | |
| download | meta-xilinx-1e4c4d152c62eca55b513f78e7c1cfb9c0876536.tar.gz | |
soc-versal.inc: Setting default versal SOC_FAMILY to prime
Default versal SOC_FAMILY is changed to "prime" from "s80"
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
| -rw-r--r-- | meta-xilinx-bsp/conf/machine/include/soc-versal.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/meta-xilinx-bsp/conf/machine/include/soc-versal.inc b/meta-xilinx-bsp/conf/machine/include/soc-versal.inc index c32880b1..d15f4909 100644 --- a/meta-xilinx-bsp/conf/machine/include/soc-versal.inc +++ b/meta-xilinx-bsp/conf/machine/include/soc-versal.inc | |||
| @@ -2,9 +2,11 @@ DEFAULTTUNE ?= "cortexa72-cortexa53" | |||
| 2 | SOC_FAMILY ?= "versal" | 2 | SOC_FAMILY ?= "versal" |
| 3 | 3 | ||
| 4 | # Available SOC_VARIANT's for versal: | 4 | # Available SOC_VARIANT's for versal: |
| 5 | # virt | 5 | # "-prime" - Versal deafult Prime Devices |
| 6 | # "-ai-core" - Versal AI-core Devices | ||
| 7 | # "-premium" - Versal Premium Devices | ||
| 6 | 8 | ||
| 7 | SOC_VARIANT ?= "s80" | 9 | SOC_VARIANT ?= "-prime" |
| 8 | 10 | ||
| 9 | require soc-tune-include.inc | 11 | require soc-tune-include.inc |
| 10 | require xilinx-soc-family.inc | 12 | require xilinx-soc-family.inc |