gcc: update to early gatesgarth version

Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>

62 files changed, 641 insertions, 1051 deletions

diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
index af5a65cb..e0f7b12e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -1,26 +1,32 @@
-From d2ebb14b318166dd91fe35bf3531d758dcbc995a Mon Sep 17 00:00:00 2001
+From e3f148dff6d6d926d1f39802f54abd59bd9e887c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 13:13:57 +0530
-Subject: [PATCH 01/58] [LOCAL]: Testsuite - builtins tests require fpic
+Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
+ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Conflicts:
+
+        gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 ---
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 5 +++++
- 1 file changed, 5 insertions(+)
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 594c9297958..4103d43748d 100644
+index 594c9297958..8350d9401d2 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -48,6 +48,11 @@ if { [istarget *-*-eabi*]
+@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
     lappend additional_flags "-Wl,--allow-multiple-definition"
  }
  
++<<<<<<< HEAD
++=======
 +if [istarget "microblaze*-*-linux*"] {
 +   lappend additional_flags "-Wl,-zmuldefs"
 +   lappend additional_flags "-fPIC"
 +}
 +
++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
  foreach src [lsort [find $srcdir/$subdir *.c]] {
      if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
         c-torture-execute [list $src \
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
index 976896da..431dc7ef 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -1,11 +1,10 @@
-From 54394232ffbaa9474f8a78c6882f08a48842242e Mon Sep 17 00:00:00 2001
+From bef1a4116efded9972e693ded5152f1d8670862e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 14:31:10 +0530
-Subject: [PATCH 02/58] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C
-
-This particular testcase fails with a timeout. Instead, fail it
-at compile-time for microblaze. This speeds up the testsuite without
-removing it from the FAIL reports.
+Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
+ particular testcase fails with a timeout. Instead, fail it at compile-time
+ for microblaze. This speeds up the testsuite without removing it from the
+ FAIL reports.
 
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
new file mode 100644
index 00000000..a2dc7ccc
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -0,0 +1,35 @@
+From a063597f875142af49003e2f28b6c0f56e3b914d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:46:28 +0530
+Subject: [PATCH 03/54] [LOCAL]: For dejagnu static testing on qemu, suppress
+ warnings about multiple definitions from the test function and libc in line
+ with method used by powerpc. Dynamic linking and using a qemu binary which
+ understands sysroot resolves all test failures with builtins
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index 8350d9401d2..d7c9b281d01 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
+    lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+ 
+-<<<<<<< HEAD
+-=======
+ if [istarget "microblaze*-*-linux*"] {
+    lappend additional_flags "-Wl,-zmuldefs"
+-   lappend additional_flags "-fPIC"
+ }
+ 
+->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+        c-torture-execute [list $src \
+-- 
+2.17.1
+
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
deleted file mode 100644
index 8e6d22db..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From f0a446bcb453630d8116b30f542aee79407228ea Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:28:38 +0530
-Subject: [PATCH 03/58] [LOCAL]: Testsuite - explicitly add -fivopts for tests
- that depend on it
-
-(test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt exist in 4.6 branch)
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
- gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-index 438db882043..ede883eb284 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
--/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
- 
- void test (int *b, int *e, int stride)
-   {
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-index cbb6c850baa..34248021c23 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-@@ -1,5 +1,5 @@
- // { dg-do compile }
--// { dg-options "-O2 -fdump-tree-ivopts-details" }
-+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
- 
- class MinimalVec3
- {
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-index bda25167353..22c8a5dcffe 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-index f0770abdbbc..65d74c8e620 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-index 5f42857fe13..9bc86ee0d23 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-@@ -1,7 +1,7 @@
- /* A test for induction variable merging.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- 
- void foo(long);
- 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-index 50d86a00485..1e3eacd33d1 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fopt-info-loop-missed" } */
-+/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */
- extern void g(void);
- 
- void
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-index 2c6cfc6f831..648e6e67e80 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fdump-tree-ivopts" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
- 
- void vnum_test8(int *data) 
- { 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-index e911bfcd521..5d3e7e0801a 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-Os -fdump-tree-optimized" } */
-+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
- 
- /* Slightly changed testcase from PR middle-end/40815.  */
- void bar(char*, char*, int);
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
deleted file mode 100644
index 4974462c..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f8809fdebc3ef3927695c84224d3446fa13447d6 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:46:28 +0530
-Subject: [PATCH 04/58] [LOCAL]: For dejagnu static testing on qemu, suppress
- warnings
-
-about multiple definitions from the test function and libc in line
-with method used by powerpc. Dynamic linking and using a qemu binary
-which understands sysroot resolves all test failures with builtins
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 4103d43748d..d7c9b281d01 100644
---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -50,7 +50,6 @@ if { [istarget *-*-eabi*]
- 
- if [istarget "microblaze*-*-linux*"] {
-    lappend additional_flags "-Wl,-zmuldefs"
--   lappend additional_flags "-fPIC"
- }
- 
- foreach src [lsort [find $srcdir/$subdir *.c]] {
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
index c21492e8..661417d7 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -1,8 +1,8 @@
-From 802078fa3e76ea7fdb29f3baf1d4d9baae42bc0b Mon Sep 17 00:00:00 2001
+From c1028bcb40ccd8d61afc1ab798198948fbf74aa0 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:50:35 +0530
-Subject: [PATCH 05/58] [Patch, testsuite]: Add MicroBlaze to target-supports
- for atomic builtin tests
+Subject: [PATCH 04/54] [Patch, testsuite]: Add MicroBlaze to target-supports
+ for atomic buil. .tin tests
 
 MicroBlaze added to supported targets for atomic builtin tests.
 
@@ -19,10 +19,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 13761491e63..d2f65dac32c 100644
+index 0dfe3ae0651..86caf6db9a9 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
-@@ -7581,6 +7581,7 @@ proc check_effective_target_sync_int_long { } {
+@@ -7468,6 +7468,7 @@ proc check_effective_target_sync_int_long { } {
                  && [check_effective_target_arm_acq_rel])
              || [istarget bfin*-*linux*]
              || [istarget hppa*-*linux*]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
index 9c8cce92..d34988c5 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -1,9 +1,8 @@
-From 8c24cb4f95f46793ac7500a5d6181d93f2b0d2c5 Mon Sep 17 00:00:00 2001
+From ae5ce07a67df89dabba61414ba7dabbdabc1ee1b Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 16:20:01 +0530
-Subject: [PATCH 06/58] [Patch, testsuite]: Update MicroBlaze strings test
-
-for new scan-assembly output resulting in use of $LC label
+Subject: [PATCH 05/54] [Patch, testsuite]: Update MicroBlaze strings test for
+ new scan-assembly output resulting in use of $LC label
 
 ChangeLog/testsuite
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
index 4d1e2017..4b45fcf1 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -1,11 +1,9 @@
-From 38ece4b2dc5d34c1b88b6ea8dd8e62a0986f8f6c Mon Sep 17 00:00:00 2001
+From 49cf9cd3fedce80a63e9d03d42482dd4596c27a7 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:14:15 +0530
-Subject: [PATCH 07/58] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
- in regex match
-
-Extend regex pattern to include optional ext at the end of
-.weak to match the MicroBlaze weak label .weakext
+Subject: [PATCH 06/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
+ in regex match Extend regex pattern to include optional ext at the end of
+ .weak to match the MicroBlaze weak label .weakext
 
 ChangeLog/testsuite
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
index f96d7d57..8fa324ad 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -1,11 +1,10 @@
-From bc5f423bcfa24aa8c15548379bfc6b3f49e57c15 Mon Sep 17 00:00:00 2001
+From dc6cbb4e18a3f31441403146b8f159554c329897 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:34:27 +0530
-Subject: [PATCH 08/58] [Patch, testsuite]: Add MicroBlaze to
- check_profiling_available
-
-Testsuite, add microblaze*-*-* target in check_profiling_available
-inline with other archs setting profiling_available_saved to 0
+Subject: [PATCH 07/54] [Patch, testsuite]: Add MicroBlaze to
+ check_profiling_available Testsuite, add microblaze*-*-* target in
+ check_profiling_available inline with other archs setting
+ profiling_available_saved to 0
 
 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 ---
@@ -13,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index d2f65dac32c..d949fbd8464 100644
+index 86caf6db9a9..cbd9024ece9 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
 @@ -707,6 +707,7 @@ proc check_profiling_available { test_what } {
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch
index 45d93cee..1fa55729 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -1,12 +1,11 @@
-From eeeb8ecda7cb71c033c850ce36162c92c7d0b781 Mon Sep 17 00:00:00 2001
+From 602713d07d2e1b3a33a7f097baff270266aa4254 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:41:43 +0530
-Subject: [PATCH 09/58] [Patch, microblaze]: Fix atomic side effects.
-
-In atomic_compare_and_swapsi, add side effects to prevent incorrect
-assumptions during optimization. Previously, the outputs were
-considered unused; this generated assembly code with
-undefined side effects after invocation of the atomic.
+Subject: [PATCH 08/54] [Patch, microblaze]: Fix atomic side effects. In
+ atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
+ during optimization. Previously, the outputs were considered unused; this
+ generated assembly code with undefined side effects after invocation of the
+ atomic.
 
 Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
index 48f77215..666d344f 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -1,11 +1,9 @@
-From 834448fc3493be56cc6a4f6b504569142f7f6070 Mon Sep 17 00:00:00 2001
+From d3d065c9645d795e03dab6db827c08231e011a1f Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:45:45 +0530
-Subject: [PATCH 10/58] [Patch, microblaze]: Fix atomic boolean return value.
-
-In atomic_compare_and_swapsi, fix boolean return value.
-Previously, it contained zero if successful and non-zero
-if unsuccessful.
+Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic boolean return value.
+ In atomic_compare_and_swapsi, fix boolean return value. Previously, it
+ contained zero if successful and non-zero if unsuccessful.
 
 Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
index e60e6f2f..22bf521d 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -1,14 +1,13 @@
-From 19457459592123c41c3ce9e084e165525e4d7bb0 Mon Sep 17 00:00:00 2001
+From 8d9d1f457e1e270250d8a6700d4a1e1fa09465df Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:50:17 +0530
-Subject: [PATCH 11/58] [Patch, microblaze]: Fix the Microblaze crash with
- msmall-divides flag
-
-Compiler is crashing when we use msmall-divides and mxl-barrel-shift flag.
-This is because when use above flags microblaze_expand_divide function will be
-called for division operation. In microblaze_expand_divide function we are
-using sub_reg but MicroBlaze doesn't have subreg register due to this compiler
-was crashing. Changed the logic to avoid sub_reg call
+Subject: [PATCH 10/54] [Patch, microblaze]: Fix the Microblaze crash with
+ msmall-divides flag Compiler is crashing when we use msmall-divides and
+ mxl-barrel-shift flag. This is because when use above flags
+ microblaze_expand_divide function will be called for division operation. In
+ microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't
+ have subreg register due to this compiler was crashing. Changed the logic to
+ avoid sub_reg call
 
 Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
index b9e39928..cce812bb 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -1,11 +1,10 @@
-From 9da28a01ffb778fc5cb5df27332cef21f890a63f Mon Sep 17 00:00:00 2001
+From 03429c91d1db134e1deda4c8e58bc0939d5fedf9 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:52:56 +0530
-Subject: [PATCH 12/58] [Patch, microblaze]: Added ashrsi3_with_size_opt
-
-Added ashrsi3_with_size_opt pattern to optimize the sra instructions
-when the -Os optimization is used. lshrsi3_with_size_opt is
-being removed as it has conflicts with unsigned int variables
+Subject: [PATCH 11/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
+ ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
+ optimization is used. lshrsi3_with_size_opt is being removed as it has
+ conflicts with unsigned int variables
 
 Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
index 36af2652..e393f0fe 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -1,9 +1,9 @@
-From 07a5c8b22a1cef99b2d4570ea080c503260161e4 Mon Sep 17 00:00:00 2001
+From 6803fbc540db39865037994daa122cf10c0eb33a Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 10:57:19 +0530
-Subject: [PATCH 13/58] [Patch, microblaze]: Use bralid for profiler calls
+Subject: [PATCH 12/54] [Patch, microblaze]: Use bralid for profiler calls
+ Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 ---
  gcc/config/microblaze/microblaze.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch
index e7fb9393..b601c98a 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -1,14 +1,10 @@
-From c2a6652176751bc95e2f990179e90cfe58026feb Mon Sep 17 00:00:00 2001
+From 5de3888c460a341667150d569548b3309188e7e8 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 17:36:16 +0530
-Subject: [PATCH 15/58] [Patch, microblaze]: Removed moddi3 routinue
-
-Using the default moddi3 function as the existing implementation has many bugs
+Subject: [PATCH 13/54] [Patch, microblaze]: Removed moddi3 routinue Using the
+ default moddi3 function as the existing implementation has many bugs
 
 Signed-off-by:Nagaraju <nmekala@xilix.com>
-
-Conflicts:
-        libgcc/config/microblaze/moddi3.S
 ---
  libgcc/config/microblaze/moddi3.S     | 121 --------------------------
  libgcc/config/microblaze/t-microblaze |   3 +-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
index 13c3ccd9..3bd6efd5 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -1,9 +1,8 @@
-From 9a4253a92a5e1811693ea1707b5fc272908ec556 Mon Sep 17 00:00:00 2001
+From b9a9e8f9d0994c76819ec605a0b7cd113f3b2cf0 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 14:41:58 +0530
-Subject: [PATCH 16/58] [Patch, microblaze]: Add INIT_PRIORITY support
-
-Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
+Subject: [PATCH 14/54] [Patch, microblaze]: Add INIT_PRIORITY support Added
+ TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
 
 These macros allows users to control the order of initialization
 of objects defined at namespace scope with the init_priority
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch
deleted file mode 100644
index 51563ecb..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 616f16089f0b01ab02008d7291df0972a99782e0 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 11:10:21 +0530
-Subject: [PATCH 14/58] [Patch, microblaze]: Disable fivopts by default
-
-Turn off ivopts by default. Interferes with cse.
-
-Changelog
-
-2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-
- * gcc/common/config/microblaze/microblaze-common.c
-   (microblaze_option_optimization_table): Disable fivopts by default.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 4391f939626..0b9d5a1b453 100644
---- a/gcc/common/config/microblaze/microblaze-common.c
-+++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -24,6 +24,15 @@
- #include "common/common-target.h"
- #include "common/common-target-def.h"
- 
-+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
-+static const struct default_options microblaze_option_optimization_table[] =
-+  {
-+    /* Turn off ivopts by default. It messes up cse. */
-+    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
-+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-+    { OPT_LEVELS_NONE, 0, NULL, 0 }
-+  };
-+
- #undef TARGET_DEFAULT_TARGET_FLAGS
- #define TARGET_DEFAULT_TARGET_FLAGS    TARGET_DEFAULT
- 
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
index cfc06f74..ba20cf07 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -1,11 +1,9 @@
-From 27c27a8876152bac78059a1b2d5a6f0ac9b8cee2 Mon Sep 17 00:00:00 2001
+From f448485f5e0507a7ab8be7f83c08f807200a3501 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 15:23:57 +0530
-Subject: [PATCH 17/58] [Patch, microblaze]: Add optimized lshrsi3
-
-When barrel shifter is not present, the immediate value
-is greater than #5 and optimization is -OS, the
-compiler will generate shift operation using loop.
+Subject: [PATCH 15/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel
+ shifter is not present, the immediate value is greater than #5 and
+ optimization is -OS, the compiler will generate shift operation using loop.
 
 Changelog
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
index b78a9814..0c865224 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -1,11 +1,10 @@
-From f43cb8572131074c7ce43a1d39c7ba6c85611e18 Mon Sep 17 00:00:00 2001
+From 386b8dcef2d774e9138515814be0fd579ade5af5 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:04:37 +0530
-Subject: [PATCH 19/58] [Patch, microblaze]: Add cbranchsi4_reg
-
-This patch optimizes the generation of  pcmpne/pcmpeq instruction if the
-compare instruction has no immediate values.For the immediate values the
-xor instruction is generated
+Subject: [PATCH 16/54] [Patch, microblaze]: Add cbranchsi4_reg This patch
+ optimizes the generation of  pcmpne/pcmpeq instruction if the compare
+ instruction has no immediate values.For the immediate values the xor
+ instruction is generated
 
 Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
 Signed-off-by: Ajit Agarwal  <ajitkum@xilinx.com>
@@ -31,7 +30,7 @@ Conflicts:
  7 files changed, 18 insertions(+), 18 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 96f7bb67f6c..76ffc682df2 100644
+index 982b2abd2d4..c2f88813a8d 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
 @@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
index cc1c3d7e..504083f3 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -1,22 +1,19 @@
-From 1bbf48097cf2da98e03139b499a5a74bc68e6abc Mon Sep 17 00:00:00 2001
+From b6298861681965533c9b6dac5e26fbd62b52839d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:11:04 +0530
-Subject: [PATCH 20/58] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
-
-The changes are made in the patch for the inline expansion of
-the fsqrt builtin with fqrt instruction. The sqrt math function
-takes double as argument and return double as argument. The
-pattern is selected while expanding the unary op through
-expand_unop which passes DFmode and the DFmode pattern was
-not there returning zero. Thus the sqrt math function is not
-inlined and expanded. The pattern with DFmode argument is added.
-Also the source and destination argument is not same the DF
-through two different consecutive registers with lower 32 bit
-is the argument passed to sqrt and the higher 32 bit is zero.
-If the source and destinations are different the DFmode 64 bits
-registers is not set properly giving the problem in runtime. Such
-changes are taken care in the implementation of the pattern for
-DFmode for inline expansion of the sqrt.
+Subject: [PATCH 17/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
+ The changes are made in the patch for the inline expansion of the fsqrt
+ builtin with fqrt instruction. The sqrt math function takes double as
+ argument and return double as argument. The pattern is selected while
+ expanding the unary op through expand_unop which passes DFmode and the DFmode
+ pattern was not there returning zero. Thus the sqrt math function is not
+ inlined and expanded. The pattern with DFmode argument is added. Also the
+ source and destination argument is not same the DF through two different
+ consecutive registers with lower 32 bit is the argument passed to sqrt and
+ the higher 32 bit is zero. If the source and destinations are different the
+ DFmode 64 bits registers is not set properly giving the problem in runtime.
+ Such changes are taken care in the implementation of the pattern for DFmode
+ for inline expansion of the sqrt.
 
 ChangeLog:
 2015-06-16  Ajit Agarwal  <ajitkum@xilinx.com>
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
index 2e5afed8..14095d83 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -1,17 +1,14 @@
-From b066cb189302814fcd91b38f2f9da830a2c5b8fe Mon Sep 17 00:00:00 2001
+From a8c6c13cc322ecc300bb2cdf22e3d6f1680e56be Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:07:24 +0530
-Subject: [PATCH 22/58] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
- insn definitions
-
-Change adddi3 to handle DI immediates as the second operand, this
-requires modification to the output template however reduces the need to
-specify seperate templates for 16-bit positive/negative immediate
-operands. The use of 32-bit immediates for the addi and addic
-instructions is handled by the assembler, which will emit the imm
-instructions when required. This conveniently handles the optimizable
-cases where the immediate constant value does not need the higher half
-words of the operands upper/lower words.
+Subject: [PATCH 18/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
+ insn definitions Change adddi3 to handle DI immediates as the second operand,
+ this requires modification to the output template however reduces the need to
+ specify seperate templates for 16-bit positive/negative immediate operands.
+ The use of 32-bit immediates for the addi and addic instructions is handled
+ by the assembler, which will emit the imm instructions when required. This
+ conveniently handles the optimizable cases where the immediate constant value
+ does not need the higher half words of the operands upper/lower words.
 
 Change the constraints of the subdi3 instruction definition such that it
 does not match the second operand as an immediate value. This is because
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
index fa16749e..4a490119 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -1,13 +1,11 @@
-From 98018d020d9fbae38ea19627dec64d03d7f21fac Mon Sep 17 00:00:00 2001
+From 3a9ee185eb462f880ceb4ddd125d4a98e0759873 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:18:41 +0530
-Subject: [PATCH 23/58] [Patch, microblaze]: Update ashlsi3 & movsf patterns
-
-This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in
-print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay
-and movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX
-is generating 64-bit value which our instruction doesn't support
-so using gen_int_mode function
+Subject: [PATCH 19/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns
+ This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
+ of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
+ patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
+ instruction doesn't support so using gen_int_mode function
 
 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
               :Ajit Agarwal  <ajitkum@xilinx.com>
@@ -24,9 +22,23 @@ ChangeLog:
      updated the 'F' case to use "unsinged int" instead
      of HOST_WIDE_INT_PRINT_HEX
 ---
+ gcc/config/microblaze/microblaze.c  |  2 +-
  gcc/config/microblaze/microblaze.md | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
+ 2 files changed, 9 insertions(+), 3 deletions(-)
 
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 9eae5515c60..0a4619eec0c 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2468,7 +2468,7 @@ print_operand (FILE * file, rtx op, int letter)
+          unsigned long value_long;
+          REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
+                                       value_long);
+-         fprintf (file, "0x%lx", value_long);
++         fprintf (file, "0x%08x", (unsigned int) value_long);
+        }
+       else
+        {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
 index efd2c34e0b7..be8bbda2bfb 100644
 --- a/gcc/config/microblaze/microblaze.md
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
index 8e0eda3c..07cf635d 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -1,61 +1,28 @@
-From 3f98e90620e0ae6d76a1ba18e97389feb095c3e4 Mon Sep 17 00:00:00 2001
+From bfdb38133201f7df01d09dc7e7ee3043a35c1d3e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 19:50:34 +0530
-Subject: [PATCH 24/58] [Patch, microblaze]: 8-stage pipeline for microblaze
+Date: Mon, 9 Nov 2020 19:54:39 +0530
+Subject: [PATCH 20/54] [Patch, microblaze]: 8-stage pipeline for microblaze
 
 This patch adds the support for the 8-stage pipeline. The new 8-stage
 pipeline reduces the latencies of float & integer division drastically
 
 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (define_automaton mbpipe_8): New
-
-  *microblaze.c (microblaze_option_override): Update
-    Updated the logic to generate only when MB version is 10.0
-
-  *microblaze.h (pipeline_type): Update
-          Update the enum with MICROBLAZE_PIPE_8
-
-  *microblaze.opt (mxl-frequency): New
-         New flag added for 8-stage pipeline
 ---
- gcc/config/microblaze/microblaze.c   | 18 ++++++-
+ gcc/config/microblaze/microblaze.c   | 11 ++++
  gcc/config/microblaze/microblaze.h   |  3 +-
  gcc/config/microblaze/microblaze.md  | 79 +++++++++++++++++++++++++++-
  gcc/config/microblaze/microblaze.opt |  4 ++
- 4 files changed, 100 insertions(+), 4 deletions(-)
+ 4 files changed, 94 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a4bdf66f045..a3996119bd7 100644
+index 0a4619eec0c..0dc96e481b7 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
- /* Set to one if the targeted core has the CLZ insn.  */
- int microblaze_has_clz = 0;
- 
-+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
-+int microblaze_has_bitfield = 0;
-+
- /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
-    version having only a particular type of pipeline. There can still be 
-    options on the CPU to scale pipeline features up or down. :( 
-@@ -1739,7 +1742,7 @@ microblaze_option_override (void)
-   register int i, start;
-   register int regno;
-   register machine_mode mode;
--  int ver;
-+  int ver,ver_int;
- 
-   microblaze_section_threshold = (global_options_set.x_g_switch_value
-                                  ? g_switch_value
-@@ -1840,6 +1843,19 @@ microblaze_option_override (void)
+@@ -1840,6 +1840,17 @@ microblaze_option_override (void)
                    "%<-mcpu=v8.30.a%>");
          TARGET_REORDER = 0;
      }
-+  ver = ver_int - microblaze_version_to_int("v10.0");
++  ver = microblaze_version_to_int("v10.0");
 +  if (ver < 0)
 +    {
 +        if (TARGET_AREA_OPTIMIZED_2)
@@ -65,14 +32,12 @@ index a4bdf66f045..a3996119bd7 100644
 +    {
 +        if (TARGET_AREA_OPTIMIZED_2)
 +          microblaze_pipe = MICROBLAZE_PIPE_8;
-+        if (TARGET_BARREL_SHIFT)
-+          microblaze_has_bitfield = 1;
 +    }
  
    if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
      error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1e155e4041c..8b0db2c1718 100644
+index 8aa3f155790..8a668278337 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -27,7 +27,8 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
deleted file mode 100644
index b4d03172..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From fe7962c6cc54a5d5f80db90ccc06b8603ddeb74f Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:33:31 +0530
-Subject: [PATCH 21/58] [Patch] OPT: Update heuristics for loop-invariant for
- address arithmetic
-
-The changes are made in the patch to update the heuristics
-for loop invariant for address arithmetic. The heuristics is
-changed to calculate the estimated register pressure cost when
-ira based register pressure is not enabled. The estimated
-register pressure cost modifies the existing calculation cost
-associated to perform the Loop invariant code motion for address
-arithmetic.
-
-ChangeLog:
-2015-06-17  Ajit Agarwal  <ajitkum@xilinx.com>
-            Nagaraju Mekala <nmekala@xilinx.com>
-
-        * loop-invariant.c (gain_for_invariant): update the
-        heuristics for estimate_reg_pressure_cost.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
-              Nagaraju Mekala nmekala@xilinx.com
----
- gcc/loop-invariant.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index 37ae6549e56..f6385d6cf43 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- 
-   if (! flag_ira_loop_pressure)
-     {
--      size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
--                                              regs_used, speed, call_p)
--                  - estimate_reg_pressure_cost (new_regs[0],
--                                                regs_used, speed, call_p));
-+      size_cost = estimate_reg_pressure_cost (regs_needed[0],
-+                                              regs_used, speed, call_p);
-     }
-   else if (ret < 0)
-     return -1;
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
new file mode 100644
index 00000000..f362cea8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -0,0 +1,58 @@
+From af01da22797795408d45dcf03076dc8153c7029e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 9 Nov 2020 21:14:54 +0530
+Subject: [PATCH 21/54] [Patch, microblaze]: Correct the const high double
+ immediate value with this patch the loading of the DI mode immediate values
+ will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
+ functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
+ of the unsigned long long constants also
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.c                | 6 ++++--
+ gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++
+ 2 files changed, 13 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 0dc96e481b7..5d395f047f7 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2452,14 +2452,16 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
++      long l[2];
+       if (code == CONST_DOUBLE)
+        {
+          if (GET_MODE (op) == DFmode)
+            REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+          else
+            {
+-             val[0] = CONST_DOUBLE_HIGH (op);
+-             val[1] = CONST_DOUBLE_LOW (op);
++             REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
++             val[1] = l[WORDS_BIG_ENDIAN == 0];
++             val[0] = l[WORDS_BIG_ENDIAN != 0];
+            }
+        }
+       else if (code == CONST_INT)
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c
+new file mode 100644
+index 00000000000..b6b55d5ad65
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/long.c
+@@ -0,0 +1,9 @@
++#define BASEADDR 0xF0000000ULL
++int main ()
++{
++  unsigned long long start;
++  start = (unsigned long long) BASEADDR;
++  return 0;
++}
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
+-- 
+2.17.1
+
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
index 3869db15..3faef052 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -1,12 +1,11 @@
-From ea79d97f430d554921d94d30cb8db851cce6664b Mon Sep 17 00:00:00 2001
+From 7349def8102c09fd09e735daa9fc890bee323e79 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 11:49:58 +0530
-Subject: [PATCH 27/58] [Fix, microblaze]: Fix internal compiler error with
- msmall-divides
-
-This patch will fix the internal error microblaze_expand_divide function which comes because
-of rtx PLUS where the mem_rtx is of type SI and the operand is of type QImode.
-This patch modifies the mem_rtx as QImode and Plus as QImode to fix the error.
+Subject: [PATCH 22/54] [Fix, microblaze]: Fix internal compiler error with
+ msmall-divides This patch will fix the internal error
+ microblaze_expand_divide function which comes because of rtx PLUS where the
+ mem_rtx is of type SI and the operand is of type QImode. This patch modifies
+ the mem_rtx as QImode and Plus as QImode to fix the error.
 
 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
                Ajit Agarwal  <ajitkum@xilinx.com>
@@ -20,10 +19,10 @@ ChangeLog:
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 73d0e010cda..f7c29ef28f5 100644
+index 5d395f047f7..29b2f6b016b 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3902,7 +3902,7 @@ microblaze_expand_divide (rtx operands[])
+@@ -3767,7 +3767,7 @@ microblaze_expand_divide (rtx operands[])
    emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
    emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
    mem_rtx = gen_rtx_MEM (QImode,
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
index 3f9dd69b..1c4f8ca9 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -1,8 +1,8 @@
-From fa067a4b7b65aae3671bb02d77c580c9e35fc384 Mon Sep 17 00:00:00 2001
+From ad3d0a29a4895351008ce959138c13b8f5924464 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:03:39 +0530
-Subject: [PATCH 28/58] [patch,microblaze]: Fix the calculation of high word in
- a long long 64-bit
+Subject: [PATCH 23/54] [patch,microblaze]: Fix the calculation of high word in
+ a long long 6. .4-bit
 
 This patch will change the calculation of high word in a long long 64-bit.
 Earlier to this patch the high word of long long word (0xF0000000ULL) is
@@ -27,10 +27,10 @@ ChangeLog:
  1 file changed, 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index f7c29ef28f5..0a73a6c32b4 100644
+index 29b2f6b016b..4710def18cf 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2603,9 +2603,6 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2468,9 +2468,6 @@ print_operand (FILE * file, rtx op, int letter)
          {
           val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
           val[1] = INTVAL (op) & 0x00000000ffffffffLL;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
index dfdb479c..590cb38c 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
@@ -1,7 +1,7 @@
-From 341bf8ad4e55693d00d4d8c916f4c347e7186dd4 Mon Sep 17 00:00:00 2001
+From 50f5f8341ba39f2e12eef4a149e59f71f032f7d3 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:14:51 +0530
-Subject: [PATCH 29/58] [Patch, microblaze]: Add new bit-field instructions
+Date: Tue, 10 Nov 2020 09:51:24 +0530
+Subject: [PATCH 24/54] [Patch, microblaze]: Add new bit-field instructions
 
 This patches adds new bsefi and bsifi instructions.
 BSEFI- The instruction shall extract a bit field from a
@@ -12,18 +12,37 @@ from a register at another position in the destination register.
 The rest of the bits in the destination register shall be unchanged
 
 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-  2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (Update): Added new patterns
 ---
+ gcc/config/microblaze/microblaze.c  |  5 ++
  gcc/config/microblaze/microblaze.h  |  2 +
  gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++
- 2 files changed, 75 insertions(+)
+ 3 files changed, 80 insertions(+)
 
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 4710def18cf..14c652325a8 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn.  */
+ int microblaze_has_clz = 0;
+ 
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
+    version having only a particular type of pipeline. There can still be 
+    options on the CPU to scale pipeline features up or down. :( 
+@@ -1850,6 +1853,8 @@ microblaze_option_override (void)
+     {
+         if (TARGET_AREA_OPTIMIZED_2)
+           microblaze_pipe = MICROBLAZE_PIPE_8;
++        if (TARGET_BARREL_SHIFT)
++          microblaze_has_bitfield = 1;
+     }
+ 
+   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8b0db2c1718..b5b7b22cec9 100644
+index 8a668278337..857cb1cd9d0 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
@@ -34,16 +53,16 @@ index 8b0db2c1718..b5b7b22cec9 100644
  extern enum pipeline_type microblaze_pipe;
  
  #define OBJECT_FORMAT_ELF
-@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
- 
+@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe;
  /* Do we have CLZ?  */
  #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
-+#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
  
++#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
  /* The default is to support PIC.  */
  #define TARGET_SUPPORTS_PIC 1
+ 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index c407a81c51e..fa6aabdb9d4 100644
+index c407a81c51e..3e6e2b9276d 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -982,6 +982,8 @@
@@ -72,7 +91,7 @@ index c407a81c51e..fa6aabdb9d4 100644
 +       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 +                        (match_operand:SI 2 "immediate_operand" "I")
 +                        (match_operand:SI 3 "immediate_operand" "I")))]
-+"TARGET_HAS_BITFIELD"
++""
 +"
 +{
 +  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
@@ -98,7 +117,7 @@ index c407a81c51e..fa6aabdb9d4 100644
 +       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 +                        (match_operand:SI 2 "immediate_operand" "I")
 +                        (match_operand:SI 3 "immediate_operand" "I")))]
-+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
++ "TARGET_BARREL_SHIFT && (UINTVAL (operands[2]) > 0)
 +   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
 +  "bsefi %0,%1,%2,%3"
 +  [(set_attr "type" "bshift")
@@ -109,7 +128,7 @@ index c407a81c51e..fa6aabdb9d4 100644
 +                        (match_operand:SI 1 "immediate_operand" "I")
 +                        (match_operand:SI 2 "immediate_operand" "I"))
 +       (match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD"
++ ""
 +  "
 +{
 +  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
@@ -131,7 +150,7 @@ index c407a81c51e..fa6aabdb9d4 100644
 +                        (match_operand:SI 1 "immediate_operand" "I")
 +                        (match_operand:SI 2 "immediate_operand" "I"))
 +       (match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
++ "TARGET_BARREL_SHIFT && UINTVAL (operands[1]) > 0
 +   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
 +  "bsifi %0, %3, %1, %2"
 +  [(set_attr "type" "bshift")
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
index bb773239..da24f113 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
@@ -1,20 +1,18 @@
-From df38540af411564f428079335c8d1e695dc1d723 Mon Sep 17 00:00:00 2001
+From cb67b2e64c0d5bd32d36cb32def5f889122fc37a Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:42:10 +0530
-Subject: [PATCH 30/58] [Patch, microblaze]: Fix bug in MB version calculation
-
-This patch fixes the bug in microblaze_version_to_int function.
-Earlier the conversion of vXX.YY.Z to int has a bug which is
-fixed now.
+Subject: [PATCH 25/54] [Patch, microblaze]: Fix bug in MB version calculation
+ This patch fixes the bug in microblaze_version_to_int function. Earlier the
+ conversion of vXX.YY.Z to int has a bug which is fixed now.
 
 Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
                 Nagaraju Mekala <nmekala@xilix.com>
 ---
- gcc/config/microblaze/microblaze.c | 145 ++++++++++++++---------------
- 1 file changed, 69 insertions(+), 76 deletions(-)
+ gcc/config/microblaze/microblaze.c | 147 ++++++++++++++---------------
+ 1 file changed, 70 insertions(+), 77 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0a73a6c32b4..4b5699671e8 100644
+index 14c652325a8..451db9c79b0 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -242,6 +242,63 @@ section *sdata2_section;
@@ -101,7 +99,7 @@ index 0a73a6c32b4..4b5699671e8 100644
               *total = COSTS_N_INSNS (1);
             else
               *total = COSTS_N_INSNS (3);
-@@ -1677,65 +1732,6 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
+@@ -1677,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
    return 0;
  }
  
@@ -167,6 +165,14 @@ index 0a73a6c32b4..4b5699671e8 100644
  static void
  microblaze_option_override (void)
  {
+   register int i, start;
+   register int regno;
+   register machine_mode mode;
+-  int ver;
++  int ver,ver_int;
+ 
+   microblaze_section_threshold = (global_options_set.x_g_switch_value
+                                  ? g_switch_value
 @@ -1763,13 +1759,13 @@ microblaze_option_override (void)
    /* Check the MicroBlaze CPU version for any special action to be done.  */
    if (microblaze_select_cpu == NULL)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch
deleted file mode 100644
index f1b793f3..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From eca67041b3d6e20663313732df0038d75fd2da8d Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:08:40 +0530
-Subject: [PATCH 25/58] [Patch,rtl Optimization]: Better register pressure
- estimate for loop invariant code motion
-
-Calculate the loop liveness used for regs for calculating the register pressure
-in the cost estimation.  Loop liveness is based on the following properties.
-We only need to find the set of objects that are live at the birth or the header
-of the loop. We don't need to calculate the live through the loop by considering
-live in and live out of all the basic blocks of the loop. This is based on the
-point that the set of objects that are live-in at the birth or header of the loop
-will be live-in at every node in the loop.
-
-If a v live is out at the header of the loop then the variable is live-in at every node
-in the loop. To prove this, consider a loop L with header h such that the variable v
-defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i
-from the dominance property, i.e. h is strictly dominated by d. Furthermore, there
-exists a path from h to a use of v which does not go through d. For every node p in
-the loop, since the loop is strongly connected and node is a component of the CFG,
-there exists a path, consisting only of nodes of L from p to h. Concatenating these
-two paths proves that v is live-in and live-out of p.
-
-Calculate the live-out and live-in for the exit edge of the loop. This patch considers
-liveness for not only the loop latch but also the liveness outside the loops.
-
-ChangeLog:
-2016-01-22  Ajit Agarwal  <ajitkum@xilinx.com>
-
-        * loop-invariant.c
-        (find_invariants_to_move): Add the logic of regs_used based
-        on liveness.
-        * cfgloopanal.c
-        (estimate_reg_pressure_cost): Update the heuristics in presence
-        of call_p.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
----
- gcc/cfgloopanal.c    |  4 ++-
- gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++-----------
- 2 files changed, 50 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
-index 0b33e8272a7..7be8606e4f0 100644
---- a/gcc/cfgloopanal.c
-+++ b/gcc/cfgloopanal.c
-@@ -418,7 +418,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
-   if (regs_needed + target_res_regs <= available_regs)
-     return 0;
- 
--  if (regs_needed <= available_regs)
-+  if ((regs_needed <= available_regs)
-+      || (call_p && (regs_needed <=
-+          (available_regs + target_clobbered_regs))))
-     /* If we are close to running out of registers, try to preserve
-        them.  */
-     cost = target_reg_cost [speed] * n_new;
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index f6385d6cf43..8596b5c984d 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
-        size_cost = 0;
-     }
- 
--  return comp_cost - size_cost;
-+  return comp_cost - size_cost + 1;
- }
- 
- /* Finds invariant with best gain for moving.  Returns the gain, stores
-@@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p)
-     /* REGS_USED is actually never used when the flag is on.  */
-     regs_used = 0;
-   else
--    /* We do not really do a good job in estimating number of
--       registers used; we put some initial bound here to stand for
--       induction variables etc.  that we do not detect.  */
-+    /* The logic used in estimating the number of regs_used is changed.
-+       Now it will be based on liveness of the loop. */
-     {
--      unsigned int n_regs = DF_REG_SIZE (df);
--
--      regs_used = 2;
--
--      for (i = 0; i < n_regs; i++)
--       {
--         if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i))
--           {
--             /* This is a value that is used but not changed inside loop.  */
--             regs_used++;
--           }
--       }
-+      int  i;
-+      edge e;
-+      vec<edge> edges;
-+      bitmap_head regs_live;
-+
-+      bitmap_initialize (&regs_live, &reg_obstack);
-+      edges = get_loop_exit_edges (curr_loop);
-+
-+      /* Loop liveness is based on the following properties.
-+         We only need to find the set of objects that are live at the
-+         birth or the header of the loop.
-+         We don't need to calculate the live through the loop considering
-+         live-in and live-out of all the basic blocks of the loop. This is
-+         based on the point that the set of objects that are live-in at the
-+         birth or header of the loop will be live-in at every block in the
-+         loop.
-+
-+         If a v live out at the header of the loop then the variable is
-+         live-in at every node in the Loop. To prove this, consider a loop
-+         L with header h such that the variable v defined at d is live-in
-+         at h. Since v is live at h, d is not part of L. This follows from
-+         the dominance property, i.e. h is strictly dominated by d. Furthermore,
-+         there exists a path from h to a use of v which does not go through d.
-+         For every node of the loop, p, since the loop is strongly connected
-+         component of the CFG, there exists a path, consisting only of nodes
-+         of L from p to h. Concatenating these two paths prove that v is
-+         live-in and live-out of p.  */
-+
-+       bitmap_ior_into (&regs_live, DF_LR_IN (curr_loop->header));
-+       bitmap_ior_into (&regs_live, DF_LR_OUT (curr_loop->header));
-+
-+       /* Calculate the live-out and live-in for the exit edge of the loop.
-+          This considers liveness for not only the loop latch but also the
-+          liveness outside the loops.  */
-+
-+       FOR_EACH_VEC_ELT (edges, i, e)
-+         {
-+           bitmap_ior_into (&regs_live, DF_LR_OUT (e->src));
-+           bitmap_ior_into (&regs_live, DF_LR_IN (e->dest));
-+         }
-+
-+       regs_used = bitmap_count_bits (&regs_live) + 2;
-+       bitmap_clear (&regs_live);
-+       edges.release ();
-     }
- 
-   if (! flag_ira_loop_pressure)
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch
index 0c80cf81..c0719f6e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -1,10 +1,9 @@
-From 87da245d89fffe6a025037b4a53f66dafa7e1f84 Mon Sep 17 00:00:00 2001
+From fdb2f23a69182da516c7bf89a9e0011e55120f94 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 23 Feb 2017 17:09:04 +0530
-Subject: [PATCH 31/58] Fixing the issue with the builtin_alloc.
-
-register r18 was not properly handling the stack pattern
-which was resolved by using free available register
+Subject: [PATCH 26/54] Fixing the issue with the builtin_alloc. register r18
+ was not properly handling the stack pattern which was resolved by using free
+ available register
 
 signed-off-by:nagaraju mekala <nmekala@xilinx.com>
 ---
@@ -12,7 +11,7 @@ signed-off-by:nagaraju mekala <nmekala@xilinx.com>
  1 file changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fa6aabdb9d4..9de46d0ce24 100644
+index 3e6e2b9276d..d938efcd762 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -2078,10 +2078,10 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch
deleted file mode 100644
index cbc1b7b8..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 711652dd187e5b8d7aa12ecc9f569f10b1521bd1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:25:48 +0530
-Subject: [PATCH 26/58] [Patch, microblaze]: Correct the const high double
- immediate value
-
-With this patch the loading of the DI mode immediate values will be
-using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
-functions, as CONST_DOUBLE_HIGH was returning the sign extension value
-even of the unsigned long long constants also
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
- *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
-        REAL_VALUE_TO_TARGET_DOUBLE
- *long.c (new): Added new testcase
----
- gcc/config/microblaze/microblaze.c         |  6 ++++--
- gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
- 2 files changed, 14 insertions(+), 2 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a3996119bd7..73d0e010cda 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2587,14 +2587,16 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
-+      long l[2];
-       if (code == CONST_DOUBLE)
-        {
-          if (GET_MODE (op) == DFmode)
-            REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-          else
-            {
--             val[0] = CONST_DOUBLE_HIGH (op);
--             val[1] = CONST_DOUBLE_LOW (op);
-+              REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-+              val[1] = l[WORDS_BIG_ENDIAN == 0];
-+              val[0] = l[WORDS_BIG_ENDIAN != 0];
-            }
-        }
-       else if (code == CONST_INT)
-diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
-new file mode 100644
-index 00000000000..4d4518619d1
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/microblaze/long.c
-@@ -0,0 +1,10 @@
-+/* { dg-options "-O0" } */
-+#define BASEADDR 0xF0000000ULL
-+int main ()
-+{
-+  unsigned long long start;
-+  start = (unsigned long long) BASEADDR;
-+  return 0;
-+}
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
index 458af563..7627b765 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
@@ -1,15 +1,17 @@
-From 3e8779308d1901b273b2b360bea719aa72d24ab9 Mon Sep 17 00:00:00 2001
+From 336d984c580345eccdeb889af8ef8c986afc1dad Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 19 Feb 2018 18:06:16 +0530
-Subject: [PATCH 32/58] [Patch,Microblaze]: update in constraints for bitfield
+Subject: [PATCH 27/54] [Patch,Microblaze]: update in constraints for bitfield
  insert and extract instructions.
 
+Conflicts:
+        gcc/config/microblaze/microblaze.md
 ---
- gcc/config/microblaze/microblaze.md | 43 +++++------------------------
- 1 file changed, 7 insertions(+), 36 deletions(-)
+ gcc/config/microblaze/microblaze.md | 45 +++++------------------------
+ 1 file changed, 8 insertions(+), 37 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 9de46d0ce24..fe94807182b 100644
+index d938efcd762..63ad94b972f 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -2492,33 +2492,17 @@
@@ -22,7 +24,8 @@ index 9de46d0ce24..fe94807182b 100644
         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
                          (match_operand:SI 2 "immediate_operand" "I")
                          (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
++"TARGET_HAS_BITFIELD"
+ ""
 -"
 -{
 -  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
@@ -42,7 +45,6 @@ index 9de46d0ce24..fe94807182b 100644
 -                         operands[2], operands[3]));
 -  DONE;
 -}")
-+""
 +)
  
 -(define_insn "extv_32"
@@ -51,10 +53,11 @@ index 9de46d0ce24..fe94807182b 100644
    [(set (match_operand:SI 0 "register_operand" "=r")
         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
                          (match_operand:SI 2 "immediate_operand" "I")
-@@ -2535,21 +2519,8 @@
+@@ -2534,22 +2518,9 @@
+                         (match_operand:SI 1 "immediate_operand" "I")
                          (match_operand:SI 2 "immediate_operand" "I"))
         (match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
+- ""
 -  "
 -{
 -  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
@@ -70,6 +73,7 @@ index 9de46d0ce24..fe94807182b 100644
 -                         operands[2], operands[3]));
 -  DONE;
 -}")
++ "TARGET_HAS_BITFIELD"
 +""
 +)
  
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
index 32433470..f12cea24 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -1,7 +1,7 @@
-From eb90da1d616dfb7481b3f7c74a2be40e921a24f2 Mon Sep 17 00:00:00 2001
+From e4f5435e6e77afe0150bf36ec9d3d055cf25a089 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 4 Jun 2018 10:10:18 +0530
-Subject: [PATCH 33/58] [Patch,Microblaze] : Removed fsqrt generation for
+Subject: [PATCH 28/54] [Patch,Microblaze] : Removed fsqrt generation for
  double values.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 33/58] [Patch,Microblaze] : Removed fsqrt generation for
  1 file changed, 14 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fe94807182b..a527da70f8a 100644
+index 63ad94b972f..7695b105baa 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -526,20 +526,6 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
index acf14b23..d9603721 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
@@ -1,24 +1,23 @@
-From 9600049313b095d6d7d8ea46a7ab783fabae71a2 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 3 Apr 2018 16:48:39 +0530
-Subject: [PATCH 34/58] Intial commit of 64-bit Microblaze
+From 1a7fda96cb247bad0a4df61cd8fd3e65c0e6f35d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 10 Nov 2020 12:52:54 +0530
+Subject: [PATCH 29/54] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze
 
-Added load store pattern movdi and also adding missing files
 ---
- gcc/config/microblaze/constraints.md      |   5 +
+ gcc/config/microblaze/constraints.md      |   6 +
  gcc/config/microblaze/microblaze-protos.h |   1 +
  gcc/config/microblaze/microblaze.c        | 109 ++++--
  gcc/config/microblaze/microblaze.h        |   4 +-
- gcc/config/microblaze/microblaze.md       | 394 +++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.md       | 395 +++++++++++++++++++++-
  gcc/config/microblaze/microblaze.opt      |   7 +-
  gcc/config/microblaze/t-microblaze        |   7 +-
- 7 files changed, 490 insertions(+), 37 deletions(-)
+ 7 files changed, 492 insertions(+), 37 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index b9fc6e3fae2..f636b035280 100644
+index b9fc6e3fae2..123395717e0 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
-@@ -52,6 +52,11 @@
+@@ -52,6 +52,12 @@
    (and (match_code "const_int")
         (match_test "ival > 0 && ival < 0x10000")))
  
@@ -27,11 +26,12 @@ index b9fc6e3fae2..f636b035280 100644
 +  (and (match_code "const_int")
 +       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
 +
++
  ;; Define floating point constraints
  
  (define_constraint "G"
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 76ffc682df2..b8a3321dbdf 100644
+index c2f88813a8d..460feac4ac5 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
 @@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
@@ -43,10 +43,10 @@ index 76ffc682df2..b8a3321dbdf 100644
  extern void print_operand (FILE *, rtx, int);
  extern void print_operand_address (FILE *, rtx);
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 4b5699671e8..8a3ccae558a 100644
+index 451db9c79b0..99a1cd5c0be 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3562,11 +3562,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+@@ -3432,11 +3432,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
    op0 = operands[0];
    op1 = operands[1];
  
@@ -61,7 +61,7 @@ index 4b5699671e8..8a3ccae558a 100644
        emit_move_insn (op0, temp);
        return true;
      }
-@@ -3631,12 +3631,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+@@ -3501,12 +3501,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
                   && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
                       || !SMALL_INT (p1)))))
         {
@@ -76,7 +76,7 @@ index 4b5699671e8..8a3ccae558a 100644
           return true;
         }
      }
-@@ -3767,7 +3767,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3637,7 +3637,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
    rtx cmp_op0 = operands[1];
    rtx cmp_op1 = operands[2];
    rtx label1 = operands[3];
@@ -85,7 +85,7 @@ index 4b5699671e8..8a3ccae558a 100644
    rtx condition;
  
    gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
-@@ -3776,23 +3776,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3646,23 +3646,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
    if (cmp_op1 == const0_rtx)
      {
        comp_reg = cmp_op0;
@@ -128,7 +128,7 @@ index 4b5699671e8..8a3ccae558a 100644
      }
  }
  
-@@ -3803,7 +3816,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3673,7 +3686,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
    rtx cmp_op0 = operands[1];
    rtx cmp_op1 = operands[2];
    rtx label1 = operands[3];
@@ -137,7 +137,7 @@ index 4b5699671e8..8a3ccae558a 100644
    rtx condition;
  
    gcc_assert ((GET_CODE (cmp_op0) == REG)
-@@ -3814,30 +3827,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3684,30 +3697,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code),
@@ -213,7 +213,7 @@ index 4b5699671e8..8a3ccae558a 100644
      }
  }
  
-@@ -3854,6 +3900,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+@@ -3724,6 +3770,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
    emit_jump_insn (gen_condjump (condition, operands[3]));
  }
  
@@ -234,7 +234,7 @@ index 4b5699671e8..8a3ccae558a 100644
  
  static bool
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index b5b7b22cec9..4931895e650 100644
+index 857cb1cd9d0..c0358603380 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
@@ -263,7 +263,7 @@ index b5b7b22cec9..4931895e650 100644
  #define FLOAT_TYPE_SIZE         32
  #define DOUBLE_TYPE_SIZE        64
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a527da70f8a..bcf2b9244f8 100644
+index 7695b105baa..4d8429d9a90 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -497,7 +497,6 @@
@@ -456,7 +456,7 @@ index a527da70f8a..bcf2b9244f8 100644
  ;; Those for integer source operand are ordered
  ;; widest source type first.
  
-@@ -1011,6 +1122,31 @@
+@@ -1011,6 +1122,32 @@
  )
  
  
@@ -485,10 +485,11 @@ index a527da70f8a..bcf2b9244f8 100644
 +  [(set_attr "type"    "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
 +  (set_attr "mode"     "DI")
 +  (set_attr "length"   "8,8,8,8,12,8,12")])
++
  
  (define_insn "*movdi_internal"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
-@@ -1423,6 +1559,36 @@
+@@ -1423,6 +1560,36 @@
    (set_attr "length"   "4,4")]
  )
  
@@ -525,7 +526,7 @@ index a527da70f8a..bcf2b9244f8 100644
  ;; The following patterns apply when there is no barrel shifter present
  
  (define_insn "*ashlsi3_with_mul_delay"
-@@ -1548,6 +1714,36 @@
+@@ -1548,6 +1715,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts
  ;;----------------------------------------------------------------
@@ -562,7 +563,7 @@ index a527da70f8a..bcf2b9244f8 100644
  (define_expand "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -1657,6 +1853,36 @@
+@@ -1657,6 +1854,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts (logical)
  ;;----------------------------------------------------------------
@@ -599,7 +600,7 @@ index a527da70f8a..bcf2b9244f8 100644
  
  (define_expand "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
-@@ -1803,6 +2029,8 @@
+@@ -1803,6 +2030,8 @@
    (set_attr "length"   "4")]
  )              
  
@@ -608,7 +609,7 @@ index a527da70f8a..bcf2b9244f8 100644
  ;;----------------------------------------------------------------
  ;; Setting a register from an floating point comparison. 
  ;;----------------------------------------------------------------
-@@ -1818,6 +2046,18 @@
+@@ -1818,6 +2047,18 @@
     (set_attr "length"    "4")]
  )
  
@@ -627,7 +628,7 @@ index a527da70f8a..bcf2b9244f8 100644
  ;;----------------------------------------------------------------
  ;; Conditional branches
  ;;----------------------------------------------------------------
-@@ -1930,6 +2170,115 @@
+@@ -1930,6 +2171,115 @@
     (set_attr "length"   "12")]
  )
  
@@ -743,7 +744,7 @@ index a527da70f8a..bcf2b9244f8 100644
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
-@@ -2478,17 +2827,33 @@
+@@ -2478,17 +2828,33 @@
    DONE;
  }")
  
@@ -782,7 +783,7 @@ index a527da70f8a..bcf2b9244f8 100644
    [(set (match_operand:SI 0 "register_operand" "=r")
         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
                          (match_operand:SI 2 "immediate_operand" "I")
-@@ -2505,8 +2870,21 @@
+@@ -2505,8 +2871,21 @@
                          (match_operand:SI 2 "immediate_operand" "I"))
         (match_operand:SI 3 "register_operand" "r"))]
   "TARGET_HAS_BITFIELD"
@@ -822,7 +823,7 @@ index a29c6f8df90..bbe48b06da6 100644
 +MicroBlaze 64-bit mode.
 +
 diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 41fa9a92081..7671f63c5b5 100644
+index 41fa9a92081..e9a1921ae26 100644
 --- a/gcc/config/microblaze/t-microblaze
 +++ b/gcc/config/microblaze/t-microblaze
 @@ -1,8 +1,11 @@
@@ -834,8 +835,8 @@ index 41fa9a92081..7671f63c5b5 100644
  MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
 +MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
  MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
-+#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
  
  # Extra files
  microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch
index e7872d54..88a0d0ba 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch
@@ -1,16 +1,16 @@
-From 8660e76d664ee4b42a83a4c15344b072d3c879df Mon Sep 17 00:00:00 2001
+From 53799d63bd26a04265a55f68ca57e3462ed6eeb7 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 27 Jul 2018 15:23:41 +0530
-Subject: [PATCH 35/58] Intial commit for 64bit-MB sources.
+Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
+ code later.
 
-Need to cleanup the code later.
 ---
  gcc/config/microblaze/constraints.md    |   2 +-
  gcc/config/microblaze/microblaze-c.c    |   6 +
  gcc/config/microblaze/microblaze.c      | 218 ++++++---
  gcc/config/microblaze/microblaze.h      |  63 ++-
  gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++------
- gcc/config/microblaze/t-microblaze      |   7 +-
+ gcc/config/microblaze/t-microblaze      |   3 +-
  libgcc/config/microblaze/crti.S         |   4 +-
  libgcc/config/microblaze/crtn.S         |   4 +-
  libgcc/config/microblaze/divdi3.S       |  98 ++++
@@ -20,7 +20,7 @@ Need to cleanup the code later.
  libgcc/config/microblaze/t-microblaze   |  11 +-
  libgcc/config/microblaze/udivdi3.S      | 107 +++++
  libgcc/config/microblaze/umoddi3.S      | 110 +++++
- 15 files changed, 1232 insertions(+), 236 deletions(-)
+ 15 files changed, 1230 insertions(+), 234 deletions(-)
  create mode 100644 libgcc/config/microblaze/divdi3.S
  create mode 100644 libgcc/config/microblaze/divdi3_table.c
  create mode 100644 libgcc/config/microblaze/moddi3.S
@@ -29,7 +29,7 @@ Need to cleanup the code later.
  create mode 100644 libgcc/config/microblaze/umoddi3.S
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index f636b035280..c2b0a21c53b 100644
+index 123395717e0..b8ef1650f92 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -39,8 +39,8 @@ index f636b035280..c2b0a21c53b 100644
 -       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
 +       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
  
- ;; Define floating point constraints
  
+ ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
 index d8c88e510e5..dbcd21fc6ee 100644
 --- a/gcc/config/microblaze/microblaze-c.c
@@ -57,7 +57,7 @@ index d8c88e510e5..dbcd21fc6ee 100644
 +    }
  }  
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 8a3ccae558a..3ecda553fe6 100644
+index 99a1cd5c0be..3c815444574 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
@@ -141,7 +141,7 @@ index 8a3ccae558a..3ecda553fe6 100644
        break;
  
      case E_QImode:
-@@ -2285,7 +2299,7 @@ compute_frame_size (HOST_WIDE_INT size)
+@@ -2155,7 +2169,7 @@ compute_frame_size (HOST_WIDE_INT size)
  
           if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
             /* Don't account for link register. It is accounted specially below.  */
@@ -150,7 +150,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  
           mask |= (1L << (regno - GP_REG_FIRST));
         }
-@@ -2554,7 +2568,7 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2424,7 +2438,7 @@ print_operand (FILE * file, rtx op, int letter)
  
        if ((letter == 'M' && !WORDS_BIG_ENDIAN)
           || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
@@ -159,7 +159,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  
        fprintf (file, "%s", reg_names[regnum]);
      }
-@@ -2580,6 +2594,7 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2450,6 +2464,7 @@ print_operand (FILE * file, rtx op, int letter)
    else if (letter == 'h' || letter == 'j')
      {
        long val[2];
@@ -167,8 +167,8 @@ index 8a3ccae558a..3ecda553fe6 100644
        long l[2];
        if (code == CONST_DOUBLE)
         {
-@@ -2592,12 +2607,12 @@ print_operand (FILE * file, rtx op, int letter)
-               val[0] = l[WORDS_BIG_ENDIAN != 0];
+@@ -2462,12 +2477,12 @@ print_operand (FILE * file, rtx op, int letter)
+              val[0] = l[WORDS_BIG_ENDIAN != 0];
             }
         }
 -      else if (code == CONST_INT)
@@ -184,7 +184,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      }
    else if (code == CONST_DOUBLE)
      {
-@@ -2791,7 +2806,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
+@@ -2661,7 +2676,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
  
      switch_to_section (get_section (section, 0, NULL));
      assemble_align (POINTER_SIZE);
@@ -196,7 +196,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      output_addr_const (asm_out_file, symbol);
      fputs ("\n", asm_out_file);
  }
-@@ -2814,7 +2832,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
+@@ -2684,7 +2702,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
  
      switch_to_section (get_section (section, 0, NULL));
      assemble_align (POINTER_SIZE);
@@ -208,7 +208,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      output_addr_const (asm_out_file, symbol);
      fputs ("\n", asm_out_file);
  }
-@@ -2880,7 +2901,7 @@ save_restore_insns (int prologue)
+@@ -2750,7 +2771,7 @@ save_restore_insns (int prologue)
    /* For interrupt_handlers, need to save/restore the MSR.  */
    if (microblaze_is_interrupt_variant ())
      {
@@ -217,7 +217,7 @@ index 8a3ccae558a..3ecda553fe6 100644
                                  gen_rtx_PLUS (Pmode, base_reg_rtx,
                                                GEN_INT (current_frame_info.
                                                         gp_offset -
-@@ -2888,8 +2909,8 @@ save_restore_insns (int prologue)
+@@ -2758,8 +2779,8 @@ save_restore_insns (int prologue)
  
        /* Do not optimize in flow analysis.  */
        MEM_VOLATILE_P (isr_mem_rtx) = 1;
@@ -228,7 +228,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      }
  
    if (microblaze_is_interrupt_variant () && !prologue)
-@@ -2897,8 +2918,8 @@ save_restore_insns (int prologue)
+@@ -2767,8 +2788,8 @@ save_restore_insns (int prologue)
        emit_move_insn (isr_reg_rtx, isr_mem_rtx);
        emit_move_insn (isr_msr_rtx, isr_reg_rtx);
        /* Do not optimize in flow analysis.  */
@@ -239,7 +239,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      }
  
    for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-@@ -2909,9 +2930,9 @@ save_restore_insns (int prologue)
+@@ -2779,9 +2800,9 @@ save_restore_insns (int prologue)
             /* Don't handle here. Already handled as the first register.  */
             continue;
  
@@ -251,7 +251,7 @@ index 8a3ccae558a..3ecda553fe6 100644
           if (microblaze_is_interrupt_variant () || save_volatiles)
             /* Do not optimize in flow analysis.  */
             MEM_VOLATILE_P (mem_rtx) = 1;
-@@ -2926,7 +2947,7 @@ save_restore_insns (int prologue)
+@@ -2796,7 +2817,7 @@ save_restore_insns (int prologue)
               insn = emit_move_insn (reg_rtx, mem_rtx);
             }
  
@@ -260,7 +260,7 @@ index 8a3ccae558a..3ecda553fe6 100644
         }
      }
  
-@@ -2936,8 +2957,8 @@ save_restore_insns (int prologue)
+@@ -2806,8 +2827,8 @@ save_restore_insns (int prologue)
        emit_move_insn (isr_mem_rtx, isr_reg_rtx);
  
        /* Do not optimize in flow analysis.  */
@@ -271,7 +271,7 @@ index 8a3ccae558a..3ecda553fe6 100644
      }
  
    /* Done saving and restoring */
-@@ -3027,7 +3048,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
+@@ -2897,7 +2918,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
  
    switch_to_section (s);
    assemble_align (POINTER_SIZE);
@@ -283,7 +283,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    output_addr_const (asm_out_file, symbol);
    fputs ("\n", asm_out_file);
  }
-@@ -3171,10 +3195,10 @@ microblaze_expand_prologue (void)
+@@ -3041,10 +3065,10 @@ microblaze_expand_prologue (void)
         {
           if (offset != 0)
             ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
@@ -297,7 +297,7 @@ index 8a3ccae558a..3ecda553fe6 100644
         }
      }
  
-@@ -3183,15 +3207,23 @@ microblaze_expand_prologue (void)
+@@ -3053,15 +3077,23 @@ microblaze_expand_prologue (void)
        rtx fsiz_rtx = GEN_INT (fsiz);
  
        rtx_insn *insn = NULL;
@@ -323,7 +323,7 @@ index 8a3ccae558a..3ecda553fe6 100644
                                  gen_rtx_PLUS (Pmode, stack_pointer_rtx,
                                                const0_rtx));
  
-@@ -3199,7 +3231,7 @@ microblaze_expand_prologue (void)
+@@ -3069,7 +3101,7 @@ microblaze_expand_prologue (void)
             /* Do not optimize in flow analysis.  */
             MEM_VOLATILE_P (mem_rtx) = 1;
  
@@ -332,7 +332,7 @@ index 8a3ccae558a..3ecda553fe6 100644
           insn = emit_move_insn (mem_rtx, reg_rtx);
           RTX_FRAME_RELATED_P (insn) = 1;
         }
-@@ -3309,12 +3341,12 @@ microblaze_expand_epilogue (void)
+@@ -3179,12 +3211,12 @@ microblaze_expand_epilogue (void)
        if (!crtl->is_leaf || interrupt_handler)
         {
           mem_rtx =
@@ -347,7 +347,7 @@ index 8a3ccae558a..3ecda553fe6 100644
           emit_move_insn (reg_rtx, mem_rtx);
         }
  
-@@ -3330,15 +3362,25 @@ microblaze_expand_epilogue (void)
+@@ -3200,15 +3232,25 @@ microblaze_expand_epilogue (void)
        /* _restore_ registers for epilogue.  */
        save_restore_insns (0);
        emit_insn (gen_blockage ());
@@ -377,7 +377,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
                                                     MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  }
-@@ -3505,9 +3547,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3375,9 +3417,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
    else
      this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
  
@@ -394,7 +394,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  
    /* Apply the offset from the vtable, if required.  */
    if (vcall_offset)
-@@ -3520,7 +3567,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3390,7 +3437,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
      rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
      emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
  
@@ -406,7 +406,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    }
  
    /* Generate a tail call to the target function.  */
-@@ -3696,7 +3746,7 @@ microblaze_eh_return (rtx op0)
+@@ -3566,7 +3616,7 @@ microblaze_eh_return (rtx op0)
  /* Queue an .ident string in the queue of top-level asm statements.
     If the string size is below the threshold, put it into .sdata2.
     If the front-end is done, we must be being called from toplev.c.
@@ -415,7 +415,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  void 
  microblaze_asm_output_ident (const char *string)
  {
-@@ -3751,9 +3801,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+@@ -3621,9 +3671,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
    emit_block_move (m_tramp, assemble_trampoline_template (),
                    GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
  
@@ -427,7 +427,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    emit_move_insn (mem, fnaddr);
  }
  
-@@ -3777,7 +3827,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3647,7 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -436,7 +436,7 @@ index 8a3ccae558a..3ecda553fe6 100644
          emit_jump_insn (gen_condjump (condition, label1));
        else
          emit_jump_insn (gen_long_condjump (condition, label1));
-@@ -3896,7 +3946,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+@@ -3766,7 +3816,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
    rtx comp_reg = gen_reg_rtx (SImode);
  
    emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
@@ -445,7 +445,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    emit_jump_insn (gen_condjump (condition, operands[3]));
  }
  
-@@ -3906,10 +3956,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+@@ -3776,10 +3826,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
    rtx condition;
    rtx cmp_op0 = XEXP (operands[0], 0);
    rtx cmp_op1 = XEXP (operands[0], 1);
@@ -458,7 +458,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    emit_jump_insn (gen_long_condjump (condition, operands[3]));
  }
  
-@@ -3930,8 +3980,8 @@ microblaze_expand_divide (rtx operands[])
+@@ -3800,8 +3850,8 @@ microblaze_expand_divide (rtx operands[])
  {
    /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
  
@@ -469,7 +469,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    rtx regqi = gen_reg_rtx (QImode);
    rtx_code_label *div_label = gen_label_rtx ();
    rtx_code_label *div_end_label = gen_label_rtx ();
-@@ -3939,17 +3989,31 @@ microblaze_expand_divide (rtx operands[])
+@@ -3809,17 +3859,31 @@ microblaze_expand_divide (rtx operands[])
    rtx mem_rtx;
    rtx ret;
    rtx_insn *jump, *cjump, *insn;
@@ -508,7 +508,7 @@ index 8a3ccae558a..3ecda553fe6 100644
    mem_rtx = gen_rtx_MEM (QImode,
                              gen_rtx_PLUS (QImode, regt1, div_table_rtx));
  
-@@ -4096,7 +4160,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+@@ -3966,7 +4030,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
                {
                  insn =
                    emit_insn_before (gen_iprefetch
@@ -517,7 +517,7 @@ index 8a3ccae558a..3ecda553fe6 100644
                                      before_4);
                  recog_memoized (insn);
                  INSN_LOCATION (insn) = INSN_LOCATION (before_4);
-@@ -4106,7 +4170,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+@@ -3976,7 +4040,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
             }
         }
  }
@@ -546,7 +546,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  /* Insert instruction prefetch instruction at the fall
     through path of the function call.  */
  
-@@ -4259,6 +4343,17 @@ microblaze_starting_frame_offset (void)
+@@ -4129,6 +4213,17 @@ microblaze_starting_frame_offset (void)
  #undef TARGET_LRA_P
  #define TARGET_LRA_P hook_bool_void_false
  
@@ -564,7 +564,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  #undef TARGET_FRAME_POINTER_REQUIRED
  #define TARGET_FRAME_POINTER_REQUIRED  microblaze_frame_pointer_required
  
-@@ -4268,6 +4363,9 @@ microblaze_starting_frame_offset (void)
+@@ -4138,6 +4233,9 @@ microblaze_starting_frame_offset (void)
  #undef  TARGET_TRAMPOLINE_INIT
  #define TARGET_TRAMPOLINE_INIT         microblaze_trampoline_init
  
@@ -575,7 +575,7 @@ index 8a3ccae558a..3ecda553fe6 100644
  #define TARGET_PROMOTE_FUNCTION_MODE   default_promote_function_mode_always_promote
  
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 4931895e650..1f6e2059545 100644
+index c0358603380..f6ad4d9fc21 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
@@ -672,9 +672,9 @@ index 4931895e650..1f6e2059545 100644
  #define ARG_POINTER_CFA_OFFSET(FNDECL)         0
 +#define DWARF_CIE_DATA_ALIGNMENT -1
  
- #define REG_PARM_STACK_SPACE(FNDECL)            microblaze_reg_parm_stack_space(FNDECL)
+ #define REG_PARM_STACK_SPACE(FNDECL)           (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
  
- #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
+ #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
  
 -#define STACK_BOUNDARY                         32
 +#define STACK_BOUNDARY                         (TARGET_MB_64 ? 64 : 32)
@@ -744,7 +744,7 @@ index 4931895e650..1f6e2059545 100644
  /* Default to -G 8 */
  #ifndef MICROBLAZE_DEFAULT_GVALUE
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bcf2b9244f8..bef750c026a 100644
+index 4d8429d9a90..33a8b12ef3b 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -26,6 +26,7 @@
@@ -1054,7 +1054,7 @@ index bcf2b9244f8..bef750c026a 100644
  (define_insn "extendsidi2"
    [(set (match_operand:DI 0 "register_operand" "=d,d,d")
         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-@@ -1090,68 +1135,117 @@
+@@ -1090,69 +1135,118 @@
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
@@ -1200,6 +1200,7 @@ index bcf2b9244f8..bef750c026a 100644
 +  (set_attr "length"   "4,4,12,4,8,4,8")])
 +
  
+ 
  (define_insn "*movdi_internal"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
         (match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
@@ -1208,7 +1209,7 @@ index bcf2b9244f8..bef750c026a 100644
    { 
      switch (which_alternative)
      {
-@@ -1183,7 +1277,8 @@
+@@ -1184,7 +1278,8 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1218,7 +1219,7 @@ index bcf2b9244f8..bef750c026a 100644
  
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-@@ -1195,12 +1290,22 @@
+@@ -1196,12 +1291,22 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1242,7 +1243,7 @@ index bcf2b9244f8..bef750c026a 100644
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
-@@ -1272,6 +1377,8 @@
+@@ -1273,6 +1378,8 @@
    (set_attr "length"   "4,4,8,4,8,4,8")])
  
  
@@ -1251,7 +1252,7 @@ index bcf2b9244f8..bef750c026a 100644
  ;; 16-bit Integer moves
  
  ;; Unlike most other insns, the move insns can't be split with
-@@ -1304,8 +1411,8 @@
+@@ -1305,8 +1412,8 @@
    "@
     addik\t%0,r0,%1\t# %X1
     addk\t%0,%1,r0
@@ -1262,7 +1263,7 @@ index bcf2b9244f8..bef750c026a 100644
     sh%i0\t%z1,%0
     sh%i0\t%z1,%0"
    [(set_attr "type"    "arith,move,load,no_delay_load,store,no_delay_store")
-@@ -1348,7 +1455,7 @@
+@@ -1349,7 +1456,7 @@
     lbu%i1\t%0,%1
     lbu%i1\t%0,%1
     sb%i0\t%z1,%0
@@ -1271,7 +1272,7 @@ index bcf2b9244f8..bef750c026a 100644
    [(set_attr "type"    "arith,arith,move,load,no_delay_load,store,no_delay_store")
    (set_attr "mode"     "QI")
    (set_attr "length"   "4,4,8,4,8,4,8")])
-@@ -1421,7 +1528,7 @@
+@@ -1422,7 +1529,7 @@
     addik\t%0,r0,%F1
     lw%i1\t%0,%1
     sw%i0\t%z1,%0
@@ -1280,7 +1281,7 @@ index bcf2b9244f8..bef750c026a 100644
    [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
    (set_attr "mode"      "SF")
    (set_attr "length"    "4,4,4,4,4,4,4")])
-@@ -1460,6 +1567,33 @@
+@@ -1461,6 +1568,33 @@
  ;; movdf_internal
  ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
  ;;
@@ -1314,7 +1315,7 @@ index bcf2b9244f8..bef750c026a 100644
  (define_insn "*movdf_internal"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
          (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
-@@ -1494,7 +1628,8 @@
+@@ -1495,7 +1629,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1324,7 +1325,7 @@ index bcf2b9244f8..bef750c026a 100644
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
    "")
-@@ -1505,7 +1640,8 @@
+@@ -1506,7 +1641,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1334,7 +1335,7 @@ index bcf2b9244f8..bef750c026a 100644
    [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
    (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
    "")
-@@ -2005,6 +2141,31 @@ else
+@@ -2006,6 +2142,31 @@ else
    "
  )
  
@@ -1366,7 +1367,7 @@ index bcf2b9244f8..bef750c026a 100644
  (define_insn "seq_internal_pat" 
    [(set (match_operand:SI 0 "register_operand" "=d")
         (eq:SI 
-@@ -2065,8 +2226,8 @@ else
+@@ -2066,8 +2227,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1377,7 +1378,7 @@ index bcf2b9244f8..bef750c026a 100644
                        (label_ref (match_operand 3 ""))
                        (pc)))]
    ""
-@@ -2078,13 +2239,13 @@ else
+@@ -2079,13 +2240,13 @@ else
  (define_expand "cbranchsi4_reg"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1394,7 +1395,7 @@ index bcf2b9244f8..bef750c026a 100644
    DONE;
  })
  
-@@ -2109,6 +2270,26 @@ else
+@@ -2110,6 +2271,26 @@ else
                       (label_ref (match_operand 1))
                       (pc)))])
  
@@ -1421,7 +1422,7 @@ index bcf2b9244f8..bef750c026a 100644
  (define_insn "branch_zero"
    [(set (pc)
         (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-@@ -2129,6 +2310,47 @@ else
+@@ -2130,6 +2311,47 @@ else
     (set_attr "length"  "4")]
  )
  
@@ -1469,7 +1470,7 @@ index bcf2b9244f8..bef750c026a 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2312,7 +2534,7 @@ else
+@@ -2313,7 +2535,7 @@ else
  ;; Indirect jumps. Jump to register values. Assuming absolute jumps
  
  (define_insn "indirect_jump_internal1"
@@ -1478,7 +1479,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    "bra%?\t%0"
    [(set_attr "type"    "jump")
-@@ -2325,7 +2547,7 @@ else
+@@ -2326,7 +2548,7 @@ else
    (use (label_ref (match_operand 1 "" "")))]
    ""
    {
@@ -1487,7 +1488,7 @@ index bcf2b9244f8..bef750c026a 100644
  
      if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
        emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-@@ -2337,7 +2559,7 @@ else
+@@ -2338,7 +2560,7 @@ else
  
  (define_insn "tablejump_internal1"
    [(set (pc)
@@ -1496,7 +1497,7 @@ index bcf2b9244f8..bef750c026a 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2347,9 +2569,9 @@ else
+@@ -2348,9 +2570,9 @@ else
  
  (define_expand "tablejump_internal3"
    [(parallel [(set (pc)
@@ -1509,7 +1510,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    ""
  )
-@@ -2410,7 +2632,7 @@ else
+@@ -2411,7 +2633,7 @@ else
         (minus (reg 1) (match_operand 1 "register_operand" "")))
     (set (reg 1)
         (minus (reg 1) (match_dup 1)))]
@@ -1518,7 +1519,7 @@ index bcf2b9244f8..bef750c026a 100644
    { 
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx reg = gen_reg_rtx (Pmode);
-@@ -2435,7 +2657,7 @@ else
+@@ -2436,7 +2658,7 @@ else
  (define_expand "save_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1527,7 +1528,7 @@ index bcf2b9244f8..bef750c026a 100644
    {
      emit_move_insn (operands[0], operands[1]);
      DONE;
-@@ -2445,7 +2667,7 @@ else
+@@ -2446,7 +2668,7 @@ else
  (define_expand "restore_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1536,7 +1537,7 @@ index bcf2b9244f8..bef750c026a 100644
    {
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-@@ -2492,7 +2714,7 @@ else
+@@ -2493,7 +2715,7 @@ else
  
  (define_insn "<optab>_internal"
    [(any_return)
@@ -1545,7 +1546,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    {
      if (microblaze_is_break_handler ())
-@@ -2525,7 +2747,7 @@ else
+@@ -2526,7 +2748,7 @@ else
  (define_expand "call"
    [(parallel [(call (match_operand 0 "memory_operand" "m")
                     (match_operand 1 "" "i"))
@@ -1554,7 +1555,7 @@ index bcf2b9244f8..bef750c026a 100644
               (use (match_operand 2 "" ""))
               (use (match_operand 3 "" ""))])]
    ""
-@@ -2546,12 +2768,12 @@ else
+@@ -2547,12 +2769,12 @@ else
  
      if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
        emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
@@ -1569,7 +1570,7 @@ index bcf2b9244f8..bef750c026a 100644
                                      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
          DONE;
-@@ -2561,7 +2783,7 @@ else
+@@ -2562,7 +2784,7 @@ else
  (define_expand "call_internal0"
    [(parallel [(call (match_operand 0 "" "")
                     (match_operand 1 "" ""))
@@ -1578,7 +1579,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    {
    }
-@@ -2570,18 +2792,34 @@ else
+@@ -2571,18 +2793,34 @@ else
  (define_expand "call_internal_plt0"
    [(parallel [(call (match_operand 0 "" "")
                     (match_operand 1 "" ""))
@@ -1619,7 +1620,7 @@ index bcf2b9244f8..bef750c026a 100644
    "flag_pic"
    {
      register rtx target2 = gen_rtx_REG (Pmode, 
-@@ -2593,10 +2831,41 @@ else
+@@ -2594,10 +2832,41 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -1663,7 +1664,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    {
      register rtx target = operands[0];
-@@ -2630,7 +2899,7 @@ else
+@@ -2631,7 +2900,7 @@ else
    [(parallel [(set (match_operand 0 "register_operand" "=d")
                    (call (match_operand 1 "memory_operand" "m")
                          (match_operand 2 "" "i")))
@@ -1672,7 +1673,7 @@ index bcf2b9244f8..bef750c026a 100644
               (use (match_operand 3 "" ""))])] ;; next_arg_reg
    ""
    {
-@@ -2651,13 +2920,13 @@ else
+@@ -2652,13 +2921,13 @@ else
      if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
        emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
                         operands[2],
@@ -1688,7 +1689,7 @@ index bcf2b9244f8..bef750c026a 100644
                                      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
      DONE;
-@@ -2669,7 +2938,7 @@ else
+@@ -2670,7 +2939,7 @@ else
    [(parallel [(set (match_operand 0 "" "")
                    (call (match_operand 1 "" "")
                          (match_operand 2 "" "")))
@@ -1697,7 +1698,7 @@ index bcf2b9244f8..bef750c026a 100644
               ])]
    ""
    {}
-@@ -2679,18 +2948,35 @@ else
+@@ -2680,18 +2949,35 @@ else
    [(parallel[(set (match_operand 0 "" "")
                    (call (match_operand 1 "" "")
                          (match_operand 2 "" "")))
@@ -1739,7 +1740,7 @@ index bcf2b9244f8..bef750c026a 100644
    "flag_pic"
    { 
      register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-@@ -2702,11 +2988,46 @@ else
+@@ -2703,11 +2989,46 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -1788,7 +1789,7 @@ index bcf2b9244f8..bef750c026a 100644
    ""
    { 
      register rtx target = operands[1];
-@@ -2880,7 +3201,6 @@ else
+@@ -2881,7 +3202,6 @@ else
  
    ;;if (!register_operand (operands[0], VOIDmode))
    ;;  FAIL;
@@ -1797,10 +1798,10 @@ index bcf2b9244f8..bef750c026a 100644
                           operands[2], operands[3]));
    DONE;
 diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 7671f63c5b5..9fc80b142ce 100644
+index e9a1921ae26..9fc80b142ce 100644
 --- a/gcc/config/microblaze/t-microblaze
 +++ b/gcc/config/microblaze/t-microblaze
-@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
+@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
  MULTILIB_DIRNAMES = bs m mh le m64
  MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
  MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
@@ -1808,13 +1809,8 @@ index 7671f63c5b5..9fc80b142ce 100644
 +MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
 +MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
  MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+ MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
 diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
 index d0146083db6..005825f1ec5 100644
 --- a/libgcc/config/microblaze/crti.S
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch
index 63290129..0113c65d 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch
@@ -1,7 +1,7 @@
-From e259b63769bf3cc437a665059add98d9480d942c Mon Sep 17 00:00:00 2001
+From 67d89be9ace8f658354fb1378e986451ef435d60 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 3 Aug 2018 15:41:39 +0530
-Subject: [PATCH 36/58] re-arrangement of the compare branches
+Subject: [PATCH 31/54] re-arrangement of the compare branches
 
 ---
  gcc/config/microblaze/microblaze.c  |  28 ++----
@@ -9,10 +9,10 @@ Subject: [PATCH 36/58] re-arrangement of the compare branches
  2 files changed, 73 insertions(+), 96 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 3ecda553fe6..cba5d86225c 100644
+index 3c815444574..046bfd05558 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -3827,11 +3827,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3697,11 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
      {
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -25,7 +25,7 @@ index 3ecda553fe6..cba5d86225c 100644
      }
  
    else if (code == EQ || code == NE)
-@@ -3842,10 +3838,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+@@ -3712,10 +3708,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
        else
          emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
        condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
@@ -37,7 +37,7 @@ index 3ecda553fe6..cba5d86225c 100644
      }
    else
      {
-@@ -3878,10 +3871,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3748,10 +3741,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
        comp_reg = cmp_op0;
        condition = gen_rtx_fmt_ee (signed_condition (code),
                                    mode, comp_reg, const0_rtx);
@@ -49,7 +49,7 @@ index 3ecda553fe6..cba5d86225c 100644
      }
    else if (code == EQ)
      {
-@@ -3896,10 +3886,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3766,10 +3756,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
                                             cmp_op1));
         }
        condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
@@ -61,7 +61,7 @@ index 3ecda553fe6..cba5d86225c 100644
   
      }
    else if (code == NE)
-@@ -3915,10 +3902,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+@@ -3785,10 +3772,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
                                             cmp_op1));
         }
        condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
@@ -73,7 +73,7 @@ index 3ecda553fe6..cba5d86225c 100644
      }
    else
      {
-@@ -3960,7 +3944,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+@@ -3830,7 +3814,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
  
    emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
    condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
@@ -83,10 +83,10 @@ index 3ecda553fe6..cba5d86225c 100644
  
  /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bef750c026a..29ebbfc0c03 100644
+index 33a8b12ef3b..cfe9e5312d1 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2270,7 +2270,27 @@ else
+@@ -2271,7 +2271,27 @@ else
                       (label_ref (match_operand 1))
                       (pc)))])
  
@@ -115,7 +115,7 @@ index bef750c026a..29ebbfc0c03 100644
    [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                                  [(match_operand 1 "register_operand" "d")
-@@ -2281,9 +2301,9 @@ else
+@@ -2282,9 +2302,9 @@ else
    "TARGET_MB_64"
    {
      if (operands[3] == pc_rtx) 
@@ -127,7 +127,7 @@ index bef750c026a..29ebbfc0c03 100644
    }
    [(set_attr "type"    "branch")
     (set_attr "mode"    "none")
-@@ -2312,9 +2332,9 @@ else
+@@ -2313,9 +2333,9 @@ else
  
  (define_insn "branch_compare64"
    [(set (pc)
@@ -140,7 +140,7 @@ index bef750c026a..29ebbfc0c03 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2351,6 +2371,47 @@ else
+@@ -2352,6 +2372,47 @@ else
     (set_attr "length"   "12")]
  )
  
@@ -188,7 +188,7 @@ index bef750c026a..29ebbfc0c03 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2433,74 +2494,6 @@ else
+@@ -2434,74 +2495,6 @@ else
  
  })
  
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
index 9be04781..b74c79ec 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -1,7 +1,7 @@
-From 589c4453ab01570d47e6e37e4e546d65398cf58e Mon Sep 17 00:00:00 2001
+From 410348f4fd9b641afa24e6c6b6a62a4c74d18862 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 8 Aug 2018 17:37:26 +0530
-Subject: [PATCH 37/58] [Patch,Microblaze] :  previous commit broke the
+Subject: [PATCH 32/54] [Patch,Microblaze] :  previous commit broke the
  handling of SI Branch compare for Microblaze 32-bit..
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 37/58] [Patch,Microblaze] :  previous commit broke the
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 29ebbfc0c03..1a8853056d7 100644
+index cfe9e5312d1..592757baf2f 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2226,8 +2226,8 @@ else
+@@ -2227,8 +2227,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
index 464b5a6d..353bfa90 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -1,7 +1,7 @@
-From cfc6628cdf81a7ab268d2699c9bbc465865681c5 Mon Sep 17 00:00:00 2001
+From 802c136f1a41ebfed3b25419e48331038f284e2b Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 11 Sep 2018 13:43:48 +0530
-Subject: [PATCH 38/58] [Patch, Microblaze] : Support of multilibs with m64 ...
+Subject: [PATCH 33/54] [Patch, Microblaze] : Support of multilibs with m64 ...
 
 ---
  gcc/config/microblaze/microblaze-c.c  |  1 +
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch
index c9d4b8c7..c508b158 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch
@@ -1,21 +1,19 @@
-From 0405777c25bb8110ebfd8ea69c7df062a4c03d6b Mon Sep 17 00:00:00 2001
+From 2b2c6e96c3aefc86c880be05d93685a4ce97c9f1 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 11 Sep 2018 14:58:00 +0530
-Subject: [PATCH 39/58] Fix various issues
+Subject: [PATCH 34/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
+ extension issue
 
-Fixed issues like:
-1 Interrupt alignment issue
-2 Sign extension issue
 ---
  gcc/config/microblaze/microblaze.c  | 16 ++++++++++------
  gcc/config/microblaze/microblaze.md |  2 +-
  2 files changed, 11 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index cba5d86225c..b94902b8fbb 100644
+index 046bfd05558..498c8ca191f 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2307,9 +2307,14 @@ compute_frame_size (HOST_WIDE_INT size)
+@@ -2177,9 +2177,14 @@ compute_frame_size (HOST_WIDE_INT size)
  
    total_size += gp_reg_size;
  
@@ -32,7 +30,7 @@ index cba5d86225c..b94902b8fbb 100644
  
    /* No space to be allocated for link register in leaf functions with no other
       stack requirements.  */
-@@ -2594,7 +2599,6 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2464,7 +2469,6 @@ print_operand (FILE * file, rtx op, int letter)
    else if (letter == 'h' || letter == 'j')
      {
        long val[2];
@@ -40,7 +38,7 @@ index cba5d86225c..b94902b8fbb 100644
        long l[2];
        if (code == CONST_DOUBLE)
         {
-@@ -2609,10 +2613,10 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2479,10 +2483,10 @@ print_operand (FILE * file, rtx op, int letter)
         }
        else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
          {
@@ -55,7 +53,7 @@ index cba5d86225c..b94902b8fbb 100644
    else if (code == CONST_DOUBLE)
      {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 1a8853056d7..7cc26e7d786 100644
+index 592757baf2f..e7c7cf3e8b5 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1096,7 +1096,7 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch
index d5fbf703..61d35261 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch
@@ -1,11 +1,14 @@
-From c4d60b379c8d0a5621a0dc2a3a12fb40fe45e83e Mon Sep 17 00:00:00 2001
+From 051d744c06ed3f11f603e37768eece57784c2583 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 26 Nov 2019 17:26:15 +0530
-Subject: [PATCH 40/58] Fixed below issues:
+Subject: [PATCH 35/54] Fixed below issues:
 
 - Floating point print issues in 64bit mode
 - Dejagnu Jump related issues
 - Added dbl instruction
+
+Conflicts:
+        gcc/config/microblaze/microblaze.md
 ---
  gcc/config/microblaze/microblaze.c  | 12 +++-
  gcc/config/microblaze/microblaze.h  |  7 +++
@@ -15,10 +18,10 @@ Subject: [PATCH 40/58] Fixed below issues:
  5 files changed, 125 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index b94902b8fbb..12b1da852dd 100644
+index 498c8ca191f..e32de46fa62 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2603,7 +2603,12 @@ print_operand (FILE * file, rtx op, int letter)
+@@ -2473,7 +2473,12 @@ print_operand (FILE * file, rtx op, int letter)
        if (code == CONST_DOUBLE)
         {
           if (GET_MODE (op) == DFmode)
@@ -31,8 +34,8 @@ index b94902b8fbb..12b1da852dd 100644
 +           }
           else
             {
-               REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-@@ -4006,7 +4011,10 @@ microblaze_expand_divide (rtx operands[])
+              REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
+@@ -3876,7 +3881,10 @@ microblaze_expand_divide (rtx operands[])
                              gen_rtx_PLUS (QImode, regt1, div_table_rtx));
  
    insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
@@ -45,7 +48,7 @@ index b94902b8fbb..12b1da852dd 100644
    LABEL_NUSES (div_end_label) = 1; 
    emit_barrier ();
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1f6e2059545..a36e06316aa 100644
+index f6ad4d9fc21..60c552958b8 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -888,10 +888,17 @@ do {                                                                       \
@@ -67,7 +70,7 @@ index 1f6e2059545..a36e06316aa 100644
  /* We need to group -lm as well, since some Newlib math functions 
     reference __errno!  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7cc26e7d786..013c77651c3 100644
+index e7c7cf3e8b5..74bb30cb9e8 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -527,6 +527,15 @@
@@ -86,7 +89,7 @@ index 7cc26e7d786..013c77651c3 100644
  (define_insn "fix_truncsfsi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
          (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-@@ -1300,7 +1309,7 @@
+@@ -1301,7 +1310,7 @@
  (define_insn "movdi_long_int"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
         (match_operand:DI 1 "general_operand"      "i"))]
@@ -95,7 +98,7 @@ index 7cc26e7d786..013c77651c3 100644
    "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
    [(set_attr "type"    "no_delay_arith")
    (set_attr "mode"     "DI")
-@@ -1583,7 +1592,7 @@
+@@ -1584,7 +1593,7 @@
            return "ll%i1\t%0,%1";
        case 3:
        {
@@ -104,7 +107,7 @@ index 7cc26e7d786..013c77651c3 100644
        }
        case 5:
         return "sl%i0\t%1,%0";
-@@ -2373,9 +2382,9 @@ else
+@@ -2374,9 +2383,9 @@ else
  
  (define_insn "long_branch_compare"
    [(set (pc)
@@ -117,7 +120,7 @@ index 7cc26e7d786..013c77651c3 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2497,6 +2506,20 @@ else
+@@ -2498,6 +2507,20 @@ else
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
@@ -138,7 +141,7 @@ index 7cc26e7d786..013c77651c3 100644
  (define_insn "jump"
    [(set (pc)
         (label_ref (match_operand 0 "" "")))]
-@@ -2542,17 +2565,25 @@ else
+@@ -2543,17 +2566,25 @@ else
    {
      //gcc_assert (GET_MODE (operands[0]) == Pmode);
  
@@ -169,7 +172,7 @@ index 7cc26e7d786..013c77651c3 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2560,11 +2591,21 @@ else
+@@ -2561,11 +2592,21 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -194,7 +197,7 @@ index 7cc26e7d786..013c77651c3 100644
    ""
    ""
  )
-@@ -2595,6 +2636,23 @@ else
+@@ -2596,6 +2637,23 @@ else
    ""
  )
  
@@ -218,7 +221,7 @@ index 7cc26e7d786..013c77651c3 100644
  ;;----------------------------------------------------------------
  ;; Function prologue/epilogue and stack allocation
  ;;----------------------------------------------------------------
-@@ -3101,7 +3159,7 @@ else
+@@ -3102,7 +3160,7 @@ else
  ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
  ;; between "mfs" and "addik" instructions.
  (define_insn "set_got"
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch
index 75ee48fa..3f52e879 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch
@@ -1,17 +1,16 @@
-From 90edf612331af9b7e99105112c2067a3f085daef Mon Sep 17 00:00:00 2001
+From 2bb5cef1a85d63ebf155bcb0070492b0ad298dd8 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 9 Oct 2018 10:07:08 +0530
-Subject: [PATCH 41/58] Fix various
+Subject: [PATCH 36/54] -Added double arith instructions -Fixed prologue stack
+ pointer decrement issue
 
--Added double arith instructions
--Fixed prologue stack pointer decrement issue
 ---
  gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++----
  gcc/config/microblaze/t-microblaze  |  7 +++
  2 files changed, 76 insertions(+), 9 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 013c77651c3..645f48f2847 100644
+index 74bb30cb9e8..1401d6b77ff 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -527,6 +527,66 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
index 2e66625b..2253b759 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -1,7 +1,7 @@
-From c7f6fb9d81ce322f71cbef7cc1f5cb2fb8956a27 Mon Sep 17 00:00:00 2001
+From 2feba7c8902be8d5c4cc99feca0581472c16de0c Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 12 Oct 2018 16:07:36 +0530
-Subject: [PATCH 42/58] Fixed the issue in the delay slot with swap
+Subject: [PATCH 37/54] Fixed the issue in the delay slot with swap
  instructions
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 42/58] Fixed the issue in the delay slot with swap
  1 file changed, 6 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 645f48f2847..6a1e45a5b66 100644
+index 1401d6b77ff..a91108cf0e5 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -443,6 +443,9 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
index 3d532c6a..57905e66 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -1,7 +1,7 @@
-From 16a9a232ae430e691c13157dd5988f9c5c7dfb71 Mon Sep 17 00:00:00 2001
+From 10d59c50195cff30c4e74959ef4cebc9065808a4 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Sat, 13 Oct 2018 21:12:43 +0530
-Subject: [PATCH 43/58] Fixed the load store issue with the 32bit arith
+Subject: [PATCH 38/54] Fixed the load store issue with the 32bit arith
  libraries
 
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
index d34c103d..8f46859a 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -1,14 +1,14 @@
-From b3766742c4e1d401d4f7cdc55a90262681689a20 Mon Sep 17 00:00:00 2001
+From e51fb2d87f412d1f7045050c5c2df664766de706 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Mon, 15 Oct 2018 12:00:10 +0530
-Subject: [PATCH 44/58] extending the Dwarf support to 64bit Microblaze
+Subject: [PATCH 39/54] extending the Dwarf support to 64bit Microblaze
 
 ---
  gcc/config/microblaze/microblaze.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index a36e06316aa..8504a841406 100644
+index 60c552958b8..747adcc7a70 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch
index a69c71dd..e7e581e3 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -1,7 +1,7 @@
-From bdc9429b5f2300e39ecdf1db63f4d35f8e18a932 Mon Sep 17 00:00:00 2001
+From 61be4b342d470aeb7ad1c0cc5e90f5afdc906c00 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 16 Oct 2018 07:55:46 +0530
-Subject: [PATCH 45/58] fixing the typo errors in umodsi3 file
+Subject: [PATCH 40/54] fixing the typo errors in umodsi3 file
 
 ---
  libgcc/config/microblaze/umodsi3.S | 6 +++---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
index a5f7afb6..9f9afdb9 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -1,14 +1,14 @@
-From 2226c8b836bdc9d0e2a281d971288e4bcb50d503 Mon Sep 17 00:00:00 2001
+From b1eb7b1f6c33246ded3501364279a5f002cd8de0 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 46/58] fixing the 32bit LTO related issue9(1014024)
+Subject: [PATCH 41/54] fixing the 32bit LTO related issue9(1014024)
 
 ---
  gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
  1 file changed, 14 insertions(+), 10 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8504a841406..0c493b6f6e4 100644
+index 747adcc7a70..bfa7bc9a01c 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
index 42296396..fb31d663 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -1,7 +1,7 @@
-From 8ed304d49f66bc36b39dac8e804a7cdeda642739 Mon Sep 17 00:00:00 2001
+From e0820fe8c8d9b7504595794fe6e65151d22e2acf Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 19 Oct 2018 14:26:25 +0530
-Subject: [PATCH 47/58] Fixed the missing stack adjustment in prologue of
+Subject: [PATCH 42/54] Fixed the missing stack adjustment in prologue of
  modsi3 function
 
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
index 92fa9e57..ce8b1384 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -1,7 +1,7 @@
-From d12f2da2ae7fa7946aef94c161730c7b851c086a Mon Sep 17 00:00:00 2001
+From 1f288ec920d938accb084dc0d1d6f6115950c014 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 24 Oct 2018 18:31:04 +0530
-Subject: [PATCH 48/58] [Patch,Microblaze] : corrected SPN for dlong
+Subject: [PATCH 43/54] [Patch,Microblaze] : corrected SPN for dlong
  instruction mapping.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 48/58] [Patch,Microblaze] : corrected SPN for dlong
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6a1e45a5b66..53dbe4e4060 100644
+index a91108cf0e5..19801f8edcc 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -602,9 +602,9 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
index 346157ce..fec0a2af 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -1,7 +1,7 @@
-From dfe4f5aa180a7b4c15b4b586b253541aa9d29e52 Mon Sep 17 00:00:00 2001
+From eed2bf4db9bdfc0da1c3f77ce746fb5bfa460b3c Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 29 Nov 2018 17:55:08 +0530
-Subject: [PATCH 49/58] fixing the long & long long mingw toolchain issue
+Subject: [PATCH 44/54] fixing the long & long long mingw toolchain issue
 
 ---
  gcc/config/microblaze/constraints.md | 2 +-
@@ -9,7 +9,7 @@ Subject: [PATCH 49/58] fixing the long & long long mingw toolchain issue
  2 files changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index c2b0a21c53b..4a6cf419671 100644
+index b8ef1650f92..89db511c453 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -19,10 +19,10 @@ index c2b0a21c53b..4a6cf419671 100644
 -       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
 +       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
  
- ;; Define floating point constraints
  
+ ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 53dbe4e4060..5d277014e42 100644
+index 19801f8edcc..8f0ae901b77 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -648,8 +648,8 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
index 360bdb51..15acc1cb 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -1,17 +1,17 @@
-From b21e115bc1af625b2ae1acb893027af6af3c2d16 Mon Sep 17 00:00:00 2001
+From 682f65fa3a6b37c207b0d727dd22b6f8cc5d8d3d Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 14 Mar 2019 18:11:04 +0530
-Subject: [PATCH 50/58] Fix the MB-64 bug of handling QI objects
+Subject: [PATCH 45/54] Fix the MB-64 bug of handling QI objects
 
 ---
  gcc/config/microblaze/microblaze.md | 14 +++++++-------
  1 file changed, 7 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 5d277014e42..a1363935c42 100644
+index 8f0ae901b77..207d2bf1b55 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2347,11 +2347,11 @@ else
+@@ -2348,11 +2348,11 @@ else
  
  (define_insn "branch_zero_64"
    [(set (pc)
@@ -26,7 +26,7 @@ index 5d277014e42..a1363935c42 100644
    ]
    "TARGET_MB_64"
    {
-@@ -2367,11 +2367,11 @@ else
+@@ -2368,11 +2368,11 @@ else
  
  (define_insn "long_branch_zero"
    [(set (pc)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
index 6b7bb2a1..eebf6ee7 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -1,17 +1,15 @@
-From ed17f79b22769e5a256e3990715e32e943bfd929 Mon Sep 17 00:00:00 2001
+From 444a09859149f8d21777a1c859ef2305ff86b211 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Fri, 29 Mar 2019 12:08:39 +0530
-Subject: [PATCH 51/58] [Patch,Microblaze] : Check the possibiity of peephole2
- opt
+Subject: [PATCH 46/54] [Patch,Microblaze] : We will check the possibility of
+ peephole2 optimization,if we can then we will fix the compiler issue.
 
-We will check the possibility of peephole2
-optimization,if we can then we will fix the compiler issue.
 ---
  gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------
  1 file changed, 38 insertions(+), 25 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a1363935c42..626eade9468 100644
+index 207d2bf1b55..9b88666c0a6 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -882,31 +882,44 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
index 45505cf1..34378812 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -1,7 +1,7 @@
-From d845981b381b0174d97dda8a78d82cf8fcae7ca1 Mon Sep 17 00:00:00 2001
+From 7cc6db7ad5bf2fac80a81711c70ac1147ab87b2c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 17 Apr 2019 12:36:16 +0530
-Subject: [PATCH 52/58] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+Subject: [PATCH 47/54] [Patch,MicroBlaze]: fixed typos in mul,div and mod
  assembly files.
 
 ---
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch
index 8dce8476..94be6aff 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -1,24 +1,25 @@
-From e3b95d5646d4197bff81105c12bcbc5e7dba1725 Mon Sep 17 00:00:00 2001
+From f6b896effc198b8d9d1e6f33889f029da5e5d96c Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 18 Apr 2019 16:00:37 +0530
-Subject: [PATCH 53/58] [Patch, microblaze]: MB-64 removal of barrel-shift
- instructions from default
+Subject: [PATCH 48/54] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+ 17 14:11:00 2019 +0530
 
-By default MB-64 is generatting barrel-shift instructions. It has been
-removed from default. Barrel-shift instructions will be generated only if
-barrel-shifter is enabled. Similarly to double instructions as well.
+    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
+    By default MB-64 is generatting barrel-shift instructions. It has been
+    removed from default. Barrel-shift instructions will be generated only if
+    barrel-shifter is enabled. Similarly to double instructions as well.
 
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
 ---
  gcc/config/microblaze/microblaze.c  |   2 +-
  gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++--
  2 files changed, 252 insertions(+), 19 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 12b1da852dd..5b4c21af365 100644
+index e32de46fa62..7b48c011550 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -4000,7 +4000,7 @@ microblaze_expand_divide (rtx operands[])
+@@ -3870,7 +3870,7 @@ microblaze_expand_divide (rtx operands[])
    emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
  
    if (TARGET_MB_64) {
@@ -28,7 +29,7 @@ index 12b1da852dd..5b4c21af365 100644
      }
    else  {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 626eade9468..6cc62666269 100644
+index 9b88666c0a6..60afd9be288 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -547,7 +547,7 @@
@@ -146,7 +147,7 @@ index 626eade9468..6cc62666269 100644
          else   
           return "addlik\t%0,r0,%1";
       case 3:
-@@ -1388,7 +1424,7 @@
+@@ -1389,7 +1425,7 @@
  (define_insn "movdi_long_int"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
         (match_operand:DI 1 "general_operand"      "i"))]
@@ -155,7 +156,7 @@ index 626eade9468..6cc62666269 100644
    "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
    [(set_attr "type"    "no_delay_arith")
    (set_attr "mode"     "DI")
-@@ -1655,6 +1691,33 @@
+@@ -1656,6 +1692,33 @@
  ;; movdf_internal
  ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
  ;;
@@ -189,7 +190,7 @@ index 626eade9468..6cc62666269 100644
  (define_insn "*movdf_internal_64"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
          (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-@@ -1671,7 +1734,13 @@
+@@ -1672,7 +1735,13 @@
            return "ll%i1\t%0,%1";
        case 3:
        {
@@ -204,7 +205,7 @@ index 626eade9468..6cc62666269 100644
        }
        case 5:
         return "sl%i0\t%1,%0";
-@@ -1791,11 +1860,21 @@
+@@ -1792,11 +1861,21 @@
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -227,7 +228,7 @@ index 626eade9468..6cc62666269 100644
  else
    FAIL;
  }    
-@@ -1805,7 +1884,7 @@ else
+@@ -1806,7 +1885,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -236,7 +237,7 @@ index 626eade9468..6cc62666269 100644
    "@
    bsllli\t%0,%1,%2
    bslll\t%0,%1,%2"
-@@ -1813,6 +1892,51 @@ else
+@@ -1814,6 +1893,51 @@ else
    (set_attr "mode"     "DI,DI")
    (set_attr "length"   "4,4")]
  )
@@ -288,7 +289,7 @@ index 626eade9468..6cc62666269 100644
  ;; The following patterns apply when there is no barrel shifter present
  
  (define_insn "*ashlsi3_with_mul_delay"
-@@ -1946,11 +2070,21 @@ else
+@@ -1947,11 +2071,21 @@ else
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -311,7 +312,7 @@ index 626eade9468..6cc62666269 100644
  else
    FAIL;
  }    
-@@ -1960,7 +2094,7 @@ else
+@@ -1961,7 +2095,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -320,7 +321,7 @@ index 626eade9468..6cc62666269 100644
    "@
     bslrai\t%0,%1,%2
     bslra\t%0,%1,%2"
-@@ -1968,6 +2102,51 @@ else
+@@ -1969,6 +2103,51 @@ else
    (set_attr "mode"     "DI,DI")
    (set_attr "length"   "4,4")]
    )
@@ -372,7 +373,7 @@ index 626eade9468..6cc62666269 100644
  (define_expand "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2085,11 +2264,21 @@ else
+@@ -2086,11 +2265,21 @@ else
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -395,7 +396,7 @@ index 626eade9468..6cc62666269 100644
  else
    FAIL;
  }    
-@@ -2099,7 +2288,7 @@ else
+@@ -2100,7 +2289,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -404,7 +405,7 @@ index 626eade9468..6cc62666269 100644
    "@
     bslrli\t%0,%1,%2
     bslrl\t%0,%1,%2"
-@@ -2108,6 +2297,50 @@ else
+@@ -2109,6 +2298,50 @@ else
    (set_attr "length"   "4,4")]
    )
  
@@ -455,7 +456,7 @@ index 626eade9468..6cc62666269 100644
  (define_expand "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2235,7 +2468,7 @@ else
+@@ -2236,7 +2469,7 @@ else
         (eq:DI 
                (match_operand:DI 1 "register_operand" "d")
                (match_operand:DI 2 "register_operand" "d")))]
@@ -464,7 +465,7 @@ index 626eade9468..6cc62666269 100644
    "pcmpleq\t%0,%1,%2"
    [(set_attr "type"    "arith")
     (set_attr "mode"    "DI")
-@@ -2247,7 +2480,7 @@ else
+@@ -2248,7 +2481,7 @@ else
         (ne:DI 
                (match_operand:DI 1 "register_operand" "d")
                (match_operand:DI 2 "register_operand" "d")))]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
index 4ab3cec9..81ecbf8e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -1,14 +1,14 @@
-From 3198a31122bb0436d298d29e986bb69bc3c526a9 Mon Sep 17 00:00:00 2001
+From adb1b8d8cc2a8fb99f474d9166db9f68b8f3f8b4 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Fri, 23 Aug 2019 16:16:53 +0530
-Subject: [PATCH 55/58] Added new MB-64 single register arithmetic instructions
+Subject: [PATCH 49/54] Added new MB-64 single register arithmetic instructions
 
 ---
  gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++
  1 file changed, 56 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6cc62666269..696be7b300f 100644
+index 60afd9be288..1ad139cbd44 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -654,6 +654,18 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
index afe3ae96..d452b988 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -1,7 +1,7 @@
-From 1dadde6d9a49010a495529c9b5ea6c2bb75cc5f1 Mon Sep 17 00:00:00 2001
+From 797697692635d4c536181cb007b3b0d63d2431c1 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 26 Aug 2019 15:55:22 +0530
-Subject: [PATCH 56/58] [Patch,MicroBlaze] : Added support for 64 bit Immediate
+Subject: [PATCH 50/54] [Patch,MicroBlaze] : Added support for 64 bit Immediate
  values.
 
 ---
@@ -10,7 +10,7 @@ Subject: [PATCH 56/58] [Patch,MicroBlaze] : Added support for 64 bit Immediate
  2 files changed, 3 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 4a6cf419671..2432b480a2c 100644
+index 89db511c453..9ad2b099310 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -53,9 +53,9 @@
@@ -23,10 +23,10 @@ index 4a6cf419671..2432b480a2c 100644
 -       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
 +       (match_test "ival > (long long)-9223372036854775808  && ival < (long long)9223372036854775807")))
  
- ;; Define floating point constraints
  
+ ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 696be7b300f..f0a9701ab18 100644
+index 1ad139cbd44..93de8d831fd 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1334,8 +1334,7 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
index ebd707c9..3e0c483b 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
@@ -1,7 +1,7 @@
-From ab73daf6bf1bc652e9557386cba5eb237af66350 Mon Sep 17 00:00:00 2001
+From 697db2e2c2519f27011fbd1960cd8860133aaa84 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 9 Jan 2020 12:30:41 +0530
-Subject: [PATCH 57/58] [Patch, microblaze]: Fix Compiler crash with
+Subject: [PATCH 51/54] [Patch, microblaze]: Fix Compiler crash with
  -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
  struct values in registers. Currently we are only handling SImode With this
  patch all other modes are handled properly
@@ -23,10 +23,10 @@ ChangeLog:
  2 files changed, 10 insertions(+), 20 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 5b4c21af365..31869982d27 100644
+index 7b48c011550..1bba77dab6d 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -4038,7 +4038,16 @@ microblaze_function_value (const_tree valtype,
+@@ -3908,7 +3908,16 @@ microblaze_function_value (const_tree valtype,
                            const_tree func ATTRIBUTE_UNUSED,
                            bool outgoing ATTRIBUTE_UNUSED)
  {
@@ -45,7 +45,7 @@ index 5b4c21af365..31869982d27 100644
  
  /* Implement TARGET_SCHED_ADJUST_COST.  */
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0c493b6f6e4..5eb95c2600a 100644
+index bfa7bc9a01c..d467a7ee65d 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
index 70e05117..91c7c026 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -1,7 +1,7 @@
-From 6bdb6f300593c4a633a8ec485ac2744a97b51460 Mon Sep 17 00:00:00 2001
+From d7d6835bd839150e864cbb0d9c9c7a497e93bbb8 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Wed, 8 May 2019 14:12:03 +0530
-Subject: [PATCH 54/58] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+Subject: [PATCH 52/54] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
  disable fivopts by default
 
 Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
@@ -10,26 +10,30 @@ Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
    (microblaze_option_optimization_table): Disable fivopts by default.
 
 Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+
+Conflicts:
+        gcc/common/config/microblaze/microblaze-common.c
 ---
- gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
+ gcc/common/config/microblaze/microblaze-common.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
 
 diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 0b9d5a1b453..cf2db8afe36 100644
+index 4391f939626..cf2db8afe36 100644
 --- a/gcc/common/config/microblaze/microblaze-common.c
 +++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -27,13 +27,15 @@
- /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
- static const struct default_options microblaze_option_optimization_table[] =
-   {
--    /* Turn off ivopts by default. It messes up cse. */
+@@ -24,7 +24,18 @@
+ #include "common/common-target.h"
+ #include "common/common-target-def.h"
+ 
++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
++static const struct default_options microblaze_option_optimization_table[] =
++  {
 +    /* Turn off ivopts by default. It messes up cse. 
 +    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
-     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
--    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-     { OPT_LEVELS_NONE, 0, NULL, 0 }
-   };
- 
++    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
++    { OPT_LEVELS_NONE, 0, NULL, 0 }
++  };
++
  #undef TARGET_DEFAULT_TARGET_FLAGS
  #define TARGET_DEFAULT_TARGET_FLAGS    TARGET_DEFAULT
  
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
index 1f8decc7..377154d7 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -1,7 +1,7 @@
-From 59273a71f1f180456d87eb4a1a5f95fcc6d17003 Mon Sep 17 00:00:00 2001
+From e146b21e18e51ab6ce77af2c39cdf3375606c1eb Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 16:42:44 +0530
-Subject: [PATCH 18/58] [Patch, microblaze]: Reducing Stack space for arguments
+Date: Tue, 24 Nov 2020 12:26:32 +0530
+Subject: [PATCH 53/54] [Patch, microblaze]: Reducing Stack space for arguments
 
 Currently in Microblaze target stack space for arguments in register is being
 allocated even if there are no arguments in the function.
@@ -9,13 +9,6 @@ This patch will optimize the extra 24 bytes that are being allocated.
 
 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
               :Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2015-04-17 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-    *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
-    *microblaze.c (REG_PARM_STACK_SPACE): Modify
 ---
  gcc/config/microblaze/microblaze-protos.h |   1 +
  gcc/config/microblaze/microblaze.c        | 132 +++++++++++++++++++++-
@@ -23,10 +16,10 @@ ChangeLog:
  3 files changed, 134 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 982b2abd2d4..96f7bb67f6c 100644
+index 460feac4ac5..b8a3321dbdf 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx);
+@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx);
  extern int label_mentioned_p (rtx);
  extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
  extern void microblaze_eh_return (rtx op0);
@@ -35,10 +28,10 @@ index 982b2abd2d4..96f7bb67f6c 100644
  
  /* Declare functions in microblaze-c.c.  */
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 9eae5515c60..a4bdf66f045 100644
+index 1bba77dab6d..dac0596bc7d 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -2057,6 +2057,136 @@ microblaze_must_save_register (int regno)
+@@ -2080,6 +2080,136 @@ microblaze_must_save_register (int regno)
    return 0;
  }
  
@@ -120,8 +113,8 @@ index 9eae5515c60..a4bdf66f045 100644
 +  args_so_far = pack_cumulative_args (&args_so_far_v);
 +
 +  /* When incoming, we will have been passed the function decl.
-+   *      It is necessary to use the decl to handle K&R style functions,
-+   *      where TYPE_ARG_TYPES may not be available.  */
++ *    *      It is necessary to use the decl to handle K&R style functions,
++ *       *      where TYPE_ARG_TYPES may not be available.  */
 +  if (incoming)
 +    {
 +      gcc_assert (DECL_P (fun));
@@ -153,7 +146,7 @@ index 9eae5515c60..a4bdf66f045 100644
 +
 +      FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
 +      {
-+        num_of_args++;
++        num_of_args;
 +        if (microblaze_parm_needs_stack (args_so_far, arg_type))
 +         return true;
 +      }
@@ -175,30 +168,30 @@ index 9eae5515c60..a4bdf66f045 100644
  /* Return the bytes needed to compute the frame pointer from the current
     stack pointer.
  
-@@ -3403,7 +3533,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+@@ -3470,7 +3600,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
    emit_insn (gen_indirect_jump (temp2));
  
    /* Run just enough of rest_of_compilation.  This sequence was
 -     "borrowed" from rs6000.c.  */
-+     "borrowed" from microblaze.c.  */
++     "borrowed" from microblaze.c */
    insn = get_insns ();
    shorten_branches (insn);
    assemble_start_function (thunk_fndecl, fnname);
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8aa3f155790..1e155e4041c 100644
+index d467a7ee65d..be6c798c889 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
-@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
- 
+@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info;
  #define ARG_POINTER_CFA_OFFSET(FNDECL)         0
+ #define DWARF_CIE_DATA_ALIGNMENT -1
  
 -#define REG_PARM_STACK_SPACE(FNDECL)           (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
-+#define REG_PARM_STACK_SPACE(FNDECL)            microblaze_reg_parm_stack_space(FNDECL)
++#define REG_PARM_STACK_SPACE(FNDECL)           microblaze_reg_parm_stack_space(FNDECL)
  
 -#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
-+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)   1
  
- #define STACK_BOUNDARY                         32
+ #define STACK_BOUNDARY                         (TARGET_MB_64 ? 64 : 32)
  
 -- 
 2.17.1
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch
deleted file mode 100644
index e3c4b87b..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From dd73d8ba32c0c24f17a54538b9bb54beb5d8d4e0 Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Thu, 13 Aug 2020 16:28:57 -0500
-Subject: [PATCH 58/58] microblaze: Avoid UINTPTR_TYPE macro redefinition
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- gcc/config/microblaze/microblaze.h | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 5eb95c2600a..4cb98bac849 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -246,11 +246,6 @@ extern enum pipeline_type microblaze_pipe;
- #undef PTRDIFF_TYPE
- #define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
- 
--/*#undef INTPTR_TYPE
--#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
--#undef UINTPTR_TYPE
--#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
--
- #define DATA_ALIGNMENT(TYPE, ALIGN)                                    \
-   ((((ALIGN) < BITS_PER_WORD)                                          \
-     && (TREE_CODE (TYPE) == ARRAY_TYPE                                 \
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0059-microblaze-multilib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch
index af8ebf3b..af8ebf3b 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0059-microblaze-multilib-hack.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
index 7e8c1fa5..f1ba2ea6 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
@@ -4,61 +4,56 @@ FILESEXTRAPATHS_append_microblaze := ":${THISDIR}/gcc-10"
 SRC_URI_append_microblaze = " \
     file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
     file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \
-    file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \
-    file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
-    file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
-    file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
-    file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
-    file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
-    file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \
-    file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
-    file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
-    file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
-    file://0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
-    file://0014-Patch-microblaze-Disable-fivopts-by-default.patch \
-    file://0015-Patch-microblaze-Removed-moddi3-routinue.patch \
-    file://0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
-    file://0017-Patch-microblaze-Add-optimized-lshrsi3.patch \
-    file://0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
-    file://0019-Patch-microblaze-Add-cbranchsi4_reg.patch \
-    file://0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
-    file://0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \
-    file://0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
-    file://0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
-    file://0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
-    file://0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch \
-    file://0026-Patch-microblaze-Correct-the-const-high-double-immed.patch \
-    file://0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
-    file://0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
-    file://0029-Patch-microblaze-Add-new-bit-field-instructions.patch \
-    file://0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
-    file://0031-Fixing-the-issue-with-the-builtin_alloc.patch \
-    file://0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
-    file://0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
-    file://0034-Intial-commit-of-64-bit-Microblaze.patch \
-    file://0035-Intial-commit-for-64bit-MB-sources.patch \
-    file://0036-re-arrangement-of-the-compare-branches.patch \
-    file://0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
-    file://0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
-    file://0039-Fix-various-issues.patch \
-    file://0040-Fixed-below-issues.patch \
-    file://0041-Fix-various.patch \
-    file://0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
-    file://0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
-    file://0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
-    file://0045-fixing-the-typo-errors-in-umodsi3-file.patch \
-    file://0046-fixing-the-32bit-LTO-related-issue9-1014024.patch \
-    file://0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
-    file://0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
-    file://0049-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-    file://0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
-    file://0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch \
-    file://0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
-    file://0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch \
-    file://0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
-    file://0055-Added-new-MB-64-single-register-arithmetic-instructi.patch \
-    file://0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
-    file://0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
-    file://0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch \
-    file://0059-microblaze-multilib-hack.patch \
+    file://0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
+    file://0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
+    file://0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
+    file://0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
+    file://0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
+    file://0008-Patch-microblaze-Fix-atomic-side-effects.patch \
+    file://0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
+    file://0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
+    file://0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
+    file://0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
+    file://0013-Patch-microblaze-Removed-moddi3-routinue.patch \
+    file://0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
+    file://0015-Patch-microblaze-Add-optimized-lshrsi3.patch \
+    file://0016-Patch-microblaze-Add-cbranchsi4_reg.patch \
+    file://0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
+    file://0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
+    file://0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
+    file://0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
+    file://0021-Patch-microblaze-Correct-the-const-high-double-immed.patch \
+    file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
+    file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
+    file://0024-Patch-microblaze-Add-new-bit-field-instructions.patch \
+    file://0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
+    file://0026-Fixing-the-issue-with-the-builtin_alloc.patch \
+    file://0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
+    file://0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
+    file://0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \
+    file://0030-Intial-commit-for-64bit-MB-sources.patch \
+    file://0031-re-arrangement-of-the-compare-branches.patch \
+    file://0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
+    file://0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
+    file://0034-Fixed-issues-like.patch \
+    file://0035-Fixed-below-issues.patch \
+    file://0036-Added-double-arith-instructions.patch \
+    file://0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
+    file://0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
+    file://0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
+    file://0040-fixing-the-typo-errors-in-umodsi3-file.patch \
+    file://0041-fixing-the-32bit-LTO-related-issue9-1014024.patch \
+    file://0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
+    file://0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
+    file://0044-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+    file://0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
+    file://0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
+    file://0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
+    file://0048-Author-Nagaraju-nmekala-xilinx.com.patch \
+    file://0049-Added-new-MB-64-single-register-arithmetic-instructi.patch \
+    file://0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
+    file://0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
+    file://0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
+    file://0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
+    file://microblaze-mulitlib-hack.patch \
 "