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authorNathan Rossi <nathan@nathanrossi.com>2016-05-26 19:56:40 +1000
committerNathan Rossi <nathan@nathanrossi.com>2016-05-26 21:39:22 +1000
commit2fedda61238ab814ec1701e15b4107a7965b4591 (patch)
tree91b680ffa6235224cb184f80fe0ff8a790c1b965
parent0da91a210552ec1dda97c953540b98ac2d91507a (diff)
downloadmeta-xilinx-2fedda61238ab814ec1701e15b4107a7965b4591.tar.gz
recipes-zynqmp/qemu_2.5%: Patches no longer required
QEMU 2.6+ is available in oe-core, these patches are available in 2.6.0. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat
-rw-r--r--recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch90
-rw-r--r--recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch37
-rw-r--r--recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch49
-rw-r--r--recipes-zynqmp/qemu/qemu_2.5%.bbappend9
4 files changed, 0 insertions, 185 deletions
diff --git a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch b/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
deleted file mode 100644
index 50a17c48..00000000
--- a/recipes-zynqmp/qemu/files/4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch
+++ /dev/null
@@ -1,90 +0,0 @@
1From 9b3c2f321954251e3eb0c908786d0b6953fe9f79 Mon Sep 17 00:00:00 2001
2From: Alistair Francis <alistair.francis@xilinx.com>
3Date: Thu, 18 Feb 2016 14:16:17 +0000
4Subject: [PATCH] target-arm: Add the pmceid0 and pmceid1 registers
5
6Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
7Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8Tested-by: Nathan Rossi <nathan@nathanrossi.com>
9Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis@xilinx.com
10[PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU
11 does not currently implement any events.]
12Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14Upstream-Status: Backport
15---
16 target-arm/cpu-qom.h | 2 ++
17 target-arm/cpu.c | 2 ++
18 target-arm/cpu64.c | 2 ++
19 target-arm/helper.c | 16 ++++++++++++++++
20 4 files changed, 22 insertions(+), 0 deletions(-)
21
22diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
23index 07c0a71..1cc4502 100644
24--- a/target-arm/cpu-qom.h
25+++ b/target-arm/cpu-qom.h
26@@ -148,6 +148,8 @@ typedef struct ARMCPU {
27 uint32_t id_pfr0;
28 uint32_t id_pfr1;
29 uint32_t id_dfr0;
30+ uint32_t pmceid0;
31+ uint32_t pmceid1;
32 uint32_t id_afr0;
33 uint32_t id_mmfr0;
34 uint32_t id_mmfr1;
35diff --git a/target-arm/cpu.c b/target-arm/cpu.c
36index f2393cd..e95b030 100644
37--- a/target-arm/cpu.c
38+++ b/target-arm/cpu.c
39@@ -1156,6 +1156,8 @@ static void cortex_a15_initfn(Object *obj)
40 cpu->id_pfr0 = 0x00001131;
41 cpu->id_pfr1 = 0x00011011;
42 cpu->id_dfr0 = 0x02010555;
43+ cpu->pmceid0 = 0x0000000;
44+ cpu->pmceid1 = 0x00000000;
45 cpu->id_afr0 = 0x00000000;
46 cpu->id_mmfr0 = 0x10201105;
47 cpu->id_mmfr1 = 0x20000000;
48diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
49index c5bc19a..fa5eda2 100644
50--- a/target-arm/cpu64.c
51+++ b/target-arm/cpu64.c
52@@ -135,6 +135,8 @@ static void aarch64_a57_initfn(Object *obj)
53 cpu->id_isar5 = 0x00011121;
54 cpu->id_aa64pfr0 = 0x00002222;
55 cpu->id_aa64dfr0 = 0x10305106;
56+ cpu->pmceid0 = 0x00000000;
57+ cpu->pmceid1 = 0x00000000;
58 cpu->id_aa64isar0 = 0x00011120;
59 cpu->id_aa64mmfr0 = 0x00001124;
60 cpu->dbgdidr = 0x3516d000;
61diff --git a/target-arm/helper.c b/target-arm/helper.c
62index a420a2a..6a4ec01 100644
63--- a/target-arm/helper.c
64+++ b/target-arm/helper.c
65@@ -4324,6 +4324,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
66 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
67 .access = PL1_R, .type = ARM_CP_CONST,
68 .resetvalue = 0 },
69+ { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
70+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
71+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
72+ .resetvalue = cpu->pmceid0 },
73+ { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
74+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
75+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
76+ .resetvalue = cpu->pmceid0 },
77+ { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
78+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
79+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
80+ .resetvalue = cpu->pmceid1 },
81+ { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
82+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
83+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
84+ .resetvalue = cpu->pmceid1 },
85 REGINFO_SENTINEL
86 };
87 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
88--
891.7.0.4
90
diff --git a/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch b/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch
deleted file mode 100644
index f5fb581c..00000000
--- a/recipes-zynqmp/qemu/files/8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch
+++ /dev/null
@@ -1,37 +0,0 @@
1From 8a83ffc2dafad3499b87a736b17ab1b203fdb00b Mon Sep 17 00:00:00 2001
2From: Alistair Francis <alistair.francis@xilinx.com>
3Date: Thu, 18 Feb 2016 14:16:17 +0000
4Subject: [PATCH] target-arm: Add PMUSERENR_EL0 register
5
6The Linux kernel accesses this register early in its setup.
7
8Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
9Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
10Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis@xilinx.com
12Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13Upstream-Status: Backport
14---
15 target-arm/helper.c | 6 ++++++
16 1 files changed, 6 insertions(+), 0 deletions(-)
17
18diff --git a/target-arm/helper.c b/target-arm/helper.c
19index 9e47f3d..5a0447b 100644
20--- a/target-arm/helper.c
21+++ b/target-arm/helper.c
22@@ -1105,6 +1105,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
23 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
24 .resetvalue = 0,
25 .writefn = pmuserenr_write, .raw_writefn = raw_write },
26+ { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
27+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
28+ .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS,
29+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
30+ .resetvalue = 0,
31+ .writefn = pmuserenr_write, .raw_writefn = raw_write },
32 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
33 .access = PL1_RW,
34 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
35--
361.7.0.4
37
diff --git a/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch b/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch
deleted file mode 100644
index 8465deec..00000000
--- a/recipes-zynqmp/qemu/files/978364f12adebb4b8d90fdeb71242cb3c1405740.patch
+++ /dev/null
@@ -1,49 +0,0 @@
1From 978364f12adebb4b8d90fdeb71242cb3c1405740 Mon Sep 17 00:00:00 2001
2From: Alistair Francis <alistair.francis@xilinx.com>
3Date: Thu, 18 Feb 2016 14:16:17 +0000
4Subject: [PATCH] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
5
6Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
7Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
8Tested-by: Nathan Rossi <nathan@nathanrossi.com>
9Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis@xilinx.com
11Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12Upstream-Status: Backport
13---
14 target-arm/helper.c | 12 ++++++++++++
15 1 files changed, 12 insertions(+), 0 deletions(-)
16
17diff --git a/target-arm/helper.c b/target-arm/helper.c
18index 6a4ec01..9e47f3d 100644
19--- a/target-arm/helper.c
20+++ b/target-arm/helper.c
21@@ -1057,6 +1057,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
22 .accessfn = pmreg_access,
23 .writefn = pmovsr_write,
24 .raw_writefn = raw_write },
25+ { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
26+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
27+ .access = PL0_RW, .accessfn = pmreg_access,
28+ .type = ARM_CP_ALIAS,
29+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
30+ .writefn = pmovsr_write,
31+ .raw_writefn = raw_write },
32 /* Unimplemented so WI. */
33 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
34 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
35@@ -1107,6 +1114,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
36 .access = PL1_RW, .type = ARM_CP_ALIAS,
37 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
38 .writefn = pmintenclr_write, },
39+ { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
40+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
41+ .access = PL1_RW, .type = ARM_CP_ALIAS,
42+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
43+ .writefn = pmintenclr_write },
44 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
45 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
46 .access = PL1_RW, .writefn = vbar_write,
47--
481.7.0.4
49
diff --git a/recipes-zynqmp/qemu/qemu_2.5%.bbappend b/recipes-zynqmp/qemu/qemu_2.5%.bbappend
deleted file mode 100644
index 6f7cb506..00000000
--- a/recipes-zynqmp/qemu/qemu_2.5%.bbappend
+++ /dev/null
@@ -1,9 +0,0 @@
1
2FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
3
4SRC_URI += " \
5 file://4054bfa9e7986c9b7d2bf70f9e10af9647e376fc.patch \
6 file://8a83ffc2dafad3499b87a736b17ab1b203fdb00b.patch \
7 file://978364f12adebb4b8d90fdeb71242cb3c1405740.patch \
8 "
9
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-26 04:45:36 +0000