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| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-08-04 17:52:45 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-08-04 19:17:10 +0530 |
| commit | 36623c0153f39211180677f0ba72025494f34ede (patch) | |
| tree | ce032d7b8b522f339af457be652686bccc8d5fcd | |
| parent | 9cf0d717a112aed173961cdc2ba4ca0dcdafd6cc (diff) | |
| download | meta-xilinx-36623c0153f39211180677f0ba72025494f34ede.tar.gz | |
embeddedsw : Updated SRCREV for 2023.2_2419
xilpm: versal_common: server: Fixed PLM compilation warning
esw: Add support for stack and heap configuration in sdt flow
axidma: Fix base address in examples for SDT flow
vphy: added Dir for clock primitive
v_hdmitxss1: added compliance related changes
v_hdmirxss1: added compliance related changes
v_hdmiphy1: added Dir for clock primitive
VersalNet: Trng: Fix compilation warning
Revert "sw_apps: zynq_fsbl: fixed addresses issue in SDT flow"
sysmonpsv: Add support for SDT
sw_services:xilsecure:Initialize KeySizeInWords to avoid invalid value incase of glitch
sw_services:xilsecure:Rename XSecure_AesDpaCmDecryptKat to XSecure_AesDpaCmDecryptData
sw_services:xilsecure:Add volatile keyword for SStatus variable
mcdma: Fix canonical definiton in interupt example
mcdma: Fix interrupt ids in interrupt example
v_hdmirx1: Handle Rx data when there is delay between Rx clock and data
BSP: fix style issues
BSP: Remove XPAR_CPU_ID dependency
scugic: Fix style issues.
scugic: Remove XPAR_CPU_ID dependency
sw_apps: zynq_fsbl: fixed addresses issue in SDT flow
VPROCSS: Added Overview to addtogroup instead of driver version
VPROCSS: Driver version is incremented to v2_12
VPROCSS: Error correction in tcl file
xilpm: versal: server: Validate PwrDomain pointer
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 871ea843..5b849331 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" | |||
| 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
| 9 | 9 | ||
| 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
| 11 | ESW_REV[2023.2] = "45caafc34f34bd84b057cb51ae215a16fe9b88cd" | 11 | ESW_REV[2023.2] = "3296a4acd4b09942d03ced91147a1062b6e9b204" |
| 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 13 | 13 | ||
| 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |