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author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-07-24 14:25:58 +0530 |
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committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-07-24 18:57:09 +0530 |
commit | 6f0ac2d36e1cfbb974855e8ce3bfac40706201b0 (patch) | |
tree | 1be32df21d0da2b4e46d78e9f523371a2555b3cf | |
parent | 0e091d07e4ab746e7e34dd13cecf159352036648 (diff) | |
download | meta-xilinx-6f0ac2d36e1cfbb974855e8ce3bfac40706201b0.tar.gz |
embeddedsw : Updated SRCREV for 2023.2_8215
lib: sw_services: xilskey: Use CMake Cache variable for conditional checks
xadcps: Modify addtogroup
sysmon: Modify addtogroup
sysmonpsv: Modify addtogroup
dp14txss:tx_only: Removed custom print
xxvethernet: Update example dependency files in yaml
emaclite: Update yaml file with example details
axiethernet: Update example dependency files in yaml
lib: sw_apps: srec_bootloader: Fix style issues
lib: sw_apps: srec_bootloader: Add srec bootloader to embeddedsw repo
mipiciss:Uprevved to include VEK280_REVB and RC Programming
mipicsiss:Added Support for VEK280_REVB and RC programming to Support HDMI2.1
usb: usbps: fix code formatting issues with checkpatch
scugic: Fix XScuGic_DeviceInterruptHandler for SDT flow
sw_services: xilocp: Add access permission for XOCP_API_GEN_SHARED_SECRET
sw_services: xilsecure: Calculation of shared secret
sw_services: xilskey: update the xilskey library to support vitisng flow
xilpm: versal: server: Add Laguna housecleaning
sw_apps: versal_plm: Update the versal_plm template app to support vitisng flow.
sw_services: xilnvm: Update the xilnvm library to support vitisng flow.
sw_services: xilpuf: Update the xilpuf library to support vitisng flow.
bsp: standalone: updated the cmake list file
sw_services: xilsecure: Update the xilsecure library to support vitisng flow.
sw_services: xilloader: Update the xilloader library to support vitisng flow.
sw_services: xilplmi: Update the xilplmi library to support vitisng flow.
sw_services: xilpdi: Update the xilpdi library to support vitisng flow.
sw_apps: rsa_auth_app: update the rsa auth app to support vitisng flow.
Revert "sw_apps: zynqmp_fsbl: Update the zynqmp_fsbl template app to support vitisng flow."
xilffs: Update xilffs.yaml file
xilloader: Measure SPK ID and Encryption Revoke ID before PCR extend
FRMBUF Drivers: Corrected Frmbuf rd and wr Yaml files
gpiops: Add support zynq platform in sdt flow
qspips: Fix syntax issues in CMakeLists.txt
scripts: pyesw: library_utils: Pull the library based on the supported_processor list
scripts:pyesw:repo: Adding a check to continue scanning if a yaml reading fails
scuwdt: Fix formatting issues
scuwdt: Add support for system device tree based flow
scuwdt: Update addtogroup from version num to overview
scuwdt: Update copyright information.
scuwdt: Increment the version number
scripts: pyesw: open-amp: Update apps to use single unified SDT location
scripts: pyesw: build_app: openamp: pass app name for apps
scripts: pyesw: open-amp: update library name for open-amp to openamp
qspips: Fix code formatting issues with checkpatch
qspips: Add support for system device-tree flow for example
qspips: Update the driver to support for system device-tree flow
dp21txss: Fix Macro definations for 20Gbps and 13.5Gbps
dp21: Fix Macro definations for 20Gbps and 13.5Gbps
sysmonpsu: Add SDT support
csudma: Fix additional line in yaml file
xilocp: clear DICE CDI SEED
freertos10_xilinx: sync xparameters.h with standalone BSP
TPG: Ported driver for decoupling flow.
TPG: Added yaml file for decoupling flow support
TPG: incremeted driver version
VTC: Ported driver for decoupling flow.
VTC: Added yaml file for decoupling flow support
VTC: IP version is incremented
FrmBuf_Wr: Ported driver for decoupling flow.
FrmBuf_Wr: Added yaml file for decoupling flow support
FrmBuf_Rd: Ported driver for decoupling flow.
FrmBuf_Rd: Added yaml file for decoupling flow support
sw_apps: zynq_fsbl: update the zynq_fsbl template app to support vitisng flow.
dfeofdm: Add SDT examples
dfemix: Add SDT examples
sw_apps: zynqmp_fsbl: Update the zynqmp_fsbl template app to support vitisng flow.
dfeequ: Add SDT examples
xilpm:versal_net: save and restore subsystem flags and ipi masks
dfeccf: Add SDT examples
BSP: riscv: Fix style issues
BSP:riscv: Add missing CSR definitions
BSP: riscv: Add checks in exception init
lib: sw_apps: openamp: sdt: Move common files to single directory
lib: sw_apps: openamp: sdt: Update YAML to use openamp instead of open-amp
ThirdParty: sw_services: OpenAMP: sdt: Move YAML to be consistent with directory structure
ThirdParty: sw_services: OpenAMP: sdt: Add descriptions for Libmetal and OpenAMP
mcdma: Fix code formatting using checkpatch tool
mcdma: Add support for SDT flow in examples
mcdma: Fix LookUpConfig in SDT flow
BSP: Do not define ARMv8 specific macros for other processors
qspipsu: Update dependency_files inorder to pull dependency files automatically
emacps: Update dependency_files inorder to pull dependency files automatically
bram: Fix formatting issues
bram: Add system-device-tree support for example
bram: Update the driver for system device tree flow
bram: Update the driver version
scripts: pyesw: library_utils: Update dependency_files if the supported platforms are not present
Revert "xiplmi: Removed Error Action from Error Table while disabling error"
sw_services:xilsecure:Parameter name change in xilsecure mld
xilpm: versal_common: server: Change IPI Access permissions for PM API
xilpm : cfg: Add Check for master if defined before the returning a macro string
vphy: Added support for clock primitive
vphy: Added support for clock primitive
v_hdmiphy1: Added clock primitive
v_hdmiphy1: Added clock primitive
v_hdmitxss1: Fixed the define for VEK280
v_hdmirxss1: Fixed the define for VEK280
dp14txss:zcu_pt_dp14_hdcp:Added support to the hdcp app to work with any combination of hdcp1.3/2.2 on rx and tx
xilpm: versal_common: Bug fix for XPmPinFunc_GetFuncName
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
-rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 002f1c66..31670d9e 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
@@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "master-next" | |||
8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
9 | 9 | ||
10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
11 | ESW_REV[2023.2] = "59e453fa60231b5b946ce4a92e202b51f36e6a6e" | 11 | ESW_REV[2023.2] = "914cae1dc327bd1356a28222f561f585ab1210f5" |
12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
13 | 13 | ||
14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |