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| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-07-31 17:01:18 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-07-31 17:57:23 +0530 |
| commit | 76acc49c42cfaf0dda6f33744598f573275ba5d6 (patch) | |
| tree | ea861aa3d3cf236c5eb38602620f8f9b0063fa4a | |
| parent | 3a94f29d7b56abc56c5837cb75e094d12cd7e1f8 (diff) | |
| download | meta-xilinx-76acc49c42cfaf0dda6f33744598f573275ba5d6.tar.gz | |
embeddedsw : Updated SRCREV for 2023.2_7299
xilpm: versal: server: SRST support for xcvp1902
xilpm: versal: server: SRST support for xcvp1902
lib: sw_services: xilpm: Auto generate device specific macro for xcvp1902
sw_services:xilsecure:Updated PCIE IDE KAT macro names
sw_services:xilloader:Added example for LoadPDI from IS
freertos10_xilinx: ARM_CR5: Invoke XTimer_ReleaseTickTimer to release tick timer
lib: sw_services: xiltimer: Add xiltimer release support
ttcps: Invoke XTtcPs_Release to release ttc node
ttcps: Add support for ttc release node
gpio: Use proper base address macro in xgpio_low_level_example for non-sdt flow
ipipsu: Fix MISRA-C violations
cmake: UserConfig.cmake: Remove the quotes around variable initialization
dp21rxss: Enable HDCP2X Timer handler calling function only when HDCP2X is enabled.
dp21rxss: dp21rxss: Added AMD copyright under the Xilinx copyright for the 2023.1 modified files
dp21rxss: Added AMD copyright.
sw_services: xilmailbox: Fix code formatting issues with checkpatch
sw_services: xilmailbox: Restructure the code for more modularity
xadcps: Add SDT Support
cmake: toolchainfiles: microblaze_toolchain.cmake: Add no-relax linker flags by default
sw_services:xilplmi: Add XilStl SW triggered error events
BSP:standalone: Add XilStl errors to SW errors list
xilpm: versal_net: increase byte buffer size
xilpm: versal_net: power down core only if it powered up
versal_psmfw: enable IEN during pwr down
rfdc: Remove duplicate from yaml
lib: sw_apps: Update the hello_world and empty_application to support all c++ file extensions
drivers: tmr_inject: Fix compilation issue
qspipsu: Fix code format issue
qspipsu: Fix wrong init sequence
dmaps: Remove arm,primecell compatible string
qspips: Generate BUS_WIDTH define in xparameters.h in sdt flow
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index f9aca205..65af85a7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" | |||
| 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
| 9 | 9 | ||
| 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
| 11 | ESW_REV[2023.2] = "49600aaa2b6c6aa14f5b7d8924f7a1257ded6cf6" | 11 | ESW_REV[2023.2] = "1bcb421cce4011d8bd6a06bbc6834e7207762713" |
| 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 13 | 13 | ||
| 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |