diff options
| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-07-12 18:08:28 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-07-12 19:27:10 +0530 |
| commit | 85ef223f5670cb2f48856b1e069d92e252f51fd3 (patch) | |
| tree | dd11b7a24dd95215e40731f750b530aaebb2ab74 | |
| parent | 4a80aacb60eab96543dc981f4376ec529246a725 (diff) | |
| download | meta-xilinx-85ef223f5670cb2f48856b1e069d92e252f51fd3.tar.gz | |
linux-xlnx : Updated SRCREV for 2023.2_8535
dt-bindings: can: xilinx_can: Add reset description
can: xilinx_can: Add missing kernel-doc rstc description
can: dev: add transceiver capabilities to xilinx_can
misc: xilinx-ai-engine: Added support to capture utilization.
drivers: clk: zynqmp: calculate closest mux rate
net: axienet: Implement work queue to enable/disable link training
net: axienet: Add switchable 1/10/25G MAC support
dt-bindings: net: axienet: Update binding doc for 1/10G/25G MAC
misc: xilinx-ai-engine: Add sysfs nodes to show DMA buffer descriptor metadata
misc: xilinx-ai-engine: Add DMA buffer descriptor register attributes
ptp: Add support for EXTTS
dt-bindings: ptp: xilinx: Add interrupts property
ptp: xilinx: Add timer-syncer-1588-3.0 support
dt-bindings: ptp: xilinx: Add xlnx,timer-syncer-1588-3.0 compatible string
ptp: Add support for checking has-timer-syncer IP mode
dt-bindings: ptp: xilinx: Add xlnx,has-timer-syncer
drivers: iio: adc: xilinx-ams: Add over temperature interrupts
staging: xlnx_tsmux: Fix kernel-doc typo for structure names
arm64: configs: Enable PHY_XILINX_HDMIPHY for zynqmp and versal
phy: xilinx-xhdmiphy: Fix compilation errors
clk: si5324: Fix kernel-doc typo for si5324_regmap_is_writeable func
usb: dwc3: dwc3-xilinx: added usb-wakeup irq support
usb: dwc3: xilinx: enable pme interrupt for versal
dt-bindings: usb: dwc3: Add interrupt-names property support for wakeup interrupt
mtd: spi-nor: issi: Disable 16bit status register write
mtd: spi-nor: Add flash protection support for OSPI flashes
mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected
dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register
drivers: clk: zynqmp: update divider round rate logic
v4l: xilinx: dprx: Remove 0x200 obsolete register usage
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| -rw-r--r-- | meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb index c8dce760..6d45f90e 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2023.2.bb | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | LINUX_VERSION = "6.1.30" | 1 | LINUX_VERSION = "6.1.30" |
| 2 | YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.1;destsuffix=yocto-kmeta" | 2 | YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.1;destsuffix=yocto-kmeta" |
| 3 | KBRANCH="xlnx_rebase_v6.1_LTS" | 3 | KBRANCH="xlnx_rebase_v6.1_LTS" |
| 4 | SRCREV = "c8780751e11b1803eaf3e75ace5eccb3138f06d3" | 4 | SRCREV = "153f7bc5328f94aaf844698f816800996821a96b" |
| 5 | SRCREV_meta = "185bcfcbe480c742247d9117011794c69682914f" | 5 | SRCREV_meta = "185bcfcbe480c742247d9117011794c69682914f" |
| 6 | 6 | ||
| 7 | KCONF_AUDIT_LEVEL="0" | 7 | KCONF_AUDIT_LEVEL="0" |