diff options
| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-08-05 01:24:24 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-08-05 02:47:11 +0530 |
| commit | a043eb87127d589cb4b2a3a692e18e0441c097e9 (patch) | |
| tree | 4e833df04851ce22416522d1eee5225275baaa2a | |
| parent | 36623c0153f39211180677f0ba72025494f34ede (diff) | |
| download | meta-xilinx-a043eb87127d589cb4b2a3a692e18e0441c097e9.tar.gz | |
u-boot-xlnx : Updated SRCREV for 2023.2_6015
spi: zynqmp_qpsi: Enable invalidate_cache for ZynqMP and Versal
xilinx: board: Add support to pick bootscr address from DT
dm: core: ofnode: Add ofnode_read_bootscript_address()
Revert "arm64: xilinx: Replace _ from clock node names by -"
arm64: zynqmp: Get clock node name back with _
arm64: versal: Increase the number of DRAM banks to 36
spi: zynq: Configure lqspi register based on memory configuration
arm64: versal-net: Add sysmon node entry
xilinx: zynqmp: Do not setup boot_targets if driver is not enabled
xilinx: versal: Do not setup boot_targets if driver is not enabled
xilinx: versal-net: Do not setup boot_targets if driver is not enabled
arm64: xilinx: Do not use _ in DT node names
arm64: zynqmp: Use s/gtr_sel/gtr-sel/ for DT node name
arm64: zynqmp: Use s/heartbeat_led/heartbeat-led/ for DT node name
arm64: xilinx: Replace _ from clock node names by -
arm64: zynqmp: Rename xlnx,mio_bank to xlnx,mio-bank for DLC21
arm64: versal-net: Remove xlnx,device_id property from VNX
arm64: versal-net: Remove ref_clk node from VNX board
mtd: spi-nor: Update block protection flags for flash parts
net: zynq_gem: Add missing newline (upstream sync)
xilinx: versal-net: Remove additional newline in board.c
spi: spi-uclass: Dont return error for single cs
spi: spi-uclass: Move restricting multi_cs_cap code
dm: core: Remove debug print from of_read_u64_index
mtd: spi-nor: Add support for locking on Spansion nor flashes
mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes
mtd: spi-nor: Add support for locking on ISSI nor flashes
mtd: spi-nor: Add support for locking on Macronix nor flashes
clk: zynqmp: Add gem rx and tsu clocks to return register
clk: zynqmp: Add set_rate support for gem rx and tsu clks
arm64: zynqmp: Add resets property for CAN nodes
spi: zynq: Add support for parallel-memories and stacked-memories
spi: zynqmp_qspi: Add parallel memories support in GQSPI driver
spi: spi-uclass: Read chipselect and restrict capabilities
mtd: spi-nor: Add parallel and stacked memories support in spi-nor
dm: core: support reading a single indexed u64 value
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| -rw-r--r-- | meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc index 86080392..f3ad3b34 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc | |||
| @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2023.01" | |||
| 2 | 2 | ||
| 3 | UBRANCH = "xlnx_rebase_v2023.01" | 3 | UBRANCH = "xlnx_rebase_v2023.01" |
| 4 | 4 | ||
| 5 | SRCREV = "d627991fce3232f7d95c736868bc001a8624fc46" | 5 | SRCREV = "40fc929c8b210e7d4a45ca40881c888fb53b9926" |
| 6 | 6 | ||
| 7 | LICENSE = "GPL-2.0-or-later" | 7 | LICENSE = "GPL-2.0-or-later" |
| 8 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" | 8 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" |