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author | Mark Hatle <mark.hatle@amd.com> | 2025-02-03 15:11:12 -0700 |
---|---|---|
committer | Mark Hatle <mark.hatle@amd.com> | 2025-03-30 14:16:15 -0600 |
commit | 20bdea31fd72571eea76271a1c7c6b2e72816a2d (patch) | |
tree | 15e586bdf1822434d51ae52e06d35a084651a638 | |
parent | 6f3228a648a7ee82a0af424382d4dc55b6ee3dc5 (diff) | |
download | meta-xilinx-20bdea31fd72571eea76271a1c7c6b2e72816a2d.tar.gz |
meta-xilinx-core: arm-trusted-firmware: Move to new TFA_CONSOLE
gen-machine-conf is moving to using TFA_CONSOLE to match the newer TFA
recipe implementations. Adjust the older arm-trusted-firmware to match
while retaining compatibility with prior ATF_CONSOLE if required.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
-rw-r--r-- | meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 485d3b17..fec6a994 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | |||
@@ -50,15 +50,16 @@ ATF_CONSOLE_DEFAULT:zynqmp = "cadence" | |||
50 | ATF_CONSOLE_DEFAULT:versal = "pl011" | 50 | ATF_CONSOLE_DEFAULT:versal = "pl011" |
51 | ATF_CONSOLE_DEFAULT:versal-net = "pl011" | 51 | ATF_CONSOLE_DEFAULT:versal-net = "pl011" |
52 | ATF_CONSOLE ?= "${ATF_CONSOLE_DEFAULT}" | 52 | ATF_CONSOLE ?= "${ATF_CONSOLE_DEFAULT}" |
53 | TFA_CONSOLE ?= "${ATF_CONSOLE}" | ||
53 | 54 | ||
54 | DEBUG_ATF_DEFAULT = "" | 55 | DEBUG_ATF_DEFAULT = "" |
55 | DEBUG_ATF_DEFAULT:versal = "1" | 56 | DEBUG_ATF_DEFAULT:versal = "1" |
56 | DEBUG_ATF_DEFAULT:versal-net = "1" | 57 | DEBUG_ATF_DEFAULT:versal-net = "1" |
57 | DEBUG_ATF ?= "${DEBUG_ATF_DEFAULT}" | 58 | DEBUG_ATF ?= "${DEBUG_ATF_DEFAULT}" |
58 | 59 | ||
59 | EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" | 60 | EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_CONSOLE=${TFA_CONSOLE}' if d.getVar('TFA_CONSOLE', True) != '' else ''}" |
60 | EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" | 61 | EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${TFA_CONSOLE}' if d.getVar('TFA_CONSOLE', True) != '' else ''}" |
61 | EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" | 62 | EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_CONSOLE=${TFA_CONSOLE}' if d.getVar('TFA_CONSOLE', True) != '' else ''}" |
62 | EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}" | 63 | EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}" |
63 | 64 | ||
64 | OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" | 65 | OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" |
@@ -129,16 +130,16 @@ INSANE_SKIP:${PN}:append:versal-net = " buildpaths" | |||
129 | 130 | ||
130 | python() { | 131 | python() { |
131 | soc_family = d.getVar('SOC_FAMILY') | 132 | soc_family = d.getVar('SOC_FAMILY') |
132 | atf_console = d.getVar('ATF_CONSOLE') | 133 | atf_console = d.getVar('TFA_CONSOLE') |
133 | 134 | ||
134 | # See plat/xilinx/<soc_family>/platform.mk | 135 | # See plat/xilinx/<soc_family>/platform.mk |
135 | if soc_family and soc_family == "zynqmp": | 136 | if soc_family and soc_family == "zynqmp": |
136 | if not atf_console in [ 'cadence', 'cadence0', 'cadence1', 'dcc' ]: | 137 | if not atf_console in [ 'cadence', 'cadence0', 'cadence1', 'dcc' ]: |
137 | raise bb.parse.SkipRecipe('ATF_CONSOLE (%s) is not configured properly for ZynqMP, only cadence, cadence0, cadence1, and dcc are valid options.' % (atf_console)) | 138 | raise bb.parse.SkipRecipe('TFA_CONSOLE (%s) is not configured properly for ZynqMP, only cadence, cadence0, cadence1, and dcc are valid options.' % (atf_console)) |
138 | elif soc_family and soc_family == "versal": | 139 | elif soc_family and soc_family == "versal": |
139 | if not atf_console in [ 'pl011', 'pl011_0', 'pl011_1', 'dcc' ]: | 140 | if not atf_console in [ 'pl011', 'pl011_0', 'pl011_1', 'dcc' ]: |
140 | raise bb.parse.SkipRecipe('ATF_CONSOLE (%s) is not configured properly for Versal, only pl011, pl011_0, pl011_1, and dcc are valid options.' % (atf_console)) | 141 | raise bb.parse.SkipRecipe('TFA_CONSOLE (%s) is not configured properly for Versal, only pl011, pl011_0, pl011_1, and dcc are valid options.' % (atf_console)) |
141 | elif soc_family and soc_family == "versal-net": | 142 | elif soc_family and soc_family == "versal-net": |
142 | if not atf_console in [ 'pl011', 'pl011_0', 'pl011_1', 'dcc' ]: | 143 | if not atf_console in [ 'pl011', 'pl011_0', 'pl011_1', 'dcc' ]: |
143 | raise bb.parse.SkipRecipe('ATF_CONSOLE (%s) is not configured properly for Versal-Net, only pl011, pl011_0, pl011_1, and dcc are valid options.' % (atf_console)) | 144 | raise bb.parse.SkipRecipe('TFA_CONSOLE (%s) is not configured properly for Versal-Net, only pl011, pl011_0, pl011_1, and dcc are valid options.' % (atf_console)) |
144 | } | 145 | } |