boot-jtag: Fix fpga-overlay typo

boot-jtag script had a type for fpga-overlay and due to this it fails
to build with below errors when fpga-overlay is enabled for zynqmp or
versal devices.

$ MACHINE=zynqmp-zcu104-sdt-full devtool boot-jtag --image core-image-full-cmdline --hw_server zcu104-5
NOTE: Starting bitbake server...
NOTE: Started PRServer with DBfile: /scratch/sandeep/yocto/2024.2/yp-dev/build-yp-native/cache/prserv.sqlite3, Address: 127.0.0.1:33765, PID: 1586408
NOTE: Reconnecting to bitbake server...
NOTE: Retrying server connection (#1)... (09:43:24.858854)
NOTE: Started PRServer with DBfile: /scratch/sandeep/yocto/2024.2/yp-dev/build-yp-native/cache/prserv.sqlite3, Address: 127.0.0.1:35749, PID: 1586439
Loading cache: 100% |###############################################################################################################################################################################| Time: 0:00:06
Loaded 26502 entries from dependency cache.
Parsing recipes: 100% |#############################################################################################################################################################################| Time: 0:00:02
Parsing of 18552 .bb files complete (18543 cached, 9 parsed). 26511 targets, 13521 skipped, 81 masked, 0 errors.
INFO: HW_SERVER Connected to: zcu104-5
INFO: Using DISTRO IMAGE: core-image-full-cmdline
INFO: SOC FAMILY: zynqmp
INFO: MACHINE: zynqmp-zcu104-sdt-full
INFO: fpga-overlay MACHINE_FEATURES is not enabled, Hence PL bitstream or PDI will be loaded at initial boot.
Traceback (most recent call last):
  File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/scripts/devtool", line 350, in <module>
    ret = main()
  File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/scripts/devtool", line 337, in main
    ret = args.func(args, config, basepath, workspace)
  File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/../meta-xilinx/meta-xilinx-core/lib/devtool/boot-jtag.py", line 82, in bootjtag
    data['bit'] = glob.glob(os.path.join(deploy_dir, '*' + machine + '.bit'))[0]
IndexError: list index out of range

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/meta-xilinx-core/lib/devtool/boot-jtag.py b/meta-xilinx-core/lib/devtool/boot-jtag.py
index 2d8a7d8f..ce38edf9 100644
--- a/meta-xilinx-core/lib/devtool/boot-jtag.py
+++ b/meta-xilinx-core/lib/devtool/boot-jtag.py
@@ -68,7 +68,7 @@ def bootjtag(args, config, basepath, workspace):
     print("INFO: MACHINE: " + machine)
 
     if arch != 'microblazeel':
-        if "fpga-overaly" in machine_features:
+        if "fpga-overlay" in machine_features:
             print("INFO: fpga-overlay MACHINE_FEATURES is enabled, Hence PL bitstream or PDI will not be loaded at initial boot, User can load from u-boot or linux.")
         else:
             print("INFO: fpga-overlay MACHINE_FEATURES is not enabled, Hence PL bitstream or PDI will be loaded at initial boot.")
@@ -78,7 +78,7 @@ def bootjtag(args, config, basepath, workspace):
 
     # For MB, Zynq 7000 and ZynqMP.
     if arch == 'microblazeel' or soc == 'zynq' or soc == 'zynqmp':
-        if not "fpga-overaly" in machine_features:
+        if not "fpga-overlay" in machine_features:
             data['bit'] = glob.glob(os.path.join(deploy_dir, '*' + machine + '.bit'))[0]
         data['uboot'] = os.path.join(deploy_dir, 'u-boot.elf')
         data['dtb'] = os.path.join(deploy_dir, machine + '-system.dtb')
@@ -122,7 +122,7 @@ def bootjtag(args, config, basepath, workspace):
         lines.append('    if { [ta] != "" } break;')
         lines.append('    after 50')
         lines.append('}')
-        if not "fpga-overaly" in machine_features:
+        if not "fpga-overlay" in machine_features:
             lines.append('')
             lines.append('puts stderr "INFO: Configuring the PL ..."')
             lines.append('puts stderr "INFO: Downloading bitstream: ' + data['bit'] + '"')