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authorNathan Rossi <nathan@nathanrossi.com>2017-09-29 17:52:14 +1000
committerNathan Rossi <nathan@nathanrossi.com>2017-10-18 17:59:53 +1000
commit6463de465e89bebfa4b20ae7cdd1533a524a271f (patch)
tree29c34c40f1f6f74473350fcaaad818f0ea8ac635
parent09e9c3e8428d780b6056918b61766247d87e5b59 (diff)
downloadmeta-xilinx-6463de465e89bebfa4b20ae7cdd1533a524a271f.tar.gz
Drop Xilinx v2016.x release recipes
These recipes were primarily kept to make the transition for ZynqMP from Non PMU Firmware to PMU Firmware easier for users. However these releases are now outdated (by at least a year) and users should have already transitioned or sorted out a long term strategy if not. This change also drops any patches that were only used/available for these recipes. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Diffstat
-rw-r--r--recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2016.3.bb7
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/arm-zynqmp-xilinx_zynqmp.h-Auto-boot-in-JTAG-if-imag.patch48
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch1065
-rw-r--r--recipes-bsp/u-boot/u-boot-xlnx_2016.4.bb29
-rw-r--r--recipes-bsp/u-boot/u-boot/0001-fdt-add-memory-bank-decoding-functions-for-board-set.patch144
-rw-r--r--recipes-bsp/u-boot/u-boot/0002-ARM-zynq-Replace-board-specific-with-generic-memory-.patch170
-rw-r--r--recipes-bsp/u-boot/u-boot/0003-ARM64-zynqmp-Replace-board-specific-with-generic-mem.patch156
-rw-r--r--recipes-kernel/linux/linux-xlnx/4.6/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch299
-rw-r--r--recipes-kernel/linux/linux-xlnx/4.6/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch607
-rw-r--r--recipes-kernel/linux/linux-xlnx/4.6/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch65
-rw-r--r--recipes-kernel/linux/linux-xlnx_2016.4.bb12
11 files changed, 0 insertions, 2602 deletions
diff --git a/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2016.3.bb b/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2016.3.bb
deleted file mode 100644
index dc5e3fa1..00000000
--- a/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2016.3.bb
+++ /dev/null
@@ -1,7 +0,0 @@
1include arm-trusted-firmware.inc
2
3XILINX_RELEASE_VERSION = "v2016.3"
4SRCREV ?= "a9e3716615a23c78e3cdea5b5b2f840f89817cb1"
5
6PV = "1.2-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
7
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/arm-zynqmp-xilinx_zynqmp.h-Auto-boot-in-JTAG-if-imag.patch b/recipes-bsp/u-boot/u-boot-xlnx/arm-zynqmp-xilinx_zynqmp.h-Auto-boot-in-JTAG-if-imag.patch
deleted file mode 100644
index badff7e6..00000000
--- a/recipes-bsp/u-boot/u-boot-xlnx/arm-zynqmp-xilinx_zynqmp.h-Auto-boot-in-JTAG-if-imag.patch
+++ /dev/null
@@ -1,48 +0,0 @@
1From 9d44bd18191a56331273beb7c26b18afe154c82c Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Fri, 4 Nov 2016 21:33:14 +1000
4Subject: [PATCH] arm: zynqmp: xilinx_zynqmp.h: Auto boot in JTAG if images in
5 memory
6
7Add a command that checks if the Kernel image (in aarch64 Image format)
8and optionally a rootfs is in memory and automatically boot these images
9if in JTAG boot mode.
10
11This allows for simpler boot automation in JTAG boot environments
12(including QEMU) where manual interaction would otherwise be required.
13
14Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
15Upstream-Status: Denied [Upstream prefers FIT instead]
16---
17 include/configs/xilinx_zynqmp.h | 8 +++++---
18 1 file changed, 5 insertions(+), 3 deletions(-)
19
20diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
21index 4714b3317d..0441f3f24f 100644
22--- a/include/configs/xilinx_zynqmp.h
23+++ b/include/configs/xilinx_zynqmp.h
24@@ -246,8 +246,10 @@
25 "run xen_prepare_dt_qemu && " \
26 "tftpb 6000000 xen.ub && tftpb 0x1000000 image.ub && " \
27 "bootm 6000000 0x1000000 $fdt_addr\0" \
28- "jtagboot=tftpboot 80000 Image && tftpboot $fdt_addr system.dtb && " \
29- "tftpboot 6000000 rootfs.cpio.ub && booti 80000 6000000 $fdt_addr\0" \
30+ "jtagmemboot=if itest.w *0x80038 == 0x644d5241; then if iminfo 0x6000000; then booti 0x80000 0x6000000 $fdt_addr; else booti 0x80000 - $fdt_addr; fi; fi\0" \
31+ "jtagboot=run jtagmemboot || " \
32+ "tftpboot 80000 Image && tftpboot $fdt_addr system.dtb && " \
33+ "tftpboot 6000000 rootfs.cpio.ub && booti 80000 6000000 $fdt_addr\0" \
34 "nosmp=setenv bootargs $bootargs maxcpus=1\0" \
35 "nfsroot=setenv bootargs $bootargs root=/dev/nfs nfsroot=$serverip:/mnt/sata,tcp ip=$ipaddr:$serverip:$serverip:255.255.255.0:zynqmp:eth0:off rw\0" \
36 "sdroot0=setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait\0" \
37@@ -269,7 +271,7 @@
38
39 /* Do not preserve environment */
40 #define CONFIG_ENV_IS_NOWHERE 1
41-#define CONFIG_ENV_SIZE 0x1000
42+#define CONFIG_ENV_SIZE 0x2000
43
44 /* Monitor Command Prompt */
45 /* Console I/O Buffer Size */
46--
472.11.0
48
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch
deleted file mode 100644
index 3959c552..00000000
--- a/recipes-bsp/u-boot/u-boot-xlnx/microblaze-kc705-Convert-microblaze-generic-to-k.patch
+++ /dev/null
@@ -1,1065 +0,0 @@
1From 5b6177a13aa531125cf5a80cfca9746ea37d98e8 Mon Sep 17 00:00:00 2001
2From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
3Date: Wed, 14 Sep 2016 14:34:48 -0700
4Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to kc705-microblazeel
5
6This is an update to earlier kc705-trd patch done by Nathan Rossi. Starting
7from v2016.1, KC705 will no longer refer to deprecated KC705 TRD application.
8
9Change the microblaze-generic board to match the kc705-microblazeel. This patch
10is not intended for upstream and serves as an intermediate solution
11until OF support in upstream u-boot allows for easy support for custom
12microblaze boards.
13
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
16---
17 arch/microblaze/dts/microblaze-generic.dts | 442 ++++++++++++++++++++++++++
18 board/xilinx/microblaze-generic/config.mk | 30 +-
19 configs/microblaze-generic_defconfig | 17 +-
20 include/configs/microblaze-generic.h | 488 +++++++++++------------------
21 4 files changed, 631 insertions(+), 346 deletions(-)
22
23diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
24index 08a1396..f46c185 100644
25--- a/arch/microblaze/dts/microblaze-generic.dts
26+++ b/arch/microblaze/dts/microblaze-generic.dts
27@@ -2,8 +2,450 @@
28 / {
29 #address-cells = <1>;
30 #size-cells = <1>;
31+ model = "Xilinx MicroBlaze";
32+ compatible = "xlnx,microblaze";
33 aliases {
34+ serial0 = &rs232_uart;
35+ ethernet0 = &axi_ethernet;
36 } ;
37 chosen {
38+ bootargs = "console=ttyS0,115200 earlyprintk";
39+ stdout-path = "serial0:115200ns";
40 } ;
41+ memory {
42+ device_type = "memory";
43+ reg = <0x80000000 0x40000000>;
44+ };
45+ cpus {
46+ #address-cells = <1>;
47+ #cpus = <1>;
48+ #size-cells = <0>;
49+ microblaze_0: cpu@0 {
50+ bus-handle = <&amba_pl>;
51+ clock-frequency = <200000000>;
52+ clocks = <&clk_cpu>;
53+ compatible = "xlnx,microblaze-9.6";
54+ d-cache-baseaddr = <0x0000000080000000>;
55+ d-cache-highaddr = <0x00000000bfffffff>;
56+ d-cache-line-size = <0x20>;
57+ d-cache-size = <0x4000>;
58+ device_type = "cpu";
59+ i-cache-baseaddr = <0x0000000080000000>;
60+ i-cache-highaddr = <0x00000000BFFFFFFF>;
61+ i-cache-line-size = <0x10>;
62+ i-cache-size = <0x4000>;
63+ interrupt-handle = <&microblaze_0_axi_intc>;
64+ model = "microblaze,9.6";
65+ timebase-frequency = <200000000>;
66+ xlnx,addr-size = <0x20>;
67+ xlnx,addr-tag-bits = <0x10>;
68+ xlnx,allow-dcache-wr = <0x1>;
69+ xlnx,allow-icache-wr = <0x1>;
70+ xlnx,area-optimized = <0x0>;
71+ xlnx,async-interrupt = <0x1>;
72+ xlnx,async-wakeup = <0x3>;
73+ xlnx,avoid-primitives = <0x0>;
74+ xlnx,base-vectors = <0x0000000000000000>;
75+ xlnx,branch-target-cache-size = <0x0>;
76+ xlnx,cache-byte-size = <0x4000>;
77+ xlnx,d-axi = <0x1>;
78+ xlnx,d-lmb = <0x1>;
79+ xlnx,d-lmb-mon = <0x0>;
80+ xlnx,daddr-size = <0x20>;
81+ xlnx,data-size = <0x20>;
82+ xlnx,dc-axi-mon = <0x0>;
83+ xlnx,dcache-addr-tag = <0x10>;
84+ xlnx,dcache-always-used = <0x1>;
85+ xlnx,dcache-byte-size = <0x4000>;
86+ xlnx,dcache-data-width = <0x0>;
87+ xlnx,dcache-force-tag-lutram = <0x0>;
88+ xlnx,dcache-line-len = <0x8>;
89+ xlnx,dcache-use-writeback = <0x0>;
90+ xlnx,dcache-victims = <0x0>;
91+ xlnx,debug-counter-width = <0x20>;
92+ xlnx,debug-enabled = <0x1>;
93+ xlnx,debug-event-counters = <0x5>;
94+ xlnx,debug-external-trace = <0x0>;
95+ xlnx,debug-interface = <0x0>;
96+ xlnx,debug-latency-counters = <0x1>;
97+ xlnx,debug-profile-size = <0x0>;
98+ xlnx,debug-trace-size = <0x2000>;
99+ xlnx,div-zero-exception = <0x1>;
100+ xlnx,dp-axi-mon = <0x0>;
101+ xlnx,dynamic-bus-sizing = <0x0>;
102+ xlnx,ecc-use-ce-exception = <0x0>;
103+ xlnx,edge-is-positive = <0x1>;
104+ xlnx,enable-discrete-ports = <0x0>;
105+ xlnx,endianness = <0x1>;
106+ xlnx,fault-tolerant = <0x0>;
107+ xlnx,fpu-exception = <0x0>;
108+ xlnx,freq = <0xbebc200>;
109+ xlnx,fsl-exception = <0x0>;
110+ xlnx,fsl-links = <0x0>;
111+ xlnx,i-axi = <0x0>;
112+ xlnx,i-lmb = <0x1>;
113+ xlnx,i-lmb-mon = <0x0>;
114+ xlnx,iaddr-size = <0x20>;
115+ xlnx,ic-axi-mon = <0x0>;
116+ xlnx,icache-always-used = <0x1>;
117+ xlnx,icache-data-width = <0x0>;
118+ xlnx,icache-force-tag-lutram = <0x0>;
119+ xlnx,icache-line-len = <0x4>;
120+ xlnx,icache-streams = <0x1>;
121+ xlnx,icache-victims = <0x8>;
122+ xlnx,ill-opcode-exception = <0x1>;
123+ xlnx,imprecise-exceptions = <0x0>;
124+ xlnx,instr-size = <0x20>;
125+ xlnx,interconnect = <0x2>;
126+ xlnx,interrupt-is-edge = <0x0>;
127+ xlnx,interrupt-mon = <0x0>;
128+ xlnx,ip-axi-mon = <0x0>;
129+ xlnx,lockstep-master = <0x0>;
130+ xlnx,lockstep-select = <0x0>;
131+ xlnx,lockstep-slave = <0x0>;
132+ xlnx,mmu-dtlb-size = <0x4>;
133+ xlnx,mmu-itlb-size = <0x2>;
134+ xlnx,mmu-privileged-instr = <0x0>;
135+ xlnx,mmu-tlb-access = <0x3>;
136+ xlnx,mmu-zones = <0x2>;
137+ xlnx,num-sync-ff-clk = <0x2>;
138+ xlnx,num-sync-ff-clk-debug = <0x2>;
139+ xlnx,num-sync-ff-clk-irq = <0x1>;
140+ xlnx,num-sync-ff-dbg-clk = <0x1>;
141+ xlnx,number-of-pc-brk = <0x1>;
142+ xlnx,number-of-rd-addr-brk = <0x0>;
143+ xlnx,number-of-wr-addr-brk = <0x0>;
144+ xlnx,opcode-0x0-illegal = <0x1>;
145+ xlnx,optimization = <0x0>;
146+ xlnx,pc-width = <0x20>;
147+ xlnx,pvr = <0x2>;
148+ xlnx,pvr-user1 = <0x00>;
149+ xlnx,pvr-user2 = <0x00000000>;
150+ xlnx,reset-msr = <0x00000000>;
151+ xlnx,reset-msr-bip = <0x0>;
152+ xlnx,reset-msr-dce = <0x0>;
153+ xlnx,reset-msr-ee = <0x0>;
154+ xlnx,reset-msr-eip = <0x0>;
155+ xlnx,reset-msr-ice = <0x0>;
156+ xlnx,reset-msr-ie = <0x0>;
157+ xlnx,sco = <0x0>;
158+ xlnx,trace = <0x0>;
159+ xlnx,unaligned-exceptions = <0x1>;
160+ xlnx,use-barrel = <0x1>;
161+ xlnx,use-branch-target-cache = <0x0>;
162+ xlnx,use-config-reset = <0x0>;
163+ xlnx,use-dcache = <0x1>;
164+ xlnx,use-div = <0x1>;
165+ xlnx,use-ext-brk = <0x0>;
166+ xlnx,use-ext-nm-brk = <0x0>;
167+ xlnx,use-extended-fsl-instr = <0x0>;
168+ xlnx,use-fpu = <0x0>;
169+ xlnx,use-hw-mul = <0x2>;
170+ xlnx,use-icache = <0x1>;
171+ xlnx,use-interrupt = <0x2>;
172+ xlnx,use-mmu = <0x3>;
173+ xlnx,use-msr-instr = <0x1>;
174+ xlnx,use-non-secure = <0x0>;
175+ xlnx,use-pcmp-instr = <0x1>;
176+ xlnx,use-reorder-instr = <0x1>;
177+ xlnx,use-stack-protection = <0x0>;
178+ };
179+ };
180+ clocks {
181+ #address-cells = <1>;
182+ #size-cells = <0>;
183+ clk_cpu: clk_cpu@0 {
184+ #clock-cells = <0>;
185+ clock-frequency = <200000000>;
186+ clock-output-names = "clk_cpu";
187+ compatible = "fixed-clock";
188+ reg = <0>;
189+ };
190+ clk_bus_0: clk_bus_0@1 {
191+ #clock-cells = <0>;
192+ clock-frequency = <200000000>;
193+ clock-output-names = "clk_bus_0";
194+ compatible = "fixed-clock";
195+ reg = <1>;
196+ };
197+ };
198+ amba_pl: amba_pl {
199+ #address-cells = <1>;
200+ #size-cells = <1>;
201+ compatible = "simple-bus";
202+ ranges ;
203+ axi_ethernet: ethernet@40c00000 {
204+ axistream-connected = <&axi_ethernet_dma>;
205+ axistream-control-connected = <&axi_ethernet_dma>;
206+ clock-frequency = <100000000>;
207+ compatible = "xlnx,axi-ethernet-1.00.a";
208+ device_type = "network";
209+ interrupt-parent = <&microblaze_0_axi_intc>;
210+ interrupts = <4 2>;
211+ phy-mode = "gmii";
212+ reg = <0x40c00000 0x40000>;
213+ xlnx = <0x0>;
214+ xlnx,axiliteclkrate = <0x0>;
215+ xlnx,axisclkrate = <0x0>;
216+ xlnx,enableasyncsgmii = <0x0>;
217+ xlnx,gt-type = <0x0>;
218+ xlnx,gtinex = <0x0>;
219+ xlnx,gtlocation = <0x0>;
220+ xlnx,gtrefclksrc = <0x0>;
221+ xlnx,phy-type = <0x1>;
222+ xlnx,phyaddr = <0x1>;
223+ xlnx,rable = <0x0>;
224+ xlnx,rxcsum = <0x0>;
225+ xlnx,rxlane0-placement = <0x0>;
226+ xlnx,rxlane1-placement = <0x0>;
227+ xlnx,rxmem = <0x1000>;
228+ xlnx,rxnibblebitslice0used = <0x1>;
229+ xlnx,tx-in-upper-nibble = <0x1>;
230+ xlnx,txcsum = <0x0>;
231+ xlnx,txlane0-placement = <0x0>;
232+ xlnx,txlane1-placement = <0x0>;
233+ axi_ethernet_mdio: mdio {
234+ #address-cells = <1>;
235+ #size-cells = <0>;
236+ };
237+ };
238+ axi_ethernet_dma: dma@41e00000 {
239+ #dma-cells = <1>;
240+ axistream-connected = <&axi_ethernet>;
241+ axistream-control-connected = <&axi_ethernet>;
242+ clock-frequency = <200000000>;
243+ clock-names = "s_axi_lite_aclk";
244+ clocks = <&clk_bus_0>;
245+ compatible = "xlnx,eth-dma";
246+ interrupt-parent = <&microblaze_0_axi_intc>;
247+ interrupts = <3 2 2 2>;
248+ reg = <0x41e00000 0x10000>;
249+ };
250+ axi_timer_0: timer@41c00000 {
251+ clock-frequency = <200000000>;
252+ clocks = <&clk_bus_0>;
253+ compatible = "xlnx,xps-timer-1.00.a";
254+ interrupt-parent = <&microblaze_0_axi_intc>;
255+ interrupts = <5 2>;
256+ reg = <0x41c00000 0x10000>;
257+ xlnx,count-width = <0x20>;
258+ xlnx,gen0-assert = <0x1>;
259+ xlnx,gen1-assert = <0x1>;
260+ xlnx,one-timer-only = <0x0>;
261+ xlnx,trig0-assert = <0x1>;
262+ xlnx,trig1-assert = <0x1>;
263+ };
264+ calib_complete_gpio: gpio@40010000 {
265+ #gpio-cells = <2>;
266+ compatible = "xlnx,xps-gpio-1.00.a";
267+ gpio-controller ;
268+ reg = <0x40010000 0x10000>;
269+ xlnx,all-inputs = <0x1>;
270+ xlnx,all-inputs-2 = <0x0>;
271+ xlnx,all-outputs = <0x0>;
272+ xlnx,all-outputs-2 = <0x0>;
273+ xlnx,dout-default = <0x00000000>;
274+ xlnx,dout-default-2 = <0x00000000>;
275+ xlnx,gpio-width = <0x1>;
276+ xlnx,gpio2-width = <0x20>;
277+ xlnx,interrupt-present = <0x0>;
278+ xlnx,is-dual = <0x0>;
279+ xlnx,tri-default = <0xFFFFFFFF>;
280+ xlnx,tri-default-2 = <0xFFFFFFFF>;
281+ };
282+ dip_switches_4bits: gpio@40020000 {
283+ #gpio-cells = <2>;
284+ compatible = "xlnx,xps-gpio-1.00.a";
285+ gpio-controller ;
286+ reg = <0x40020000 0x10000>;
287+ xlnx,all-inputs = <0x1>;
288+ xlnx,all-inputs-2 = <0x0>;
289+ xlnx,all-outputs = <0x0>;
290+ xlnx,all-outputs-2 = <0x0>;
291+ xlnx,dout-default = <0x00000000>;
292+ xlnx,dout-default-2 = <0x00000000>;
293+ xlnx,gpio-width = <0x4>;
294+ xlnx,gpio2-width = <0x20>;
295+ xlnx,interrupt-present = <0x0>;
296+ xlnx,is-dual = <0x0>;
297+ xlnx,tri-default = <0xFFFFFFFF>;
298+ xlnx,tri-default-2 = <0xFFFFFFFF>;
299+ };
300+ iic_main: i2c@40800000 {
301+ #address-cells = <1>;
302+ #size-cells = <0>;
303+ clock-frequency = <200000000>;
304+ clocks = <&clk_bus_0>;
305+ compatible = "xlnx,xps-iic-2.00.a";
306+ interrupt-parent = <&microblaze_0_axi_intc>;
307+ interrupts = <1 2>;
308+ reg = <0x40800000 0x10000>;
309+ };
310+ led_8bits: gpio@40030000 {
311+ #gpio-cells = <2>;
312+ compatible = "xlnx,xps-gpio-1.00.a";
313+ gpio-controller ;
314+ reg = <0x40030000 0x10000>;
315+ xlnx,all-inputs = <0x0>;
316+ xlnx,all-inputs-2 = <0x0>;
317+ xlnx,all-outputs = <0x1>;
318+ xlnx,all-outputs-2 = <0x0>;
319+ xlnx,dout-default = <0x00000000>;
320+ xlnx,dout-default-2 = <0x00000000>;
321+ xlnx,gpio-width = <0x8>;
322+ xlnx,gpio2-width = <0x20>;
323+ xlnx,interrupt-present = <0x0>;
324+ xlnx,is-dual = <0x0>;
325+ xlnx,tri-default = <0xFFFFFFFF>;
326+ xlnx,tri-default-2 = <0xFFFFFFFF>;
327+ };
328+ linear_flash: flash@60000000 {
329+ bank-width = <2>;
330+ compatible = "cfi-flash";
331+ reg = <0x60000000 0x8000000>;
332+ xlnx,axi-clk-period-ps = <0x1388>;
333+ xlnx,include-datawidth-matching-0 = <0x1>;
334+ xlnx,include-datawidth-matching-1 = <0x1>;
335+ xlnx,include-datawidth-matching-2 = <0x1>;
336+ xlnx,include-datawidth-matching-3 = <0x1>;
337+ xlnx,include-negedge-ioregs = <0x0>;
338+ xlnx,lflash-period-ps = <0x1388>;
339+ xlnx,linear-flash-sync-burst = <0x0>;
340+ xlnx,max-mem-width = <0x10>;
341+ xlnx,mem-a-lsb = <0x0>;
342+ xlnx,mem-a-msb = <0x1f>;
343+ xlnx,mem0-type = <0x2>;
344+ xlnx,mem0-width = <0x10>;
345+ xlnx,mem1-type = <0x0>;
346+ xlnx,mem1-width = <0x10>;
347+ xlnx,mem2-type = <0x0>;
348+ xlnx,mem2-width = <0x10>;
349+ xlnx,mem3-type = <0x0>;
350+ xlnx,mem3-width = <0x10>;
351+ xlnx,num-banks-mem = <0x1>;
352+ xlnx,page-size = <0x10>;
353+ xlnx,parity-type-mem-0 = <0x0>;
354+ xlnx,parity-type-mem-1 = <0x0>;
355+ xlnx,parity-type-mem-2 = <0x0>;
356+ xlnx,parity-type-mem-3 = <0x0>;
357+ xlnx,port-diff = <0x0>;
358+ xlnx,s-axi-en-reg = <0x0>;
359+ xlnx,s-axi-mem-addr-width = <0x20>;
360+ xlnx,s-axi-mem-data-width = <0x20>;
361+ xlnx,s-axi-mem-id-width = <0x1>;
362+ xlnx,s-axi-reg-addr-width = <0x5>;
363+ xlnx,s-axi-reg-data-width = <0x20>;
364+ xlnx,synch-pipedelay-0 = <0x1>;
365+ xlnx,synch-pipedelay-1 = <0x1>;
366+ xlnx,synch-pipedelay-2 = <0x1>;
367+ xlnx,synch-pipedelay-3 = <0x1>;
368+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
369+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
370+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
371+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
372+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
373+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
374+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
375+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
376+ xlnx,thzce-ps-mem-0 = <0x88b8>;
377+ xlnx,thzce-ps-mem-1 = <0x1b58>;
378+ xlnx,thzce-ps-mem-2 = <0x1b58>;
379+ xlnx,thzce-ps-mem-3 = <0x1b58>;
380+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
381+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
382+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
383+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
384+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
385+ xlnx,tlzwe-ps-mem-1 = <0x0>;
386+ xlnx,tlzwe-ps-mem-2 = <0x0>;
387+ xlnx,tlzwe-ps-mem-3 = <0x0>;
388+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
389+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
390+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
391+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
392+ xlnx,twc-ps-mem-0 = <0x11170>;
393+ xlnx,twc-ps-mem-1 = <0x3a98>;
394+ xlnx,twc-ps-mem-2 = <0x3a98>;
395+ xlnx,twc-ps-mem-3 = <0x3a98>;
396+ xlnx,twp-ps-mem-0 = <0x13880>;
397+ xlnx,twp-ps-mem-1 = <0x2ee0>;
398+ xlnx,twp-ps-mem-2 = <0x2ee0>;
399+ xlnx,twp-ps-mem-3 = <0x2ee0>;
400+ xlnx,twph-ps-mem-0 = <0x13880>;
401+ xlnx,twph-ps-mem-1 = <0x2ee0>;
402+ xlnx,twph-ps-mem-2 = <0x2ee0>;
403+ xlnx,twph-ps-mem-3 = <0x2ee0>;
404+ xlnx,use-startup = <0x0>;
405+ xlnx,use-startup-int = <0x0>;
406+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
407+ xlnx,wr-rec-time-mem-1 = <0x6978>;
408+ xlnx,wr-rec-time-mem-2 = <0x6978>;
409+ xlnx,wr-rec-time-mem-3 = <0x6978>;
410+ };
411+ microblaze_0_axi_intc: interrupt-controller@41200000 {
412+ #interrupt-cells = <2>;
413+ compatible = "xlnx,xps-intc-1.00.a";
414+ interrupt-controller ;
415+ reg = <0x41200000 0x10000>;
416+ xlnx,kind-of-intr = <0x0>;
417+ xlnx,num-intr-inputs = <0x6>;
418+ };
419+ push_buttons_5bits: gpio@40040000 {
420+ #gpio-cells = <2>;
421+ compatible = "xlnx,xps-gpio-1.00.a";
422+ gpio-controller ;
423+ reg = <0x40040000 0x10000>;
424+ xlnx,all-inputs = <0x1>;
425+ xlnx,all-inputs-2 = <0x0>;
426+ xlnx,all-outputs = <0x0>;
427+ xlnx,all-outputs-2 = <0x0>;
428+ xlnx,dout-default = <0x00000000>;
429+ xlnx,dout-default-2 = <0x00000000>;
430+ xlnx,gpio-width = <0x5>;
431+ xlnx,gpio2-width = <0x20>;
432+ xlnx,interrupt-present = <0x0>;
433+ xlnx,is-dual = <0x0>;
434+ xlnx,tri-default = <0xFFFFFFFF>;
435+ xlnx,tri-default-2 = <0xFFFFFFFF>;
436+ };
437+ reset_gpio: gpio@40000000 {
438+ #gpio-cells = <2>;
439+ compatible = "xlnx,xps-gpio-1.00.a";
440+ gpio-controller ;
441+ reg = <0x40000000 0x10000>;
442+ xlnx,all-inputs = <0x0>;
443+ xlnx,all-inputs-2 = <0x0>;
444+ xlnx,all-outputs = <0x1>;
445+ xlnx,all-outputs-2 = <0x0>;
446+ xlnx,dout-default = <0x00000000>;
447+ xlnx,dout-default-2 = <0x00000000>;
448+ xlnx,gpio-width = <0x1>;
449+ xlnx,gpio2-width = <0x20>;
450+ xlnx,interrupt-present = <0x0>;
451+ xlnx,is-dual = <0x0>;
452+ xlnx,tri-default = <0xFFFFFFFF>;
453+ xlnx,tri-default-2 = <0xFFFFFFFF>;
454+ };
455+ rs232_uart: serial@44a00000 {
456+ clock-frequency = <200000000>;
457+ clocks = <&clk_bus_0>;
458+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
459+ current-speed = <115200>;
460+ device_type = "serial";
461+ interrupt-parent = <&microblaze_0_axi_intc>;
462+ interrupts = <0 2>;
463+ port-number = <0>;
464+ reg = <0x44a00000 0x10000>;
465+ reg-offset = <0x1000>;
466+ reg-shift = <2>;
467+ xlnx,external-xin-clk-hz = <0x17d7840>;
468+ xlnx,external-xin-clk-hz-d = <0x19>;
469+ xlnx,has-external-rclk = <0x0>;
470+ xlnx,has-external-xin = <0x0>;
471+ xlnx,is-a-16550 = <0x1>;
472+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
473+ xlnx,use-modem-ports = <0x1>;
474+ xlnx,use-user-ports = <0x1>;
475+ };
476+ };
477 } ;
478diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
479index 1dee2d6..cb75fde 100644
480--- a/board/xilinx/microblaze-generic/config.mk
481+++ b/board/xilinx/microblaze-generic/config.mk
482@@ -1,20 +1,10 @@
483-#
484-# (C) Copyright 2007 - 2016 Michal Simek
485-#
486-# Michal SIMEK <monstr@monstr.eu>
487-#
488-# SPDX-License-Identifier: GPL-2.0+
489-#
490-
491-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
492-
493-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
494-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
495-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
496-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
497-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
498-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
499-
500-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
501-
502-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
503+TEXT_BASE = 0x80400000
504+CONFIG_SYS_TEXT_BASE = 0x80400000
505+
506+PLATFORM_CPPFLAGS += -mxl-barrel-shift
507+PLATFORM_CPPFLAGS += -mno-xl-soft-div
508+PLATFORM_CPPFLAGS += -mxl-pattern-compare
509+PLATFORM_CPPFLAGS += -mxl-multiply-high
510+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
511+PLATFORM_CPPFLAGS += -mcpu=v9.6
512+PLATFORM_CPPFLAGS += -fgnu89-inline
513diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
514index a66cd3b..d90bd7c 100644
515--- a/configs/microblaze-generic_defconfig
516+++ b/configs/microblaze-generic_defconfig
517@@ -1,31 +1,20 @@
518 CONFIG_MICROBLAZE=y
519-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
520-CONFIG_SPL_DM=y
521 CONFIG_TARGET_MICROBLAZE_GENERIC=y
522 CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
523 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
524 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
525 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
526-CONFIG_SYS_TEXT_BASE=0x29000000
527+CONFIG_SYS_TEXT_BASE=0x80400000
528 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
529-CONFIG_SPL=y
530-CONFIG_FIT=y
531-CONFIG_FIT_VERBOSE=y
532-CONFIG_BOOTDELAY=-1
533+CONFIG_BOOTDELAY=4
534 CONFIG_HUSH_PARSER=y
535-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
536+CONFIG_SYS_PROMPT="U-Boot> "
537 CONFIG_CMD_ASKENV=y
538-CONFIG_CMD_GPIO=y
539 # CONFIG_CMD_SETEXPR is not set
540-CONFIG_CMD_TFTPPUT=y
541 CONFIG_CMD_DHCP=y
542 CONFIG_CMD_MII=y
543 CONFIG_CMD_PING=y
544-CONFIG_SPL_OF_CONTROL=y
545 CONFIG_OF_EMBED=y
546-CONFIG_NETCONSOLE=y
547 CONFIG_DM_ETH=y
548 CONFIG_XILINX_AXIEMAC=y
549-CONFIG_XILINX_EMACLITE=y
550 CONFIG_SYS_NS16550=y
551-CONFIG_XILINX_UARTLITE=y
552diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
553index 6ae4e0d..c14c87e 100644
554--- a/include/configs/microblaze-generic.h
555+++ b/include/configs/microblaze-generic.h
556@@ -1,330 +1,194 @@
557-/*
558- * (C) Copyright 2007-2010 Michal Simek
559- *
560- * Michal SIMEK <monstr@monstr.eu>
561- *
562- * SPDX-License-Identifier: GPL-2.0+
563- */
564-
565 #ifndef __CONFIG_H
566 #define __CONFIG_H
567
568-#include "../board/xilinx/microblaze-generic/xparameters.h"
569-
570-/* MicroBlaze CPU */
571-#define MICROBLAZE_V5 1
572-
573-/* linear and spi flash memory */
574-#ifdef XILINX_FLASH_START
575-#define FLASH
576-#undef SPIFLASH
577-#undef RAMENV /* hold environment in flash */
578-#else
579-#ifdef XILINX_SPI_FLASH_BASEADDR
580-#undef FLASH
581-#define SPIFLASH
582-#undef RAMENV /* hold environment in flash */
583-#else
584-#undef FLASH
585-#undef SPIFLASH
586-#define RAMENV /* hold environment in RAM */
587-#endif
588-#endif
589-
590-/* uart */
591-# define CONFIG_BAUDRATE 115200
592 /* The following table includes the supported baudrates */
593-# define CONFIG_SYS_BAUDRATE_TABLE \
594- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
595-
596-/* setting reset address */
597-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
598+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
599
600-/* gpio */
601-#ifdef XILINX_GPIO_BASEADDR
602-# define CONFIG_XILINX_GPIO
603-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
604-#endif
605-#define CONFIG_BOARD_LATE_INIT
606-
607-/* watchdog */
608-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
609-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
610-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
611-# ifndef CONFIG_SPL_BUILD
612-# define CONFIG_HW_WATCHDOG
613-# define CONFIG_XILINX_TB_WATCHDOG
614-# endif
615-#endif
616+/* use serial multi for all serial devices */
617+#define CONFIG_SERIAL_MULTI
618+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
619
620-#define CONFIG_SYS_MALLOC_LEN 0xC0000
621-
622-/* Stack location before relocation */
623-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
624- CONFIG_SYS_MALLOC_F_LEN)
625-
626-/*
627- * CFI flash memory layout - Example
628- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
629- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
630- *
631- * SECT_SIZE = 0x20000; 128kB is one sector
632- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
633- *
634- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
635- * FREE 256kB
636- * 0x2204_0000 CONFIG_ENV_ADDR
637- * ENV_AREA 128kB
638- * 0x2206_0000
639- * FREE
640- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
641- *
642- */
643-
644-#ifdef FLASH
645-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
646-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
647-# define CONFIG_SYS_FLASH_CFI 1
648-# define CONFIG_FLASH_CFI_DRIVER 1
649-/* ?empty sector */
650-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
651-/* max number of memory banks */
652-# define CONFIG_SYS_MAX_FLASH_BANKS 1
653-/* max number of sectors on one chip */
654-# define CONFIG_SYS_MAX_FLASH_SECT 512
655-/* hardware flash protection */
656-# define CONFIG_SYS_FLASH_PROTECTION
657-/* use buffered writes (20x faster) */
658-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
659-# ifdef RAMENV
660-# define CONFIG_ENV_IS_NOWHERE 1
661-# define CONFIG_ENV_SIZE 0x1000
662-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
663-
664-# else /* FLASH && !RAMENV */
665-# define CONFIG_ENV_IS_IN_FLASH 1
666-/* 128K(one sector) for env */
667-# define CONFIG_ENV_SECT_SIZE 0x20000
668-# define CONFIG_ENV_ADDR \
669- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
670-# define CONFIG_ENV_SIZE 0x20000
671-# endif /* FLASH && !RAMBOOT */
672-#else /* !FLASH */
673-
674-#ifdef SPIFLASH
675-# define CONFIG_SYS_NO_FLASH 1
676-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
677-# define CONFIG_SPI 1
678-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
679-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
680-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
681-
682-# ifdef RAMENV
683-# define CONFIG_ENV_IS_NOWHERE 1
684-# define CONFIG_ENV_SIZE 0x1000
685-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
686-
687-# else /* SPIFLASH && !RAMENV */
688-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
689-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
690-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
691-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
692-/* 128K(two sectors) for env */
693-# define CONFIG_ENV_SECT_SIZE 0x10000
694-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
695-/* Warning: adjust the offset in respect of other flash content and size */
696-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
697-# endif /* SPIFLASH && !RAMBOOT */
698-#else /* !SPIFLASH */
699-
700-/* ENV in RAM */
701-# define CONFIG_SYS_NO_FLASH 1
702-# define CONFIG_ENV_IS_NOWHERE 1
703-# define CONFIG_ENV_SIZE 0x1000
704-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
705-#endif /* !SPIFLASH */
706-#endif /* !FLASH */
707-
708-#if defined(XILINX_USE_ICACHE)
709-# define CONFIG_ICACHE
710-#else
711-# undef CONFIG_ICACHE
712-#endif
713-
714-#if defined(XILINX_USE_DCACHE)
715-# define CONFIG_DCACHE
716-#else
717-# undef CONFIG_DCACHE
718-#endif
719+/* Board name */
720
721-#ifndef XILINX_DCACHE_BYTE_SIZE
722-#define XILINX_DCACHE_BYTE_SIZE 32768
723-#endif
724-
725-/*
726- * BOOTP options
727- */
728+/* processor - microblaze_0 */
729+#define XILINX_USE_MSR_INSTR 1
730+#define XILINX_USE_ICACHE 1
731+#define XILINX_USE_DCACHE 1
732+#define XILINX_DCACHE_BYTE_SIZE 16384
733+#define XILINX_PVR 2
734+#define MICROBLAZE_V5
735+#define CONFIG_CMD_IRQ
736+#define CONFIG_DCACHE
737+#define CONFIG_ICACHE
738+
739+/* main_memory - ddr3_sdram */
740+
741+/* Memory testing handling */
742+#define CONFIG_SYS_MEMTEST_START 0x80000000
743+#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000)
744+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */
745+
746+/* global pointer options */
747+#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE)
748+
749+/* Size of malloc() pool */
750+#define SIZE 0x100000
751+#define CONFIG_SYS_MALLOC_LEN SIZE
752+#define CONFIG_SYS_MONITOR_LEN SIZE
753+#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
754+#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
755+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
756+
757+/* stack */
758+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
759+
760+/* No of_control support yet*/
761+
762+/* uart - rs232_uart */
763+#define CONFIG_UART16550 1
764+#define CONFIG_CONS_INDEX 1
765+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
766+#define CONFIG_SYS_NS16550_REG_SIZE -4
767+#define CONSOLE_ARG "console=console=ttyS0,115200\0"
768+#define CONFIG_SYS_NS16550_SERIAL
769+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
770+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
771+#define CONFIG_SYS_NS16550_CLK 200000000
772+#define CONFIG_BAUDRATE 115200
773+
774+/* ethernet - axi_ethernet */
775+#define CONFIG_PHY_XILINX
776+#define CONFIG_PHY_GIGE
777+#define CONFIG_PHY_MARVELL
778+#define CONFIG_PHY_NATSEMI
779+#define CONFIG_NET_MULTI
780+#define CONFIG_BOOTP_MAY_FAIL
781+#define CONFIG_NETCONSOLE 1
782+#define CONFIG_SERVERIP 172.25.229.115
783+#define CONFIG_IPADDR
784+
785+/* nor_flash - linear_flash */
786+#define CONFIG_SYS_FLASH_BASE 0x60000000
787+#define CONFIG_SYS_FLASH_END 0x68000000
788+#define CONFIG_SYS_MAX_FLASH_SECT 2048
789+#define CONFIG_SYS_FLASH_PROTECTION
790+#define CONFIG_SYS_FLASH_EMPTY_INFO
791+#define CONFIG_SYS_FLASH_CFI
792+#define CONFIG_FLASH_CFI_DRIVER
793+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
794+#define CONFIG_SYS_MAX_FLASH_BANKS 1
795+#define CONFIG_ENV_IS_IN_FLASH
796+#define CONFIG_ENV_ADDR 0x60b80000
797+#define CONFIG_ENV_SIZE 0x20000
798+#define CONFIG_ENV_SECT_SIZE 0x20000
799+
800+/* timer - axi_timer_0 */
801+#define CONFIG_SYS_TIMER_0_ADDR 0x41C00000
802+#define CONFIG_SYS_TIMER_0 1
803+#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
804+#define CONFIG_SYS_TIMER_0_IRQ 5
805+#define FREQUENCE 200000000
806+#define XILINX_CLOCK_FREQ 200000000
807+
808+/* gpio - reset_gpio */
809+#define XILINX_GPIO_BASEADDR 0x40000000
810+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
811+#define CONFIG_XILINX_GPIO
812+
813+/* intc - microblaze_0_axi_intc */
814+#define CONFIG_SYS_INTC_0_ADDR 0x41200000
815+#define CONFIG_SYS_INTC_0_NUM 6
816+#define CONFIG_SYS_INTC_0 1
817+
818+/* FPGA */
819+
820+/* Make the BOOTM LEN big enough for the compressed image */
821+#define CONFIG_SYS_BOOTM_LEN 0x4000000
822+
823+
824+/* BOOTP options */
825+#define CONFIG_BOOTP_SERVERIP
826 #define CONFIG_BOOTP_BOOTFILESIZE
827 #define CONFIG_BOOTP_BOOTPATH
828 #define CONFIG_BOOTP_GATEWAY
829 #define CONFIG_BOOTP_HOSTNAME
830
831-/*
832- * Command line configuration.
833- */
834-#define CONFIG_CMD_IRQ
835-#define CONFIG_CMD_MFSL
836-
837-#if defined(FLASH)
838-# define CONFIG_CMD_JFFS2
839-# define CONFIG_CMD_UBI
840-# undef CONFIG_CMD_UBIFS
841-
842-# if !defined(RAMENV)
843-# define CONFIG_CMD_SAVES
844-# endif
845-
846-#else
847-#if defined(SPIFLASH)
848-
849-# if !defined(RAMENV)
850-# define CONFIG_CMD_SAVES
851-# endif
852-#else
853-# undef CONFIG_CMD_JFFS2
854-# undef CONFIG_CMD_UBI
855-# undef CONFIG_CMD_UBIFS
856-#endif
857-#endif
858-
859-#if defined(CONFIG_CMD_JFFS2)
860-# define CONFIG_MTD_PARTITIONS
861-#endif
862-
863-#if defined(CONFIG_CMD_UBIFS)
864-# define CONFIG_CMD_UBI
865-# define CONFIG_LZO
866-#endif
867-
868-#if defined(CONFIG_CMD_UBI)
869-# define CONFIG_MTD_PARTITIONS
870-# define CONFIG_RBTREE
871-#endif
872-
873-#if defined(CONFIG_MTD_PARTITIONS)
874-/* MTD partitions */
875-#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
876-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
877-#define CONFIG_FLASH_CFI_MTD
878-#define MTDIDS_DEFAULT "nor0=flash-0"
879-
880-/* default mtd partition table */
881-#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
882- "256k(env),3m(kernel),1m(romfs),"\
883- "1m(cramfs),-(jffs2)"
884-#endif
885-
886-/* size of console buffer */
887-#define CONFIG_SYS_CBSIZE 512
888- /* print buffer size */
889-#define CONFIG_SYS_PBSIZE \
890- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
891-/* max number of command args */
892-#define CONFIG_SYS_MAXARGS 15
893-#define CONFIG_SYS_LONGHELP
894-/* default load address */
895-#define CONFIG_SYS_LOAD_ADDR 0
896-
897-#define CONFIG_BOOTARGS "root=romfs"
898-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
899-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
900-
901-/* architecture dependent code */
902-#define CONFIG_SYS_USR_EXCEP /* user exception */
903-
904-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
905-
906-#ifndef CONFIG_EXTRA_ENV_SETTINGS
907-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
908- "nor0=flash-0\0"\
909- "mtdparts=mtdparts=flash-0:"\
910- "256k(u-boot),256k(env),3m(kernel),"\
911- "1m(romfs),1m(cramfs),-(jffs2)\0"\
912- "nc=setenv stdout nc;"\
913- "setenv stdin nc\0" \
914- "serial=setenv stdout serial;"\
915- "setenv stdin serial\0"
916-#endif
917-
918+/*Command line configuration.*/
919 #define CONFIG_CMDLINE_EDITING
920+#define CONFIG_CMD_SAVES
921
922-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
923-
924-/* Enable flat device tree support */
925-#define CONFIG_LMB 1
926-
927-#if defined(CONFIG_XILINX_AXIEMAC)
928-# define CONFIG_MII 1
929-# define CONFIG_PHY_GIGE 1
930-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
931-# define CONFIG_PHY_ATHEROS 1
932-# define CONFIG_PHY_BROADCOM 1
933-# define CONFIG_PHY_DAVICOM 1
934-# define CONFIG_PHY_LXT 1
935-# define CONFIG_PHY_MARVELL 1
936-# define CONFIG_PHY_MICREL 1
937-# define CONFIG_PHY_MICREL_KSZ9021
938-# define CONFIG_PHY_NATSEMI 1
939-# define CONFIG_PHY_REALTEK 1
940-# define CONFIG_PHY_VITESSE 1
941-#else
942-# undef CONFIG_MII
943-#endif
944+/* Miscellaneous configurable options */
945+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
946+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
947
948-/* SPL part */
949-#define CONFIG_CMD_SPL
950-#define CONFIG_SPL_FRAMEWORK
951-#define CONFIG_SPL_LIBCOMMON_SUPPORT
952-#define CONFIG_SPL_LIBGENERIC_SUPPORT
953-#define CONFIG_SPL_SERIAL_SUPPORT
954-#define CONFIG_SPL_BOARD_INIT
955+/* Boot Argument Buffer Size */
956+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
957+#define CONFIG_SYS_LONGHELP
958
959-#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
960+/* architecture dependent code */
961+#define CONFIG_SYS_USR_EXCEP /* user exception */
962+#define CONFIG_SYS_HZ 1000
963+
964+/* Use the HUSH parser */
965+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
966+
967+/* Don't define BOOTARGS, we get it from the DTB chosen fragment */
968+#undef CONFIG_BOOTARGS
969+
970+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
971+
972+#define CONFIG_LMB
973+
974+/* Initial memory map for Linux */
975+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
976+
977+/* PREBOOT */
978+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
979+
980+/* Extra U-Boot Env settings */
981+#define CONFIG_EXTRA_ENV_SETTINGS \
982+ SERIAL_MULTI \
983+ CONSOLE_ARG \
984+ ESERIAL0 \
985+ "nc=setenv stdout nc;setenv stdin nc;\0" \
986+ "ethaddr=00:0a:35:00:22:01\0" \
987+ "autoload=no\0" \
988+ "clobstart=0x81000000\0" \
989+ "netstart=0x81000000\0" \
990+ "dtbnetstart=0x82800000\0" \
991+ "loadaddr=0x81000000\0" \
992+ "bootsize=0x80000\0" \
993+ "bootstart=0x60b00000\0" \
994+ "boot_img=u-boot-s.bin\0" \
995+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
996+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
997+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
998+ "bootenvsize=0x20000\0" \
999+ "bootenvstart=0x60b80000\0" \
1000+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
1001+ "kernelsize=0xc00000\0" \
1002+ "kernelstart=0x60ba0000\0" \
1003+ "kernel_img=image.ub\0" \
1004+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
1005+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
1006+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
1007+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
1008+ "fpgasize=0xb00000\0" \
1009+ "fpgastart=0x60000000\0" \
1010+ "fpga_img=system.bit.bin\0" \
1011+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
1012+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
1013+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
1014+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
1015+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
1016+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
1017+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
1018+ "default_bootcmd=bootm ${kernelstart}\0" \
1019+""
1020+
1021+/* BOOTCOMMAND */
1022+#define CONFIG_BOOTCOMMAND "run default_bootcmd"
1023+
1024+#undef CONFIG_SPL_BUILD /* Disable SPL by default*/
1025
1026-#define CONFIG_SPL_RAM_DEVICE
1027-#ifdef CONFIG_SYS_FLASH_BASE
1028-# define CONFIG_SPL_NOR_SUPPORT
1029-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
1030 #endif
1031-
1032-/* for booting directly linux */
1033-#define CONFIG_SPL_OS_BOOT
1034-
1035-#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
1036- 0x60000)
1037-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
1038- 0x40000)
1039-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
1040- 0x1000000)
1041-
1042-/* SP location before relocation, must use scratch RAM */
1043-/* BRAM start */
1044-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
1045-/* BRAM size - will be generated */
1046-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
1047-
1048-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
1049- CONFIG_SYS_INIT_RAM_SIZE - \
1050- CONFIG_SYS_MALLOC_F_LEN)
1051-
1052-/* Just for sure that there is a space for stack */
1053-#define CONFIG_SPL_STACK_SIZE 0x100
1054-
1055-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1056-
1057-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
1058- CONFIG_SYS_INIT_RAM_ADDR - \
1059- CONFIG_SYS_MALLOC_F_LEN - \
1060- CONFIG_SPL_STACK_SIZE)
1061-
1062-#endif /* __CONFIG_H */
1063--
10642.7.4
1065
diff --git a/recipes-bsp/u-boot/u-boot-xlnx_2016.4.bb b/recipes-bsp/u-boot/u-boot-xlnx_2016.4.bb
deleted file mode 100644
index 9730cb33..00000000
--- a/recipes-bsp/u-boot/u-boot-xlnx_2016.4.bb
+++ /dev/null
@@ -1,29 +0,0 @@
1include u-boot-xlnx.inc
2include u-boot-spl-zynq-init.inc
3
4XILINX_RELEASE_VERSION = "v2016.4"
5SRCREV = "0b94ce5ed4a6c2cd0fec7b8337e776b03e387347"
6PV = "v2016.07-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
7
8SRC_URI_append = " \
9 file://0001-fdt-add-memory-bank-decoding-functions-for-board-set.patch \
10 file://0002-ARM-zynq-Replace-board-specific-with-generic-memory-.patch \
11 file://0003-ARM64-zynqmp-Replace-board-specific-with-generic-mem.patch \
12 file://arm-zynqmp-xilinx_zynqmp.h-Auto-boot-in-JTAG-if-imag.patch \
13 "
14
15SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
16
17LICENSE = "GPLv2+"
18LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
19
20# u-boot 2016.07 has support for these
21HAS_PLATFORM_INIT ?= " \
22 zynq_microzed_config \
23 zynq_zed_config \
24 zynq_zc702_config \
25 zynq_zc706_config \
26 zynq_zybo_config \
27 xilinx_zynqmp_zcu102_config \
28 "
29
diff --git a/recipes-bsp/u-boot/u-boot/0001-fdt-add-memory-bank-decoding-functions-for-board-set.patch b/recipes-bsp/u-boot/u-boot/0001-fdt-add-memory-bank-decoding-functions-for-board-set.patch
deleted file mode 100644
index b7d179f8..00000000
--- a/recipes-bsp/u-boot/u-boot/0001-fdt-add-memory-bank-decoding-functions-for-board-set.patch
+++ /dev/null
@@ -1,144 +0,0 @@
1From 623f60198b38c4fdae596038cd5956e44b6224a4 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 19 Dec 2016 00:03:34 +1000
4Subject: [PATCH 1/3] fdt: add memory bank decoding functions for board setup
5
6Add two functions for use by board implementations to decode the memory
7banks of the /memory node so as to populate the global data with
8ram_size and board info for memory banks.
9
10The fdtdec_setup_memory_size() function decodes the first memory bank
11and sets up the gd->ram_size with the size of the memory bank. This
12function should be called from the boards dram_init().
13
14The fdtdec_setup_memory_banksize() function decode the memory banks
15(up to the CONFIG_NR_DRAM_BANKS) and populates the base address and size
16into the gd->bd->bi_dram array of banks. This function should be called
17from the boards dram_init_banksize().
18
19Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
20Cc: Simon Glass <sjg@chromium.org>
21Cc: Michal Simek <monstr@monstr.eu>
22Reviewed-by: Simon Glass <sjg@chromium.org>
23Signed-off-by: Michal Simek <michal.simek@xilinx.com>
24Upstream-Status: Backport
25---
26 include/fdtdec.h | 34 ++++++++++++++++++++++++++++++++++
27 lib/fdtdec.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
28 2 files changed, 90 insertions(+)
29
30diff --git a/include/fdtdec.h b/include/fdtdec.h
31index 27887c8c21..d074478f14 100644
32--- a/include/fdtdec.h
33+++ b/include/fdtdec.h
34@@ -976,6 +976,40 @@ struct display_timing {
35 */
36 int fdtdec_decode_display_timing(const void *blob, int node, int index,
37 struct display_timing *config);
38+
39+/**
40+ * fdtdec_setup_memory_size() - decode and setup gd->ram_size
41+ *
42+ * Decode the /memory 'reg' property to determine the size of the first memory
43+ * bank, populate the global data with the size of the first bank of memory.
44+ *
45+ * This function should be called from a boards dram_init(). This helper
46+ * function allows for boards to query the device tree for DRAM size instead of
47+ * hard coding the value in the case where the memory size cannot be detected
48+ * automatically.
49+ *
50+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
51+ * invalid
52+ */
53+int fdtdec_setup_memory_size(void);
54+
55+/**
56+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
57+ *
58+ * Decode the /memory 'reg' property to determine the address and size of the
59+ * memory banks. Use this data to populate the global data board info with the
60+ * phys address and size of memory banks.
61+ *
62+ * This function should be called from a boards dram_init_banksize(). This
63+ * helper function allows for boards to query the device tree for memory bank
64+ * information instead of hard coding the information in cases where it cannot
65+ * be detected automatically.
66+ *
67+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
68+ * invalid
69+ */
70+int fdtdec_setup_memory_banksize(void);
71+
72 /**
73 * Set up the device tree ready for use
74 */
75diff --git a/lib/fdtdec.c b/lib/fdtdec.c
76index 4e619c49a2..81f47ef2c7 100644
77--- a/lib/fdtdec.c
78+++ b/lib/fdtdec.c
79@@ -1174,6 +1174,62 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
80 return ret;
81 }
82
83+int fdtdec_setup_memory_size(void)
84+{
85+ int ret, mem;
86+ struct fdt_resource res;
87+
88+ mem = fdt_path_offset(gd->fdt_blob, "/memory");
89+ if (mem < 0) {
90+ debug("%s: Missing /memory node\n", __func__);
91+ return -EINVAL;
92+ }
93+
94+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, &res);
95+ if (ret != 0) {
96+ debug("%s: Unable to decode first memory bank\n", __func__);
97+ return -EINVAL;
98+ }
99+
100+ gd->ram_size = (phys_size_t)(res.end - res.start + 1);
101+ debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
102+
103+ return 0;
104+}
105+
106+#if defined(CONFIG_NR_DRAM_BANKS)
107+int fdtdec_setup_memory_banksize(void)
108+{
109+ int bank, ret, mem;
110+ struct fdt_resource res;
111+
112+ mem = fdt_path_offset(gd->fdt_blob, "/memory");
113+ if (mem < 0) {
114+ debug("%s: Missing /memory node\n", __func__);
115+ return -EINVAL;
116+ }
117+
118+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
119+ ret = fdt_get_resource(gd->fdt_blob, mem, "reg", bank, &res);
120+ if (ret == -FDT_ERR_NOTFOUND)
121+ break;
122+ if (ret != 0)
123+ return -EINVAL;
124+
125+ gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
126+ gd->bd->bi_dram[bank].size =
127+ (phys_size_t)(res.end - res.start + 1);
128+
129+ debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
130+ __func__, bank,
131+ (unsigned long long)gd->bd->bi_dram[bank].start,
132+ (unsigned long long)gd->bd->bi_dram[bank].size);
133+ }
134+
135+ return 0;
136+}
137+#endif
138+
139 int fdtdec_setup(void)
140 {
141 #if CONFIG_IS_ENABLED(OF_CONTROL)
142--
1432.11.0
144
diff --git a/recipes-bsp/u-boot/u-boot/0002-ARM-zynq-Replace-board-specific-with-generic-memory-.patch b/recipes-bsp/u-boot/u-boot/0002-ARM-zynq-Replace-board-specific-with-generic-memory-.patch
deleted file mode 100644
index 41806966..00000000
--- a/recipes-bsp/u-boot/u-boot/0002-ARM-zynq-Replace-board-specific-with-generic-memory-.patch
+++ /dev/null
@@ -1,170 +0,0 @@
1From de9bf1b591a80ef8fce8cad5c3d5a1139d136a77 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 19 Dec 2016 00:03:34 +1000
4Subject: [PATCH 2/3] ARM: zynq: Replace board specific with generic memory
5 bank decoding
6
7The dram_init and dram_init_banksize functions were using a board
8specific implementation for decoding the memory banks from the fdt. This
9board specific implementation uses a static variable 'tmp' which makes
10these functions unsafe for execution from within the board_init_f
11context.
12
13This unsafe use of a static variable was causing a specific bug when
14using the zynq_zybo configuration, U-Boot would generate the following
15error during image load. This was caused due to dram_init overwriting
16the relocations for the 'image' variable within the do_bootm function.
17Out of coincidence the un-initialized memory has a compression type
18which is the same as the value for the relocation type R_ARM_RELATIVE.
19
20 Uncompressing Invalid Image ... Unimplemented compression type 23
21
22It should be noted that this is just one way the issue could surface,
23other cases my not be observed in normal boot flow. Depending on the
24size of various sections, and location of relocations within __rel_dyn
25and the compiler/linker the outcome of this bug can differ greatly.
26
27This change makes the dram_init* functions use a generic implementation
28of decoding and populating memory bank and size data.
29
30Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
31Fixes: 758f29d0f8 ("ARM: zynq: Support systems with more memory banks")
32Cc: Michal Simek <monstr@monstr.eu>
33Signed-off-by: Michal Simek <michal.simek@xilinx.com>
34Upstream-Status: Backport
35---
36 board/xilinx/zynq/board.c | 112 ++--------------------------------------------
37 1 file changed, 3 insertions(+), 109 deletions(-)
38
39diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
40index 2c86940957..5cd9bbf711 100644
41--- a/board/xilinx/zynq/board.c
42+++ b/board/xilinx/zynq/board.c
43@@ -124,121 +124,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
44 }
45
46 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
47-/*
48- * fdt_get_reg - Fill buffer by information from DT
49- */
50-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
51- const u32 *cell, int n)
52-{
53- int i = 0, b, banks;
54- int parent_offset = fdt_parent_offset(fdt, nodeoffset);
55- int address_cells = fdt_address_cells(fdt, parent_offset);
56- int size_cells = fdt_size_cells(fdt, parent_offset);
57- char *p = buf;
58- u64 val;
59- u64 vals;
60-
61- debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
62- __func__, address_cells, size_cells, buf, cell);
63-
64- /* Check memory bank setup */
65- banks = n % (address_cells + size_cells);
66- if (banks)
67- panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
68- n, address_cells, size_cells);
69-
70- banks = n / (address_cells + size_cells);
71-
72- for (b = 0; b < banks; b++) {
73- debug("%s: Bank #%d:\n", __func__, b);
74- if (address_cells == 2) {
75- val = cell[i + 1];
76- val <<= 32;
77- val |= cell[i];
78- val = fdt64_to_cpu(val);
79- debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
80- __func__, val, p, &cell[i]);
81- *(phys_addr_t *)p = val;
82- } else {
83- debug("%s: addr32=%x, ptr=%p\n",
84- __func__, fdt32_to_cpu(cell[i]), p);
85- *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
86- }
87- p += sizeof(phys_addr_t);
88- i += address_cells;
89-
90- debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
91- sizeof(phys_addr_t));
92-
93- if (size_cells == 2) {
94- vals = cell[i + 1];
95- vals <<= 32;
96- vals |= cell[i];
97- vals = fdt64_to_cpu(vals);
98-
99- debug("%s: size64=%llx, ptr=%p, cell=%p\n",
100- __func__, vals, p, &cell[i]);
101- *(phys_size_t *)p = vals;
102- } else {
103- debug("%s: size32=%x, ptr=%p\n",
104- __func__, fdt32_to_cpu(cell[i]), p);
105- *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
106- }
107- p += sizeof(phys_size_t);
108- i += size_cells;
109-
110- debug("%s: ps=%p, i=%x, size=%zu\n",
111- __func__, p, i, sizeof(phys_size_t));
112- }
113-
114- /* Return the first address size */
115- return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
116-}
117-
118-#define FDT_REG_SIZE sizeof(u32)
119-/* Temp location for sharing data for storing */
120-/* Up to 64-bit address + 64-bit size */
121-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
122-
123 void dram_init_banksize(void)
124 {
125- int bank;
126-
127- memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
128-
129- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
130- debug("Bank #%d: start %llx\n", bank,
131- (unsigned long long)gd->bd->bi_dram[bank].start);
132- debug("Bank #%d: size %llx\n", bank,
133- (unsigned long long)gd->bd->bi_dram[bank].size);
134- }
135+ fdtdec_setup_memory_banksize();
136 }
137
138 int dram_init(void)
139 {
140- int node, len;
141- const void *blob = gd->fdt_blob;
142- const u32 *cell;
143-
144- memset(&tmp, 0, sizeof(tmp));
145-
146- /* find or create "/memory" node. */
147- node = fdt_subnode_offset(blob, 0, "memory");
148- if (node < 0) {
149- printf("%s: Can't get memory node\n", __func__);
150- return node;
151- }
152-
153- /* Get pointer to cells and lenght of it */
154- cell = fdt_getprop(blob, node, "reg", &len);
155- if (!cell) {
156- printf("%s: Can't get reg property\n", __func__);
157- return -1;
158- }
159-
160- gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
161-
162- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
163+ if (fdtdec_setup_memory_size() != 0)
164+ return -EINVAL;
165
166 zynq_ddrc_init();
167
168--
1692.11.0
170
diff --git a/recipes-bsp/u-boot/u-boot/0003-ARM64-zynqmp-Replace-board-specific-with-generic-mem.patch b/recipes-bsp/u-boot/u-boot/0003-ARM64-zynqmp-Replace-board-specific-with-generic-mem.patch
deleted file mode 100644
index 2e6e9e31..00000000
--- a/recipes-bsp/u-boot/u-boot/0003-ARM64-zynqmp-Replace-board-specific-with-generic-mem.patch
+++ /dev/null
@@ -1,156 +0,0 @@
1From 950f86ca38325c9ae7874895d2cdbdda5496e712 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 19 Dec 2016 00:03:34 +1000
4Subject: [PATCH 3/3] ARM64: zynqmp: Replace board specific with generic memory
5 bank decoding
6
7The dram_init and dram_init_banksize functions were using a board
8specific implementation for decoding the memory banks from the fdt. This
9board specific implementation uses a static variable 'tmp' which makes
10these functions unsafe for execution from within the board_init_f
11context.
12
13This change makes the dram_init* functions use a generic implementation
14of decoding and populating memory bank and size data.
15
16Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
17Fixes: 8d59d7f63b ("ARM64: zynqmp: Read RAM information from DT")
18Cc: Michal Simek <michal.simek@xilinx.com>
19Signed-off-by: Michal Simek <michal.simek@xilinx.com>
20Upstream-Status: Backport
21---
22 board/xilinx/zynqmp/zynqmp.c | 112 ++-----------------------------------------
23 1 file changed, 3 insertions(+), 109 deletions(-)
24
25diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
26index a23c38acd9..4e5871b76a 100644
27--- a/board/xilinx/zynqmp/zynqmp.c
28+++ b/board/xilinx/zynqmp/zynqmp.c
29@@ -180,121 +180,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
30 }
31
32 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
33-/*
34- * fdt_get_reg - Fill buffer by information from DT
35- */
36-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
37- const u32 *cell, int n)
38-{
39- int i = 0, b, banks;
40- int parent_offset = fdt_parent_offset(fdt, nodeoffset);
41- int address_cells = fdt_address_cells(fdt, parent_offset);
42- int size_cells = fdt_size_cells(fdt, parent_offset);
43- char *p = buf;
44- u64 val;
45- u64 vals;
46-
47- debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
48- __func__, address_cells, size_cells, buf, cell);
49-
50- /* Check memory bank setup */
51- banks = n % (address_cells + size_cells);
52- if (banks)
53- panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
54- n, address_cells, size_cells);
55-
56- banks = n / (address_cells + size_cells);
57-
58- for (b = 0; b < banks; b++) {
59- debug("%s: Bank #%d:\n", __func__, b);
60- if (address_cells == 2) {
61- val = cell[i + 1];
62- val <<= 32;
63- val |= cell[i];
64- val = fdt64_to_cpu(val);
65- debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
66- __func__, val, p, &cell[i]);
67- *(phys_addr_t *)p = val;
68- } else {
69- debug("%s: addr32=%x, ptr=%p\n",
70- __func__, fdt32_to_cpu(cell[i]), p);
71- *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
72- }
73- p += sizeof(phys_addr_t);
74- i += address_cells;
75-
76- debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
77- sizeof(phys_addr_t));
78-
79- if (size_cells == 2) {
80- vals = cell[i + 1];
81- vals <<= 32;
82- vals |= cell[i];
83- vals = fdt64_to_cpu(vals);
84-
85- debug("%s: size64=%llx, ptr=%p, cell=%p\n",
86- __func__, vals, p, &cell[i]);
87- *(phys_size_t *)p = vals;
88- } else {
89- debug("%s: size32=%x, ptr=%p\n",
90- __func__, fdt32_to_cpu(cell[i]), p);
91- *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
92- }
93- p += sizeof(phys_size_t);
94- i += size_cells;
95-
96- debug("%s: ps=%p, i=%x, size=%zu\n",
97- __func__, p, i, sizeof(phys_size_t));
98- }
99-
100- /* Return the first address size */
101- return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
102-}
103-
104-#define FDT_REG_SIZE sizeof(u32)
105-/* Temp location for sharing data for storing */
106-/* Up to 64-bit address + 64-bit size */
107-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
108-
109 void dram_init_banksize(void)
110 {
111- int bank;
112-
113- memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
114-
115- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
116- debug("Bank #%d: start %llx\n", bank,
117- (unsigned long long)gd->bd->bi_dram[bank].start);
118- debug("Bank #%d: size %llx\n", bank,
119- (unsigned long long)gd->bd->bi_dram[bank].size);
120- }
121+ fdtdec_setup_memory_banksize();
122 }
123
124 int dram_init(void)
125 {
126- int node, len;
127- const void *blob = gd->fdt_blob;
128- const u32 *cell;
129-
130- memset(&tmp, 0, sizeof(tmp));
131-
132- /* find or create "/memory" node. */
133- node = fdt_subnode_offset(blob, 0, "memory");
134- if (node < 0) {
135- printf("%s: Can't get memory node\n", __func__);
136- return node;
137- }
138-
139- /* Get pointer to cells and lenght of it */
140- cell = fdt_getprop(blob, node, "reg", &len);
141- if (!cell) {
142- printf("%s: Can't get reg property\n", __func__);
143- return -1;
144- }
145-
146- gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
147-
148- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
149+ if (fdtdec_setup_memory_size() != 0)
150+ return -EINVAL;
151
152 return 0;
153 }
154--
1552.11.0
156
diff --git a/recipes-kernel/linux/linux-xlnx/4.6/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/recipes-kernel/linux/linux-xlnx/4.6/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
deleted file mode 100644
index 1b78e9b9..00000000
--- a/recipes-kernel/linux/linux-xlnx/4.6/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
+++ /dev/null
@@ -1,299 +0,0 @@
1From 9f144ae13de8a48eda11af4d5738338894ad92c6 Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:14:13 +1000
4Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
5
6Add the dglnt_encoder driver that enables DRM support for the VGA and
7HDMI output ports found on many Digilent boards.
8
9Upstream-Status: Pending
10
11Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
12Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
13---
14 .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++
15 drivers/gpu/drm/xilinx/Kconfig | 6 +
16 drivers/gpu/drm/xilinx/Makefile | 1 +
17 drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++
18 4 files changed, 247 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
20 create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
21
22diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
23new file mode 100644
24index 0000000000..242b24e482
25--- /dev/null
26+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
27@@ -0,0 +1,23 @@
28+Device-Tree bindings for Digilent DRM Encoder Slave
29+
30+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
31+The VGA or HDMI port must be connected to a Xilinx display pipeline via an
32+axi2vid IP core.
33+
34+Required properties:
35+ - compatible: Should be "digilent,drm-encoder".
36+
37+Optional properties:
38+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
39+ connector. This is used to obtain the supported resolutions
40+ of an attached monitor. If not defined, then a default
41+ set of resolutions is used and the display will initialize
42+ to 720p. Note most VGA connectors on Digilent boards do
43+ not have the DDC bus routed out.
44+
45+Example:
46+
47+ encoder_0: digilent_encoder {
48+ compatible = "digilent,drm-encoder";
49+ dglnt,edid-i2c = <&i2c1>;
50+ };
51diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
52index a713b17673..c32a4a679e 100644
53--- a/drivers/gpu/drm/xilinx/Kconfig
54+++ b/drivers/gpu/drm/xilinx/Kconfig
55@@ -21,3 +21,9 @@ config DRM_XILINX_DP_SUB
56 select DRM_XILINX_DP
57 help
58 DRM driver for Xilinx Display Port Subsystem.
59+
60+config DRM_DIGILENT_ENCODER
61+ tristate "Digilent VGA/HDMI DRM Encoder Driver"
62+ depends on DRM_XILINX
63+ help
64+ DRM slave encoder for Video-out on Digilent boards.
65diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
66index 705472c338..a571bd96cf 100644
67--- a/drivers/gpu/drm/xilinx/Makefile
68+++ b/drivers/gpu/drm/xilinx/Makefile
69@@ -10,3 +10,4 @@ xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
70 obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
71 obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
72 obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
73+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
74diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
75new file mode 100644
76index 0000000000..26a23986f9
77--- /dev/null
78+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
79@@ -0,0 +1,217 @@
80+/*
81+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
82+ *
83+ * Copyright (C) 2015 Digilent
84+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
85+ *
86+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
87+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
88+ *
89+ * This software is licensed under the terms of the GNU General Public
90+ * License version 2, as published by the Free Software Foundation, and
91+ * may be copied, distributed, and modified under those terms.
92+ *
93+ * This program is distributed in the hope that it will be useful,
94+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
95+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
96+ * GNU General Public License for more details.
97+ */
98+
99+#include <drm/drmP.h>
100+#include <drm/drm_edid.h>
101+#include <drm/drm_encoder_slave.h>
102+
103+#include <linux/device.h>
104+#include <linux/module.h>
105+#include <linux/err.h>
106+#include <linux/i2c.h>
107+#include <linux/of.h>
108+#include <linux/of_platform.h>
109+#include <linux/platform_device.h>
110+
111+#define DGLNT_ENC_MAX_FREQ 150000
112+#define DGLNT_ENC_MAX_H 1920
113+#define DGLNT_ENC_MAX_V 1080
114+#define DGLNT_ENC_PREF_H 1280
115+#define DGLNT_ENC_PREF_V 720
116+
117+struct dglnt_encoder {
118+ struct drm_encoder *encoder;
119+ struct i2c_adapter *i2c_bus;
120+ bool i2c_present;
121+};
122+
123+static inline struct dglnt_encoder *to_dglnt_encoder(
124+ struct drm_encoder *encoder)
125+{
126+ return to_encoder_slave(encoder)->slave_priv;
127+}
128+
129+static bool dglnt_mode_fixup(struct drm_encoder *encoder,
130+ const struct drm_display_mode *mode,
131+ struct drm_display_mode *adjusted_mode)
132+{
133+ return true;
134+}
135+
136+static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
137+ struct drm_display_mode *mode,
138+ struct drm_display_mode *adjusted_mode)
139+{
140+}
141+
142+static void
143+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
144+{
145+}
146+
147+static void dglnt_encoder_save(struct drm_encoder *encoder)
148+{
149+}
150+
151+static void dglnt_encoder_restore(struct drm_encoder *encoder)
152+{
153+}
154+
155+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
156+ struct drm_display_mode *mode)
157+{
158+ if (mode &&
159+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
160+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
161+ (mode->clock <= DGLNT_ENC_MAX_FREQ) &&
162+ (mode->hdisplay <= DGLNT_ENC_MAX_H) &&
163+ (mode->vdisplay <= DGLNT_ENC_MAX_V))
164+ return MODE_OK;
165+ return MODE_BAD;
166+}
167+
168+static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
169+ struct drm_connector *connector)
170+{
171+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
172+ struct edid *edid;
173+ int num_modes = 0;
174+
175+ if (dglnt->i2c_present) {
176+ edid = drm_get_edid(connector, dglnt->i2c_bus);
177+ drm_mode_connector_update_edid_property(connector, edid);
178+ if (edid) {
179+ num_modes = drm_add_edid_modes(connector, edid);
180+ kfree(edid);
181+ }
182+ } else {
183+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
184+ DGLNT_ENC_MAX_V);
185+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
186+ DGLNT_ENC_PREF_V);
187+ }
188+ return num_modes;
189+}
190+
191+static enum drm_connector_status dglnt_encoder_detect(
192+ struct drm_encoder *encoder,
193+ struct drm_connector *connector)
194+{
195+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
196+
197+ if (dglnt->i2c_present) {
198+ if (drm_probe_ddc(dglnt->i2c_bus))
199+ return connector_status_connected;
200+ return connector_status_disconnected;
201+ } else
202+ return connector_status_unknown;
203+}
204+
205+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
206+ .dpms = dglnt_encoder_dpms,
207+ .save = dglnt_encoder_save,
208+ .restore = dglnt_encoder_restore,
209+ .mode_fixup = dglnt_mode_fixup,
210+ .mode_valid = dglnt_encoder_mode_valid,
211+ .mode_set = dglnt_encoder_mode_set,
212+ .detect = dglnt_encoder_detect,
213+ .get_modes = dglnt_encoder_get_modes,
214+};
215+
216+static int dglnt_encoder_encoder_init(struct platform_device *pdev,
217+ struct drm_device *dev,
218+ struct drm_encoder_slave *encoder)
219+{
220+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
221+ struct device_node *sub_node;
222+
223+ encoder->slave_priv = dglnt;
224+ encoder->slave_funcs = &dglnt_encoder_slave_funcs;
225+
226+ dglnt->encoder = &encoder->base;
227+
228+ /* get i2c adapter for edid */
229+ dglnt->i2c_present = false;
230+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
231+ if (sub_node) {
232+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
233+ if (!dglnt->i2c_bus)
234+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
235+ else
236+ dglnt->i2c_present = true;
237+ of_node_put(sub_node);
238+ }
239+
240+ return 0;
241+}
242+
243+static int dglnt_encoder_probe(struct platform_device *pdev)
244+{
245+ struct dglnt_encoder *dglnt;
246+
247+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
248+ if (!dglnt)
249+ return -ENOMEM;
250+
251+ platform_set_drvdata(pdev, dglnt);
252+
253+ return 0;
254+}
255+
256+static int dglnt_encoder_remove(struct platform_device *pdev)
257+{
258+ return 0;
259+}
260+
261+static const struct of_device_id dglnt_encoder_of_match[] = {
262+ { .compatible = "digilent,drm-encoder", },
263+ { /* end of table */ },
264+};
265+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
266+
267+static struct drm_platform_encoder_driver dglnt_encoder_driver = {
268+ .platform_driver = {
269+ .probe = dglnt_encoder_probe,
270+ .remove = dglnt_encoder_remove,
271+ .driver = {
272+ .owner = THIS_MODULE,
273+ .name = "dglnt-drm-enc",
274+ .of_match_table = dglnt_encoder_of_match,
275+ },
276+ },
277+
278+ .encoder_init = dglnt_encoder_encoder_init,
279+};
280+
281+static int __init dglnt_encoder_init(void)
282+{
283+ return platform_driver_register(&dglnt_encoder_driver.platform_driver);
284+}
285+
286+static void __exit dglnt_encoder_exit(void)
287+{
288+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
289+}
290+
291+module_init(dglnt_encoder_init);
292+module_exit(dglnt_encoder_exit);
293+
294+MODULE_AUTHOR("Digilent, Inc.");
295+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
296+MODULE_LICENSE("GPL v2");
297--
2982.10.2
299
diff --git a/recipes-kernel/linux/linux-xlnx/4.6/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/recipes-kernel/linux/linux-xlnx/4.6/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
deleted file mode 100644
index 5551b816..00000000
--- a/recipes-kernel/linux/linux-xlnx/4.6/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
+++ /dev/null
@@ -1,607 +0,0 @@
1From b1c1dbc241385fcf1f85c5be9a6fb30fd70c784d Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:16:06 +1000
4Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
5
6Add support for the axi_dynclk IP Core available from Digilent. This IP
7core dynamically configures the clock resources inside a Xilinx FPGA to
8generate a clock with a software programmable frequency.
9
10Upstream-Status: Pending
11
12Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
13Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
14---
15 drivers/clk/Kconfig | 8 +
16 drivers/clk/Makefile | 1 +
17 drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 556 insertions(+)
19 create mode 100644 drivers/clk/clk-dglnt-dynclk.c
20
21diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
22index d42af55820..e276d9a27e 100644
23--- a/drivers/clk/Kconfig
24+++ b/drivers/clk/Kconfig
25@@ -158,6 +158,14 @@ config CLK_QORIQ
26 This adds the clock driver support for Freescale QorIQ platforms
27 using common clock framework.
28
29+config COMMON_CLK_DGLNT_DYNCLK
30+ tristate "Digilent axi_dynclk Driver"
31+ depends on ARCH_ZYNQ || MICROBLAZE
32+ help
33+ ---help---
34+ Support for the Digilent AXI Dynamic Clock core for Xilinx
35+ FPGAs.
36+
37 config COMMON_CLK_XGENE
38 bool "Clock driver for APM XGene SoC"
39 default y
40diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
41index e861470ef1..6c0a5a8d6b 100644
42--- a/drivers/clk/Makefile
43+++ b/drivers/clk/Makefile
44@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
45 obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
46 obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
47 obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
48+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o
49 obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
50 obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
51 obj-$(CONFIG_MACH_LOONGSON32) += clk-ls1x.o
52diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
53new file mode 100644
54index 0000000000..496ad5fc90
55--- /dev/null
56+++ b/drivers/clk/clk-dglnt-dynclk.c
57@@ -0,0 +1,547 @@
58+/*
59+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
60+ *
61+ * Copyright (C) 2015 Digilent
62+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
63+ *
64+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
65+ *
66+ * This software is licensed under the terms of the GNU General Public
67+ * License version 2, as published by the Free Software Foundation, and
68+ * may be copied, distributed, and modified under those terms.
69+ *
70+ * This program is distributed in the hope that it will be useful,
71+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
72+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
73+ * GNU General Public License for more details.
74+ */
75+
76+#include <linux/platform_device.h>
77+#include <linux/clk-provider.h>
78+#include <linux/clk.h>
79+#include <linux/slab.h>
80+#include <linux/io.h>
81+#include <linux/of.h>
82+#include <linux/module.h>
83+#include <linux/err.h>
84+#include <linux/kernel.h>
85+
86+#define CLK_BIT_WEDGE 13
87+#define CLK_BIT_NOCOUNT 12
88+
89+/* This value is used to signal an error */
90+#define ERR_CLKCOUNTCALC 0xFFFFFFFF
91+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
92+
93+#define DYNCLK_DIV_1_REGMASK 0x1041
94+/* 25 MHz (125 KHz / 5) */
95+#define DYNCLK_DEFAULT_FREQ 125000
96+
97+#define MMCM_FREQ_VCOMIN 600000
98+#define MMCM_FREQ_VCOMAX 1200000
99+#define MMCM_FREQ_PFDMIN 10000
100+#define MMCM_FREQ_PFDMAX 450000
101+#define MMCM_FREQ_OUTMIN 4000
102+#define MMCM_FREQ_OUTMAX 800000
103+#define MMCM_DIV_MAX 106
104+#define MMCM_FB_MIN 2
105+#define MMCM_FB_MAX 64
106+#define MMCM_CLKDIV_MAX 128
107+#define MMCM_CLKDIV_MIN 1
108+
109+#define OFST_DISPLAY_CTRL 0x0
110+#define OFST_DISPLAY_STATUS 0x4
111+#define OFST_DISPLAY_CLK_L 0x8
112+#define OFST_DISPLAY_FB_L 0x0C
113+#define OFST_DISPLAY_FB_H_CLK_H 0x10
114+#define OFST_DISPLAY_DIV 0x14
115+#define OFST_DISPLAY_LOCK_L 0x18
116+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
117+
118+static const u64 lock_lookup[64] = {
119+ 0b0011000110111110100011111010010000000001,
120+ 0b0011000110111110100011111010010000000001,
121+ 0b0100001000111110100011111010010000000001,
122+ 0b0101101011111110100011111010010000000001,
123+ 0b0111001110111110100011111010010000000001,
124+ 0b1000110001111110100011111010010000000001,
125+ 0b1001110011111110100011111010010000000001,
126+ 0b1011010110111110100011111010010000000001,
127+ 0b1100111001111110100011111010010000000001,
128+ 0b1110011100111110100011111010010000000001,
129+ 0b1111111111111000010011111010010000000001,
130+ 0b1111111111110011100111111010010000000001,
131+ 0b1111111111101110111011111010010000000001,
132+ 0b1111111111101011110011111010010000000001,
133+ 0b1111111111101000101011111010010000000001,
134+ 0b1111111111100111000111111010010000000001,
135+ 0b1111111111100011111111111010010000000001,
136+ 0b1111111111100010011011111010010000000001,
137+ 0b1111111111100000110111111010010000000001,
138+ 0b1111111111011111010011111010010000000001,
139+ 0b1111111111011101101111111010010000000001,
140+ 0b1111111111011100001011111010010000000001,
141+ 0b1111111111011010100111111010010000000001,
142+ 0b1111111111011001000011111010010000000001,
143+ 0b1111111111011001000011111010010000000001,
144+ 0b1111111111010111011111111010010000000001,
145+ 0b1111111111010101111011111010010000000001,
146+ 0b1111111111010101111011111010010000000001,
147+ 0b1111111111010100010111111010010000000001,
148+ 0b1111111111010100010111111010010000000001,
149+ 0b1111111111010010110011111010010000000001,
150+ 0b1111111111010010110011111010010000000001,
151+ 0b1111111111010010110011111010010000000001,
152+ 0b1111111111010001001111111010010000000001,
153+ 0b1111111111010001001111111010010000000001,
154+ 0b1111111111010001001111111010010000000001,
155+ 0b1111111111001111101011111010010000000001,
156+ 0b1111111111001111101011111010010000000001,
157+ 0b1111111111001111101011111010010000000001,
158+ 0b1111111111001111101011111010010000000001,
159+ 0b1111111111001111101011111010010000000001,
160+ 0b1111111111001111101011111010010000000001,
161+ 0b1111111111001111101011111010010000000001,
162+ 0b1111111111001111101011111010010000000001,
163+ 0b1111111111001111101011111010010000000001,
164+ 0b1111111111001111101011111010010000000001,
165+ 0b1111111111001111101011111010010000000001,
166+ 0b1111111111001111101011111010010000000001,
167+ 0b1111111111001111101011111010010000000001,
168+ 0b1111111111001111101011111010010000000001,
169+ 0b1111111111001111101011111010010000000001,
170+ 0b1111111111001111101011111010010000000001,
171+ 0b1111111111001111101011111010010000000001,
172+ 0b1111111111001111101011111010010000000001,
173+ 0b1111111111001111101011111010010000000001,
174+ 0b1111111111001111101011111010010000000001,
175+ 0b1111111111001111101011111010010000000001,
176+ 0b1111111111001111101011111010010000000001,
177+ 0b1111111111001111101011111010010000000001,
178+ 0b1111111111001111101011111010010000000001,
179+ 0b1111111111001111101011111010010000000001,
180+ 0b1111111111001111101011111010010000000001,
181+ 0b1111111111001111101011111010010000000001,
182+ 0b1111111111001111101011111010010000000001
183+};
184+
185+static const u32 filter_lookup_low[64] = {
186+ 0b0001011111,
187+ 0b0001010111,
188+ 0b0001111011,
189+ 0b0001011011,
190+ 0b0001101011,
191+ 0b0001110011,
192+ 0b0001110011,
193+ 0b0001110011,
194+ 0b0001110011,
195+ 0b0001001011,
196+ 0b0001001011,
197+ 0b0001001011,
198+ 0b0010110011,
199+ 0b0001010011,
200+ 0b0001010011,
201+ 0b0001010011,
202+ 0b0001010011,
203+ 0b0001010011,
204+ 0b0001010011,
205+ 0b0001010011,
206+ 0b0001010011,
207+ 0b0001010011,
208+ 0b0001010011,
209+ 0b0001100011,
210+ 0b0001100011,
211+ 0b0001100011,
212+ 0b0001100011,
213+ 0b0001100011,
214+ 0b0001100011,
215+ 0b0001100011,
216+ 0b0001100011,
217+ 0b0001100011,
218+ 0b0001100011,
219+ 0b0001100011,
220+ 0b0001100011,
221+ 0b0001100011,
222+ 0b0001100011,
223+ 0b0010010011,
224+ 0b0010010011,
225+ 0b0010010011,
226+ 0b0010010011,
227+ 0b0010010011,
228+ 0b0010010011,
229+ 0b0010010011,
230+ 0b0010010011,
231+ 0b0010010011,
232+ 0b0010010011,
233+ 0b0010100011,
234+ 0b0010100011,
235+ 0b0010100011,
236+ 0b0010100011,
237+ 0b0010100011,
238+ 0b0010100011,
239+ 0b0010100011,
240+ 0b0010100011,
241+ 0b0010100011,
242+ 0b0010100011,
243+ 0b0010100011,
244+ 0b0010100011,
245+ 0b0010100011,
246+ 0b0010100011,
247+ 0b0010100011,
248+ 0b0010100011,
249+ 0b0010100011
250+};
251+
252+struct dglnt_dynclk_reg;
253+struct dglnt_dynclk_mode;
254+struct dglnt_dynclk;
255+
256+struct dglnt_dynclk_reg {
257+ u32 clk0L;
258+ u32 clkFBL;
259+ u32 clkFBH_clk0H;
260+ u32 divclk;
261+ u32 lockL;
262+ u32 fltr_lockH;
263+};
264+
265+struct dglnt_dynclk_mode {
266+ u32 freq;
267+ u32 fbmult;
268+ u32 clkdiv;
269+ u32 maindiv;
270+};
271+
272+struct dglnt_dynclk {
273+ void __iomem *base;
274+ struct clk_hw clk_hw;
275+ unsigned long freq;
276+};
277+
278+u32 dglnt_dynclk_divider(u32 divide)
279+{
280+ u32 output = 0;
281+ u32 highTime = 0;
282+ u32 lowTime = 0;
283+
284+ if ((divide < 1) || (divide > 128))
285+ return ERR_CLKDIVIDER;
286+
287+ if (divide == 1)
288+ return DYNCLK_DIV_1_REGMASK;
289+
290+ highTime = divide / 2;
291+ /* if divide is odd */
292+ if (divide & 0x1) {
293+ lowTime = highTime + 1;
294+ output = 1 << CLK_BIT_WEDGE;
295+ } else {
296+ lowTime = highTime;
297+ }
298+
299+ output |= 0x03F & lowTime;
300+ output |= 0xFC0 & (highTime << 6);
301+ return output;
302+}
303+
304+u32 dglnt_dynclk_count_calc(u32 divide)
305+{
306+ u32 output = 0;
307+ u32 divCalc = 0;
308+
309+ divCalc = dglnt_dynclk_divider(divide);
310+ if (divCalc == ERR_CLKDIVIDER)
311+ output = ERR_CLKCOUNTCALC;
312+ else
313+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
314+ return output;
315+}
316+
317+
318+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
319+ struct dglnt_dynclk_mode *clkParams)
320+{
321+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
322+ return -EINVAL;
323+
324+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
325+ if (regValues->clk0L == ERR_CLKCOUNTCALC)
326+ return -EINVAL;
327+
328+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
329+ if (regValues->clkFBL == ERR_CLKCOUNTCALC)
330+ return -EINVAL;
331+
332+ regValues->clkFBH_clk0H = 0;
333+
334+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
335+ if (regValues->divclk == ERR_CLKDIVIDER)
336+ return -EINVAL;
337+
338+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
339+ 0xFFFFFFFF);
340+
341+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
342+ 32) & 0x000000FF);
343+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
344+ 16) & 0x03FF0000);
345+
346+ return 0;
347+}
348+
349+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
350+ void __iomem *baseaddr)
351+{
352+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
353+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
354+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
355+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
356+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
357+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
358+}
359+
360+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
361+ struct dglnt_dynclk_mode *bestPick)
362+{
363+ u32 bestError = MMCM_FREQ_OUTMAX;
364+ u32 curError;
365+ u32 curClkMult;
366+ u32 curFreq;
367+ u32 divVal;
368+ u32 curFb, curClkDiv;
369+ u32 minFb = 0;
370+ u32 maxFb = 0;
371+ u32 curDiv = 1;
372+ u32 maxDiv;
373+ bool freq_found = false;
374+
375+ bestPick->freq = 0;
376+ if (parentFreq == 0)
377+ return 0;
378+
379+ /* minimum frequency is actually dictated by VCOmin */
380+ if (freq < MMCM_FREQ_OUTMIN)
381+ freq = MMCM_FREQ_OUTMIN;
382+ if (freq > MMCM_FREQ_OUTMAX)
383+ freq = MMCM_FREQ_OUTMAX;
384+
385+ if (parentFreq > MMCM_FREQ_PFDMAX)
386+ curDiv = 2;
387+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
388+ if (maxDiv > MMCM_DIV_MAX)
389+ maxDiv = MMCM_DIV_MAX;
390+
391+ while (curDiv <= maxDiv && !freq_found) {
392+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
393+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
394+ if (maxFb > MMCM_FB_MAX)
395+ maxFb = MMCM_FB_MAX;
396+ if (minFb < MMCM_FB_MIN)
397+ minFb = MMCM_FB_MIN;
398+
399+ divVal = curDiv * freq;
400+ /*
401+ * This multiplier is used to find the best clkDiv value for
402+ * each FB value
403+ */
404+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
405+
406+ curFb = minFb;
407+ while (curFb <= maxFb && !freq_found) {
408+ curClkDiv = ((curClkMult * curFb) + 500) / 1000;
409+ if (curClkDiv > MMCM_CLKDIV_MAX)
410+ curClkDiv = MMCM_CLKDIV_MAX;
411+ if (curClkDiv < MMCM_CLKDIV_MIN)
412+ curClkDiv = MMCM_CLKDIV_MIN;
413+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
414+ if (curFreq >= freq)
415+ curError = curFreq - freq;
416+ else
417+ curError = freq - curFreq;
418+ if (curError < bestError) {
419+ bestError = curError;
420+ bestPick->clkdiv = curClkDiv;
421+ bestPick->fbmult = curFb;
422+ bestPick->maindiv = curDiv;
423+ bestPick->freq = curFreq;
424+ }
425+ if (!curError)
426+ freq_found = true;
427+ curFb++;
428+ }
429+ curDiv++;
430+ }
431+ return bestPick->freq;
432+}
433+
434+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
435+{
436+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
437+}
438+
439+
440+static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
441+{
442+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
443+ unsigned int clock_state;
444+
445+ if (dglnt_dynclk->freq) {
446+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
447+ do {
448+ clock_state = readl(dglnt_dynclk->base +
449+ OFST_DISPLAY_STATUS);
450+ } while (!clock_state);
451+ }
452+ return 0;
453+}
454+
455+static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
456+{
457+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
458+
459+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
460+}
461+
462+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
463+ unsigned long rate, unsigned long parent_rate)
464+{
465+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
466+ struct dglnt_dynclk_reg clkReg;
467+ struct dglnt_dynclk_mode clkMode;
468+
469+ if (parent_rate == 0 || rate == 0)
470+ return -EINVAL;
471+ if (rate == dglnt_dynclk->freq)
472+ return 0;
473+
474+ /*
475+ * Convert from Hz to KHz, then multiply by five to account for
476+ * BUFR division
477+ */
478+ rate = (rate + 100) / 200;
479+ /* convert from Hz to KHz */
480+ parent_rate = (parent_rate + 500) / 1000;
481+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
482+ return -EINVAL;
483+
484+ /*
485+ * Write to the PLL dynamic configuration registers to configure it
486+ * with the calculated parameters.
487+ */
488+ dglnt_dynclk_find_reg(&clkReg, &clkMode);
489+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
490+ dglnt_dynclk->freq = clkMode.freq * 200;
491+ dglnt_dynclk_disable(clk_hw);
492+ dglnt_dynclk_enable(clk_hw);
493+
494+ return 0;
495+}
496+
497+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
498+ unsigned long *parent_rate)
499+{
500+ struct dglnt_dynclk_mode clkMode;
501+
502+ dglnt_dynclk_find_mode(((rate + 100) / 200),
503+ ((*parent_rate) + 500) / 1000, &clkMode);
504+
505+ return (clkMode.freq * 200);
506+}
507+
508+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
509+ unsigned long parent_rate)
510+{
511+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
512+
513+ return dglnt_dynclk->freq;
514+}
515+
516+
517+static const struct clk_ops dglnt_dynclk_ops = {
518+ .recalc_rate = dglnt_dynclk_recalc_rate,
519+ .round_rate = dglnt_dynclk_round_rate,
520+ .set_rate = dglnt_dynclk_set_rate,
521+ .enable = dglnt_dynclk_enable,
522+ .disable = dglnt_dynclk_disable,
523+};
524+
525+static const struct of_device_id dglnt_dynclk_ids[] = {
526+ { .compatible = "digilent,axi-dynclk", },
527+ { },
528+};
529+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
530+
531+static int dglnt_dynclk_probe(struct platform_device *pdev)
532+{
533+ const struct of_device_id *id;
534+ struct dglnt_dynclk *dglnt_dynclk;
535+ struct clk_init_data init;
536+ const char *parent_name;
537+ const char *clk_name;
538+ struct resource *mem;
539+ struct clk *clk;
540+
541+ if (!pdev->dev.of_node)
542+ return -ENODEV;
543+
544+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
545+ if (!id)
546+ return -ENODEV;
547+
548+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
549+ GFP_KERNEL);
550+ if (!dglnt_dynclk)
551+ return -ENOMEM;
552+
553+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
555+ if (IS_ERR(dglnt_dynclk->base))
556+ return PTR_ERR(dglnt_dynclk->base);
557+
558+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
559+ if (!parent_name)
560+ return -EINVAL;
561+
562+ clk_name = pdev->dev.of_node->name;
563+ of_property_read_string(pdev->dev.of_node, "clock-output-names",
564+ &clk_name);
565+
566+ init.name = clk_name;
567+ init.ops = &dglnt_dynclk_ops;
568+ init.flags = 0;
569+ init.parent_names = &parent_name;
570+ init.num_parents = 1;
571+
572+ dglnt_dynclk->freq = 0;
573+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
574+
575+ dglnt_dynclk->clk_hw.init = &init;
576+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
577+ if (IS_ERR(clk))
578+ return PTR_ERR(clk);
579+
580+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
581+ clk);
582+}
583+
584+static int dglnt_dynclk_remove(struct platform_device *pdev)
585+{
586+ of_clk_del_provider(pdev->dev.of_node);
587+
588+ return 0;
589+}
590+
591+static struct platform_driver dglnt_dynclk_driver = {
592+ .driver = {
593+ .name = "dglnt-dynclk",
594+ .owner = THIS_MODULE,
595+ .of_match_table = dglnt_dynclk_ids,
596+ },
597+ .probe = dglnt_dynclk_probe,
598+ .remove = dglnt_dynclk_remove,
599+};
600+module_platform_driver(dglnt_dynclk_driver);
601+
602+MODULE_LICENSE("GPL v2");
603+MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
604+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
605--
6062.10.2
607
diff --git a/recipes-kernel/linux/linux-xlnx/4.6/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/recipes-kernel/linux/linux-xlnx/4.6/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
deleted file mode 100644
index f0f51c3d..00000000
--- a/recipes-kernel/linux/linux-xlnx/4.6/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
+++ /dev/null
@@ -1,65 +0,0 @@
1From aec919daafd960b5bfcb8eb2352bc7f2857df56f Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 2 May 2016 23:46:42 +1000
4Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
5
6Fix the issues where the VTC is reset (losing its timing config).
7
8Also fix the issue where the plane destroys its DMA descriptors and
9marks the DMA channels as inactive but never recreates the descriptors
10and never updates the active state when turning DPMS back on.
11
12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
13Upstream-Status: Pending [This is a workaround]
14---
15 drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 -
16 drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 7 +++----
17 2 files changed, 3 insertions(+), 5 deletions(-)
18
19diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
20index 33a7931c2e..0f346c53de 100644
21--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
22+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
23@@ -78,7 +78,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
24 default:
25 if (crtc->vtc) {
26 xilinx_vtc_disable(crtc->vtc);
27- xilinx_vtc_reset(crtc->vtc);
28 }
29 if (crtc->cresample) {
30 xilinx_cresample_disable(crtc->cresample);
31diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
32index 7fc110a8a5..83fcfd6db5 100644
33--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
34+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
35@@ -151,9 +151,7 @@ void xilinx_drm_plane_dpms(struct drm_plane *base_plane, int dpms)
36 }
37
38 /* start dma engine */
39- for (i = 0; i < MAX_NUM_SUB_PLANES; i++)
40- if (plane->dma[i].chan && plane->dma[i].is_active)
41- dma_async_issue_pending(plane->dma[i].chan);
42+ xilinx_drm_plane_commit(base_plane);
43
44 if (plane->rgb2yuv)
45 xilinx_rgb2yuv_enable(plane->rgb2yuv);
46@@ -228,7 +226,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
47 for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
48 struct xilinx_drm_plane_dma *dma = &plane->dma[i];
49
50- if (dma->chan && dma->is_active) {
51+ if (dma->chan) {
52 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
53 desc = dmaengine_prep_interleaved_dma(dma->chan,
54 &dma->xt,
55@@ -241,6 +239,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
56 dmaengine_submit(desc);
57
58 dma_async_issue_pending(dma->chan);
59+ dma->is_active = true;
60 }
61 }
62 }
63--
642.10.2
65
diff --git a/recipes-kernel/linux/linux-xlnx_2016.4.bb b/recipes-kernel/linux/linux-xlnx_2016.4.bb
deleted file mode 100644
index 456d0023..00000000
--- a/recipes-kernel/linux/linux-xlnx_2016.4.bb
+++ /dev/null
@@ -1,12 +0,0 @@
1LINUX_VERSION = "4.6"
2XILINX_RELEASE_VERSION = "v2016.4"
3SRCREV ?= "2762bc9163bb8576f63ff82801a65576f59e1e57"
4
5include linux-xlnx.inc
6
7SRC_URI_append_zybo-linux-bd-zynq7 = " \
8 file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
9 file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
10 file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
11 "
12
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-26 05:31:39 +0000