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authorAlejandro Enedino Hernandez Samaniego <alejandr@xilinx.com>2019-04-19 15:33:26 -0700
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2019-06-28 16:32:42 -0700
commitc2f811bd347638262122ba522c2f0f55e04b6c66 (patch)
tree381b84f504dccba3f0135725bc61d61e1c453049
parent3280ab0e35873213f4d52019ff22bbcef4fe09d0 (diff)
downloadmeta-xilinx-c2f811bd347638262122ba522c2f0f55e04b6c66.tar.gz
gcc: update microblaze patches
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch87
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch51
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch466
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch479
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend4
5 files changed, 1087 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 00000000..8bc47a43
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
1From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Fri, 29 Mar 2019 12:08:39 +0530
4Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of
5 peephole2 optimization,if we can then we will fix the compiler issue.
6
7---
8 gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
9 1 file changed, 38 insertions(+), 25 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 88aee9e..8bd175f 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -880,31 +880,44 @@
16 (set_attr "mode" "SI")
17 (set_attr "length" "4")])
18
19-(define_peephole2
20- [(set (match_operand:SI 0 "register_operand")
21- (fix:SI (match_operand:SF 1 "register_operand")))
22- (set (pc)
23- (if_then_else (match_operator 2 "ordered_comparison_operator"
24- [(match_operand:SI 3 "register_operand")
25- (match_operand:SI 4 "arith_operand")])
26- (label_ref (match_operand 5))
27- (pc)))]
28- "TARGET_HARD_FLOAT && !TARGET_MB_64"
29- [(set (match_dup 1) (match_dup 3))]
30-
31- {
32- rtx condition;
33- rtx cmp_op0 = operands[3];
34- rtx cmp_op1 = operands[4];
35- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
36-
37- emit_insn (gen_cstoresf4 (comp_reg, operands[2],
38- gen_rtx_REG (SFmode, REGNO (cmp_op0)),
39- gen_rtx_REG (SFmode, REGNO (cmp_op1))));
40- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
41- emit_jump_insn (gen_condjump (condition, operands[5]));
42- }
43-)
44+;; peephole2 optimization will be done only if fint and if-then-else
45+;; are dependent.added condition for the same.
46+;; if they are dependent then gcc is giving "flow control insn inside a basic block"
47+;; testcase:
48+;; volatile float vec = 1.0;
49+;; volatile int ci = 2;
50+;; register int cj = (int)(vec);
51+;;// ci=cj;
52+;;// if (ci <0) {
53+;; if (cj < 0) {
54+;; ci = 0;
55+;; }
56+;; commenting for now.we will check the possibility of this optimization later
57+
58+;;(define_peephole2
59+;; [(set (match_operand:SI 0 "register_operand")
60+;; (fix:SI (match_operand:SF 1 "register_operand")))
61+;; (set (pc)
62+;; (if_then_else (match_operator 2 "ordered_comparison_operator"
63+;; [(match_operand:SI 3 "register_operand")
64+;; (match_operand:SI 4 "arith_operand")])
65+;; (label_ref (match_operand 5))
66+;; (pc)))]
67+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
68+;; [(set (match_dup 1) (match_dup 3))]
69+;; {
70+;; rtx condition;
71+;; rtx cmp_op0 = operands[3];
72+;; rtx cmp_op1 = operands[4];
73+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
74+;;
75+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2],
76+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)),
77+;; gen_rtx_REG (SFmode, REGNO (cmp_op1))));
78+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
79+;; emit_jump_insn (gen_condjump (condition, operands[5]));
80+;; }
81+;;)
82
83 ;;----------------------------------------------------------------
84 ;; Negation and one's complement
85--
862.7.4
87
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 00000000..be4dfad5
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
1From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 16 Apr 2019 17:20:24 +0530
4Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with
5 this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
6 before propagating constants."
7
8This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
9---
10 gcc/cprop.c | 4 ----
11 1 file changed, 4 deletions(-)
12
13diff --git a/gcc/cprop.c b/gcc/cprop.c
14index deb706b..e4df509 100644
15--- a/gcc/cprop.c
16+++ b/gcc/cprop.c
17@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
18 int success = 0;
19 rtx set = single_set (insn);
20
21-#if 0
22 bool check_rtx_costs = true;
23 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
24 int old_cost = set ? set_rtx_cost (set, speed) : 0;
25@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
26 && (GET_CODE (XEXP (note, 0)) == CONST
27 || CONSTANT_P (XEXP (note, 0)))))
28 check_rtx_costs = false;
29-#endif
30
31 /* Usually we substitute easy stuff, so we won't copy everything.
32 We however need to take care to not duplicate non-trivial CONST
33@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
34
35 validate_replace_src_group (from, to, insn);
36
37-#if 0
38 /* If TO is a constant, check the cost of the set after propagation
39 to the cost of the set before the propagation. If the cost is
40 higher, then do not replace FROM with TO. */
41@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
42 return false;
43 }
44
45-#endif
46
47 if (num_changes_pending () && apply_change_group ())
48 success = 1;
49--
502.7.4
51
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 00000000..1548faad
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
1From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 17 Apr 2019 12:36:16 +0530
4Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod
5 assembly files.
6
7---
8 libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++----
9 libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++---
10 libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++-
11 libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
12 libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
13 5 files changed, 212 insertions(+), 20 deletions(-)
14
15diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
16index 7e7d875..cfb4c05 100644
17--- a/libgcc/config/microblaze/divsi3.S
18+++ b/libgcc/config/microblaze/divsi3.S
19@@ -46,7 +46,7 @@
20 __divsi3:
21 .frame r1,0,r15
22
23- ADDIK r1,r1,-32
24+ ADDLIK r1,r1,-32
25 SLI r28,r1,0
26 SLI r29,r1,8
27 SLI r30,r1,16
28@@ -61,13 +61,23 @@ __divsi3:
29 SWI r30,r1,8
30 SWI r31,r1,12
31 #endif
32- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
33- BEQI r5,$LaResult_Is_Zero # Result is Zero
34- BGEID r5,$LaR5_Pos
35+#ifdef __arch64__
36+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
37+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
38+ BEAGEID r5,$LaR5_Pos
39+#else
40+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
41+ BEQI r5,$LaResult_Is_Zero # Result is Zero
42+ BGEID r5,$LaR5_Pos
43+#endif
44 XOR r28,r5,r6 # Get the sign of the result
45 RSUBI r5,r5,0 # Make r5 positive
46 $LaR5_Pos:
47- BGEI r6,$LaR6_Pos
48+#ifdef __arch64__
49+ BEAGEI r6,$LaR6_Pos
50+#else
51+ BGEI r6,$LaR6_Pos
52+#endif
53 RSUBI r6,r6,0 # Make r6 positive
54 $LaR6_Pos:
55 ADDIK r30,r0,0 # Clear mod
56@@ -76,26 +86,51 @@ $LaR6_Pos:
57
58 # First part try to find the first '1' in the r5
59 $LaDIV0:
60- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
61+#ifdef __arch64__
62+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000
63+#else
64+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
65+#endif
66 $LaDIV1:
67 ADD r5,r5,r5 # left shift logical r5
68+#ifdef __arch64__
69+ BEAGTID r5,$LaDIV1
70+#else
71 BGTID r5,$LaDIV1
72+#endif
73 ADDIK r29,r29,-1
74 $LaDIV2:
75 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
76 ADDC r30,r30,r30 # Move that bit into the Mod register
77 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
78+#ifdef __arch64__
79+ BEALTI r31,$LaMOD_TOO_SMALL
80+#else
81 BLTI r31,$LaMOD_TOO_SMALL
82+#endif
83 OR r30,r0,r31 # Move the r31 to mod since the result was positive
84 ADDIK r3,r3,1
85 $LaMOD_TOO_SMALL:
86 ADDIK r29,r29,-1
87+#ifdef __arch64__
88+ BEAEQi r29,$LaLOOP_END
89+#else
90 BEQi r29,$LaLOOP_END
91+#endif
92 ADD r3,r3,r3 # Shift in the '1' into div
93+#ifdef __arch64__
94+ BREAI $LaDIV2 # Div2
95+#else
96 BRI $LaDIV2 # Div2
97+#endif
98 $LaLOOP_END:
99+#ifdef __arch64__
100+ BEAGEI r28,$LaRETURN_HERE
101+ BREAID $LaRETURN_HERE
102+#else
103 BGEI r28,$LaRETURN_HERE
104 BRID $LaRETURN_HERE
105+#endif
106 RSUBI r3,r3,0 # Negate the result
107 $LaDiv_By_Zero:
108 $LaResult_Is_Zero:
109diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
110index 46ff34a..49618dd 100644
111--- a/libgcc/config/microblaze/modsi3.S
112+++ b/libgcc/config/microblaze/modsi3.S
113@@ -62,40 +62,72 @@ __modsi3:
114 swi r31,r1,12
115 #endif
116
117+#ifdef __arch64__
118+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
119+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
120+ BEAGEId r5,$LaR5_Pos
121+#else
122 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
123 BEQI r5,$LaResult_Is_Zero # Result is Zero
124 BGEId r5,$LaR5_Pos
125+#endif
126 ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
127 RSUBI r5,r5,0 # Make r5 positive
128 $LaR5_Pos:
129- BGEI r6,$LaR6_Pos
130+#ifdef __arch64__
131+ BEAGEI r6,$LaR6_Pos
132+#else
133+ BGEI r6,$LaR6_Pos
134+#endif
135 RSUBI r6,r6,0 # Make r6 positive
136 $LaR6_Pos:
137 ADDIK r3,r0,0 # Clear mod
138 ADDIK r30,r0,0 # clear div
139- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
140+#ifdef __arch64__
141+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
142 # the first bit search.
143+#else
144+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
145+ # the first bit search.
146+#endif
147 ADDIK r29,r0,32 # Initialize the loop count
148 # First part try to find the first '1' in the r5
149 $LaDIV1:
150 ADD r5,r5,r5 # left shift logical r5
151- BGEID r5,$LaDIV1 #
152+#ifdef __arch64__
153+ BEAGEID r5,$LaDIV1 #
154+#else
155+ BGEID r5,$LaDIV1 #
156+#endif
157 ADDIK r29,r29,-1
158 $LaDIV2:
159 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
160 ADDC r3,r3,r3 # Move that bit into the Mod register
161 rSUB r31,r6,r3 # Try to subtract (r30 a r6)
162+#ifdef __arch64__
163+ BEALTi r31,$LaMOD_TOO_SMALL
164+#else
165 BLTi r31,$LaMOD_TOO_SMALL
166+#endif
167 OR r3,r0,r31 # Move the r31 to mod since the result was positive
168 ADDIK r30,r30,1
169 $LaMOD_TOO_SMALL:
170 ADDIK r29,r29,-1
171+#ifdef __arch64__
172+ BEAEQi r29,$LaLOOP_END
173+ ADD r30,r30,r30 # Shift in the '1' into div
174+ BREAI $LaDIV2 # Div2
175+$LaLOOP_END:
176+ BEAGEI r28,$LaRETURN_HERE
177+ BREAId $LaRETURN_HERE
178+#else
179 BEQi r29,$LaLOOP_END
180 ADD r30,r30,r30 # Shift in the '1' into div
181 BRI $LaDIV2 # Div2
182 $LaLOOP_END:
183 BGEI r28,$LaRETURN_HERE
184 BRId $LaRETURN_HERE
185+#endif
186 rsubi r3,r3,0 # Negate the result
187 $LaDiv_By_Zero:
188 $LaResult_Is_Zero:
189@@ -108,7 +140,7 @@ $LaRETURN_HERE:
190 lli r29,r1,8
191 lli r30,r1,16
192 lli r31,r1,24
193- addik r1,r1,32
194+ addlik r1,r1,32
195 rtsd r15,8
196 nop
197 #else
198diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
199index 31a73c2..39951be 100644
200--- a/libgcc/config/microblaze/mulsi3.S
201+++ b/libgcc/config/microblaze/mulsi3.S
202@@ -43,7 +43,37 @@
203 .type __mulsi3,@function
204 #ifdef __arch64__
205 .align 3
206-#endif
207+__mulsi3:
208+ .frame r1,0,r15
209+ add r3,r0,r0
210+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero
211+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero
212+ BEAGEId r5,$L_R5_Pos
213+ XOR r4,r5,r6 # Get the sign of the result
214+ RSUBI r5,r5,0 # Make r5 positive
215+$L_R5_Pos:
216+ BEAGEI r6,$L_R6_Pos
217+ RSUBI r6,r6,0 # Make r6 positive
218+$L_R6_Pos:
219+ breai $L1
220+$L2:
221+ add r5,r5,r5
222+$L1:
223+ srl r6,r6
224+ addc r7,r0,r0
225+ beaeqi r7,$L2
226+ beaneid r6,$L2
227+ add r3,r3,r5
228+ bealti r4,$L_NegateResult
229+ rtsd r15,8
230+ nop
231+$L_NegateResult:
232+ rtsd r15,8
233+ rsub r3,r3,r0
234+$L_Result_Is_Zero:
235+ rtsd r15,8
236+ addi r3,r0,0
237+#else
238 __mulsi3:
239 .frame r1,0,r15
240 add r3,r0,r0
241@@ -74,5 +104,6 @@ $L_NegateResult:
242 $L_Result_Is_Zero:
243 rtsd r15,8
244 addi r3,r0,0
245+#endif
246 .end __mulsi3
247 .size __mulsi3, . - __mulsi3
248diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
249index 94adb6a..d4fe285 100644
250--- a/libgcc/config/microblaze/udivsi3.S
251+++ b/libgcc/config/microblaze/udivsi3.S
252@@ -59,52 +59,96 @@ __udivsi3:
253 SWI r30,r1,4
254 SWI r31,r1,8
255 #endif
256+#ifdef __arch64__
257+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
258+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero
259+#else
260 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
261 BEQID r5,$LaResult_Is_Zero # Result is Zero
262+#endif
263 ADDIK r30,r0,0 # Clear mod
264 ADDIK r29,r0,32 # Initialize the loop count
265
266 # Check if r6 and r5 are equal # if yes, return 1
267 RSUB r18,r5,r6
268+#ifdef __arch64__
269+ BEAEQID r18,$LaRETURN_HERE
270+#else
271 BEQID r18,$LaRETURN_HERE
272+#endif
273 ADDIK r3,r0,1
274
275 # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
276 XOR r18,r5,r6
277- BGEID r18,16
278+#ifdef __arch64__
279+ BEAGEID r18,16
280+#else
281+ BGEID r18,16
282+#endif
283 ADD r3,r0,r0 # We would anyways clear r3
284+#ifdef __arch64__
285+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
286+ BREAI $LCheckr6
287+ RSUB r18,r6,r5 # MICROBLAZEcmp
288+ BEALTI r18,$LaRETURN_HERE
289+#else
290 BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
291 BRI $LCheckr6
292 RSUB r18,r6,r5 # MICROBLAZEcmp
293 BLTI r18,$LaRETURN_HERE
294-
295+#endif
296 # If r6 [bit 31] is set, then return result as 1
297 $LCheckr6:
298- BGTI r6,$LaDIV0
299- BRID $LaRETURN_HERE
300+#ifdef __arch64__
301+ BEAGTI r6,$LaDIV0
302+ BREAID $LaRETURN_HERE
303+#else
304+ BGTI r6,$LaDIV0
305+ BRID $LaRETURN_HERE
306+#endif
307 ADDIK r3,r0,1
308
309 # First part try to find the first '1' in the r5
310 $LaDIV0:
311+#ifdef __arch64__
312+ BEALTI r5,$LaDIV2
313+#else
314 BLTI r5,$LaDIV2
315+#endif
316 $LaDIV1:
317 ADD r5,r5,r5 # left shift logical r5
318+#ifdef __arch64__
319+ BEAGTID r5,$LaDIV1
320+#else
321 BGTID r5,$LaDIV1
322+#endif
323 ADDIK r29,r29,-1
324 $LaDIV2:
325 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
326 ADDC r30,r30,r30 # Move that bit into the Mod register
327 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
328+#ifdef __arch64__
329+ BEALTI r31,$LaMOD_TOO_SMALL
330+#else
331 BLTI r31,$LaMOD_TOO_SMALL
332+#endif
333 OR r30,r0,r31 # Move the r31 to mod since the result was positive
334 ADDIK r3,r3,1
335 $LaMOD_TOO_SMALL:
336 ADDIK r29,r29,-1
337+#ifdef __arch64__
338+ BEAEQi r29,$LaLOOP_END
339+ ADD r3,r3,r3 # Shift in the '1' into div
340+ BREAI $LaDIV2 # Div2
341+$LaLOOP_END:
342+ BREAI $LaRETURN_HERE
343+#else
344 BEQi r29,$LaLOOP_END
345 ADD r3,r3,r3 # Shift in the '1' into div
346 BRI $LaDIV2 # Div2
347 $LaLOOP_END:
348 BRI $LaRETURN_HERE
349+#endif
350 $LaDiv_By_Zero:
351 $LaResult_Is_Zero:
352 OR r3,r0,r0 # set result to 0
353@@ -115,7 +159,7 @@ $LaRETURN_HERE:
354 LLI r29,r1,0
355 LLI r30,r1,8
356 LLI r31,r1,16
357- ADDIK r1,r1,24
358+ ADDLIK r1,r1,24
359 RTSD r15,8
360 NOP
361 #else
362diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
363index 9bf65c3..3bd5d48 100644
364--- a/libgcc/config/microblaze/umodsi3.S
365+++ b/libgcc/config/microblaze/umodsi3.S
366@@ -46,7 +46,7 @@
367 __umodsi3:
368 .frame r1,0,r15
369
370- addik r1,r1,-24
371+ addlik r1,r1,-24
372 sli r29,r1,0
373 sli r30,r1,8
374 sli r31,r1,16
375@@ -59,27 +59,77 @@ __umodsi3:
376 swi r30,r1,4
377 swi r31,r1,8
378 #endif
379+#ifdef __arch64__
380+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
381+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero
382+#else
383 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
384 BEQId r5,$LaResult_Is_Zero # Result is Zero
385+#endif
386 ADDIK r3,r0,0 # Clear div
387 ADDIK r30,r0,0 # clear mod
388 ADDIK r29,r0,32 # Initialize the loop count
389
390 # Check if r6 and r5 are equal # if yes, return 0
391 rsub r18,r5,r6
392- beqi r18,$LaRETURN_HERE
393
394+#ifdef __arch64__
395+ beaeqi r18,$LaRETURN_HERE
396+#else
397+ beqi r18,$LaRETURN_HERE
398+#endif
399 # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
400 xor r18,r5,r6
401+#ifdef __arch64__
402+ beageid r18,16
403+ addik r3,r5,0
404+ bealti r6,$LaRETURN_HERE
405+ breai $LCheckr6
406+ rsub r18,r5,r6 # MICROBLAZEcmp
407+ beagti r18,$LaRETURN_HERE
408+#else
409 bgeid r18,16
410 addik r3,r5,0
411 blti r6,$LaRETURN_HERE
412 bri $LCheckr6
413 rsub r18,r5,r6 # MICROBLAZEcmp
414 bgti r18,$LaRETURN_HERE
415-
416+#endif
417 # If r6 [bit 31] is set, then return result as r5-r6
418 $LCheckr6:
419+#ifdef __arch64__
420+ beagtid r6,$LaDIV0
421+ addik r3,r0,0
422+ addik r18,r0,0x7fffffff
423+ and r5,r5,r18
424+ and r6,r6,r18
425+ breaid $LaRETURN_HERE
426+ rsub r3,r6,r5
427+# First part: try to find the first '1' in the r5
428+$LaDIV0:
429+ BEALTI r5,$LaDIV2
430+$LaDIV1:
431+ ADD r5,r5,r5 # left shift logical r5
432+ BEAGEID r5,$LaDIV1 #
433+ ADDIK r29,r29,-1
434+$LaDIV2:
435+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
436+ ADDC r3,r3,r3 # Move that bit into the Mod register
437+ rSUB r31,r6,r3 # Try to subtract (r3 a r6)
438+ BEALTi r31,$LaMOD_TOO_SMALL
439+ OR r3,r0,r31 # Move the r31 to mod since the result was positive
440+ ADDIK r30,r30,1
441+$LaMOD_TOO_SMALL:
442+ ADDIK r29,r29,-1
443+ BEAEQi r29,$LaLOOP_END
444+ ADD r30,r30,r30 # Shift in the '1' into div
445+ BREAI $LaDIV2 # Div2
446+$LaLOOP_END:
447+ BREAI $LaRETURN_HERE
448+$LaDiv_By_Zero:
449+$LaResult_Is_Zero:
450+ or r3,r0,r0 # set result to 0
451+#else
452 bgtid r6,$LaDIV0
453 addik r3,r0,0
454 addik r18,r0,0x7fffffff
455@@ -111,7 +161,7 @@ $LaLOOP_END:
456 $LaDiv_By_Zero:
457 $LaResult_Is_Zero:
458 or r3,r0,r0 # set result to 0
459-
460+#endif
461 #ifdef __arch64__
462 $LaRETURN_HERE:
463 # Restore values of CSRs and that of r3 and the divisor and the dividend
464--
4652.7.4
466
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 00000000..76f3e17c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
1From d8b1af5c7ed5bd47d2644e20006b84f67701b856 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 18 Apr 2019 16:00:37 +0530
4Subject: [PATCH 61/61] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr
5 17 14:11:00 2019 +0530
6
7 [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
8 By default MB-64 is generatting barrel-shift instructions. It has been
9 removed from default. Barrel-shift instructions will be generated only if
10 barrel-shifter is enabled. Similarly to double instructions as well.
11
12 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
13---
14 gcc/config/microblaze/microblaze.c | 2 +-
15 gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
16 2 files changed, 252 insertions(+), 19 deletions(-)
17
18diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
19index 33d183e..c321b03 100644
20--- a/gcc/config/microblaze/microblaze.c
21+++ b/gcc/config/microblaze/microblaze.c
22@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[])
23 emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
24
25 if (TARGET_MB_64) {
26- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
27+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
28 emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
29 }
30 else {
31diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
32index 8bd175f..0d9bf8d 100644
33--- a/gcc/config/microblaze/microblaze.md
34+++ b/gcc/config/microblaze/microblaze.md
35@@ -545,7 +545,7 @@
36 [(set (match_operand:DF 0 "register_operand" "=d")
37 (plus:DF (match_operand:DF 1 "register_operand" "d")
38 (match_operand:DF 2 "register_operand" "d")))]
39- "TARGET_MB_64"
40+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
41 "dadd\t%0,%1,%2"
42 [(set_attr "type" "fadd")
43 (set_attr "mode" "DF")
44@@ -555,7 +555,7 @@
45 [(set (match_operand:DF 0 "register_operand" "=d")
46 (minus:DF (match_operand:DF 1 "register_operand" "d")
47 (match_operand:DF 2 "register_operand" "d")))]
48- "TARGET_MB_64"
49+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
50 "drsub\t%0,%2,%1"
51 [(set_attr "type" "frsub")
52 (set_attr "mode" "DF")
53@@ -565,7 +565,7 @@
54 [(set (match_operand:DF 0 "register_operand" "=d")
55 (mult:DF (match_operand:DF 1 "register_operand" "d")
56 (match_operand:DF 2 "register_operand" "d")))]
57- "TARGET_MB_64"
58+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
59 "dmul\t%0,%1,%2"
60 [(set_attr "type" "fmul")
61 (set_attr "mode" "DF")
62@@ -575,7 +575,7 @@
63 [(set (match_operand:DF 0 "register_operand" "=d")
64 (div:DF (match_operand:DF 1 "register_operand" "d")
65 (match_operand:DF 2 "register_operand" "d")))]
66- "TARGET_MB_64"
67+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
68 "ddiv\t%0,%2,%1"
69 [(set_attr "type" "fdiv")
70 (set_attr "mode" "DF")
71@@ -585,7 +585,7 @@
72 (define_insn "sqrtdf2"
73 [(set (match_operand:DF 0 "register_operand" "=d")
74 (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
75- "TARGET_MB_64"
76+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
77 "dsqrt\t%0,%1"
78 [(set_attr "type" "fsqrt")
79 (set_attr "mode" "DF")
80@@ -594,7 +594,7 @@
81 (define_insn "floatdidf2"
82 [(set (match_operand:DF 0 "register_operand" "=d")
83 (float:DF (match_operand:DI 1 "register_operand" "d")))]
84- "TARGET_MB_64"
85+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
86 "dbl\t%0,%1"
87 [(set_attr "type" "fcvt")
88 (set_attr "mode" "DF")
89@@ -603,7 +603,7 @@
90 (define_insn "fix_truncdfdi2"
91 [(set (match_operand:DI 0 "register_operand" "=d")
92 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
93- "TARGET_MB_64"
94+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
95 "dlong\t%0,%1"
96 [(set_attr "type" "fcvt")
97 (set_attr "mode" "DI")
98@@ -1299,6 +1299,34 @@
99 (set_attr "mode" "DI")
100 (set_attr "length" "4")])
101
102+(define_insn "*movdi_internal2_bshift"
103+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
104+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
105+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
106+ {
107+ switch (which_alternative)
108+ {
109+ case 0:
110+ return "addlk\t%0,%1,r0";
111+ case 1:
112+ case 2:
113+ if (GET_CODE (operands[1]) == CONST_INT &&
114+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
115+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
116+ else
117+ return "addlik\t%0,r0,%1";
118+ case 3:
119+ case 4:
120+ return "ll%i1\t%0,%1";
121+ case 5:
122+ case 6:
123+ return "sl%i0\t%z1,%0";
124+ }
125+ }
126+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
127+ (set_attr "mode" "DI")
128+ (set_attr "length" "4,4,12,4,8,4,8")])
129+
130 (define_insn "*movdi_internal2"
131 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
132 (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
133@@ -1312,7 +1340,15 @@
134 case 2:
135 if (GET_CODE (operands[1]) == CONST_INT &&
136 (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
137- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
138+ {
139+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
140+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
141+ output_asm_insn ("addlik\t%2,r0,GEN_INT(32)", operands);
142+ output_asm_insn ("addlik\t%2,%2,-1", operands);
143+ output_asm_insn ("beaneid\t%2,.-8", operands);
144+ output_asm_insn ("addlk\t%0,%0,%0", operands);
145+ return "addlik\t%0,%0,%j1 #li => la";
146+ }
147 else
148 return "addlik\t%0,r0,%1";
149 case 3:
150@@ -1386,7 +1422,7 @@
151 (define_insn "movdi_long_int"
152 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
153 (match_operand:DI 1 "general_operand" "i"))]
154- "TARGET_MB_64"
155+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
156 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
157 [(set_attr "type" "no_delay_arith")
158 (set_attr "mode" "DI")
159@@ -1653,6 +1689,33 @@
160 ;; movdf_internal
161 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
162 ;;
163+(define_insn "*movdf_internal_64_bshift"
164+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
165+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
166+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
167+ {
168+ switch (which_alternative)
169+ {
170+ case 0:
171+ return "addlk\t%0,%1,r0";
172+ case 1:
173+ return "addlk\t%0,r0,r0";
174+ case 2:
175+ case 4:
176+ return "ll%i1\t%0,%1";
177+ case 3:
178+ {
179+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
180+ }
181+ case 5:
182+ return "sl%i0\t%1,%0";
183+ }
184+ gcc_unreachable ();
185+ }
186+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
187+ (set_attr "mode" "DF")
188+ (set_attr "length" "4,4,4,16,4,4")])
189+
190 (define_insn "*movdf_internal_64"
191 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
192 (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
193@@ -1669,7 +1732,13 @@
194 return "ll%i1\t%0,%1";
195 case 3:
196 {
197- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
198+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
199+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
200+ output_asm_insn ("addlik\t%2,r0,GEN_INT(32)", operands);
201+ output_asm_insn ("addlik\t%2,%2,-1", operands);
202+ output_asm_insn ("beaneid\t%2,.-8", operands);
203+ output_asm_insn ("addlk\t%0,%0,%0", operands);
204+ return "addlik\t%0,%0,%j1 #li => la";
205 }
206 case 5:
207 return "sl%i0\t%1,%0";
208@@ -1789,11 +1858,21 @@
209 "TARGET_MB_64"
210 {
211 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
212-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
213+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
214 {
215 emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
216 DONE;
217 }
218+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
219+ {
220+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
221+ DONE;
222+ }
223+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
224+ {
225+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
226+ DONE;
227+ }
228 else
229 FAIL;
230 }
231@@ -1803,7 +1882,7 @@ else
232 [(set (match_operand:DI 0 "register_operand" "=d,d")
233 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
234 (match_operand:DI 2 "arith_operand" "I,d")))]
235- "TARGET_MB_64"
236+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
237 "@
238 bsllli\t%0,%1,%2
239 bslll\t%0,%1,%2"
240@@ -1811,6 +1890,51 @@ else
241 (set_attr "mode" "DI,DI")
242 (set_attr "length" "4,4")]
243 )
244+
245+(define_insn "ashldi3_const"
246+ [(set (match_operand:DI 0 "register_operand" "=&d")
247+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
248+ (match_operand:DI 2 "immediate_operand" "I")))]
249+ "TARGET_MB_64"
250+ {
251+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
252+
253+ output_asm_insn ("orli\t%3,r0,%2", operands);
254+ if (REGNO (operands[0]) != REGNO (operands[1]))
255+ output_asm_insn ("addlk\t%0,%1,r0", operands);
256+
257+ output_asm_insn ("addlik\t%3,%3,-1", operands);
258+ output_asm_insn ("beaneid\t%3,.-8", operands);
259+ return "addlk\t%0,%0,%0";
260+ }
261+ [(set_attr "type" "multi")
262+ (set_attr "mode" "DI")
263+ (set_attr "length" "20")]
264+)
265+
266+(define_insn "ashldi3_reg"
267+ [(set (match_operand:DI 0 "register_operand" "=&d")
268+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
269+ (match_operand:DI 2 "register_operand" "d")))]
270+ "TARGET_MB_64"
271+ {
272+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
273+ output_asm_insn ("andli\t%3,%2,31", operands);
274+ if (REGNO (operands[0]) != REGNO (operands[1]))
275+ output_asm_insn ("addlk\t%0,r0,%1", operands);
276+ /* Exit the loop if zero shift. */
277+ output_asm_insn ("beaeqid\t%3,.+24", operands);
278+ /* Emit the loop. */
279+ output_asm_insn ("addlk\t%0,%0,r0", operands);
280+ output_asm_insn ("addlik\t%3,%3,-1", operands);
281+ output_asm_insn ("beaneid\t%3,.-8", operands);
282+ return "addlk\t%0,%0,%0";
283+ }
284+ [(set_attr "type" "multi")
285+ (set_attr "mode" "DI")
286+ (set_attr "length" "28")]
287+)
288+
289 ;; The following patterns apply when there is no barrel shifter present
290
291 (define_insn "*ashlsi3_with_mul_delay"
292@@ -1944,11 +2068,21 @@ else
293 "TARGET_MB_64"
294 {
295 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
296-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
297+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
298 {
299 emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
300 DONE;
301 }
302+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
303+ {
304+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
305+ DONE;
306+ }
307+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
308+ {
309+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
310+ DONE;
311+ }
312 else
313 FAIL;
314 }
315@@ -1958,7 +2092,7 @@ else
316 [(set (match_operand:DI 0 "register_operand" "=d,d")
317 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
318 (match_operand:DI 2 "arith_operand" "I,d")))]
319- "TARGET_MB_64"
320+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
321 "@
322 bslrai\t%0,%1,%2
323 bslra\t%0,%1,%2"
324@@ -1966,6 +2100,51 @@ else
325 (set_attr "mode" "DI,DI")
326 (set_attr "length" "4,4")]
327 )
328+
329+(define_insn "ashrdi3_const"
330+ [(set (match_operand:DI 0 "register_operand" "=&d")
331+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
332+ (match_operand:DI 2 "immediate_operand" "I")))]
333+ "TARGET_MB_64"
334+ {
335+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
336+
337+ output_asm_insn ("orli\t%3,r0,%2", operands);
338+ if (REGNO (operands[0]) != REGNO (operands[1]))
339+ output_asm_insn ("addlk\t%0,%1,r0", operands);
340+
341+ output_asm_insn ("addlik\t%3,%3,-1", operands);
342+ output_asm_insn ("beaneid\t%3,.-8", operands);
343+ return "srla\t%0,%0";
344+ }
345+ [(set_attr "type" "arith")
346+ (set_attr "mode" "DI")
347+ (set_attr "length" "20")]
348+)
349+
350+(define_insn "ashrdi3_reg"
351+ [(set (match_operand:DI 0 "register_operand" "=&d")
352+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
353+ (match_operand:DI 2 "register_operand" "d")))]
354+ "TARGET_MB_64"
355+ {
356+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
357+ output_asm_insn ("andli\t%3,%2,31", operands);
358+ if (REGNO (operands[0]) != REGNO (operands[1]))
359+ output_asm_insn ("addlk\t%0,r0,%1", operands);
360+ /* Exit the loop if zero shift. */
361+ output_asm_insn ("beaeqid\t%3,.+24", operands);
362+ /* Emit the loop. */
363+ output_asm_insn ("addlk\t%0,%0,r0", operands);
364+ output_asm_insn ("addlik\t%3,%3,-1", operands);
365+ output_asm_insn ("beaneid\t%3,.-8", operands);
366+ return "srla\t%0,%0";
367+ }
368+ [(set_attr "type" "multi")
369+ (set_attr "mode" "DI")
370+ (set_attr "length" "28")]
371+)
372+
373 (define_expand "ashrsi3"
374 [(set (match_operand:SI 0 "register_operand" "=&d")
375 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
376@@ -2083,11 +2262,21 @@ else
377 "TARGET_MB_64"
378 {
379 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
380-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
381+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
382 {
383 emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
384 DONE;
385 }
386+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
387+ {
388+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
389+ DONE;
390+ }
391+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
392+ {
393+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
394+ DONE;
395+ }
396 else
397 FAIL;
398 }
399@@ -2097,7 +2286,7 @@ else
400 [(set (match_operand:DI 0 "register_operand" "=d,d")
401 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
402 (match_operand:DI 2 "arith_operand" "I,d")))]
403- "TARGET_MB_64"
404+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
405 "@
406 bslrli\t%0,%1,%2
407 bslrl\t%0,%1,%2"
408@@ -2106,6 +2295,50 @@ else
409 (set_attr "length" "4,4")]
410 )
411
412+(define_insn "lshrdi3_const"
413+ [(set (match_operand:DI 0 "register_operand" "=&d")
414+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
415+ (match_operand:DI 2 "immediate_operand" "I")))]
416+ "TARGET_MB_64"
417+ {
418+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
419+
420+ output_asm_insn ("orli\t%3,r0,%2", operands);
421+ if (REGNO (operands[0]) != REGNO (operands[1]))
422+ output_asm_insn ("addlk\t%0,%1,r0", operands);
423+
424+ output_asm_insn ("addlik\t%3,%3,-1", operands);
425+ output_asm_insn ("beaneid\t%3,.-8", operands);
426+ return "srll\t%0,%0";
427+ }
428+ [(set_attr "type" "multi")
429+ (set_attr "mode" "DI")
430+ (set_attr "length" "20")]
431+)
432+
433+(define_insn "lshrdi3_reg"
434+ [(set (match_operand:DI 0 "register_operand" "=&d")
435+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
436+ (match_operand:DI 2 "register_operand" "d")))]
437+ "TARGET_MB_64"
438+ {
439+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
440+ output_asm_insn ("andli\t%3,%2,31", operands);
441+ if (REGNO (operands[0]) != REGNO (operands[1]))
442+ output_asm_insn ("addlk\t%0,r0,%1", operands);
443+ /* Exit the loop if zero shift. */
444+ output_asm_insn ("beaeqid\t%3,.+24", operands);
445+ /* Emit the loop. */
446+ output_asm_insn ("addlk\t%0,%0,r0", operands);
447+ output_asm_insn ("addlik\t%3,%3,-1", operands);
448+ output_asm_insn ("beaneid\t%3,.-8", operands);
449+ return "srll\t%0,%0";
450+ }
451+ [(set_attr "type" "multi")
452+ (set_attr "mode" "SI")
453+ (set_attr "length" "28")]
454+)
455+
456 (define_expand "lshrsi3"
457 [(set (match_operand:SI 0 "register_operand" "=&d")
458 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
459@@ -2233,7 +2466,7 @@ else
460 (eq:DI
461 (match_operand:DI 1 "register_operand" "d")
462 (match_operand:DI 2 "register_operand" "d")))]
463- "TARGET_MB_64"
464+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
465 "pcmpleq\t%0,%1,%2"
466 [(set_attr "type" "arith")
467 (set_attr "mode" "DI")
468@@ -2245,7 +2478,7 @@ else
469 (ne:DI
470 (match_operand:DI 1 "register_operand" "d")
471 (match_operand:DI 2 "register_operand" "d")))]
472- "TARGET_MB_64"
473+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
474 "pcmplne\t%0,%1,%2"
475 [(set_attr "type" "arith")
476 (set_attr "mode" "DI")
477--
4782.7.4
479
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
index 9a404a01..a0b533ef 100644
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
@@ -58,4 +58,8 @@ file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
58 file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \ 58 file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \
59 file://0056-fix-the-lto-wrapper-issue-on-windows.patch \ 59 file://0056-fix-the-lto-wrapper-issue-on-windows.patch \
60 file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ 60 file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
61 file://0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
62 file://0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \
63 file://0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
64 file://0061-Author-Nagaraju-nmekala-xilinx.com.patch \
61" 65"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-26 06:50:26 +0000