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authorNathan Rossi <nathan@nathanrossi.com>2017-12-13 16:58:34 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-01-12 15:47:59 -0800
commit7935ef724cd7359ed97e6ae3d90ebc8f07dd7e1f (patch)
tree7c6faff836ccec34825a97fa7b7c49936e2bc4e2 /meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch
parentfb15f2e401ed07f774ea89e0c91ecd927bf09235 (diff)
downloadmeta-xilinx-rocko.tar.gz
gcc-source: Add all Xilinx MicroBlaze GCC 7.2 patchesrocko
Add all the Xilinx patches for MicroBlaze, this includes a number of bug fixes, testsuite fixes, feature improvements and additional feature support. Important changes: * v10.0 - CPU support * v10.0 - Bit-field instruction support * v10.0 - 8-stage pipeline aka 'frequency' optimized * Size optimized implementations for shift instructions Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch')
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch76
1 files changed, 0 insertions, 76 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch
deleted file mode 100644
index 9336291b..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch
+++ /dev/null
@@ -1,76 +0,0 @@
1From 6c7a10a9e077d0221cc9a6c5f5a6365815c1dca4 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 12 Jun 2017 00:28:42 +1000
4Subject: [PATCH 3/4] microblaze/sync.md: Correct behaviour and define
5 side-effects
6
7This change corrects the behaviour with regards to the bool output.
8Previously the definition would set the bool operand to true (non-zero)
9on failure, specifically at the 'cmp' against the expected operand which
10would be set non-zero when the memory != expected value. Instead of
11using the bool operand as the compare result use the clobbered %8
12operand for temporary comparison result and set the bool operand at the
13end of the definition to true (in this case the immediate value of 1).
14Also to ensure that the bool operand is 0 in all other cases the first
15instruction which is intended as a clear of the carry bit is reused to
16set the bool operand to 0 at the same time as clearing the carry bit.
17And finally the jump offsets were updated
18
19Additional to the behaviour change this change defines the side-effects
20of the atomic_compare_and_swap. Specifically the side effects where the
21bool and val operands are modified/set based on the value of the memory
22content. This prevents certain optimization behaviour from incorrectly
23optimizing away code. An example of this is the snippet below, where in
24certain cases the comparison is optimized away entirely.
25
26 mem = 2;
27 if (atomic_compare_and_swap(&mem, ...) == 2)
28 ...
29
30Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
31Upstream-Status: Unsubmitted
32---
33 gcc/config/microblaze/sync.md | 14 ++++++++------
34 1 file changed, 8 insertions(+), 6 deletions(-)
35
36diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
37index 8125bd8d63..605a9a969e 100644
38--- a/gcc/config/microblaze/sync.md
39+++ b/gcc/config/microblaze/sync.md
40@@ -18,9 +18,10 @@
41 ;; <http://www.gnu.org/licenses/>.
42
43 (define_insn "atomic_compare_and_swapsi"
44- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
45- (match_operand:SI 1 "register_operand" "=&d") ;; val output
46- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
47+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
48+ (match_operand:SI 2 "nonimmediate_operand" "+Q")) ;; memory
49+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
50+ (match_dup 2))
51 (match_operand:SI 3 "register_operand" "d") ;; expected value
52 (match_operand:SI 4 "register_operand" "d") ;; desired value
53 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
54@@ -29,15 +30,16 @@
55 (clobber (match_scratch:SI 8 "=&d"))]
56 ""
57 {
58- output_asm_insn ("addc \tr0,r0,r0", operands);
59+ output_asm_insn ("add \t%0,r0,r0", operands);
60 output_asm_insn ("lwx \t%1,%y2,r0", operands);
61 output_asm_insn ("addic\t%8,r0,0", operands);
62 output_asm_insn ("bnei \t%8,.-8", operands);
63- output_asm_insn ("cmp \t%0,%1,%3", operands);
64- output_asm_insn ("bnei \t%0,.+16", operands);
65+ output_asm_insn ("cmp \t%8,%1,%3", operands);
66+ output_asm_insn ("bnei \t%8,.+20", operands);
67 output_asm_insn ("swx \t%4,%y2,r0", operands);
68 output_asm_insn ("addic\t%8,r0,0", operands);
69 output_asm_insn ("bnei \t%8,.-28", operands);
70+ output_asm_insn ("addi \t%0,r0,1", operands);
71 return "";
72 }
73 )
74--
752.11.0
76