various: Remove SOC_VARIANT, split versal and versal-net, add machine_features

SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY
configuration.  The defined families are: zynq, zynqmp, versal and versal-net.

Our decision of breaking up versal-net from versal, is based on the SoC CPU
changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a
different SoC family.

In order to capture the individual capabilities that we used to handle via
SOC_VARIANT, we have defined the following features (some may have been
previously defined):
 - mali400 (zynqmp eg and ev)
 - vcu (zynqmp ev)
 - rfsoc (zynqmp dr RF capabiltiies)
 - aie - (versal ai & premium)
 - vdu - (versal ai)

SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by
MACHINE_ARCH.  This is based on the guideline that any recipes that use
MACHINE_FEATURES should be MACHINE_ARCH specific.

Signed-off-by: Mark Hatle <mark.hatle@amd.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb
index 9367fa2c..4783a329 100644
--- a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb
+++ b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb
@@ -49,6 +49,7 @@ SRC_URI:append = " ${@" ".join(["file://%s" % f for f in (d.getVar('EXTRA_OVERLA
 COMPATIBLE_MACHINE:zynq   = ".*"
 COMPATIBLE_MACHINE:zynqmp = ".*"
 COMPATIBLE_MACHINE:versal = ".*"
+COMPATIBLE_MACHINE:versal-net = ".*"
 
 DEPENDS += "python3-dtc-native"