summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--docs/README.dfx.user.dts.md498
-rw-r--r--meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass21
-rw-r--r--meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf6
-rw-r--r--meta-xilinx-core/conf/machine/versal-generic.conf2
-rw-r--r--meta-xilinx-core/conf/machine/versal-hbm-generic.conf6
-rw-r--r--meta-xilinx-core/conf/machine/versal-prime-generic.conf2
-rw-r--r--meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb2
-rw-r--r--meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb4
-rw-r--r--meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend2
-rw-r--r--meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc2
-rw-r--r--meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb32
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc3
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb4
-rw-r--r--meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc2
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb4
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc4
-rw-r--r--meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-xrt/xrt/xrt.inc4
-rw-r--r--meta-xilinx-standalone-experimental/README.sdt.bsp.md46
-rw-r--r--meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass4
-rw-r--r--meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc2
36 files changed, 416 insertions, 266 deletions
diff --git a/docs/README.dfx.user.dts.md b/docs/README.dfx.user.dts.md
index 724c1692..9caf866e 100644
--- a/docs/README.dfx.user.dts.md
+++ b/docs/README.dfx.user.dts.md
@@ -345,58 +345,59 @@ IMAGE_INSTALL:append = " \
345 345
346* ZynqMP 346* ZynqMP
347``` 347```
348yocto-zynqmp-generic:~$ sudo su 348yocto-zynqmp-generic:~$ cd /
349yocto-zynqmp-generic:/home/petalinux# cat /proc/interrupts 349yocto-zynqmp-generic:/$ sudo su
350yocto-zynqmp-generic:/# cat /proc/interrupts
350 CPU0 CPU1 CPU2 CPU3 351 CPU0 CPU1 CPU2 CPU3
351 11: 5820 5482 14979 6981 GICv2 30 Level arch_timer 352 11: 3399 4404 3273 3113 GICv2 30 Level arch_timer
352 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi 353 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi
353 15: 0 0 0 0 GICv2 175 Level arm-pmu 354 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc
354 16: 0 0 0 0 GICv2 176 Level arm-pmu 355 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc
355 17: 0 0 0 0 GICv2 177 Level arm-pmu 356 17: 0 0 0 0 GICv2 88 Level ams-irq
356 18: 0 0 0 0 GICv2 178 Level arm-pmu 357 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon
357 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc 358 19: 0 0 0 0 GICv2 175 Level arm-pmu
358 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc 359 20: 0 0 0 0 GICv2 176 Level arm-pmu
359 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller 360 21: 0 0 0 0 GICv2 177 Level arm-pmu
360 22: 0 0 0 0 GICv2 88 Level ams-irq 361 22: 0 0 0 0 GICv2 178 Level arm-pmu
361 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon 362 23: 379 0 0 0 GICv2 53 Level xuartps
362 24: 366 0 0 0 GICv2 53 Level xuartps 363 26: 0 0 0 0 GICv2 156 Level zynqmp-dma
363 27: 0 0 0 0 GICv2 156 Level zynqmp-dma 364 27: 0 0 0 0 GICv2 157 Level zynqmp-dma
364 28: 0 0 0 0 GICv2 157 Level zynqmp-dma 365 28: 0 0 0 0 GICv2 158 Level zynqmp-dma
365 29: 0 0 0 0 GICv2 158 Level zynqmp-dma 366 29: 0 0 0 0 GICv2 159 Level zynqmp-dma
366 30: 0 0 0 0 GICv2 159 Level zynqmp-dma 367 30: 0 0 0 0 GICv2 160 Level zynqmp-dma
367 31: 0 0 0 0 GICv2 160 Level zynqmp-dma 368 31: 0 0 0 0 GICv2 161 Level zynqmp-dma
368 32: 0 0 0 0 GICv2 161 Level zynqmp-dma 369 32: 0 0 0 0 GICv2 162 Level zynqmp-dma
369 33: 0 0 0 0 GICv2 162 Level zynqmp-dma 370 33: 0 0 0 0 GICv2 163 Level zynqmp-dma
370 34: 0 0 0 0 GICv2 163 Level zynqmp-dma 371 34: 0 0 0 0 GICv2 109 Level zynqmp-dma
371 35: 0 0 0 0 GICv2 109 Level zynqmp-dma 372 35: 0 0 0 0 GICv2 110 Level zynqmp-dma
372 36: 0 0 0 0 GICv2 110 Level zynqmp-dma 373 36: 0 0 0 0 GICv2 111 Level zynqmp-dma
373 37: 0 0 0 0 GICv2 111 Level zynqmp-dma 374 37: 0 0 0 0 GICv2 112 Level zynqmp-dma
374 38: 0 0 0 0 GICv2 112 Level zynqmp-dma 375 38: 0 0 0 0 GICv2 113 Level zynqmp-dma
375 39: 0 0 0 0 GICv2 113 Level zynqmp-dma 376 39: 0 0 0 0 GICv2 114 Level zynqmp-dma
376 40: 0 0 0 0 GICv2 114 Level zynqmp-dma 377 40: 0 0 0 0 GICv2 115 Level zynqmp-dma
377 41: 0 0 0 0 GICv2 115 Level zynqmp-dma 378 41: 0 0 0 0 GICv2 116 Level zynqmp-dma
378 42: 0 0 0 0 GICv2 116 Level zynqmp-dma 379 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller
379 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller 380 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi
380 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi 381 44: 77 0 0 0 GICv2 95 Level eth0, eth0
381 45: 325 0 0 0 GICv2 95 Level eth0, eth0 382 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon
382 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon 383 46: 2365 0 0 0 GICv2 49 Level cdns-i2c
383 47: 2798 0 0 0 GICv2 49 Level cdns-i2c 384 47: 326 0 0 0 GICv2 50 Level cdns-i2c
384 48: 326 0 0 0 GICv2 50 Level cdns-i2c 385 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog
385 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog 386 50: 0 0 0 0 GICv2 151 Level fd4a0000.display
386 51: 0 0 0 0 GICv2 151 Level fd4a0000.display 387 51: 551 0 0 0 GICv2 81 Level mmc0
387 52: 551 0 0 0 GICv2 81 Level mmc0 388 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
388 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] 389 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
389 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 390 54: 0 0 0 0 zynq-gpio 22 Edge sw19
390 55: 0 0 0 0 zynq-gpio 22 Edge sw19 391IPI0: 73 69 133 115 Rescheduling interrupts
391IPI0: 51 94 136 48 Rescheduling interrupts 392IPI1: 2590 1426 1711 13134 Function call interrupts
392IPI1: 2295 6271 2952 873 Function call interrupts
393IPI2: 0 0 0 0 CPU stop interrupts 393IPI2: 0 0 0 0 CPU stop interrupts
394IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts 394IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts
395IPI4: 0 0 0 0 Timer broadcast interrupts 395IPI4: 0 0 0 0 Timer broadcast interrupts
396IPI5: 0 0 0 0 IRQ work interrupts 396IPI5: 0 0 0 0 IRQ work interrupts
397IPI6: 0 0 0 0 CPU wake-up interrupts 397IPI6: 0 0 0 0 CPU wake-up interrupts
398Err: 0 398Err: 0
399yocto-zynqmp-generic:/home/petalinux# tree /lib/firmware/ 399yocto-zynqmp-generic:/#
400yocto-zynqmp-generic:/# tree /lib/firmware/
400/lib/firmware/ 401/lib/firmware/
401`-- xilinx 402`-- xilinx
402 `-- zcu111-pl-demo-user-dts 403 `-- zcu111-pl-demo-user-dts
@@ -405,83 +406,127 @@ yocto-zynqmp-generic:/home/petalinux# tree /lib/firmware/
405 `-- zcu111-pl-demo-user-dts.dtbo 406 `-- zcu111-pl-demo-user-dts.dtbo
406 407
4072 directories, 3 files 4082 directories, 3 files
408yocto-zynqmp-generic:/home/petalinux# fpgautil -b /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.bin -o /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.dtbo 409yocto-zynqmp-generic:/#
409[ 370.737539] fpga_manager fpga0: writing zcu111-pl-demo-user-dts.bin to Xilinx ZynqMP FPGA Manager 410yocto-zynqmp-generic:/# fpgautil -b /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.bin -o /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.dtbo
410[ 370.960368] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name 411[ 86.077583] fpga_manager fpga0: writing zcu111-pl-demo-user-dts.bin to Xilinx ZynqMP FPGA Manager
411[ 370.970508] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid 412[ 86.300854] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name
412[ 370.979755] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets 413[ 86.311158] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/pid
413[ 370.989244] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid 414[ 86.320571] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/resets
414[ 370.998947] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0 415[ 86.330230] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/uid
415[ 371.008449] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0 416[ 86.340074] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0
416[ 371.018398] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_0 417[ 86.349574] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0
417[ 371.028420] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0 418[ 86.359510] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_0
418[ 371.038442] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_1 419[ 86.369526] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0
419[ 371.048467] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_2 420[ 86.379544] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_1
420[ 371.058487] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0 421[ 86.389561] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_2
421[ 371.068852] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ddr4_0 422[ 86.399588] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0
422[ 371.096047] gpio gpiochip3: (a0000000.gpio): not an immutable chip, please consider fixing it! 423[ 86.409951] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ddr4_0
423[ 371.096223] gpio gpiochip4: (a0010000.gpio): not an immutable chip, please consider fixing it! 424[ 86.439309] a0030000.serial: ttyUL0 at MMIO 0xa0030000 (irq = 57, base_baud = 0) is a uartlite
424[ 371.115206] a0030000.serial: ttyUL0 at MMIO 0xa0030000 (irq = 58, base_baud = 0) is a uartlite 425[ 86.456365] uartlite a0030000.serial: Runtime PM usage count underflow!
425[ 371.124178] uartlite a0030000.serial: Runtime PM usage count underflow! 426[ 86.466353] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1
426[ 371.133186] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1 427Time taken to load BIN is 402.000000 Milli Seconds
427Time taken to load BIN is 409.000000 Milli Seconds
428BIN FILE loaded through FPGA manager successfully 428BIN FILE loaded through FPGA manager successfully
429yocto-zynqmp-generic:/home/petalinux# 429yocto-zynqmp-generic:/#
430``` 430```
431* Versal (DFx Static) 431* Versal (DFx Static)
432``` 432```
433yocto-vck190-dfx-2023:~$ sudo su 433yocto-vck190-versal:/$ sudo su
434root@yocto-vck190-dfx-2023:~# 434yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.pdi -o /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.dtbo
435root@yocto-vck190-dfx-2023:~# fpgautil -o /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.dtbo 435[ 110.575263] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config
436[ 257.555571] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config 436[ 110.585557] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid
437[ 257.565879] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid 437[ 110.594365] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid
438[ 257.574670] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid 438[ 110.603307] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0
439[ 257.583599] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0 439[ 110.613152] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR1
440[ 257.593434] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR1 440[ 110.623007] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR2
441[ 257.603268] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR2 441[ 110.632849] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_axi_bram_ctrl_0
442[ 257.613100] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_axi_bram_ctrl_0 442[ 110.644516] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp1
443[ 257.624762] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp1 443[ 110.656351] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp2
444[ 257.636589] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp2 444[ 110.668188] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp3
445[ 257.648415] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp3 445[ 110.682762] of-fpga-region fpga:fpga-PR0: FPGA Region probed
446[ 257.663234] of-fpga-region fpga:fpga-PR0: FPGA Region probed 446[ 110.689956] of-fpga-region fpga:fpga-PR1: FPGA Region probed
447[ 257.669135] of-fpga-region fpga:fpga-PR1: FPGA Region probed 447[ 110.695890] of-fpga-region fpga:fpga-PR2: FPGA Region probed
448[ 257.675022] of-fpga-region fpga:fpga-PR2: FPGA Region probed 448Time taken to load BIN is 133.000000 Milli Seconds
449root@yocto-vck190-dfx-2023:~# 449BIN FILE loaded through FPGA manager successfully
450yocto-vck190-versal:/#
450``` 451```
451* Versal (DFx RP) 452* Versal (DFx RP)
452``` 453```
453root@yocto-vck190-dfx-2023:~# fpgautil -b /lib/firmware/xilinx/vck190-dfx-static/rp1/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.pdi -o /lib/firmware/xilinx/vck190-dfx-static/rp1/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.dtbo -f Partial -n PR0 454yocto-vck190-versal:/$ sudo su
454[ 273.511455] fpga_manager fpga0: writing vck190-dfx-rp1rm1-dipsw.pdi to Xilinx Versal FPGA Manager 455yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.pdi -o /lib/firmware/xilinx/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.dtbo -f Partial -n PR0
455[284052.461]Loading PDI from DDR 456[ 154.155127] fpga_manager fpga0: writing vck190-dfx-rp1rm1-dipsw.pdi to Xilinx Versal FPGA Manager
456[284052.566]Monolithic/Master Device 457[173465.709]Loading PDI from DDR
457[284055.847]3.365 ms: PDI initialization time 458[173465.800]Monolithic/Master Device
458[284059.809]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700002 459[173469.235]3.520 ms: PDI initialization time
459[284065.432]---Loading Partition#: 0x0, Id: 0x103 460[173473.045]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700002
460[284069.829] 0.033 ms for Partition#: 0x0, Size: 1312 Bytes 461[173478.669]---Loading Partition#: 0x0, Id: 0x103
461[284074.973]---Loading Partition#: 0x1, Id: 0x105 462[173483.052] 0.032 ms for Partition#: 0x0, Size: 1264 Bytes
462[284079.344] 0.007 ms for Partition#: 0x1, Size: 160 Bytes 463[173488.219]---Loading Partition#: 0x1, Id: 0x203
463[284084.430]---Loading Partition#: 0x2, Id: 0x205 464[173492.599] 0.030 ms for Partition#: 0x1, Size: 672 Bytes
464[284088.844] 0.049 ms for Partition#: 0x2, Size: 960 Bytes 465[173497.682]---Loading Partition#: 0x2, Id: 0x303
465[284093.887]---Loading Partition#: 0x3, Id: 0x203 466[173503.193] 1.159 ms for Partition#: 0x2, Size: 204960 Bytes
466[284098.280] 0.030 ms for Partition#: 0x3, Size: 688 Bytes 467[173507.400]---Loading Partition#: 0x3, Id: 0x403
467[284103.342]---Loading Partition#: 0x4, Id: 0x303 468[173511.805] 0.054 ms for Partition#: 0x3, Size: 8400 Bytes
468[284108.863] 1.156 ms for Partition#: 0x4, Size: 209440 Bytes 469[173516.979]Subsystem PDI Load: Done
469[284113.052]---Loading Partition#: 0x5, Id: 0x305 470[ 154.220425] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/rp1_axi_gpio_0
470[284117.712] 0.296 ms for Partition#: 0x5, Size: 3536 Bytes 471[ 154.239592] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1
471[284122.594]---Loading Partition#: 0x6, Id: 0x403 472Time taken to load BIN is 99.000000 Milli Seconds
472[284126.991] 0.034 ms for Partition#: 0x6, Size: 8096 Bytes
473[284132.136]---Loading Partition#: 0x7, Id: 0x405
474[284136.507] 0.007 ms for Partition#: 0x7, Size: 160 Bytes
475[284141.636]Subsystem PDI Load: Done
476[ 273.615503] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/firmware-name
477[ 273.627382] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/fpga-bridges
478[ 273.636953] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/partial-fpga-config
479[ 273.647241] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/rp1_axi_gpio_0
480[ 273.660826] gpio gpiochip1: (a4010000.gpio): not an immutable chip, please consider fixing it!
481[ 273.670490] input: pl-gpio-keys as /devices/platform/pl-gpio-keys/input/input0
482Time taken to load BIN is 171.000000 Milli Seconds
483BIN FILE loaded through FPGA manager successfully 473BIN FILE loaded through FPGA manager successfully
484root@yocto-vck190-dfx-2023:~# 474yocto-vck190-versal:/#
475```
476* Versal (Segmented Configuration)
477```
478yocto-vck190-versal:/$ sudo su
479yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-full/vck190-dfx-full.pdi -o /lib/firmware/xilinx/vck190-dfx-full/vck190-dfx-full.dtbo
480[ 642.857986] fpga_manager fpga0: writing vck190-dfx-full.pdi to Xilinx Versal FPGA Manager
481[653673.622]Loading PDI from DDR
482[653673.713]Monolithic/Master Device
483[653677.159]3.531 ms: PDI initialization time
484[653680.973]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700001
485[653686.608]---Loading Partition#: 0x0, Id: 0x103
486[653705.058] 14.091 ms for Partition#: 0x0, Size: 22176 Bytes
487[653707.626]---Loading Partition#: 0x1, Id: 0x105
488[653712.243] 0.264 ms for Partition#: 0x1, Size: 4784 Bytes
489[653717.183]---Loading Partition#: 0x2, Id: 0x205
490[653725.148] 3.608 ms for Partition#: 0x2, Size: 64368 Bytes
491[653727.632]---Loading Partition#: 0x3, Id: 0x203
492[653732.018] 0.030 ms for Partition#: 0x3, Size: 672 Bytes
493[653737.107]---Loading Partition#: 0x4, Id: 0x303
494[653768.983] 27.516 ms for Partition#: 0x4, Size: 1115456 Bytes
495[653771.723]---Loading Partition#: 0x5, Id: 0x305
496[653777.150] 1.068 ms for Partition#: 0x5, Size: 69056 Bytes
497[653781.371]---Loading Partition#: 0x6, Id: 0x403
498[653785.892] 0.166 ms for Partition#: 0x6, Size: 242320 Bytes
499[653791.103]---Loading Partition#: 0x7, Id: 0x405
500ERR PldMemCtrlrMap: 0x490E
501ERR PldInitNode: 0xFFFF
502ERR XPm_InitNode: 0xFFFF
503ALERT XPm_ProcessCmd: Error 0x15 while processing command 0xC023E
504ALERT XPm_ProcessCmd: Err Code: 0x15
505[653811.158]CMD: 0x000C023E execute failed, Processed Cdo Length 0x129C
506[653817.390]CMD Payload START, Len:0x00000008
507 0x00000000F20012C0: 0x18700001 0x0000000A 0xF6110000 0x00000002
508 0x00000000F20012CC: 0x00000000 0x00000000 0x80000000 0x00000000
509 0x00000000F20012DC:
510[653834.800]CMD Payload END
511[653837.277]Error loading PL data:
512CFU_ISR: 0x00000000, CFU_STATUS: 0x00002A8C
513PMC ERR1: 0x00000000, PMC ERR2: 0x00000000
514[653848.127]PLM Error Status: 0x223E0015
515[65 851.704]XPlm _IpiDispatehHandl0:: Error:hIPI crmmand faileddfor tommanA ID: 0x1000701
516[653859.465]PLM Error Status: 0x27010015
517[ 643.063905] fpga_region region0: failed to load FPGA image
518[ 643.069420] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/firmware-name
519[ 643.079075] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid
520[ 643.087857] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid
521[ 643.096849] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_bram_ctrl_0
522[ 643.107288] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_dip_sw
523[ 643.117729] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_led
524[ 643.127906] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_pb
525[ 643.137996] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0
526[ 643.178340] 20100000000.serial: ttyUL0 at MMIO 0x20100000000 (irq = 41, base_baud = 0) is a uartlite
527[ 643.189536] uartlite 20100000000.serial: Runtime PM usage count underflow!
528[ 643.198059] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input0
529yocto-vck190-versal:/#
485``` 530```
486--- 531---
487 532
@@ -491,134 +536,133 @@ root@yocto-vck190-dfx-2023:~#
491* Verify PL GPIO DIP switches and Push buttons are registered. 536* Verify PL GPIO DIP switches and Push buttons are registered.
492* Move the DIP Switches ON/OFF and verify the interrupt counts. 537* Move the DIP Switches ON/OFF and verify the interrupt counts.
493``` 538```
494yocto-zynqmp-generic:/home/petalinux# cat /proc/interrupts 539yocto-zynqmp-generic:/# cat /proc/interrupts
495 CPU0 CPU1 CPU2 CPU3 540 CPU0 CPU1 CPU2 CPU3
496 11: 7674 7136 20210 8226 GICv2 30 Level arch_timer 541 11: 4254 6509 4214 4236 GICv2 30 Level arch_timer
497 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi 542 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi
498 15: 0 0 0 0 GICv2 175 Level arm-pmu 543 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc
499 16: 0 0 0 0 GICv2 176 Level arm-pmu 544 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc
500 17: 0 0 0 0 GICv2 177 Level arm-pmu 545 17: 0 0 0 0 GICv2 88 Level ams-irq
501 18: 0 0 0 0 GICv2 178 Level arm-pmu 546 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon
502 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc 547 19: 0 0 0 0 GICv2 175 Level arm-pmu
503 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc 548 20: 0 0 0 0 GICv2 176 Level arm-pmu
504 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller 549 21: 0 0 0 0 GICv2 177 Level arm-pmu
505 22: 0 0 0 0 GICv2 88 Level ams-irq 550 22: 0 0 0 0 GICv2 178 Level arm-pmu
506 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon 551 23: 579 0 0 0 GICv2 53 Level xuartps
507 24: 1143 0 0 0 GICv2 53 Level xuartps 552 26: 0 0 0 0 GICv2 156 Level zynqmp-dma
508 27: 0 0 0 0 GICv2 156 Level zynqmp-dma 553 27: 0 0 0 0 GICv2 157 Level zynqmp-dma
509 28: 0 0 0 0 GICv2 157 Level zynqmp-dma 554 28: 0 0 0 0 GICv2 158 Level zynqmp-dma
510 29: 0 0 0 0 GICv2 158 Level zynqmp-dma 555 29: 0 0 0 0 GICv2 159 Level zynqmp-dma
511 30: 0 0 0 0 GICv2 159 Level zynqmp-dma 556 30: 0 0 0 0 GICv2 160 Level zynqmp-dma
512 31: 0 0 0 0 GICv2 160 Level zynqmp-dma 557 31: 0 0 0 0 GICv2 161 Level zynqmp-dma
513 32: 0 0 0 0 GICv2 161 Level zynqmp-dma 558 32: 0 0 0 0 GICv2 162 Level zynqmp-dma
514 33: 0 0 0 0 GICv2 162 Level zynqmp-dma 559 33: 0 0 0 0 GICv2 163 Level zynqmp-dma
515 34: 0 0 0 0 GICv2 163 Level zynqmp-dma 560 34: 0 0 0 0 GICv2 109 Level zynqmp-dma
516 35: 0 0 0 0 GICv2 109 Level zynqmp-dma 561 35: 0 0 0 0 GICv2 110 Level zynqmp-dma
517 36: 0 0 0 0 GICv2 110 Level zynqmp-dma 562 36: 0 0 0 0 GICv2 111 Level zynqmp-dma
518 37: 0 0 0 0 GICv2 111 Level zynqmp-dma 563 37: 0 0 0 0 GICv2 112 Level zynqmp-dma
519 38: 0 0 0 0 GICv2 112 Level zynqmp-dma 564 38: 0 0 0 0 GICv2 113 Level zynqmp-dma
520 39: 0 0 0 0 GICv2 113 Level zynqmp-dma 565 39: 0 0 0 0 GICv2 114 Level zynqmp-dma
521 40: 0 0 0 0 GICv2 114 Level zynqmp-dma 566 40: 0 0 0 0 GICv2 115 Level zynqmp-dma
522 41: 0 0 0 0 GICv2 115 Level zynqmp-dma 567 41: 0 0 0 0 GICv2 116 Level zynqmp-dma
523 42: 0 0 0 0 GICv2 116 Level zynqmp-dma 568 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller
524 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller 569 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi
525 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi 570 44: 146 0 0 0 GICv2 95 Level eth0, eth0
526 45: 485 0 0 0 GICv2 95 Level eth0, eth0 571 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon
527 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon 572 46: 2365 0 0 0 GICv2 49 Level cdns-i2c
528 47: 2798 0 0 0 GICv2 49 Level cdns-i2c 573 47: 326 0 0 0 GICv2 50 Level cdns-i2c
529 48: 326 0 0 0 GICv2 50 Level cdns-i2c 574 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog
530 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog 575 50: 0 0 0 0 GICv2 151 Level fd4a0000.display
531 51: 0 0 0 0 GICv2 151 Level fd4a0000.display 576 51: 551 0 0 0 GICv2 81 Level mmc0
532 52: 551 0 0 0 GICv2 81 Level mmc0 577 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
533 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] 578 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
534 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 579 54: 0 0 0 0 zynq-gpio 22 Edge sw19
535 55: 0 0 0 0 zynq-gpio 22 Edge sw19 580 58: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N
536 59: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N 581 59: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E
537 60: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E 582 60: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S
538 61: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S 583 61: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W
539 62: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W 584 62: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C
540 63: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C 585 63: 0 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7
541 64: 0 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 586 64: 0 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6
542 65: 0 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 587 65: 0 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5
543 66: 0 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 588 66: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4
544 67: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 589 67: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3
545 68: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 590 68: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2
546 69: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 591 69: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1
547 70: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 592 70: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0
548 71: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 593IPI0: 77 79 141 123 Rescheduling interrupts
549IPI0: 64 106 160 56 Rescheduling interrupts 594IPI1: 2621 1536 1782 13236 Function call interrupts
550IPI1: 2712 6721 3259 998 Function call interrupts
551IPI2: 0 0 0 0 CPU stop interrupts 595IPI2: 0 0 0 0 CPU stop interrupts
552IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts 596IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts
553IPI4: 0 0 0 0 Timer broadcast interrupts 597IPI4: 0 0 0 0 Timer broadcast interrupts
554IPI5: 0 0 0 0 IRQ work interrupts 598IPI5: 0 0 0 0 IRQ work interrupts
555IPI6: 0 0 0 0 CPU wake-up interrupts 599IPI6: 0 0 0 0 CPU wake-up interrupts
556Err: 0 600Err: 0
557yocto-zcu111-zynqmp:/home/petalinux# 601yocto-zynqmp-generic:/#
558yocto-zcu111-zynqmp:/home/petalinux# cat /proc/interrupts 602yocto-zynqmp-generic:/#
603yocto-zynqmp-generic:/# cat /proc/interrupts
559 CPU0 CPU1 CPU2 CPU3 604 CPU0 CPU1 CPU2 CPU3
560 11: 8530 7717 22106 8626 GICv2 30 Level arch_timer 605 11: 4972 7894 4568 4673 GICv2 30 Level arch_timer
561 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi 606 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi
562 15: 0 0 0 0 GICv2 175 Level arm-pmu 607 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc
563 16: 0 0 0 0 GICv2 176 Level arm-pmu 608 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc
564 17: 0 0 0 0 GICv2 177 Level arm-pmu 609 17: 0 0 0 0 GICv2 88 Level ams-irq
565 18: 0 0 0 0 GICv2 178 Level arm-pmu 610 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon
566 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc 611 19: 0 0 0 0 GICv2 175 Level arm-pmu
567 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc 612 20: 0 0 0 0 GICv2 176 Level arm-pmu
568 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller 613 21: 0 0 0 0 GICv2 177 Level arm-pmu
569 22: 0 0 0 0 GICv2 88 Level ams-irq 614 22: 0 0 0 0 GICv2 178 Level arm-pmu
570 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon 615 23: 685 0 0 0 GICv2 53 Level xuartps
571 24: 1234 0 0 0 GICv2 53 Level xuartps 616 26: 0 0 0 0 GICv2 156 Level zynqmp-dma
572 27: 0 0 0 0 GICv2 156 Level zynqmp-dma 617 27: 0 0 0 0 GICv2 157 Level zynqmp-dma
573 28: 0 0 0 0 GICv2 157 Level zynqmp-dma 618 28: 0 0 0 0 GICv2 158 Level zynqmp-dma
574 29: 0 0 0 0 GICv2 158 Level zynqmp-dma 619 29: 0 0 0 0 GICv2 159 Level zynqmp-dma
575 30: 0 0 0 0 GICv2 159 Level zynqmp-dma 620 30: 0 0 0 0 GICv2 160 Level zynqmp-dma
576 31: 0 0 0 0 GICv2 160 Level zynqmp-dma 621 31: 0 0 0 0 GICv2 161 Level zynqmp-dma
577 32: 0 0 0 0 GICv2 161 Level zynqmp-dma 622 32: 0 0 0 0 GICv2 162 Level zynqmp-dma
578 33: 0 0 0 0 GICv2 162 Level zynqmp-dma 623 33: 0 0 0 0 GICv2 163 Level zynqmp-dma
579 34: 0 0 0 0 GICv2 163 Level zynqmp-dma 624 34: 0 0 0 0 GICv2 109 Level zynqmp-dma
580 35: 0 0 0 0 GICv2 109 Level zynqmp-dma 625 35: 0 0 0 0 GICv2 110 Level zynqmp-dma
581 36: 0 0 0 0 GICv2 110 Level zynqmp-dma 626 36: 0 0 0 0 GICv2 111 Level zynqmp-dma
582 37: 0 0 0 0 GICv2 111 Level zynqmp-dma 627 37: 0 0 0 0 GICv2 112 Level zynqmp-dma
583 38: 0 0 0 0 GICv2 112 Level zynqmp-dma 628 38: 0 0 0 0 GICv2 113 Level zynqmp-dma
584 39: 0 0 0 0 GICv2 113 Level zynqmp-dma 629 39: 0 0 0 0 GICv2 114 Level zynqmp-dma
585 40: 0 0 0 0 GICv2 114 Level zynqmp-dma 630 40: 0 0 0 0 GICv2 115 Level zynqmp-dma
586 41: 0 0 0 0 GICv2 115 Level zynqmp-dma 631 41: 0 0 0 0 GICv2 116 Level zynqmp-dma
587 42: 0 0 0 0 GICv2 116 Level zynqmp-dma 632 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller
588 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller 633 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi
589 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi 634 44: 265 0 0 0 GICv2 95 Level eth0, eth0
590 45: 527 0 0 0 GICv2 95 Level eth0, eth0 635 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon
591 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon 636 46: 2365 0 0 0 GICv2 49 Level cdns-i2c
592 47: 2798 0 0 0 GICv2 49 Level cdns-i2c 637 47: 326 0 0 0 GICv2 50 Level cdns-i2c
593 48: 326 0 0 0 GICv2 50 Level cdns-i2c 638 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog
594 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog 639 50: 0 0 0 0 GICv2 151 Level fd4a0000.display
595 51: 0 0 0 0 GICv2 151 Level fd4a0000.display 640 51: 551 0 0 0 GICv2 81 Level mmc0
596 52: 551 0 0 0 GICv2 81 Level mmc0 641 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
597 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] 642 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
598 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 643 54: 0 0 0 0 zynq-gpio 22 Edge sw19
599 55: 0 0 0 0 zynq-gpio 22 Edge sw19 644 58: 12 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N
600 59: 2 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N 645 59: 8 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E
601 60: 4 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E 646 60: 8 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S
602 61: 6 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S 647 61: 8 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W
603 62: 4 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W 648 62: 10 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C
604 63: 2 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C 649 63: 2 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7
605 64: 20 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 650 64: 4 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6
606 65: 20 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 651 65: 2 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5
607 66: 2 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 652 66: 2 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4
608 67: 8 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 653 67: 2 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3
609 68: 4 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 654 68: 2 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2
610 69: 2 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 655 69: 2 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1
611 70: 2 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 656 70: 4 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0
612 71: 2 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 657IPI0: 77 79 142 123 Rescheduling interrupts
613IPI0: 64 107 160 56 Rescheduling interrupts 658IPI1: 2641 1596 2011 13239 Function call interrupts
614IPI1: 2720 6763 3430 998 Function call interrupts
615IPI2: 0 0 0 0 CPU stop interrupts 659IPI2: 0 0 0 0 CPU stop interrupts
616IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts 660IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts
617IPI4: 0 0 0 0 Timer broadcast interrupts 661IPI4: 0 0 0 0 Timer broadcast interrupts
618IPI5: 0 0 0 0 IRQ work interrupts 662IPI5: 0 0 0 0 IRQ work interrupts
619IPI6: 0 0 0 0 CPU wake-up interrupts 663IPI6: 0 0 0 0 CPU wake-up interrupts
620Err: 0 664Err: 0
621yocto-zynqmp-generic:/home/petalinux# 665yocto-zynqmp-generic:/#
622``` 666```
623--- 667---
624 668
@@ -629,11 +673,11 @@ yocto-zynqmp-generic:/home/petalinux# fpgautil -R
629``` 673```
630* Versal (DFx RP) 674* Versal (DFx RP)
631``` 675```
632root@yocto-vck190-dfx-2023:~# fpgautil -R -n PR0 676yocto-vck190-versal:/# fpgautil -R -n PR0
633``` 677```
634* Versal (DFx Static) 678* Versal (DFx Static)
635``` 679```
636root@yocto-vck190-dfx-2023:~# fpgautil -R -n Full 680yocto-vck190-versal:/# fpgautil -R -n Full
637``` 681```
638--- 682---
639 683
diff --git a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
index 2b699d9d..188d594b 100644
--- a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
+++ b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
@@ -97,12 +97,15 @@ python() {
97 97
98 # Check for valid combination of input files in SRC_URI 98 # Check for valid combination of input files in SRC_URI
99 # Skip recipe if any of the below conditions are not satisfied. 99 # Skip recipe if any of the below conditions are not satisfied.
100 # 1. At least one bit or bin or pdi or dts or dtsi or dtbo should exists. 100 # 1. At least one bit or bin or pdi should exists.
101 # 2. More than one dtbo. 101 # 2. More than one dtbo.
102 # 3. More than one bit or bin or pdi. 102 # 3. More than one bit or bin or pdi.
103 # 4. More than one dts and zero dtsi. 103 # 4. More than one dts and zero dtsi.
104 # 5. More than one dtsi and zero dts. 104 # 5. More than one dtsi and zero dts
105 if dtsi_found or dtbo_found or bit_found or bin_found or pdi_found: 105 # 6. Both bit and bin exists.
106 # 7. Both bit or bin and pdi exits.
107 # 8. Both dts or dtsi and dtbo exists.
108 if bit_found or bin_found or pdi_found:
106 bb.debug(2, "dtsi or dtbo or bitstream or pdi found in SRC_URI") 109 bb.debug(2, "dtsi or dtbo or bitstream or pdi found in SRC_URI")
107 if bit_found and pdi_found : 110 if bit_found and pdi_found :
108 raise bb.parse.SkipRecipe("Both '.bit' and '.pdi' file found in SRC_URI, this is invalid use case.") 111 raise bb.parse.SkipRecipe("Both '.bit' and '.pdi' file found in SRC_URI, this is invalid use case.")
@@ -112,8 +115,11 @@ python() {
112 115
113 if bit_found and bin_found: 116 if bit_found and bin_found:
114 raise bb.parse.SkipRecipe("Both '.bit' and '.bin' file found in SRC_URI, either .bit or .bin file is supported but not both.") 117 raise bb.parse.SkipRecipe("Both '.bit' and '.bin' file found in SRC_URI, either .bit or .bin file is supported but not both.")
118
119 if dtsi_found and dtbo_found:
120 raise bb.parse.SkipRecipe("Both '.dts or dtsi' and '.dtbo' file found in SRC_URI, either .dts/dtsi or .dtbo file is supported but not both.")
115 else: 121 else:
116 raise bb.parse.SkipRecipe("Need one '.dtsi' or '.dtbo' or '.bit' or '.bin' or '.pdi' file added to SRC_URI ") 122 raise bb.parse.SkipRecipe("Need one '.bit' or '.bin' or '.pdi' file added to SRC_URI.")
117 123
118 # Check for valid combination of dtsi and dts files in SRC_URI 124 # Check for valid combination of dtsi and dts files in SRC_URI
119 # Following file combinations are not supported use case. 125 # Following file combinations are not supported use case.
@@ -177,10 +183,11 @@ python devicetree_do_compile:append() {
177 import glob, subprocess, shutil 183 import glob, subprocess, shutil
178 soc_family = d.getVar("SOC_FAMILY") 184 soc_family = d.getVar("SOC_FAMILY")
179 185
180 dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.dtbo'),recursive=True) if os.path.isfile(f)) 186 dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('DTSI_PATH') or '') + '/*.dtbo'),recursive=True) if os.path.isfile(f))
181 bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.bin'),recursive=True) if os.path.isfile(f)) 187 bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIN_PATH') or '') + '/*.bin'),recursive=True) if os.path.isfile(f))
188 bit_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIT_PATH') or '') + '/*.bit'),recursive=True) if os.path.isfile(f))
182 # Skip devicetree do_compile task if input file is dtbo or bin in SRC_URI 189 # Skip devicetree do_compile task if input file is dtbo or bin in SRC_URI
183 if not dtbo_count and not bin_count: 190 if not dtbo_count and not bin_count and bit_count:
184 # Convert .bit to .bin format only if dtsi is input. 191 # Convert .bit to .bin format only if dtsi is input.
185 # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit 192 # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit
186 # or .bin format and corresponding file name. Hence we are not doing .bin 193 # or .bin format and corresponding file name. Hence we are not doing .bin
diff --git a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
index bf5523ed..1028ac04 100644
--- a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
@@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "ai-edge" 7SOC_VARIANT = "ai-edge"
8 8
9# VEK280 board has 12GB memory only but default versal-generic has QB_MEM set to
10# 8G, Hence we need set 12G in QB_MEM.
11QB_MEM = "-m 12G"
12
13QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vek280.dtb"
14
9#### No additional settings should be after the Postamble 15#### No additional settings should be after the Postamble
10#### Postamble 16#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_ai_edge_generic']['versal-ai-edge-generic' != "${MACHINE}"]}" 17PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_ai_edge_generic']['versal-ai-edge-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf
index 2f35ba24..3582944b 100644
--- a/meta-xilinx-core/conf/machine/versal-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-generic.conf
@@ -84,7 +84,7 @@ QB_KERNEL_CMDLINE_APPEND ?= ""
84 84
85QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch" 85QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch"
86QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" 86QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"
87QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb" 87QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"
88 88
89# Four total serial ports defined in this model (according to the dts) 89# Four total serial ports defined in this model (according to the dts)
90# 90#
diff --git a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
index 23fffcb9..3e72da60 100644
--- a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
@@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "hbm" 7SOC_VARIANT = "hbm"
8 8
9# VHK158 has 32GB memory only but default versal-generic has QB_MEM set to 8G,
10# Since versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM
11QB_MEM = "-m 32G"
12
13QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vhk158.dtb"
14
9#### No additional settings should be after the Postamble 15#### No additional settings should be after the Postamble
10#### Postamble 16#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_hbm_generic']['versal-hbm-generic' != "${MACHINE}"]}" 17PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_hbm_generic']['versal-hbm-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/conf/machine/versal-prime-generic.conf b/meta-xilinx-core/conf/machine/versal-prime-generic.conf
index 94e9b05e..206f0e2a 100644
--- a/meta-xilinx-core/conf/machine/versal-prime-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-prime-generic.conf
@@ -6,6 +6,8 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "prime" 7SOC_VARIANT = "prime"
8 8
9QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vmk180.dtb"
10
9#### No additional settings should be after the Postamble 11#### No additional settings should be after the Postamble
10#### Postamble 12#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_prime_generic']['versal-prime-generic' != "${MACHINE}"]}" 13PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_prime_generic']['versal-prime-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
index ca447615..b33d5064 100644
--- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
@@ -1,6 +1,6 @@
1SRCBRANCH ?= "2024" 1SRCBRANCH ?= "2024"
2SRCREV = "e2fdb4fecbebe41b4cd1c0b4fbfa3496bcded485" 2SRCREV = "e2fdb4fecbebe41b4cd1c0b4fbfa3496bcded485"
3BRANCH = "2024" 3BRANCH = "xlnx_rel_v2024.1"
4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4" 4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4"
5PV = "${SRCBRANCH}+git${SRCPV}" 5PV = "${SRCBRANCH}+git${SRCPV}"
6 6
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
index 01df6033..bf779ff5 100644
--- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
@@ -1,6 +1,6 @@
1SRCBRANCH ?= "2024" 1SRCBRANCH ?= "2024"
2SRCREV = "f4a7bc0fca5b14bb8fd185918614bcc78ce93028" 2SRCREV = "7d39410ad2172be9f339c4ce565ed765ddd8c5c8"
3BRANCH = "2024" 3BRANCH = "xlnx_rel_v2024.1"
4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505" 4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505"
5PV = "${SRCBRANCH}+git${SRCPV}" 5PV = "${SRCBRANCH}+git${SRCPV}"
6REPO = "git://github.com/Xilinx/open-amp.git;protocol=https" 6REPO = "git://github.com/Xilinx/open-amp.git;protocol=https"
diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
index 6e31d1f0..b8da828d 100644
--- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
+++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
@@ -1,5 +1,5 @@
1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" 1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https"
2SRCREV = "9e880fa8bad815f01ca8ec4a3e141e5386f012fd" 2SRCREV = "30bed2bbebeae4c190a74a5d6f26f43a62135041"
3 3
4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" 4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:"
5 5
diff --git a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
index f7e18273..1f1d0606 100644
--- a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
+++ b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
@@ -6,7 +6,7 @@ SUMMARY = "Image update is used to update alternate image on compatible firmware
6LICENSE = "MIT" 6LICENSE = "MIT"
7LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSES/MIT;md5=2ac09a7a37dd6ee0ba23ce497d57d09b" 7LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSES/MIT;md5=2ac09a7a37dd6ee0ba23ce497d57d09b"
8 8
9BRANCH = "master" 9BRANCH = "xlnx_rel_v2024.1"
10SRC_URI = "git://github.com/Xilinx/linux-image_update.git;branch=${BRANCH};protocol=https" 10SRC_URI = "git://github.com/Xilinx/linux-image_update.git;branch=${BRANCH};protocol=https"
11SRCREV = "a68308f329578d3585fd335071a9184aa7f46d2e" 11SRCREV = "a68308f329578d3585fd335071a9184aa7f46d2e"
12 12
diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
index 0541a7a3..a59ef469 100644
--- a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
+++ b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
@@ -3,7 +3,7 @@ SECTION = "libs"
3REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https" 3REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https"
4 4
5BRANCH ?= "main-aie" 5BRANCH ?= "main-aie"
6SRCREV ?= "5621d74d5efa99fdddd9eca47de3294804c62c24" 6SRCREV ?= "c41476c833034259eb760d2a2f7c7118a5be727d"
7 7
8LICENSE = "BSD-3-Clause" 8LICENSE = "BSD-3-Clause"
9LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897" 9LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897"
diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
index 2c6c9cd1..cb9d95f9 100644
--- a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
+++ b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
@@ -23,7 +23,7 @@ DEPENDS = "libxaiengine"
23 23
24OECMAKE_SOURCEPATH = "${S}/${XAIEFAL_DIR}" 24OECMAKE_SOURCEPATH = "${S}/${XAIEFAL_DIR}"
25 25
26EXTRA_OECMAKE = "-DWITH_TESTS=OFF " 26EXTRA_OECMAKE = "-DWITH_TESTS=OFF -DFAL_LINUX=ON "
27EXTRA_OECMAKE:append = "${@'-DWITH_EXAMPLES=ON' if d.getVar('WITH_EXAMPLES') == 'y' else '-DWITH_EXAMPLES=OFF'}" 27EXTRA_OECMAKE:append = "${@'-DWITH_EXAMPLES=ON' if d.getVar('WITH_EXAMPLES') == 'y' else '-DWITH_EXAMPLES=OFF'}"
28 28
29FILES:${PN}-demos = " \ 29FILES:${PN}-demos = " \
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb
new file mode 100644
index 00000000..af30a17d
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb
@@ -0,0 +1,32 @@
1DESCRIPTION = "Bootbin version file - text format"
2SUMMARY = "The BIF file for bootbin requires a version file in a text format"
3LICENSE = "MIT"
4LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
5
6COMPATIBLE_MACHINE = "^$"
7
8PACKAGE_ARCH = "${MACHINE_ARCH}"
9
10BOOTBIN_VER_MAIN ?= ""
11BOOTBIN_VER_SUFFIX ?= "${@(d.getVar('XILINX_VER_BUILD') or '')[:8] if d.getVar('XILINX_VER_UPDATE') != 'release' and not d.getVar('XILINX_VER_UPDATE').startswith('update') else ''}"
12BOOTBIN_VER_FILE = "bootbin-version-string.txt"
13
14#BOOTBIN_MANIFEST_FILE ?= "bootbin-version-header.manifest"
15
16inherit deploy image-artifact-names
17
18python do_configure() {
19 if d.getVar("BOOTBIN_VER_SUFFIX"):
20 version = version + "-" + d.getVar("BOOTBIN_VER_SUFFIX")
21 with open(d.expand("${B}/${BOOTBIN_VER_FILE}"), "w") as f:
22 f.write(version)
23}
24
25do_deploy() {
26 install -m 0644 ${B}/${BOOTBIN_VER_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.txt
27 ln -s ${IMAGE_NAME}.txt ${DEPLOYDIR}/${IMAGE_LINK_NAME}.txt
28# install -m 0644 ${B}/${BOOTBIN_MANIFEST_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.manifest
29# ln -s ${IMAGE_NAME}.manifest ${DEPLOYDIR}/${IMAGE_LINK_NAME}.manifest
30}
31
32addtask deploy after do_compile
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
index fff2c7a3..cd6adcef 100644
--- a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
+++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
@@ -4,6 +4,9 @@ BOOTGEN_EXTRA_ARGS += "-dump bh"
4# specify BIF common attribute for FSBL 4# specify BIF common attribute for FSBL
5BIF_COMMON_ATTR ?= "" 5BIF_COMMON_ATTR ?= ""
6 6
7# specify BIF optional attributes
8BIF_OPTIONAL_DATA ?= ""
9
7#specify BIF partition attributes required for BOOT.bin 10#specify BIF partition attributes required for BOOT.bin
8BIF_FSBL_ATTR ??= "base-pdi plmfw psmfw" 11BIF_FSBL_ATTR ??= "base-pdi plmfw psmfw"
9BIF_ATF_ATTR ??= "arm-trusted-firmware" 12BIF_ATF_ATTR ??= "arm-trusted-firmware"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
index 4c8bfa0e..e0e1e506 100644
--- a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
+++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
@@ -125,6 +125,10 @@ python do_configure() {
125 biffd.write("the_ROM_image:\n") 125 biffd.write("the_ROM_image:\n")
126 biffd.write("{\n") 126 biffd.write("{\n")
127 127
128 if d.getVar("BIF_OPTIONAL_DATA"):
129 opt_data = d.getVar("BIF_OPTIONAL_DATA") or ""
130 biffd.write("\toptionaldata { %s }\n" % opt_data)
131
128 arch = d.getVar("SOC_FAMILY") 132 arch = d.getVar("SOC_FAMILY")
129 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split() 133 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split()
130 if bifattr: 134 if bifattr:
diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
index b0acf0ef..28f997f2 100644
--- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
+++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
@@ -8,7 +8,7 @@ REPO ?= "git://github.com/Xilinx/dfx-mgr.git;protocol=https"
8BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 8BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
9SRC_URI = "${REPO};${BRANCHARG}" 9SRC_URI = "${REPO};${BRANCHARG}"
10 10
11BRANCH = "master" 11BRANCH = "xlnx_rel_v2024.1"
12SRCREV = "ec70363a2a878737057995f922a9460d18aafa26" 12SRCREV = "ec70363a2a878737057995f922a9460d18aafa26"
13SOMAJOR = "1" 13SOMAJOR = "1"
14SOMINOR = "0" 14SOMINOR = "0"
diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
index 0cbcaac7..42e67ce6 100644
--- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
+++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
@@ -4,7 +4,7 @@ DESCRIPTION = "Xilinx libdfx Library and headers"
4LICENSE = "MIT & GPL-2.0-or-later" 4LICENSE = "MIT & GPL-2.0-or-later"
5LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7" 5LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7"
6 6
7BRANCH ?= "master" 7BRANCH ?= "xlnx_rel_v2024.1"
8REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" 8REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https"
9BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 9BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
10SRC_URI = "${REPO};${BRANCHARG}" 10SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
index b919b230..b4ac7998 100644
--- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
@@ -2,7 +2,7 @@ UBOOT_VERSION = "v2024.01"
2 2
3UBRANCH = "xlnx_rebase_v2024.01" 3UBRANCH = "xlnx_rebase_v2024.01"
4 4
5SRCREV = "12c2fe646e7e98ba98334c75e082cc10faf0413d" 5SRCREV = "a64b554a4a7e0c540dd4fbb69bcf765a88d7359f"
6 6
7LICENSE = "GPL-2.0-or-later" 7LICENSE = "GPL-2.0-or-later"
8LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" 8LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
index c4fc180e..d10504d3 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
@@ -1,6 +1,6 @@
1 1
2require qemu-devicetrees.inc 2require qemu-devicetrees.inc
3 3
4BRANCH ?= "master" 4BRANCH ?= "xlnx_rel_v2024.1"
5SRCREV ?= "c54a1cfb7076aaf8abdfe50e89245b37cdb1c077" 5SRCREV ?= "b9c88cbfaaa0c8b8be70ea3c74f4cb69fb02a080"
6 6
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
index ffaf3cdf..d48350b2 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
@@ -1,3 +1,3 @@
1XILINX_QEMU_VERSION = "v8.1.0" 1XILINX_QEMU_VERSION = "v8.1.0"
2BRANCH = "master" 2BRANCH = "xlnx_rel_v2024.1"
3SRCREV = "aa05b83770c0cd5a4f7fcbcef7efc806ae2abe9f" 3SRCREV = "2319c870e754148ec3b9d40be0d3dbee959c3251"
diff --git a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
index db99c4d7..82c411a2 100644
--- a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
+++ b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
@@ -13,7 +13,7 @@ PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm"
13FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 13FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
14 14
15REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https"
16BRANCH ?= "xlnx_rel_v2023.2" 16BRANCH ?= "xlnx_rel_v2024.1"
17SRCREV ?= "b3a772aad859cdadc8513b11c3e995546c20e75e" 17SRCREV ?= "b3a772aad859cdadc8513b11c3e995546c20e75e"
18BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 18BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
19 19
diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
index 17039abb..503cee02 100644
--- a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
@@ -9,7 +9,7 @@ PV = "${XLNX_DP_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', Fal
9 9
10S = "${WORKDIR}/git" 10S = "${WORKDIR}/git"
11 11
12BRANCH ?= "master" 12BRANCH ?= "xlnx_rel_v2024.1"
13REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" 13REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https"
14SRCREV ?= "e20942b256e6fb18eaef919c7441f65ad8afcf43" 14SRCREV ?= "e20942b256e6fb18eaef919c7441f65ad8afcf43"
15 15
diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
index 9757ae4b..73a22d30 100644
--- a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
@@ -9,7 +9,7 @@ PV = "${XLNX_HDMI_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', F
9 9
10S = "${WORKDIR}/git" 10S = "${WORKDIR}/git"
11 11
12BRANCH ?= "master" 12BRANCH ?= "xlnx_rel_v2024.1"
13REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https" 13REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https"
14SRCREV = "edd297762e0bac3f4c5b64ef67244968e22020e2" 14SRCREV = "edd297762e0bac3f4c5b64ef67244968e22020e2"
15 15
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
index 8f65469a..3008a572 100644
--- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
@@ -1,7 +1,7 @@
1LINUX_VERSION = "6.6.10" 1LINUX_VERSION = "6.6.10"
2YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" 2YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta"
3KBRANCH="xlnx_rebase_v6.6_LTS" 3KBRANCH="xlnx_rebase_v6.6_LTS"
4SRCREV = "dcac89c7c78a556240e07ac3c6c568dd5be90ef3" 4SRCREV = "73608e3d7f39dc2b44a1d3c135dec85bcb1b67f0"
5SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" 5SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865"
6 6
7KCONF_AUDIT_LEVEL="0" 7KCONF_AUDIT_LEVEL="0"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
index be8f6075..f474595c 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
@@ -11,7 +11,7 @@ S = "${WORKDIR}/git"
11 11
12FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 12FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
13 13
14BRANCH = "master" 14BRANCH = "xlnx_rel_v2024.1"
15REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" 15REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https"
16SRCREV = "91d19a16308a438596138d30d8174e148fc45584" 16SRCREV = "91d19a16308a438596138d30d8174e148fc45584"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
index bff19a9c..14226aa7 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
@@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd"
6XILINX_VCU_VERSION = "1.0.0" 6XILINX_VCU_VERSION = "1.0.0"
7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" 7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
8 8
9BRANCH ?= "master" 9BRANCH ?= "xlnx_rel_v2024.1"
10REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" 10REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https"
11SRCREV = "dc34204543b89997577bd2c9757b3c218e6caccc" 11SRCREV = "dc34204543b89997577bd2c9757b3c218e6caccc"
12 12
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
index 8c3df7db..e3f656b0 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
@@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd"
6XILINX_VCU_VERSION = "1.0.0" 6XILINX_VCU_VERSION = "1.0.0"
7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" 7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
8 8
9BRANCH ?= "master" 9BRANCH ?= "xlnx_rel_v2024.1"
10REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" 10REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https"
11SRCREV = "940f9fa933402de6f959911c236f36add5dd3a40" 11SRCREV = "940f9fa933402de6f959911c236f36add5dd3a40"
12 12
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
index 3ec61a96..1031f892 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
@@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE',
8 8
9S = "${WORKDIR}/git" 9S = "${WORKDIR}/git"
10 10
11BRANCH ?= "master" 11BRANCH ?= "xlnx_rel_v2024.1"
12REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" 12REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https"
13SRCREV = "6ee1998c53817ab0c137b8b99089337d5caba62c" 13SRCREV = "6ee1998c53817ab0c137b8b99089337d5caba62c"
14 14
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
index ccbe77a8..84f9cc2a 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
@@ -11,7 +11,7 @@ PV .= "+git${SRCPV}"
11S = "${WORKDIR}/git" 11S = "${WORKDIR}/git"
12FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 12FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
13 13
14BRANCH ?= "master" 14BRANCH ?= "xlnx_rel_v2024.1"
15REPO ?= "git://github.com/Xilinx/vdu-modules.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/vdu-modules.git;protocol=https"
16SRCREV ?= "25773344ce1e539e7136c5a30cdee98a6cf490a8" 16SRCREV ?= "25773344ce1e539e7136c5a30cdee98a6cf490a8"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
index 5186d4fc..3acbf3ef 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
@@ -11,7 +11,7 @@ inherit autotools features_check
11 11
12REQUIRED_MACHINE_FEATURES = "vdu" 12REQUIRED_MACHINE_FEATURES = "vdu"
13 13
14BRANCH ?= "master" 14BRANCH ?= "xlnx_rel_v2024.1"
15REPO ?= "git://github.com/Xilinx/vdu-ctrl-sw.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/vdu-ctrl-sw.git;protocol=https"
16SRCREV ?= "7af131e0780d52ebc7bd6173bf1b99fec4dc522f" 16SRCREV ?= "7af131e0780d52ebc7bd6173bf1b99fec4dc522f"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
index 91b2a150..5ba604f8 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
@@ -7,7 +7,7 @@ XILINX_VDU_VERSION = "1.0.0"
7PV =. "${XILINX_VDU_VERSION}-xilinx-v" 7PV =. "${XILINX_VDU_VERSION}-xilinx-v"
8PV .= "+git${SRCPV}" 8PV .= "+git${SRCPV}"
9 9
10BRANCH ?= "master" 10BRANCH ?= "xlnx_rel_v2024.1"
11REPO ?= "git://github.com/Xilinx/vdu-omx-il.git;protocol=https" 11REPO ?= "git://github.com/Xilinx/vdu-omx-il.git;protocol=https"
12SRCREV ?= "af9c6e8935799f4dcd579b0164dd05eb039b569d" 12SRCREV ?= "af9c6e8935799f4dcd579b0164dd05eb039b569d"
13 13
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
index 378a23df..86f977b4 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
@@ -13,7 +13,7 @@ inherit autotools features_check
13 13
14REQUIRED_MACHINE_FEATURES = "vdu" 14REQUIRED_MACHINE_FEATURES = "vdu"
15 15
16BRANCH ?= "master" 16BRANCH ?= "xlnx_rel_v2024.1"
17REPO ?= "git://github.com/Xilinx/vdu-firmware.git;protocol=https" 17REPO ?= "git://github.com/Xilinx/vdu-firmware.git;protocol=https"
18SRCREV ?= "724de80630edcb87d865d69f1a6c0dc61c3f9f12" 18SRCREV ?= "724de80630edcb87d865d69f1a6c0dc61c3f9f12"
19 19
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
index 7c2e932c..b301830f 100644
--- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
@@ -3,8 +3,8 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '
3SRC_URI = "${REPO};${BRANCHARG};name=xrt" 3SRC_URI = "${REPO};${BRANCHARG};name=xrt"
4 4
5BRANCH= "master" 5BRANCH= "master"
6SRCREV_xrt = "f23d53edd42fea0f0acd08c194b4750ed77127e2" 6SRCREV_xrt = "baf88820fb3fc24dda4dc08c91ecbca2c76c7b0f"
7PV = "202320.2.17.0" 7PV = "202410.2.17.0"
8 8
9SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https" 9SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https"
10SRCREV_dma_ip_drivers = "9f02769a2eddde008158c96efa39d7edb6512578" 10SRCREV_dma_ip_drivers = "9f02769a2eddde008158c96efa39d7edb6512578"
diff --git a/meta-xilinx-standalone-experimental/README.sdt.bsp.md b/meta-xilinx-standalone-experimental/README.sdt.bsp.md
new file mode 100644
index 00000000..2b2ce4b0
--- /dev/null
+++ b/meta-xilinx-standalone-experimental/README.sdt.bsp.md
@@ -0,0 +1,46 @@
1# SDT BSP
2
3This section describes the SDT BSP settings which must be added to the generated
4machine configuration file, following [Build Instructions](README.md) step 4, in
5order to use the runqemu command.
6
7## SDT BSP settings
8
9The following board settings need to be added in sdt machine configuration file
10to define which QEMU device trees should be used.
11
12> **Variable usage examples:**
13>
14> QEMU Device tree deploy directory: `QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch"`
15>
16> QEMU PMU Device tree: `QEMU_HW_DTB_PMU = "${QEMU_HW_DTB_PATH}/zynqmp-pmu.dtb"`
17>
18> QEMU PS Device tree: `QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"`
19>
20> QEMU PMC Board Device tree: `QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"`
21>
22> QEMU Memory: Some boards for example VEK280 and VH158 memory configurations are
23> different, Hence we need to adjust the same in QB_MEM to match board dtsi files.
24> Below are some examples.
25> * ZynqMP `QB_MEM = "-m 4096"`
26> * Versal VEK280 `QB_MEM = "-m 12G"`
27
28
29| Devices | Evaluation Board | QEMU PMC or PMU DTB file | QEMU PS DTB file | QB Mem |
30|---------|-------------------------------------------------------------------------------|-----------------------------|-------------------------------|--------|
31| ZynqMP | [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
32| | [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
33| | [ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
34| | [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
35| | [ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
36| | [ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
37| | [ZCU670](https://www.xilinx.com/products/boards-and-kits/zcu670.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 |
38| Versal | [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vck190.dtb` | 8G |
39| | [VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vmk180.dtb` | 8G |
40| | [VPK120](https://www.xilinx.com/products/boards-and-kits/vpk120.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk120.dtb` | 8G |
41| | [VPK180](https://www.xilinx.com/products/boards-and-kits/vpk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk180.dtb` | 8G |
42| | [VEK280](https://www.xilinx.com/products/boards-and-kits/vek280.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vek280.dtb` | 12G |
43| | [VHK158](https://www.xilinx.com/products/boards-and-kits/vhk158.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vhk158.dtb` | 32G |
44
45> **Note:** Additional information on Xilinx architectures can be found at:
46 https://www.xilinx.com/products/silicon-devices.html
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 626ebe18..90045170 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -17,7 +17,7 @@ ESW_REV[2022.1] = "56d94a506fd9f80949f4cff08e13015928603f01"
17ESW_REV[2022.2] = "5330a64c8efd14f0eef09befdbb8d3d738c33ec2" 17ESW_REV[2022.2] = "5330a64c8efd14f0eef09befdbb8d3d738c33ec2"
18ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" 18ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a"
19ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" 19ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c"
20ESW_REV[2024.1] = "827c36863db8e94c1b46e1f40fbc636467913589" 20ESW_REV[2024.1] = "7a83d27befe888ee4efc1ad90fb22a884eef6700"
21SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" 21SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}"
22 22
23EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" 23EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"
@@ -29,7 +29,7 @@ LIC_FILES_CHKSUM[xlnx_rel_v2022.1_update] = 'e62cb7a722c4430999e0a55a7234035d'
29LIC_FILES_CHKSUM[xlnx_rel_v2022.2] = 'ce611484168a6000bd35df68fc4f4290' 29LIC_FILES_CHKSUM[xlnx_rel_v2022.2] = 'ce611484168a6000bd35df68fc4f4290'
30LIC_FILES_CHKSUM[xlnx_rel_v2023.1_update] = '3c310a3ee2197a4c92c6a0e2937c207c' 30LIC_FILES_CHKSUM[xlnx_rel_v2023.1_update] = '3c310a3ee2197a4c92c6a0e2937c207c'
31LIC_FILES_CHKSUM[xlnx_rel_v2023.2_update] = '9fceecdbcad88698f265578f3d4cb26c' 31LIC_FILES_CHKSUM[xlnx_rel_v2023.2_update] = '9fceecdbcad88698f265578f3d4cb26c'
32LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '9fceecdbcad88698f265578f3d4cb26c' 32LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '443113d5aa8fd5facf31e9c5d25dc114'
33LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" 33LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}"
34 34
35SRC_URI = "${EMBEDDEDSW_SRCURI}" 35SRC_URI = "${EMBEDDEDSW_SRCURI}"
diff --git a/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc b/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc
index 5b1b6d1d..f1d54c20 100644
--- a/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc
+++ b/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc
@@ -1,4 +1,4 @@
1SRCREV = "dbf966453f3f1f06bc8b7f59a5dc3adabdc8f89f" 1SRCREV = "a4754372819eb69acb658fc013ad35c4d55bf9a5"
2XEN_URI = "git://github.com/Xilinx/xen.git;protocol=https" 2XEN_URI = "git://github.com/Xilinx/xen.git;protocol=https"
3XEN_BRANCH = "xlnx_rebase_4.18" 3XEN_BRANCH = "xlnx_rebase_4.18"
4 4
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-05-28 18:08:36 +0000