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-rw-r--r--meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass21
-rw-r--r--meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf6
-rw-r--r--meta-xilinx-core/conf/machine/versal-generic.conf2
-rw-r--r--meta-xilinx-core/conf/machine/versal-hbm-generic.conf6
-rw-r--r--meta-xilinx-core/conf/machine/versal-prime-generic.conf2
-rw-r--r--meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb2
-rw-r--r--meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb4
-rw-r--r--meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend2
-rw-r--r--meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc2
-rw-r--r--meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb32
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc3
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb4
-rw-r--r--meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc2
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb4
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc4
-rw-r--r--meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb2
-rw-r--r--meta-xilinx-core/recipes-xrt/xrt/xrt.inc4
32 files changed, 96 insertions, 36 deletions
diff --git a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
index 2b699d9d..188d594b 100644
--- a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
+++ b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass
@@ -97,12 +97,15 @@ python() {
97 97
98 # Check for valid combination of input files in SRC_URI 98 # Check for valid combination of input files in SRC_URI
99 # Skip recipe if any of the below conditions are not satisfied. 99 # Skip recipe if any of the below conditions are not satisfied.
100 # 1. At least one bit or bin or pdi or dts or dtsi or dtbo should exists. 100 # 1. At least one bit or bin or pdi should exists.
101 # 2. More than one dtbo. 101 # 2. More than one dtbo.
102 # 3. More than one bit or bin or pdi. 102 # 3. More than one bit or bin or pdi.
103 # 4. More than one dts and zero dtsi. 103 # 4. More than one dts and zero dtsi.
104 # 5. More than one dtsi and zero dts. 104 # 5. More than one dtsi and zero dts
105 if dtsi_found or dtbo_found or bit_found or bin_found or pdi_found: 105 # 6. Both bit and bin exists.
106 # 7. Both bit or bin and pdi exits.
107 # 8. Both dts or dtsi and dtbo exists.
108 if bit_found or bin_found or pdi_found:
106 bb.debug(2, "dtsi or dtbo or bitstream or pdi found in SRC_URI") 109 bb.debug(2, "dtsi or dtbo or bitstream or pdi found in SRC_URI")
107 if bit_found and pdi_found : 110 if bit_found and pdi_found :
108 raise bb.parse.SkipRecipe("Both '.bit' and '.pdi' file found in SRC_URI, this is invalid use case.") 111 raise bb.parse.SkipRecipe("Both '.bit' and '.pdi' file found in SRC_URI, this is invalid use case.")
@@ -112,8 +115,11 @@ python() {
112 115
113 if bit_found and bin_found: 116 if bit_found and bin_found:
114 raise bb.parse.SkipRecipe("Both '.bit' and '.bin' file found in SRC_URI, either .bit or .bin file is supported but not both.") 117 raise bb.parse.SkipRecipe("Both '.bit' and '.bin' file found in SRC_URI, either .bit or .bin file is supported but not both.")
118
119 if dtsi_found and dtbo_found:
120 raise bb.parse.SkipRecipe("Both '.dts or dtsi' and '.dtbo' file found in SRC_URI, either .dts/dtsi or .dtbo file is supported but not both.")
115 else: 121 else:
116 raise bb.parse.SkipRecipe("Need one '.dtsi' or '.dtbo' or '.bit' or '.bin' or '.pdi' file added to SRC_URI ") 122 raise bb.parse.SkipRecipe("Need one '.bit' or '.bin' or '.pdi' file added to SRC_URI.")
117 123
118 # Check for valid combination of dtsi and dts files in SRC_URI 124 # Check for valid combination of dtsi and dts files in SRC_URI
119 # Following file combinations are not supported use case. 125 # Following file combinations are not supported use case.
@@ -177,10 +183,11 @@ python devicetree_do_compile:append() {
177 import glob, subprocess, shutil 183 import glob, subprocess, shutil
178 soc_family = d.getVar("SOC_FAMILY") 184 soc_family = d.getVar("SOC_FAMILY")
179 185
180 dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.dtbo'),recursive=True) if os.path.isfile(f)) 186 dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('DTSI_PATH') or '') + '/*.dtbo'),recursive=True) if os.path.isfile(f))
181 bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.bin'),recursive=True) if os.path.isfile(f)) 187 bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIN_PATH') or '') + '/*.bin'),recursive=True) if os.path.isfile(f))
188 bit_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIT_PATH') or '') + '/*.bit'),recursive=True) if os.path.isfile(f))
182 # Skip devicetree do_compile task if input file is dtbo or bin in SRC_URI 189 # Skip devicetree do_compile task if input file is dtbo or bin in SRC_URI
183 if not dtbo_count and not bin_count: 190 if not dtbo_count and not bin_count and bit_count:
184 # Convert .bit to .bin format only if dtsi is input. 191 # Convert .bit to .bin format only if dtsi is input.
185 # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit 192 # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit
186 # or .bin format and corresponding file name. Hence we are not doing .bin 193 # or .bin format and corresponding file name. Hence we are not doing .bin
diff --git a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
index bf5523ed..1028ac04 100644
--- a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf
@@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "ai-edge" 7SOC_VARIANT = "ai-edge"
8 8
9# VEK280 board has 12GB memory only but default versal-generic has QB_MEM set to
10# 8G, Hence we need set 12G in QB_MEM.
11QB_MEM = "-m 12G"
12
13QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vek280.dtb"
14
9#### No additional settings should be after the Postamble 15#### No additional settings should be after the Postamble
10#### Postamble 16#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_ai_edge_generic']['versal-ai-edge-generic' != "${MACHINE}"]}" 17PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_ai_edge_generic']['versal-ai-edge-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf
index 2f35ba24..3582944b 100644
--- a/meta-xilinx-core/conf/machine/versal-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-generic.conf
@@ -84,7 +84,7 @@ QB_KERNEL_CMDLINE_APPEND ?= ""
84 84
85QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch" 85QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch"
86QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" 86QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"
87QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb" 87QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"
88 88
89# Four total serial ports defined in this model (according to the dts) 89# Four total serial ports defined in this model (according to the dts)
90# 90#
diff --git a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
index 23fffcb9..3e72da60 100644
--- a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf
@@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "hbm" 7SOC_VARIANT = "hbm"
8 8
9# VHK158 has 32GB memory only but default versal-generic has QB_MEM set to 8G,
10# Since versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM
11QB_MEM = "-m 32G"
12
13QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vhk158.dtb"
14
9#### No additional settings should be after the Postamble 15#### No additional settings should be after the Postamble
10#### Postamble 16#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_hbm_generic']['versal-hbm-generic' != "${MACHINE}"]}" 17PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_hbm_generic']['versal-hbm-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/conf/machine/versal-prime-generic.conf b/meta-xilinx-core/conf/machine/versal-prime-generic.conf
index 94e9b05e..206f0e2a 100644
--- a/meta-xilinx-core/conf/machine/versal-prime-generic.conf
+++ b/meta-xilinx-core/conf/machine/versal-prime-generic.conf
@@ -6,6 +6,8 @@ require conf/machine/versal-generic.conf
6 6
7SOC_VARIANT = "prime" 7SOC_VARIANT = "prime"
8 8
9QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vmk180.dtb"
10
9#### No additional settings should be after the Postamble 11#### No additional settings should be after the Postamble
10#### Postamble 12#### Postamble
11PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_prime_generic']['versal-prime-generic' != "${MACHINE}"]}" 13PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_prime_generic']['versal-prime-generic' != "${MACHINE}"]}"
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
index ca447615..b33d5064 100644
--- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb
@@ -1,6 +1,6 @@
1SRCBRANCH ?= "2024" 1SRCBRANCH ?= "2024"
2SRCREV = "e2fdb4fecbebe41b4cd1c0b4fbfa3496bcded485" 2SRCREV = "e2fdb4fecbebe41b4cd1c0b4fbfa3496bcded485"
3BRANCH = "2024" 3BRANCH = "xlnx_rel_v2024.1"
4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4" 4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4"
5PV = "${SRCBRANCH}+git${SRCPV}" 5PV = "${SRCBRANCH}+git${SRCPV}"
6 6
diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
index 01df6033..bf779ff5 100644
--- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
+++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb
@@ -1,6 +1,6 @@
1SRCBRANCH ?= "2024" 1SRCBRANCH ?= "2024"
2SRCREV = "f4a7bc0fca5b14bb8fd185918614bcc78ce93028" 2SRCREV = "7d39410ad2172be9f339c4ce565ed765ddd8c5c8"
3BRANCH = "2024" 3BRANCH = "xlnx_rel_v2024.1"
4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505" 4LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505"
5PV = "${SRCBRANCH}+git${SRCPV}" 5PV = "${SRCBRANCH}+git${SRCPV}"
6REPO = "git://github.com/Xilinx/open-amp.git;protocol=https" 6REPO = "git://github.com/Xilinx/open-amp.git;protocol=https"
diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
index 6e31d1f0..b8da828d 100644
--- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
+++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
@@ -1,5 +1,5 @@
1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" 1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https"
2SRCREV = "9e880fa8bad815f01ca8ec4a3e141e5386f012fd" 2SRCREV = "30bed2bbebeae4c190a74a5d6f26f43a62135041"
3 3
4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" 4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:"
5 5
diff --git a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
index f7e18273..1f1d0606 100644
--- a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
+++ b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb
@@ -6,7 +6,7 @@ SUMMARY = "Image update is used to update alternate image on compatible firmware
6LICENSE = "MIT" 6LICENSE = "MIT"
7LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSES/MIT;md5=2ac09a7a37dd6ee0ba23ce497d57d09b" 7LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSES/MIT;md5=2ac09a7a37dd6ee0ba23ce497d57d09b"
8 8
9BRANCH = "master" 9BRANCH = "xlnx_rel_v2024.1"
10SRC_URI = "git://github.com/Xilinx/linux-image_update.git;branch=${BRANCH};protocol=https" 10SRC_URI = "git://github.com/Xilinx/linux-image_update.git;branch=${BRANCH};protocol=https"
11SRCREV = "a68308f329578d3585fd335071a9184aa7f46d2e" 11SRCREV = "a68308f329578d3585fd335071a9184aa7f46d2e"
12 12
diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
index 0541a7a3..a59ef469 100644
--- a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
+++ b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc
@@ -3,7 +3,7 @@ SECTION = "libs"
3REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https" 3REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https"
4 4
5BRANCH ?= "main-aie" 5BRANCH ?= "main-aie"
6SRCREV ?= "5621d74d5efa99fdddd9eca47de3294804c62c24" 6SRCREV ?= "c41476c833034259eb760d2a2f7c7118a5be727d"
7 7
8LICENSE = "BSD-3-Clause" 8LICENSE = "BSD-3-Clause"
9LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897" 9LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897"
diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
index 2c6c9cd1..cb9d95f9 100644
--- a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
+++ b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb
@@ -23,7 +23,7 @@ DEPENDS = "libxaiengine"
23 23
24OECMAKE_SOURCEPATH = "${S}/${XAIEFAL_DIR}" 24OECMAKE_SOURCEPATH = "${S}/${XAIEFAL_DIR}"
25 25
26EXTRA_OECMAKE = "-DWITH_TESTS=OFF " 26EXTRA_OECMAKE = "-DWITH_TESTS=OFF -DFAL_LINUX=ON "
27EXTRA_OECMAKE:append = "${@'-DWITH_EXAMPLES=ON' if d.getVar('WITH_EXAMPLES') == 'y' else '-DWITH_EXAMPLES=OFF'}" 27EXTRA_OECMAKE:append = "${@'-DWITH_EXAMPLES=ON' if d.getVar('WITH_EXAMPLES') == 'y' else '-DWITH_EXAMPLES=OFF'}"
28 28
29FILES:${PN}-demos = " \ 29FILES:${PN}-demos = " \
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb
new file mode 100644
index 00000000..af30a17d
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb
@@ -0,0 +1,32 @@
1DESCRIPTION = "Bootbin version file - text format"
2SUMMARY = "The BIF file for bootbin requires a version file in a text format"
3LICENSE = "MIT"
4LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
5
6COMPATIBLE_MACHINE = "^$"
7
8PACKAGE_ARCH = "${MACHINE_ARCH}"
9
10BOOTBIN_VER_MAIN ?= ""
11BOOTBIN_VER_SUFFIX ?= "${@(d.getVar('XILINX_VER_BUILD') or '')[:8] if d.getVar('XILINX_VER_UPDATE') != 'release' and not d.getVar('XILINX_VER_UPDATE').startswith('update') else ''}"
12BOOTBIN_VER_FILE = "bootbin-version-string.txt"
13
14#BOOTBIN_MANIFEST_FILE ?= "bootbin-version-header.manifest"
15
16inherit deploy image-artifact-names
17
18python do_configure() {
19 if d.getVar("BOOTBIN_VER_SUFFIX"):
20 version = version + "-" + d.getVar("BOOTBIN_VER_SUFFIX")
21 with open(d.expand("${B}/${BOOTBIN_VER_FILE}"), "w") as f:
22 f.write(version)
23}
24
25do_deploy() {
26 install -m 0644 ${B}/${BOOTBIN_VER_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.txt
27 ln -s ${IMAGE_NAME}.txt ${DEPLOYDIR}/${IMAGE_LINK_NAME}.txt
28# install -m 0644 ${B}/${BOOTBIN_MANIFEST_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.manifest
29# ln -s ${IMAGE_NAME}.manifest ${DEPLOYDIR}/${IMAGE_LINK_NAME}.manifest
30}
31
32addtask deploy after do_compile
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
index fff2c7a3..cd6adcef 100644
--- a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
+++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
@@ -4,6 +4,9 @@ BOOTGEN_EXTRA_ARGS += "-dump bh"
4# specify BIF common attribute for FSBL 4# specify BIF common attribute for FSBL
5BIF_COMMON_ATTR ?= "" 5BIF_COMMON_ATTR ?= ""
6 6
7# specify BIF optional attributes
8BIF_OPTIONAL_DATA ?= ""
9
7#specify BIF partition attributes required for BOOT.bin 10#specify BIF partition attributes required for BOOT.bin
8BIF_FSBL_ATTR ??= "base-pdi plmfw psmfw" 11BIF_FSBL_ATTR ??= "base-pdi plmfw psmfw"
9BIF_ATF_ATTR ??= "arm-trusted-firmware" 12BIF_ATF_ATTR ??= "arm-trusted-firmware"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
index 4c8bfa0e..e0e1e506 100644
--- a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
+++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
@@ -125,6 +125,10 @@ python do_configure() {
125 biffd.write("the_ROM_image:\n") 125 biffd.write("the_ROM_image:\n")
126 biffd.write("{\n") 126 biffd.write("{\n")
127 127
128 if d.getVar("BIF_OPTIONAL_DATA"):
129 opt_data = d.getVar("BIF_OPTIONAL_DATA") or ""
130 biffd.write("\toptionaldata { %s }\n" % opt_data)
131
128 arch = d.getVar("SOC_FAMILY") 132 arch = d.getVar("SOC_FAMILY")
129 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split() 133 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split()
130 if bifattr: 134 if bifattr:
diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
index b0acf0ef..28f997f2 100644
--- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
+++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb
@@ -8,7 +8,7 @@ REPO ?= "git://github.com/Xilinx/dfx-mgr.git;protocol=https"
8BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 8BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
9SRC_URI = "${REPO};${BRANCHARG}" 9SRC_URI = "${REPO};${BRANCHARG}"
10 10
11BRANCH = "master" 11BRANCH = "xlnx_rel_v2024.1"
12SRCREV = "ec70363a2a878737057995f922a9460d18aafa26" 12SRCREV = "ec70363a2a878737057995f922a9460d18aafa26"
13SOMAJOR = "1" 13SOMAJOR = "1"
14SOMINOR = "0" 14SOMINOR = "0"
diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
index 0cbcaac7..42e67ce6 100644
--- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
+++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb
@@ -4,7 +4,7 @@ DESCRIPTION = "Xilinx libdfx Library and headers"
4LICENSE = "MIT & GPL-2.0-or-later" 4LICENSE = "MIT & GPL-2.0-or-later"
5LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7" 5LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7"
6 6
7BRANCH ?= "master" 7BRANCH ?= "xlnx_rel_v2024.1"
8REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" 8REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https"
9BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 9BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
10SRC_URI = "${REPO};${BRANCHARG}" 10SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
index b919b230..b4ac7998 100644
--- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc
@@ -2,7 +2,7 @@ UBOOT_VERSION = "v2024.01"
2 2
3UBRANCH = "xlnx_rebase_v2024.01" 3UBRANCH = "xlnx_rebase_v2024.01"
4 4
5SRCREV = "12c2fe646e7e98ba98334c75e082cc10faf0413d" 5SRCREV = "a64b554a4a7e0c540dd4fbb69bcf765a88d7359f"
6 6
7LICENSE = "GPL-2.0-or-later" 7LICENSE = "GPL-2.0-or-later"
8LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" 8LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
index c4fc180e..d10504d3 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb
@@ -1,6 +1,6 @@
1 1
2require qemu-devicetrees.inc 2require qemu-devicetrees.inc
3 3
4BRANCH ?= "master" 4BRANCH ?= "xlnx_rel_v2024.1"
5SRCREV ?= "c54a1cfb7076aaf8abdfe50e89245b37cdb1c077" 5SRCREV ?= "b9c88cbfaaa0c8b8be70ea3c74f4cb69fb02a080"
6 6
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
index ffaf3cdf..d48350b2 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc
@@ -1,3 +1,3 @@
1XILINX_QEMU_VERSION = "v8.1.0" 1XILINX_QEMU_VERSION = "v8.1.0"
2BRANCH = "master" 2BRANCH = "xlnx_rel_v2024.1"
3SRCREV = "aa05b83770c0cd5a4f7fcbcef7efc806ae2abe9f" 3SRCREV = "2319c870e754148ec3b9d40be0d3dbee959c3251"
diff --git a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
index db99c4d7..82c411a2 100644
--- a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
+++ b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
@@ -13,7 +13,7 @@ PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm"
13FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 13FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
14 14
15REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https"
16BRANCH ?= "xlnx_rel_v2023.2" 16BRANCH ?= "xlnx_rel_v2024.1"
17SRCREV ?= "b3a772aad859cdadc8513b11c3e995546c20e75e" 17SRCREV ?= "b3a772aad859cdadc8513b11c3e995546c20e75e"
18BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 18BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
19 19
diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
index 17039abb..503cee02 100644
--- a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb
@@ -9,7 +9,7 @@ PV = "${XLNX_DP_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', Fal
9 9
10S = "${WORKDIR}/git" 10S = "${WORKDIR}/git"
11 11
12BRANCH ?= "master" 12BRANCH ?= "xlnx_rel_v2024.1"
13REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" 13REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https"
14SRCREV ?= "e20942b256e6fb18eaef919c7441f65ad8afcf43" 14SRCREV ?= "e20942b256e6fb18eaef919c7441f65ad8afcf43"
15 15
diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
index 9757ae4b..73a22d30 100644
--- a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb
@@ -9,7 +9,7 @@ PV = "${XLNX_HDMI_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', F
9 9
10S = "${WORKDIR}/git" 10S = "${WORKDIR}/git"
11 11
12BRANCH ?= "master" 12BRANCH ?= "xlnx_rel_v2024.1"
13REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https" 13REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https"
14SRCREV = "edd297762e0bac3f4c5b64ef67244968e22020e2" 14SRCREV = "edd297762e0bac3f4c5b64ef67244968e22020e2"
15 15
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
index 8f65469a..3008a572 100644
--- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb
@@ -1,7 +1,7 @@
1LINUX_VERSION = "6.6.10" 1LINUX_VERSION = "6.6.10"
2YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" 2YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta"
3KBRANCH="xlnx_rebase_v6.6_LTS" 3KBRANCH="xlnx_rebase_v6.6_LTS"
4SRCREV = "dcac89c7c78a556240e07ac3c6c568dd5be90ef3" 4SRCREV = "73608e3d7f39dc2b44a1d3c135dec85bcb1b67f0"
5SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" 5SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865"
6 6
7KCONF_AUDIT_LEVEL="0" 7KCONF_AUDIT_LEVEL="0"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
index be8f6075..f474595c 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb
@@ -11,7 +11,7 @@ S = "${WORKDIR}/git"
11 11
12FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 12FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
13 13
14BRANCH = "master" 14BRANCH = "xlnx_rel_v2024.1"
15REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" 15REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https"
16SRCREV = "91d19a16308a438596138d30d8174e148fc45584" 16SRCREV = "91d19a16308a438596138d30d8174e148fc45584"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
index bff19a9c..14226aa7 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb
@@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd"
6XILINX_VCU_VERSION = "1.0.0" 6XILINX_VCU_VERSION = "1.0.0"
7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" 7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
8 8
9BRANCH ?= "master" 9BRANCH ?= "xlnx_rel_v2024.1"
10REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" 10REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https"
11SRCREV = "dc34204543b89997577bd2c9757b3c218e6caccc" 11SRCREV = "dc34204543b89997577bd2c9757b3c218e6caccc"
12 12
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
index 8c3df7db..e3f656b0 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb
@@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd"
6XILINX_VCU_VERSION = "1.0.0" 6XILINX_VCU_VERSION = "1.0.0"
7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" 7PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}"
8 8
9BRANCH ?= "master" 9BRANCH ?= "xlnx_rel_v2024.1"
10REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" 10REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https"
11SRCREV = "940f9fa933402de6f959911c236f36add5dd3a40" 11SRCREV = "940f9fa933402de6f959911c236f36add5dd3a40"
12 12
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
index 3ec61a96..1031f892 100644
--- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb
@@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE',
8 8
9S = "${WORKDIR}/git" 9S = "${WORKDIR}/git"
10 10
11BRANCH ?= "master" 11BRANCH ?= "xlnx_rel_v2024.1"
12REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" 12REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https"
13SRCREV = "6ee1998c53817ab0c137b8b99089337d5caba62c" 13SRCREV = "6ee1998c53817ab0c137b8b99089337d5caba62c"
14 14
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
index ccbe77a8..84f9cc2a 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb
@@ -11,7 +11,7 @@ PV .= "+git${SRCPV}"
11S = "${WORKDIR}/git" 11S = "${WORKDIR}/git"
12FILESEXTRAPATHS:prepend := "${THISDIR}/files:" 12FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
13 13
14BRANCH ?= "master" 14BRANCH ?= "xlnx_rel_v2024.1"
15REPO ?= "git://github.com/Xilinx/vdu-modules.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/vdu-modules.git;protocol=https"
16SRCREV ?= "25773344ce1e539e7136c5a30cdee98a6cf490a8" 16SRCREV ?= "25773344ce1e539e7136c5a30cdee98a6cf490a8"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
index 5186d4fc..3acbf3ef 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb
@@ -11,7 +11,7 @@ inherit autotools features_check
11 11
12REQUIRED_MACHINE_FEATURES = "vdu" 12REQUIRED_MACHINE_FEATURES = "vdu"
13 13
14BRANCH ?= "master" 14BRANCH ?= "xlnx_rel_v2024.1"
15REPO ?= "git://github.com/Xilinx/vdu-ctrl-sw.git;protocol=https" 15REPO ?= "git://github.com/Xilinx/vdu-ctrl-sw.git;protocol=https"
16SRCREV ?= "7af131e0780d52ebc7bd6173bf1b99fec4dc522f" 16SRCREV ?= "7af131e0780d52ebc7bd6173bf1b99fec4dc522f"
17 17
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
index 91b2a150..5ba604f8 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb
@@ -7,7 +7,7 @@ XILINX_VDU_VERSION = "1.0.0"
7PV =. "${XILINX_VDU_VERSION}-xilinx-v" 7PV =. "${XILINX_VDU_VERSION}-xilinx-v"
8PV .= "+git${SRCPV}" 8PV .= "+git${SRCPV}"
9 9
10BRANCH ?= "master" 10BRANCH ?= "xlnx_rel_v2024.1"
11REPO ?= "git://github.com/Xilinx/vdu-omx-il.git;protocol=https" 11REPO ?= "git://github.com/Xilinx/vdu-omx-il.git;protocol=https"
12SRCREV ?= "af9c6e8935799f4dcd579b0164dd05eb039b569d" 12SRCREV ?= "af9c6e8935799f4dcd579b0164dd05eb039b569d"
13 13
diff --git a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
index 378a23df..86f977b4 100644
--- a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
+++ b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb
@@ -13,7 +13,7 @@ inherit autotools features_check
13 13
14REQUIRED_MACHINE_FEATURES = "vdu" 14REQUIRED_MACHINE_FEATURES = "vdu"
15 15
16BRANCH ?= "master" 16BRANCH ?= "xlnx_rel_v2024.1"
17REPO ?= "git://github.com/Xilinx/vdu-firmware.git;protocol=https" 17REPO ?= "git://github.com/Xilinx/vdu-firmware.git;protocol=https"
18SRCREV ?= "724de80630edcb87d865d69f1a6c0dc61c3f9f12" 18SRCREV ?= "724de80630edcb87d865d69f1a6c0dc61c3f9f12"
19 19
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
index 7c2e932c..b301830f 100644
--- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
@@ -3,8 +3,8 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '
3SRC_URI = "${REPO};${BRANCHARG};name=xrt" 3SRC_URI = "${REPO};${BRANCHARG};name=xrt"
4 4
5BRANCH= "master" 5BRANCH= "master"
6SRCREV_xrt = "f23d53edd42fea0f0acd08c194b4750ed77127e2" 6SRCREV_xrt = "baf88820fb3fc24dda4dc08c91ecbca2c76c7b0f"
7PV = "202320.2.17.0" 7PV = "202410.2.17.0"
8 8
9SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https" 9SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https"
10SRCREV_dma_ip_drivers = "9f02769a2eddde008158c96efa39d7edb6512578" 10SRCREV_dma_ip_drivers = "9f02769a2eddde008158c96efa39d7edb6512578"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-06-03 13:19:12 +0000