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-rw-r--r--meta-xilinx-virtualization/recipes-devtools/qemu/qemu-xilinx-8.1/0001-arm-xenpvh-Introduce-virtio-pci-support.patch353
1 files changed, 353 insertions, 0 deletions
diff --git a/meta-xilinx-virtualization/recipes-devtools/qemu/qemu-xilinx-8.1/0001-arm-xenpvh-Introduce-virtio-pci-support.patch b/meta-xilinx-virtualization/recipes-devtools/qemu/qemu-xilinx-8.1/0001-arm-xenpvh-Introduce-virtio-pci-support.patch
new file mode 100644
index 00000000..6e3b40f7
--- /dev/null
+++ b/meta-xilinx-virtualization/recipes-devtools/qemu/qemu-xilinx-8.1/0001-arm-xenpvh-Introduce-virtio-pci-support.patch
@@ -0,0 +1,353 @@
1From 3104d411ee36487ea409ba5a1b474989326f70f2 Mon Sep 17 00:00:00 2001
2From: Vikram Garhwal <vikram.garhwal@amd.com>
3Date: Wed, 15 Nov 2023 14:19:31 -0800
4Subject: [PATCH] arm: xenpvh: Introduce virtio-pci support
5
6The bridge is needed for virtio-pci support, as QEMU can emulate the
7whole bridge with any virtio-pci devices connected to it.
8
9NOTE: A few xen-hvm-common.c and xen_native.h changes are cherry-picked from
10EPAM QEMU patches for xen-arm. This was done to keep least diff with upstream.
11
12Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
13Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
14Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
15---
16 hw/arm/xen_arm.c | 271 ++++++++++++++++++++++++++++++++++++
17 include/hw/xen/xen_native.h | 3 +
18 2 files changed, 274 insertions(+)
19
20diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
21index 1587e2a43b..a7c5b20777 100644
22--- a/hw/arm/xen_arm.c
23+++ b/hw/arm/xen_arm.c
24@@ -34,6 +34,7 @@
25 #include "hw/xen/xen-hvm-common.h"
26 #include "sysemu/tpm.h"
27 #include "hw/xen/arch_hvm.h"
28+#include "hw/pci-host/gpex.h"
29
30 #define TYPE_XEN_ARM MACHINE_TYPE_NAME("xenpvh")
31 OBJECT_DECLARE_SIMPLE_TYPE(XenArmState, XEN_ARM)
32@@ -57,6 +58,9 @@ struct XenArmState {
33
34 struct {
35 uint64_t tpm_base_addr;
36+ MemMapEntry pcie_mmio;
37+ MemMapEntry pcie_ecam;
38+ MemMapEntry pcie_mmio_high;
39 } cfg;
40 };
41
42@@ -132,6 +136,80 @@ static void xen_init_ram(MachineState *machine)
43 ram_grants = *xen_init_grant_ram();
44 }
45
46+static bool xen_validate_pcie_config(XenArmState *xam)
47+{
48+ if (xam->cfg.pcie_ecam.base == 0 &&
49+ xam->cfg.pcie_ecam.size == 0 &&
50+ xam->cfg.pcie_mmio.base == 0 &&
51+ xam->cfg.pcie_mmio.size == 0 &&
52+ xam->cfg.pcie_mmio_high.base == 0 &&
53+ xam->cfg.pcie_mmio_high.size == 0) {
54+ /* It's okay, user just don't want PCIe brige */
55+ return false;
56+ }
57+
58+ if (xam->cfg.pcie_ecam.base == 0 ||
59+ xam->cfg.pcie_ecam.size == 0 ||
60+ xam->cfg.pcie_mmio.base == 0 ||
61+ xam->cfg.pcie_mmio.size == 0 ||
62+ xam->cfg.pcie_mmio_high.base == 0 ||
63+ xam->cfg.pcie_mmio_high.size == 0) {
64+ /* User provided some PCIe options, but not all of them */
65+ error_printf("Incomplete PCIe bridge configuration\n");
66+ exit(1);
67+ }
68+
69+ return true;
70+}
71+
72+static void xen_create_pcie(XenArmState *xam)
73+{
74+ MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
75+ MemoryRegion *ecam_alias, *ecam_reg;
76+ DeviceState *dev;
77+ int i;
78+
79+ dev = qdev_new(TYPE_GPEX_HOST);
80+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
81+
82+ /* Map ECAM space */
83+ ecam_alias = g_new0(MemoryRegion, 1);
84+ ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
85+ memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
86+ ecam_reg, 0, xam->cfg.pcie_ecam.size);
87+ memory_region_add_subregion(get_system_memory(), xam->cfg.pcie_ecam.base,
88+ ecam_alias);
89+
90+ /* Map the MMIO space */
91+ mmio_alias = g_new0(MemoryRegion, 1);
92+ mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
93+ memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
94+ mmio_reg,
95+ xam->cfg.pcie_mmio.base,
96+ xam->cfg.pcie_mmio.size);
97+ memory_region_add_subregion(get_system_memory(), xam->cfg.pcie_mmio.base,
98+ mmio_alias);
99+
100+ /* Map the MMIO_HIGH space */
101+ mmio_alias_high = g_new0(MemoryRegion, 1);
102+ memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
103+ mmio_reg,
104+ xam->cfg.pcie_mmio_high.base,
105+ xam->cfg.pcie_mmio_high.size);
106+ memory_region_add_subregion(get_system_memory(),
107+ xam->cfg.pcie_mmio_high.base,
108+ mmio_alias_high);
109+
110+ /* Legacy PCI interrupts (#INTA - #INTD) */
111+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
112+ qemu_irq irq = qemu_allocate_irq(xen_set_irq, NULL,
113+ GUEST_VIRTIO_PCI_SPI_FIRST + i);
114+
115+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
116+ gpex_set_irq_num(GPEX_HOST(dev), i, GUEST_VIRTIO_PCI_SPI_FIRST + i);
117+ }
118+}
119+
120 void arch_handle_ioreq(XenIOState *state, ioreq_t *req)
121 {
122 hw_error("Invalid ioreq type 0x%x\n", req->type);
123@@ -193,6 +271,13 @@ static void xen_arm_init(MachineState *machine)
124
125 xen_create_virtio_mmio_devices(xam);
126
127+ if (xen_validate_pcie_config(xam)) {
128+ xen_create_pcie(xam);
129+ } else {
130+ DPRINTF("PCIe host bridge is not configured,"
131+ " only virtio-mmio can be used\n");
132+ }
133+
134 #ifdef CONFIG_TPM
135 if (xam->cfg.tpm_base_addr) {
136 xen_enable_tpm(xam);
137@@ -228,6 +313,150 @@ static void xen_arm_set_tpm_base_addr(Object *obj, Visitor *v,
138 }
139 #endif
140
141+static void xen_arm_get_pcie_ecam_base_addr(Object *obj, Visitor *v,
142+ const char *name, void *opaque,
143+ Error **errp)
144+{
145+ XenArmState *xam = XEN_ARM(obj);
146+ uint64_t value = xam->cfg.pcie_ecam.base;
147+
148+ visit_type_uint64(v, name, &value, errp);
149+}
150+
151+static void xen_arm_set_pcie_ecam_base_addr(Object *obj, Visitor *v,
152+ const char *name, void *opaque,
153+ Error **errp)
154+{
155+ XenArmState *xam = XEN_ARM(obj);
156+ uint64_t value;
157+
158+ if (!visit_type_uint64(v, name, &value, errp)) {
159+ return;
160+ }
161+
162+ xam->cfg.pcie_ecam.base = value;
163+}
164+
165+static void xen_arm_get_pcie_ecam_size(Object *obj, Visitor *v,
166+ const char *name, void *opaque,
167+ Error **errp)
168+{
169+ XenArmState *xam = XEN_ARM(obj);
170+ uint64_t value = xam->cfg.pcie_ecam.size;
171+
172+ visit_type_uint64(v, name, &value, errp);
173+}
174+
175+static void xen_arm_set_pcie_ecam_size(Object *obj, Visitor *v,
176+ const char *name, void *opaque,
177+ Error **errp)
178+{
179+ XenArmState *xam = XEN_ARM(obj);
180+ uint64_t value;
181+
182+ if (!visit_type_uint64(v, name, &value, errp)) {
183+ return;
184+ }
185+
186+ xam->cfg.pcie_ecam.size = value;
187+}
188+
189+static void xen_arm_get_pcie_mmio_base_addr(Object *obj, Visitor *v,
190+ const char *name, void *opaque,
191+ Error **errp)
192+{
193+ XenArmState *xam = XEN_ARM(obj);
194+ uint64_t value = xam->cfg.pcie_mmio.base;
195+
196+ visit_type_uint64(v, name, &value, errp);
197+}
198+
199+static void xen_arm_set_pcie_mmio_base_addr(Object *obj, Visitor *v,
200+ const char *name, void *opaque,
201+ Error **errp)
202+{
203+ XenArmState *xam = XEN_ARM(obj);
204+ uint64_t value;
205+
206+ if (!visit_type_uint64(v, name, &value, errp)) {
207+ return;
208+ }
209+
210+ xam->cfg.pcie_mmio.base = value;
211+}
212+
213+static void xen_arm_get_pcie_mmio_size(Object *obj, Visitor *v,
214+ const char *name, void *opaque,
215+ Error **errp)
216+{
217+ XenArmState *xam = XEN_ARM(obj);
218+ uint64_t value = xam->cfg.pcie_mmio.size;
219+
220+ visit_type_uint64(v, name, &value, errp);
221+}
222+
223+static void xen_arm_set_pcie_mmio_size(Object *obj, Visitor *v,
224+ const char *name, void *opaque,
225+ Error **errp)
226+{
227+ XenArmState *xam = XEN_ARM(obj);
228+ uint64_t value;
229+
230+ if (!visit_type_uint64(v, name, &value, errp)) {
231+ return;
232+ }
233+
234+ xam->cfg.pcie_mmio.size = value;
235+}
236+
237+static void xen_arm_get_pcie_prefetch_base_addr(Object *obj, Visitor *v,
238+ const char *name, void *opaque,
239+ Error **errp)
240+{
241+ XenArmState *xam = XEN_ARM(obj);
242+ uint64_t value = xam->cfg.pcie_mmio_high.base;
243+
244+ visit_type_uint64(v, name, &value, errp);
245+}
246+
247+static void xen_arm_set_pcie_prefetch_base_addr(Object *obj, Visitor *v,
248+ const char *name, void *opaque,
249+ Error **errp)
250+{
251+ XenArmState *xam = XEN_ARM(obj);
252+ uint64_t value;
253+
254+ if (!visit_type_uint64(v, name, &value, errp)) {
255+ return;
256+ }
257+
258+ xam->cfg.pcie_mmio_high.base = value;
259+}
260+
261+static void xen_arm_get_pcie_prefetch_size(Object *obj, Visitor *v,
262+ const char *name, void *opaque,
263+ Error **errp)
264+{
265+ XenArmState *xam = XEN_ARM(obj);
266+ uint64_t value = xam->cfg.pcie_mmio_high.size;
267+
268+ visit_type_uint64(v, name, &value, errp);
269+}
270+
271+static void xen_arm_set_pcie_prefetch_size(Object *obj, Visitor *v,
272+ const char *name, void *opaque,
273+ Error **errp)
274+{
275+ XenArmState *xam = XEN_ARM(obj);
276+ uint64_t value;
277+
278+ if (!visit_type_uint64(v, name, &value, errp)) {
279+ return;
280+ }
281+
282+ xam->cfg.pcie_mmio_high.size = value;
283+}
284+
285 static void xen_arm_machine_class_init(ObjectClass *oc, void *data)
286 {
287
288@@ -249,6 +478,48 @@ static void xen_arm_machine_class_init(ObjectClass *oc, void *data)
289
290 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
291 #endif
292+
293+ object_class_property_add(oc, "pci-ecam-base-addr", "uint64_t",
294+ xen_arm_get_pcie_ecam_base_addr,
295+ xen_arm_set_pcie_ecam_base_addr,
296+ NULL, NULL);
297+ object_class_property_set_description(oc, "pci-ecam-base-addr",
298+ "Set Base address for PCI ECAM.");
299+
300+ object_class_property_add(oc, "pci-ecam-size", "uint64_t",
301+ xen_arm_get_pcie_ecam_size,
302+ xen_arm_set_pcie_ecam_size,
303+ NULL, NULL);
304+ object_class_property_set_description(oc, "pci-ecam-size",
305+ "Set Size for PCI ECAM.");
306+
307+ object_class_property_add(oc, "pci-mmio-base-addr", "uint64_t",
308+ xen_arm_get_pcie_mmio_base_addr,
309+ xen_arm_set_pcie_mmio_base_addr,
310+ NULL, NULL);
311+ object_class_property_set_description(oc, "pci-mmio-base-addr",
312+ "Set Base address for PCI MMIO.");
313+
314+ object_class_property_add(oc, "pci-mmio-size", "uint64_t",
315+ xen_arm_get_pcie_mmio_size,
316+ xen_arm_set_pcie_mmio_size,
317+ NULL, NULL);
318+ object_class_property_set_description(oc, "pci-mmio-size",
319+ "Set size for PCI MMIO.");
320+
321+ object_class_property_add(oc, "pci-prefetch-base-addr", "uint64_t",
322+ xen_arm_get_pcie_prefetch_base_addr,
323+ xen_arm_set_pcie_prefetch_base_addr,
324+ NULL, NULL);
325+ object_class_property_set_description(oc, "pci-prefetch-base-addr",
326+ "Set Prefetch Base address for PCI.");
327+
328+ object_class_property_add(oc, "pci-prefetch-size", "uint64_t",
329+ xen_arm_get_pcie_prefetch_size,
330+ xen_arm_set_pcie_prefetch_size,
331+ NULL, NULL);
332+ object_class_property_set_description(oc, "pci-prefetch-size",
333+ "Set Prefetch size for PCI.");
334 }
335
336 static const TypeInfo xen_arm_machine_type = {
337diff --git a/include/hw/xen/xen_native.h b/include/hw/xen/xen_native.h
338index 6f09c48823..1e81189a27 100644
339--- a/include/hw/xen/xen_native.h
340+++ b/include/hw/xen/xen_native.h
341@@ -539,6 +539,9 @@ static inline int xendevicemodel_set_irq_level(xendevicemodel_handle *dmod,
342 #define GUEST_VIRTIO_MMIO_SPI_LAST 43
343 #endif
344
345+#define GUEST_VIRTIO_PCI_SPI_FIRST 44
346+#define GUEST_VIRTIO_PCI_SPI_LAST 48
347+
348 #if defined(__i386__) || defined(__x86_64__)
349 #define GUEST_RAM_BANKS 2
350 #define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */
351--
3522.30.2
353
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