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v_hdmitxss: TxOnly: Fix compilation error with Txonly design
v_hdmirxss: RxOnly: Fix compilation error with Rxonly design
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Changelog:
Fix to handle input_ports_details and output_ports_details Interface tiles metric for PLIO designs (#8064)
Changing a copy to a move for when profiling samples are written (#8065)
VITIS-11806 Command-chaining: XRT C++ Command List (#8063)
VITIS-11832 - Support transaction buffer patching in XRT (#8059)
fix printing logs on windows (#8062)
using the correct workspace path for windows (#8061)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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update Embedded SW license 2024.1 release
sw_services: xilfpga: Add doxygen fixes
sysmonpsu: Add Xiltimer to CMakeLists
scripts: pyesw: Enable user-driven customization of library options for xilpm
trngpsv: Update trngpsv minor version
trngpsx: Update trngpsx minor version
sw_services: xilsecure: Update minor version number to 24.1
sw_services:xilocp: Fix DME failure
sysmonpsv: Handle Secondary SLRs
sw_services:xilsecure:Fix Branch Past initialization
sw_services:xilsecure:Fix MISRA-C Rule 17.7
sw_services:xilsecure:Fix MISRA-C Rule 10.3
sw_services:xilsecure:Fix overrun issue
sw_services: xilpm: Enable the capability to adjust bsp config flags in the Rigel flow
freertos10_xilinx: Fix portPOINTER_SIZE_TYPE value for Cortex A78
scripts: pyesw: retarget_app: Add support for shared workspace use case
xilpm: versal_common: server: Add a macro to exclude USB idle code
bsp: Add macro to disable long values print support as needed
dp12txss: examples: Fix IIC Baseaddress for new unified version
dp12rxss: examples: Fix IIC Baseaddress for new unified version
xilpm: versal: NoC ScanClear workaround for xcvm2152
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microblaze: Change TLB mapping and free space allocation
arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
arm64: zynqmp: Disable Tri-state for SDIO
arm64: dts: zynqmp: make hw-ecc as the default ecc mode
mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOCs
mailbox: zynqmp: Move buffered IPI setup to of_match selected routine
mailbox: zynqmp: Move of_match structure closer to usage
phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate
video/hdmi: Add support for version 3 AVI Infoframe
phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode
drm: xlnx: hdmi: Set wait event flag for TMDS mode
drm: xlnx: hdmi: Fix TMDS clock calculation for RGB YUV422 YUV444 formats
phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5
drm: xlnx: hdmi: Fix overwriting the max_frl_rate variable
drm: xlnx: hdmi: Downgrade the FRL rate when sink requests
drm: xlnx: hdmi: Fix lts2 state machine
drm: xlnx: hdmi: Implement xlnx_hdmi_frl_config function
drm: xlnx: hdmi: Implement streamdown callback function
drm: xlnx: hdmi: Add support for all FRL line rates
drm: xlnx: hdmi: Implement streamup callback function
drm: xlnx: hdmi: Implement connect callback function
drm: xlnx: hdmi: Set wait event flag in ltsp state
drm: xlnx: hdmi: Fix FRL link and video clock values
drm: xlnx: hdmi: Fix VTC macros as per the IP specification
phy: xilinx-xhdmiphy: Fix MMCM parameter values for GTYE5/GTYP
drm: xlnx: hdmi: Optimize phy configuration function calls
firmware: xilinx: Dont send linux address to get fpga config get status
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xilpm: versal_common: server: Add error message for PSM-PLM version conflict
lib: sw_services: versal_common: Add check for the IPI permission access in feature check API
lwip : Add lwip_dhcp_does_acd_check
sw_services:xilnvm:versalnet:Fix for MISRA-C Rule 8.3
sw_services:xilnvm:versalnet:Fix for coverity warning
sw_services:xilnvm:versalnet:Fix MISRA-C Rule 12.1
XilSkey: efuse status bits of ultrascale devices
srec_bootloader: Fix compilation error on Microblaze RISC-V
xilpm: versal: server: Skip NoC clock gating consideration during the boot
uartns550: Fix compilation warning of interrupt example
dp14txss:zcu102_pt_hdcp: Modified applicaiton to continue without hdcp incase of wrong password entered during fetching keys from EEPROM.
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fdt_generic_devices: Add phy aliases
arm_generic_fdt: Create ethernet phy in postinit
fdt_generic_util: Add a postinit call back
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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30bed2b openamp: xlnx: Add vc-p and vn-p models
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
Cleanup clangtidy warnings (#8057)
Providing a work-around to allocate instruction buffer in HIP (#8047)
SC warning fix on RAVE and xsabin extension warning fix on Versal (#8053)
aie-status reports fix (#8051)
VITIS-11503 - Dump instruction bo created from Elf so verification can be done (#8043)
VITIS-11503 - change elf section name from mc_code to control-packet (#8054)
Defining Mailbox Macro for QDMA to fix APU crash on RAVE (#8052)
revert sdr changes (#8049)
ML Timeline Plugin should read timestamp data before AIE Profile/Debug (#8045)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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openamp: xlnx: versal: match model parsing same as VNET
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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zynqmp_pmufw: Update FPGA config reg status to use local buf
dp21txss: Add support for octa pixel mode
dp21txss: Add support for OctaPixel Mode
dp21rxss: Add support for OctaPixel Mode
dp21: Add support for octa pixel mode
dp21: Add support for OctaPixel Mode
dp21: Fix C++ warnings
dp14: Fix C++ warnings
sw_services:xilocp:Fix issue for getting swpcr data
sw_services:xilocp: Clear memory buffer after calculating PCR
xilplmi: Correct configuration read format for VP1902 device.
xilsem: Correct configuration read format for VP1902.
i2s: Fix C++ compilation errors
sw_services: xilcert: Fixed calculation of hash in serial field
xilsecure: fixed header inclusion in SDT flow
dfeofdm: Update hw version
emacps: Fix HwTail check in XEmacPs_BdRingFromHwRX
sw_services:xilnvm:Update validation check during additional PPK programming
BSP: riscv: Fix instruction cache APIs
dfeprach: Update device node name
usbpsu: Add doxygen and editorial fixes
sw_services: xilpm: Remove usage of GSW ERROR register in BISR code
esw: In SDT flow for the Microblaze processor, include libgloss in the link libraries by default
sw_services:xilskey:Add description for XILSKEY_PUF_KEK_REGEN_RDY_TIMEOUT
xilpm: versal_common: server: Remove PGGS2 and PGGS3 related code
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net: axienet: Correct tx_buff size when DRE is not enabled
clk: clocking-wizard: calculate dividers fractional parts
v4l: xilinx: dprxss: Fix xhdcp1x_rx_init() function declaration
v4l: xilinx: dprxss: Fix gcc warning
staging: xilinx_hdcp: Fix gcc warning
mtd: spi-nor: Use same bit mask macro in spi & spi-nor core
Revert "drivers: clk: zynqmp: add hack to use old algorithm for divider round rate"
fpga: Fix the reset handling
remoteproc: zynqmp_r5: Clean up support for Versal NET CTCM
mtd: spi-nor: Add support for BP3 at SR bit 5
mtd: spi-nor: Use params->size for flash size info
mtd: spi-nor: Avoid writing EAR register for flashes less than 16MB
mtd: spi-nor: Use nor->info->id[0] for manufacturer id
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driver:src:Softpartition boundary Isolation fixed
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Updated sysmonpsv to 4.2
Revert "sysmonpsv: Added SSIT Support"
BSP: riscv: Fix FPU context handling in trap handler
vphy: Added support for DP2.1
sw_services:xilocp:Fix review comments for XOcp_DmeXppuConfig
sw_services:xilloader:Fixed doxygen comments format
TPG: Addition of bool library in header file
bsp: cortexr52: Use PMU as default timer for Cortex-R52
sw_services: xilplmi: Fix MISRA-C violation 8.6
sw_services: xilplmi: Fix MISRA-C violation 2.2
sw_services: xilplmi: Fix MISRA-C violation 17.8
sw_services: xilplmi: Fix MISRA-C violation 10.3
mipicsiss: example: update GPIO address.
sw_apps: zynqmp_pmufw: Correct typo for SOM specific macro
dp21: Fix linking issues in C++
dp14: Fix linking issues in C++
dp12: Fix linking issues in C++
rfdc: NCO Frequency
xilplmi: added CDO debug prints
intc: Fix xintc_low_level_example for HW designs with fast interrupts
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VEK280 SDT QEMU doesn't come up with PLM, this to default
QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for
VEK280 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vek280.dtb and also adjust the QB_MEM to 12GB
to match with board dtsi file, we need set same in QB_MEM
for QEMU boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Update README with QB_MEM info to boot QEMU using SDT builds.
Also fix typo in README.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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VHK158 SDT QEMU doesn't come up with PLM, this to default
QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for
VHK158 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vmk158.dtb and also adjust the QB_MEM to 32GB
as versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM
for QEMU boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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The SRCREV update contains below commits:
assists: generate_config_object: Enable user-driven customization of library options
assists: generate_config_object: Addressed the scenario where, not all masters are reset masters
lopper:assists:baremetallinker: Do not consider linear SPIs for memory tests
lopper:assists:gen_domain_dts: Remove axi_noc and noc_ddr4 IPs from linux ignore list
base: add expression to clock phandle description
Signed-off-by: Onkar Harsh <onkar.harsh@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add system device tree bsp README which provide BSP settings such
as QEMU PMC/PMU DTB, QEMU PS DTB etc.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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QEMU PLM error code are observed as shown below.
[13422.262]****************************************
[13422.490]Xilinx Versal Platform Loader and Manager
[13422.508]Release 2024.1 Mar 30 2024 - 14:13:53
[13422.562]Platform Version: v0.0 PMC: v0.0, PS: v0.0
[13422.588]BOOTMODE: 0x5, MULTIBOOT: 0xF0000000
[13422.608]****************************************
[13427.899]Non Secure Boot
[13441.028]PLM Initialization Time
[13441.090]***********Boot PDI Load: Started***********
[13441.191]Loading PDI from SD1
[13441.218]Monolithic/Master Device
[14850.660]1409.510 ms: PDI initialization time
[14850.719]+++Loading Image#: 0x1, Name: lpd, Id: 0x04210002
[14850.755]---Loading Partition#: 0x1, Id: 0xC
[14892.625] 41.831 ms for Partition#: 0x1, Size: 11360 Bytes
[14893.706]---Loading Partition#: 0x2, Id: 0x0
[14902.163] 7.679 ms for Partition#: 0x2, Size: 65104 Bytes
PSM Firmware version: 2024.1 [Build: Mar 30 2024 14:13:53 ]
[15013.595]+++Loading Image#: 0x2, Name: pl_cfi, Id: 0x18700000
[15014.589]---Loading Partition#: 0x3, Id: 0x3
[21947.779]Polling 0xF11A0000 Mask: 0xFFFFFFFF ExpectedValue: 0x14CAA093
[21949.039]MaskPoll: Addr: 0x0F11A0000, Mask: 0xFFFFFFFF, ExpVal: 0x14CAA093, Timeout: 1000000, RegVal: 0x14CA8093 ...ERROR
[21951.067]CMD: 0x00040101 execute failed, Processed Cdo Length 0x84
[21952.260]CMD Payload START, Len:0x00000004
0x00000000F20000A8: 0xF11A0000 0xFFFFFFFF 0x14CAA093 0x00000001
0x00000000F20000B4:
[21954.516]CMD Payload END
[21955.035]Error loading PL data:
CFU_ISR: 0x00000000, CFU_STATUS: 0x0000080C
PMC ERR1: 0x00000000, PMC ERR2: 0x00000000
[21957.810]PLM Error Status: 0x21010001
[21958.489]============Register Dump============
[21959.269]PMC_TAP_IDCODE: 0x14CA8093
[21959.887]EFUSE_CACHE_IP_DISABLE_0(EXTENDED IDCODE): 0x00004000
[21960.901]PMC_TAP_VERSION: 0x03000000
[21961.516]CRP_BOOT_MODE_USER: 0x00000005
[21962.179]CRP_BOOT_MODE_POR: 0x00000005
[21962.823]CRP_RESET_REASON: 0x00000202
[21963.462]PMC_GLOBAL_PMC_MULTI_BOOT: 0xF0000000
[21964.242]PMC_GLOBAL_PWR_STATUS: 0x00000000
[21964.946]PMC_GLOBAL_PMC_GSW_ERR: 0x00000000
[21965.666]PMC_GLOBAL_PLM_ERR: 0x00000000
[21966.342]PMC_GLOBAL_PMC_ERR1_STATUS: 0x00000000
[21967.136]PMC_GLOBAL_PMC_ERR2_STATUS: 0x00000000
[21967.917]PMC_GLOBAL_GICP0_IRQ_STATUS: 0x20000000
[21968.713]PMC_GLOBAL_GICP1_IRQ_STATUS: 0x00000000
[21969.507]PMC_GLOBAL_GICP2_IRQ_STATUS: 0x00000000
[21970.307]PMC_GLOBAL_GICP3_IRQ_STATUS: 0x00000000
[21971.113]PMC_GLOBAL_GICP4_IRQ_STATUS: 0x00000000
[21971.921]PMC_GLOBAL_GICP_PMC_IRQ_STATUS: 0x00000000
[21972.767]============Register Dump============
This is due to default QEMU_HW_DTB_PS used from versal-generic.conf
file doesn't work for VMK180 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vmk180.dtb.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Update QEMU_HW_DTB_PMC to use board-versal-pmc-virt.dtb instead of
board-versal-pmc-vc-p-a2197-00.dtb as board-versal-pmc-vc-p-a2197-00.dtb
dtb targets tenzing board.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
mtd: spi-nor: Remove SPI_NOR_OCTAL_READ flag
soc: zynqmp: Add the IDcode for TEG variant
zlib: Remove incorrect ZLIB_VERSION
zlib: Port fix for CVE-2016-9841 to U-Boot
zlib: Rename write variable to wnext (window write index)
zlib: Rename this variable to here (current decoding table entry)
configs: versal: Disable the config for spansion flash
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m25p80: Consider 4byte address for octal ddr mode
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vck190: Add 2g OSPI flash
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versal: Add support for xqvm1102, xqve2102, xqvp2502, xqvp1052 and xqve2302
versal: Add support for xave2602 and xave2802
versal: SE variants support
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versal: Add support for the SE variant of xcvp1002
versal: Add support for the SE variant of xcvm2152
versal: Add support for xcvm2152
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1. Update versal dfx static and partial load instructions.
2. Add Versal segmented configuration load instructions.
3. Also update zynqmp logs.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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1. Make bit or bin or pdi as required input for firmware recipes. If bit
or bin or pdi of respective soc_family is not included then raise
bitbake parse skip recipe errors.
2. Check for absolute dtbo/bin/bit path if any of these files exits
in SRC_URI.
3. Skip recipe if both dtbo and dts/dtsi found in SRC_URI.
4. Fix logic to convert from bit to bin for zynqmp or zynq soc family.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
Configure both channel IDs for aie_trace & aie_profile (#8038)
Fix bug in Edge sw_emu flow (#8044)
add cmake definition for linux builds (#8042)
Improvements to AIE trace on clients (#8039)
Fixing the map operator logic (#8040)
Implementation of Hip stream apis (#8018)
Hip test tidy up (#8029)
Simplifying hip memory APIs interfaces. (#8037)
CR-1192489: Memory Module Metric Event IDs are produced in tiles where no Mem
Port kernel driver to Linux 6.8 (#8005)
Fix on client to correct partition info device query request (#8033)
VITIS-11112 HIP Binding: Memory Management. (#7983)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add a version header file in plain text format required for Versal
machines using the optional data field in the BIF file for version
information
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
(cherry picked from commit c6ae24ee38a69e4bcd463337aed43276d70845df)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add optional data section to BIF file generation code to be used with
version or other information
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
(cherry picked from commit cdeb46c57358e579be9f1c1be95a544fd0e713e4)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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missing one commit form latest
d67410d openamp: xlnx: Update model parsing
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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FAL now has a compile switch when compiling for Linux platforms, this
change will enable this flag when compiling FAL examples.
Signed-off-by: Gregory Williams <gregory.williams@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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apps: zynqmp_r5: zynqmp: Add default values in case they are missing in BSP
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driver: src: Remove old resource manager code
fal: src: rsc: Fix broadcast all bug for Linux backend
fal: src: rsc: Add error logs for all resource types
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OpenAMP passthrough to a domU
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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sw_apps: zynqmp_pmufw: Add ipipsu driver dependency in metadata file
sw_apps: versal_psmfw: Add ipipsu driver dependency in metadata file
sw_services: xilpm: Add ipipsu driver dependency in metadata file
tmrctr: Update examples to complete execution within 1 seconds
scripts: pyesw: create_bsp: Update the top-level CMake file to include the bsp include folder
scripts: pyesw: Generate preprocessed file always inside domain directory
emacps: Fix the mask for XEmacPs_BdGetBufAddr
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d67410d openamp: xlnx: Update model parsing
9e880fa openamp: xlnx: remove a2197
e4b6f3b lopper: assists: gen_domain_dts: Update symbol node entry for gic_its node
5069563 base/phandle: add resets and assigned-clocks
4d61969 lopper: assists: gen_domain_dts: Add option to keep TCM nodes
5666b57 lopper: assists: baremetal_validate_comp_xlnx: Update the assist to handle use cases where dev_type is missing in the driver yaml
88f9171 lopper: assists: baremetal_validate_comp_xlnx: Update mem_type check for microblaze_riscv
fa2aab9 lopper: assists: baremetal_xparameters_xlnx: Generate reg and interrupt defines for all possible ranges
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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when user changes any config in u-boot menu config then
we are saving that in user-<timestamp>.cfg.
While adding that user*.cfg to SRC_URI space is missing
and it was treated as different file and getting compilation issue.
The space missed in below line
meta-xilinx/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc#L19.
Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add Xen INITRD image creation steps for JTAG or SD INITRD
boot modes.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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1. Add missing xen jtag boot steps.
2. Add info on how to calculate zynqmp xen image offset for JTAG boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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1. Add missing xen jtag boot steps.
2. Add info on how to calculate Versal xen image offset for JTAG boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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This reverts commit 1c8cb60444e8e5170a46ae8a5657e164f6657f37.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
VITIS-9887: xrt support for multiple graph linking and compilation (#8030)
VITIS-11100 Display all AIE columns (#8015)
VITIS-11102 Remove device status from Ryzen report json (#8031)
Providing build metadata to version file (#8028)
initial trace updates for client (#7980)
removed debug line (#8026)
Only use the XDP Static DB methods supported for Client Flow in ML Timeline Plugin (#8025)
adding new job notify-slack (#8019)
Incorporate partition shifts and support ML metadata (#8021)
Adjusting build number for TA to pick up the build (#8024)
Add noshim to ishim. Next maybeshim? (#8023)
Handle an error for aie_trace plugin on client (#8020)
Update cmake to pick up HIP header files from Linux distribution area… (#8022)
Update Aie Enums to be compatible with future changes (#7910)
XRT support for independent AIE graph compilation and linking (#7999)
Change Shell name for RAVE Platform (#8017)
HIP tests for GPU and other build improvements (#8008)
VITIS-11114 - Command, Event, kernel_start, and copy_buffer classes and Event API Implementation Part1 (#8007)
VITIS-11369 Improve get xclbin name method (#7997)
Hide symbols from xrt.h header (#7998)
Added variable to store the actual buffer size in xobj (#8014)
Adding os_ver in matrix (#8016)
removed headers related to xcl apis from xdp code (#8009)
patch fix for build number for windows (#8013)
Modifying build number and fix SJ release intermittent issue (#8012)
add xrt::elf raw elf data constructor (#7963)
master pipeline for xrt in Gh actions (#8004)
Do not move an r-value (#8003)
Update license (#8001)
Adjustments to identifying, handling, and reporting active core/memory modules in AIE profile & trace (#7990)
Adjusting profiling API logging to account for recursive calls to monitored APIs (#8000)
CR-1123282 - Use get_size sdr request to receive sensor (#7944)
Update skd files to remove xcl apis (#7995)
Replacing xcl Apis : xclDeviceInfo2 and xclGetSysfsPath (#7994)
calculate correct global index for event tiles vector (#7991)
Workaround to limit Aperture Size Limit as part of QDMA Queues for SOFT QDMA IP. (#7979)
CR1178636: AIE Memory Read Throughputs are 0 (#7981)
VITIS-11517 Remove ReportMemory from Ryzen in XRT (#7978)
change buf size to decrease throughput (#7986)
fix for IVT failure (#7989)
Further cleanup of xcl apis for pcie build (#7988)
VITIS-11114 - HIP API initial Implementation (#7951)
Use xrt::ip to read registers for XDP PL Deadlock Diagnosis (#7984)
Replace xclOpen/Close in XDP (#7985)
Fix seg fault when device not available is provided (#7972)
VITIS-9706: xrt support for adf event apis (#7926)
VITIS-11418 Upgrade AIE partition report. (#7976)
Fix TXT tests for Linux (#7982)
libqdma: Updating QDMA to its latest commit (#7977)
Initial implementation of Hip module and function apis (#7964)
xclbinutil changes to support multiple aie.resources.bin (#7970)
CRs 1191344 & 1190977 - Bug fixes for AIE profile/trace on Edge (#7974)
Move metadata Reader to static database (#7949)
Add an aie trace timestamp binary data format (#7966)
build number is - ${{ github.run_number }}_${{ github.run_attempt }} (#7969)
Fixing clock rate retrieval in case of zero (#7975)
Delete .github/workflows/xrt-pr-comment-ci.yaml (#7973)
CR-1191367 Use PCI revision ID and deivce ID to identify device (#7971)
Clean up hip tests to please clang-tidy (#7965)
VITIS-11112 HIP Binding: Memory Management (#7929)
Seperated bar mapping from probe in the xbmgmt driver. (#7927)
xbutil fix help menu (#7960)
XRT build drops a kernel-doc directory in the PWD (#7935)
add initial support for transforming PDIs in AIE_PARTITION (#7954)
Use debug_ip_layout_path device query in place of xclGetDebugIPlayoutPath (#7962)
Enable clang-tidy for hip tests (#7943)
using branch for test summary instead of version (#7961)
Updating trace clock for PL (#7959)
CR-1190692 Add method to set read range on xrt::ip (#7957)
CR-1187549 (#7956)
Add support for debug buffer object in XRT for internal use (#7955)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Building libmetal and openamp using poky core-image-minimal requires
providers, Hence set default libmetal and openamp provider.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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meta-xilinx-standalone-experimental failes to parse with below errors
ERROR: No recipes in default available for:
/scratch/sandeep/yocto/2024.1/yp-bc/sources/poky/../meta-xilinx/meta-xilinx-standalone-experimental/recipes-openamp/libmetal/libmetal-xlnx_%.bbappend
/scratch/sandeep/yocto/2024.1/yp-bc/sources/poky/../meta-xilinx/meta-xilinx-standalone-experimental/recipes-openamp/open-amp/open-amp-xlnx_%.bbappend
Hence add openamp-layer dependency to LAYERDEPENDS variable.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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