| Commit message (Collapse) | Author | Age | Files | Lines |
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xilpm: versal_net: server: fix gcc warnings
sw_services:xilnvm:Fix bug in reading PUF secure control bits
bsp: standalone: Fixed source code-format issue.
zynqmp_rpu_bsp: Fix standalone coverity static analysis
sw_services: xilmailbox: Updated XIpiPs_PollforDone logic to improve AES client performance
sw_services: xilsecure:Fixed MISRA C violation for Rule 10.3
sw_services: xilsecure:Fixed MISRA C violation for Rule 12.2
sw_services: xilsecure:Fixed MISRA C violation for Rule 2.5
sw_services: xilsecure:Fixed MISRA C violation for Rule 12.1
sw_services: xilsecure:Fixed MISRA C violation for Rule 8.3
csudma: examples: Add support for system device-tree flow
csudma: Format examples using checkpatch
scugic: Initialize priority of SGI and PPI interrupts
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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gen_yocto_machine.py: Add config option for INCLUDE_MACHINE_NAME
gen-machineconf: Update Copyright year
gen_yocto_machine.py: Include SOC_VARIANT specific machine file
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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1. Add AMD Copyright notice.
2. Fix pdi_path typo in usage.
3. If dt-processor is run with two different zynqmp/versal sdt dts
then <cpu>-linux.dts and multiconfig dts were overwritten.
Generate dts files in build/conf/dts/<machine_name>/ directory
instead of build/conf/dts. This way when user use same build
directory for building different machine target it will avoid
overwriting dts files.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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The xrt_git.bbappend was in the wrong directory and was not applying the
correct changes to enable the AI Engine. Move the bbappen into the xrt
subdirectory will correct this.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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sw_services: xilloader: Redundancy check implemented incorrectly
xilloader: versal_net: Added support for cluster flags in ATF handoff params
xilpm: versal_net: server: add PMC_GPIO device in pre-alloc list
xilplmi: Update default WDT timeout for VERSAL_NET
sw_services:xilsecure:Fix xilsecure sha client example failure
csudma: Fix Assert condition in XCsuDma_Transfer for VERSAL_NET
lib: bsp: standalone: Update R5 ZyqnMP CMakeLists.txt as per latest soucre file
xilplmi: versal_net: Fix PMC IRO frequency logic
zynqmp_pmufw: Remove API ID enum
xilpm: versal: common: Remove API ID enum
xilpm: versal_net: common: Remove API ID enum
xilpm: zynqmp: client: Remove API ID enum
lib: bsp: standalone: Move API ID enum to common place
prd: Increment driver version, copyright and addtogroup version
prc: Increment driver version, copyright and addtogroup version
dfxasm: Increment driver version, copyright and addtogroup version
devcfg: Increment driver version, copyright and addtogroup version
sw_apps: img_rcvry: Added support for kd240 boards
lib: sw_apps: freertos: Enable lwip examples for Versal-Net
lib: sw_apps: Enable lwip standalone examples for Versal-Net.
lwip213: Add Versal-Net support for PS GEM.
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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get_config.py: Display stdout in run_cmd
Remove unused IMAGE_FSTYPES assignment
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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versal: Add support for xcvc1502
versal: Add support for xcvm1302
versal: Add support for xcvm1402
versal: Add support for xcvp1502
versal: Add support for xcvm2302
versal: Add support for xcvm2902 device
versal: Add support for xcvp1702 device
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/nvram: Add get_u32 abstraction to Xilinx eFuse
xlnx-efuse: Add get_u32 abstraction
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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mdio: handle 16 bit mdio writes
versal: efuse: Block reset from setting 2 registers
hw/nvram: Fix incorrect guest-error log from Xilinx Zynqmp eFuse
hw/nvram: Fix incorrect guest-error log from Xilinx Versal eFuse
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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gen_config.py: Generate TUNE_FEATURES based on XSA params
gen_plnx_machine.py: regenerating the configs
gen_config.py: adding new type to get_config_value
gen_plnx_machine.py: Reformat using autopep8
gen-machineconf: Update --menuconfig arg
gen_config.py: Generate the multi config targets dynamically
config_zynqmp:remove the default muticonfig targets
config_versal:remove the default muticonfig targets
Kconfig.part:remove static yocto multiconfigs
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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sw_services:xilloader:Add partial pdi loading from Image Store
BSP: cortexr5: Separate out CortexR52 MPU APIs
asm_vectors: fix kernel boot header
sw_apps: zynqmp_pmufw: Add support of parallel build
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Changes from 2023.1 branch:
arm64: dts: versal-net: Fix msi controller node name
arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb
arm64: xilinx: Fix indentation and trailing spaces in dts
arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
arm64: zynqmp: Assign TSU clock frequency for KR260
arm64: zynqmp: Remove interrupt/reg-names for AMS
arm64: zynqmp: Rename ams_ps/pl node names
arm64: zynqmp: Remove ltc2954 node from DT
arm64: zynqmp: Fix gpio comment about No of gpios
Revert "spi: zynqmp_qspi: Remove enabling interrupts code"
arm64: zynqmp: Update the i2c0 node for zcu1285
arm64: versal_net: Update RMII property
arm64: versal-net: Update spi-tx-bus-width to 4
arm64: versal-net: Update spi-max-freq to 150Mhz
arm64: versal-net: Add new parallel DT binding for tenzing se9 board
arm64: zynqmp: Add new parallel DT binding for ZC1751+DC1 board
arm64: versal: Enable ADIN ethernet phy
arm64: zynqmp: Enable ADIN ethernet phy
arm64: versal-net: dts: add cpuidle node
cmd: sf/nand: Print and return failure when 0 length is passed
arm64: zynqmp: Fix User MTD partition size
xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
arm: xilinx: Setting default i2c clock frequency to 400kHz
arm: dts: versal-net: add usb-wakeup interrupt in dwc-xilinx core
arm: dts: versal-net: add ref_clk property for REFCLKPER calculation
test: py: tests: Add test case for USB device
test: py: tests: Add dhcp abort test
test: py: tests: Add pxe command test
Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Added changelog above.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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gen-machineconf: decode has been removed in python 3.10
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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lib: bsp: standalone: Include bspconfig.h in boot.S for system device-tree flow
lib: bsp: standalone: Use XScuGic_LookupConfigBaseAddr() API for xsct flow
Update addtogroup to Overview and AMD copyright
versal_rpu_bsp: Fixed some MISRA-C violations.
xilpm: versal_net: client: add idle call back support
zynqmp_pmufw: bypass smmu during suspend
Updated change logs for plm & its libraries
lib: sw_services: xiltimer: Fix ifdef check in the microblaze_sleep.c
lib: bsp: standalone: Fix race conditions in the versal r5 mpu.c
lib: bsp: standalone: Fix race conditions in the A72 translation table
update Embedded SW license file for 2023.1
Revert "XilinxProcessorIPLib: drivers: aiengine: Add support for system device-tree flow"
freertos: gicv3: check group 1 IAR in NS EL1 irq handler
iomodule: Updated data types for few variables.
iomodule: Typecasting condition expressions with bool.
iomodule: Added parentheses to Expressions.
iomodule: Added U to Numericals.
sw_services: xilplmi: Address third party review comments
sw_services: xilplmi: Fix third party review comments
xilsem: Add support for psxl IP name
sw_services:xilloader:updated examples to support versalnet
XilNvm:Voltage, Temp Monitoring before efuse program
lib: sw_apps: freertos_hello_world: Add support for system device-tree flow
ThirdParty: bsp: freertos10_xilinx: Add support for system device-tree flow
lib: sw_apps: memory_tests: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: iomodule: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: ipipsu: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: common: Add meta-data required for system device-tree flow
XilinxProcessorIPLib: drivers: tmrctr: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: scugic: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: csudma: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: ttcps: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: uartpsv: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: uartps: Add support for system device-tree flow
lib: sw_services: xiltimer: Add support for system device-tree flow
scripts: Add linker template and processor spec files
cmake: Add required cmake meta-data
lib: bsp: standalone: src: common: Much needed improvements in xinterrupt_wrap.c
lib: bsp: standalone: Add meta-data for the system device-tree flow
lib: bsp: standalone: Update common code to support system device-tree flow
lib: bsp: standalone: Add support for microblaze in system device-tree flow
lib: bsp: standalone: Add support for cortexr5 in system device-tree flow
lib: bsp: standalone: Add support for ARMv8 in system device-tree flow
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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name
libomxil-xlnx change:
chore: update to revision d20230406
libvcu-xlnx changes:
Update name of ctrlsw level test application binaries
chore: update to revision d20230406
Revert "Update name of ctrlsw level test application binaries"
vcu-firmware changes:
chore: update to revision d20230405
Signed-off-by: Neel Gandhi <neel.gandhi@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
(cherry picked from commit 2ba0c89b9aae7459b3d9e3c328c1db3fea4dc617)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
xlnx-efuse: Avoid unnecessary backstore write
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Update aiefal version to match what is present in Vitis tools.
Signed-off-by: Gregory Williams <gregory.williams@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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usb: dwc3: otg: Enable OTG support in dwc3-core driver
usb: dwc3: fixed OTG feature failure for xilinx platform
usb: dwc3: core: disable 3.0 clock when operating in 2.0 device mode
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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changelog :
CR-1150767 Fix for clock throttling documentation. (#7502) (#7505)
reporting 1 or 2 MEM tile channels (#7497)
Signed-off-by: rbramand <rbramand@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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rfdc: Enable workaround for a specific version of libidn.so needed by cmake
XilinxProcessorIPLib: drivers: aiengine: Add support for system device-tree flow
plm: versal: Remove xplm_modules from PPU1 RAM
XilinxProcessorIPLib: drivers: CMakeLists.txt: Add required cmake meta-data for libxil
xilpuf: Fix PUF auxiliary convergence error
versal_psmfw: versal_net: reduce partition count
xilpm: versal: server: Update BFR-B pre-config sequence
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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mtd: spi-nor: Fix flash lock failure in Macronix flashes
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Makefile: Add auto-gen-dts target
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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versal-pmx-iou-slcr: Init the mux configuration
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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fal: data: Update version to 1.4
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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xlnx_dp: fetch data after vertical sync
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Kconfig.part: Add config option for BB_NUMBER_PARSE_THREADS in tool
Kconfig-aarch64.part:Kconfig-arm.part: Update help section for package_feeds
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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changelog :
fix for channel numbers in MEM tiles (#7496)
CR-1159385: Finished BD event is missing for memtile trace for AIE-ML designs for input_channels (#7495)
Signed-off-by: rbramand <rbramand@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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versal_psmfw: versal_net: set local power state at last
emacps: example: Fix GEM1 base address check.
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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mtd: spi-nor: Fix flash protection failure on Winbond 16MB flash parts
net: axienet: Fix memory leak issue
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Inclusion of security_flags.inc lead to a number of problems with the
baremetal distributions:
*ARM v8*
aarch64-xilinx-elf-ld: testA53.elf: error: PHDR segment not covered by LOAD segment
aarch64-xilinx-elf-ld: warning: testA53.elf has a LOAD segment with RWX permissions
*ARM v7*
arm-xilinx-eabi-ld: .../aarch32-xilinx-eabi/usr/lib/thumb/v7-a+fp/hard/crtbegin.o:
relocation R_ARM_THM_MOVW_ABS_NC against `a local symbol' can not be used when
making a shared object; recompile with -fPIC
The configuration that works:
export CFLAGS=" -O2 -pipe -g -feliminate-unused-debug-types "
export CXXFLAGS=" -O2 -pipe -g -feliminate-unused-debug-types "
export LDFLAGS="-Wl,-O1 -Wl,--hash-style=gnu -Wl,--as-needed -Wl,-z,relro,-z,now"
export CPPFLAGS=""
Configuration that provides the warnings/errors:
export CFLAGS=" -O2 -pipe -g -feliminate-unused-debug-types "
export CXXFLAGS=" -O2 -pipe -g -feliminate-unused-debug-types "
export LDFLAGS="-Wl,-O1 -Wl,--hash-style=gnu -Wl,--as-needed "
export CPPFLAGS=""
The LDFLAGS was introdued by the security_flags.inc, the
SECURITY_CFLGAS:class-target ?= "" and
SECURITY_LDFLAGS:class-target ?= "" was supposed to prevent this, however
the cross compiler is built in the cross or canadian-cross or other
context and NOT target. Additionally the SDK environment is configured
in the nativesdk environment, so the default values may not match the
configured (target) compiler and CFLAGS. Removing security_flags.inc
resolves both of these issues, as the security flags don't really do
anything on a baremetal configuration, by default, anyway.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add version bump for 2023.1 release to ai-engine-driver and aiefal
Changelog:
driver: src: Update minor version for 2023.1
Signed-off-by: Gregory Williams <gregory.williams@amd.com>
Added SRCREV update
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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driver: src: Update minor version for 2023.1
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Revert "firmware: xilinx: znqmp_pm_init_finalize as late_initcall"
Revert "soc: xilinx: znqmp_pm_init_finalize as late_initcall of PM driver"
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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dfeofdm: Update documentation
lib: sw_apps: memory_tests: Update copyright year
lib: bsp: Added support to- use ttc as sleeptimer for cortexR52
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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sdps: Fix doxygen warnings
freertos10_xilinx: ARM_CR5: Use group 1 interrupts for CortexR52
scugic: Use IRQ for CortexR52 interrupts by default
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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mtd: spi-nor: Fix Flash protection failure on ISSI 1G flash parts
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Disable items that don't work on microblaze
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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While systemd is not recommended for use on microblaze, it does work.
However, additional configuration items are requried in this case. So
enable the minimum options, as defined from the systemd README file.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Rebase/rework microblaze patches for the latest systemd version
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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github.com no longer supports git protocol, enable https protocol
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Disable standard bitstream-extraction, the zybo-linux-bd recipe handles
this task.
Zybo-linux-bd is used to provide the reference files, but needs to provide
the files in the matching locations to other components.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Adding meta-xilinx-core was contaminating the PACKAGECONFIG hash when
building mesa-native. Workaround this by only adjusting the value
when class-target is defined.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Memory manger issue fixed for xbtest (#7492) (#7494)
Fixed CU context related issue. (#7487) (#7493)
2023.1 : Use correct BO handle to export and use the exported bo handle for AIE APIs for GMIO AIE Trace offload (#7491)
Signed-off-by: rbramand <rbramand@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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gen_config.py: Enabling ro for EXT4 boot
u-boot_bsp.tcl:processor.yaml: Remove config.mk from PetaLinux
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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