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* Updated SRCREV for 2022Sivaprasad Addepalli2021-11-291-1/+1
| | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> (cherry picked from commit 6e71b6801254a618761513f3e71a2aa565e86d10) Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2022Sivaprasad Addepalli2021-11-231-1/+1
| | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> (cherry picked from commit fbe2f95f885b2524f9235e3ce9a3624e79a80afd) Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* bootbin: Adjust BIF_PARTITION_ATTRMark Hatle2021-11-181-1/+19
| | | | | | | | | | | The order is critical for the system to boot properly. Add a comment explaing the requirements, making the various parts parameterized to allow the optional parameters to be adjusted. The bitstream element will typically be added by a bbappend in a layer such as meta-xilinx-tools. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2022Sivaprasad Addepalli2021-11-181-1/+1
| | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> (cherry picked from commit f4e22e0a2616d34248add50fd08b8fd9923bb8d4) Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2022Sivaprasad Addepalli2021-11-151-2/+2
| | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> (cherry picked from commit 5a464cd21783fb5ba3b648a2f69f663f13de990c) Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Move from 2021.2 to 2022.1Mark Hatle2021-11-153-0/+0
| | | | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com> (cherry picked from commit eef9f49887e2471768b649450a0769859fd63ba5) Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Convert to new override syntaxMark Hatle2021-11-154-11/+11
| | | | | | Fix various overrides that have been missed in previous conversion. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* arm-trusted-firmware.inc: Use atf MEM_BASE, MEM_SIZE from DDR only for zynqmpAshwini Lomate2021-11-151-2/+4
| | | | | Signed-off-by: Ashwini Lomate <ashwini.lomate@xilinx.com> Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-11-021-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Update to bootgen SRCREV to point to latest commit on branch.RamyaSree2021-11-021-1/+1
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-11-021-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* device-tree: Fix GPL-2.0 referenceMark Hatle2021-10-251-1/+1
| | | | | | The GPL-2.0 license was removed and replaced by GPL-2.0-or-later. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* arm-trusted-firmware: Move to latest srcrev for 2021.2Mark Hatle2021-10-251-1/+1
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* manual changes for overrides syntaxSai Hari Chandana Kalluri2021-10-061-2/+2
| | | | Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
* **TEMPORARY** atf: set ATF_MEM_BASE, ATF_MEM_SIZE to bypass size issues with ↵Sai Hari Chandana Kalluri2021-09-281-2/+2
| | | | | | | | | latest gcc version Set ATF_MEM_BASE, ATF_MEM_SIZE to bypass size issues with latest gcc version. Revert after ATF source code has upgraded to latest version Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
* manual changes for overrides syntax fixesSai Hari Chandana Kalluri2021-09-283-7/+7
| | | | Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
* Convert to new override syntaxSai Hari Chandana Kalluri2021-09-2818-128/+128
| | | | | | | | | | This is the result of automated script (0.9.0) conversion: oe-core/scripts/contrib/convert-overrides.py . converting the metadata to use ":" as the override character instead of "_". Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
* bootgen: Updated commit Id to point the release branchRamyaSree2021-09-281-2/+2
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* u-boot-xlnx: Update branch and SRCREV for 2021.2Mark Hatle2021-09-281-2/+2
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xilinx-bootbin: Adjust configuration to work on non-xilinx BSPMark Hatle2021-09-281-1/+1
| | | | | | | If BIF_PARTITION_ATTR is not defind, a python exception is generated. Set a default value or "" to avoid failure in the replacement function. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xilinx-bootbin: Make board specificMark Hatle2021-09-281-1/+3
| | | | | | | Depends on various board specific packages, so this must also be board specific. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-xlnx: Make board specificMark Hatle2021-09-281-0/+4
| | | | | | | Various parameters change and trigger rebuilds based on board specific dependencies. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* u-boot-zynq-scr: Sync with zynqmp-dr PACKAGE_ARCH mechanismMark Hatle2021-09-281-8/+6
| | | | | | | Use the same approach as fsbl and pmufw. The previous implementation could have picked the wrong PACKAGE_ARCH in some cases. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-zynq-uenv: Remove incorrect dependency processingMark Hatle2021-09-281-3/+0
| | | | | | | | | | An RDEPEND can not be turned into a DEPEND directly. Indirectly the system is capable of doing this via various mapping, but the function in use can not do this safely. Also move ultra96 firmware from RRECOMMEND to RDEPEND. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* bootgen: Update SRCREV to 2021.2 versionMark Hatle2021-09-281-2/+2
| | | | | | | | It appears the previous SRCREV is no longer present, update to latest srcrev. License change just updates the year. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* u-boot-zynq-scr: Remove fdt_high env from boot.scrRaju Kumar Pothuraju2021-09-281-21/+0
| | | | | | | | | | | As per the U-boot fdt_high and initrd_high got deprecated and need to use the bootm_low/bootm_size instead. to increase bootm_low address use the config value(CONFIG_SYS_BOOTMAPSZ) or define bootm_low in the boot script since this is a boot time generated values. Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* boot.cmd.ubifs: Rename QSPI_FIT_IMAGE_LOADADDRESS to FIT_IMAGE_LOADADDRESSRaju Kumar Pothuraju2021-09-281-3/+2
| | | | | Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-zyqn-uenv: Update KERNEL LOAD ADDRESS for zynqmpSandeep Gundlupet Raju2021-09-271-1/+1
| | | | | | | | | | | | | While booting aarch64 kernel it warns with below message. Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! Update KERNEL LOAD ADDRESS for zynqmp to 0x200000. There is a 2MB enforcement for aarch64 boot images. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-zyqn-scr: Update KERNEL OFFSET for versalSandeep Gundlupet Raju2021-09-271-2/+2
| | | | | | | | | | | | | While booting aarch64 kernel it warns with below message. [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! Update KERNEL OFFSET for versal to 0x200000. There is a 2MB enforcement for aarch64 boot images. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-271-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xilinx-bootbin: Support 'bitstream'Mark Hatle2021-09-271-1/+2
| | | | | | | Unlike the other recipes, there is no 'bitstream' recipe, everything is expected to provide "virtual/bitstream" instead. So allow this behavior. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* base-pdi: Warn the user earlier if config is missingMark Hatle2021-09-271-0/+5
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* device-tree: Create deploy link to DTBMark Hatle2021-09-271-1/+16
| | | | | | | Bootbin support requires the dtb to be available in the deploydir as 'system.dtb'. This matches existing meta-xilinx-tools behavior. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* extract-cdo: Move from meta-xilinx-toolsMark Hatle2021-09-271-0/+34
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Enabling bootbin wiring for decoupling flow for zynqmp and versalJaewon Lee2021-09-2710-131/+98
| | | | Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-08-07 00:25:21 +0000