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* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* lopper: update to latest latest SRCREVBen Levinsky2021-09-281-1/+1
| | | | | | | Update to match upstream repo of lopper. Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* linux-xlnx.inc: Fix reference to kernel branchMark Hatle2021-09-281-1/+1
| | | | | | | The reference was not used in any xilinx code, however external recipes may have relied on this value and loaded the wrong kernel. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xrt_git:zocl_git:update commitidrbramand2021-09-281-1/+1
| | | | | Signed-off-by: rbramand <rbramand@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* bootgen: Update SRCREV to 2021.2 versionMark Hatle2021-09-281-2/+2
| | | | | | | | It appears the previous SRCREV is no longer present, update to latest srcrev. License change just updates the year. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xrt: adding libffi and elfutils dependency for ps kernel supportch vamshi krishna2021-09-281-1/+1
| | | | | Signed-off-by: ch vamshi krishna <chvamshi@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* xrt_git:zocl_git:update commitidrbramand2021-09-281-1/+1
| | | | | Signed-off-by: rbramand <rbramand@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* ivas: Update SRC_URI and SRCREV for 2021pankajd2021-09-284-14/+11
| | | | | Signed-off-by: pankajd <pankajd@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* vcu: Updated SRCREV for 2021Mark Hatle2021-09-283-3/+3
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* lopper: Move to AUTOREV to fixed revMark Hatle2021-09-281-2/+1
| | | | | | Set to the latest maste rev Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* u-boot-zynq-scr: Remove fdt_high env from boot.scrRaju Kumar Pothuraju2021-09-281-21/+0
| | | | | | | | | | | As per the U-boot fdt_high and initrd_high got deprecated and need to use the bootm_low/bootm_size instead. to increase bootm_low address use the config value(CONFIG_SYS_BOOTMAPSZ) or define bootm_low in the boot script since this is a boot time generated values. Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* kernel-simpleimage.bbclass: Use proper variable to get the kernel image.Ashwini Lomate2021-09-281-2/+2
| | | | | | | This patch will use proper variable to get kernel image Signed-off-by: Ashwini Lomate <ashwini.lomate@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-281-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-282-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* vcu: Updated SRCREV for 2021Mark Hatle2021-09-281-1/+1
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* ivas: Updated IVAS Repo path and SRCREV for 2021pankajd2021-09-284-6/+6
| | | | | Signed-off-by: pankajd <pankajd@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* boot.cmd.ubifs: Rename QSPI_FIT_IMAGE_LOADADDRESS to FIT_IMAGE_LOADADDRESSRaju Kumar Pothuraju2021-09-281-3/+2
| | | | | Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-271-1/+1
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* qemu: Updated SRCREV for 2021Mark Hatle2021-09-272-2/+2
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-zyqn-uenv: Update KERNEL LOAD ADDRESS for zynqmpSandeep Gundlupet Raju2021-09-271-1/+1
| | | | | | | | | | | | | While booting aarch64 kernel it warns with below message. Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! Update KERNEL LOAD ADDRESS for zynqmp to 0x200000. There is a 2MB enforcement for aarch64 boot images. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* u-boot-zyqn-scr: Update KERNEL OFFSET for versalSandeep Gundlupet Raju2021-09-271-2/+2
| | | | | | | | | | | | | While booting aarch64 kernel it warns with below message. [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! Update KERNEL OFFSET for versal to 0x200000. There is a 2MB enforcement for aarch64 boot images. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Updated SRCREV for 2021Sivaprasad Addepalli2021-09-272-2/+2
| | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* lopper: Move to master branchAppana Durga Kedareswara rao2021-09-271-1/+1
| | | | | | master branch contains all the latest fixes/enhancments. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
* xilinx-bootbin: Support 'bitstream'Mark Hatle2021-09-271-1/+2
| | | | | | | Unlike the other recipes, there is no 'bitstream' recipe, everything is expected to provide "virtual/bitstream" instead. So allow this behavior. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* base-pdi: Warn the user earlier if config is missingMark Hatle2021-09-271-0/+5
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* device-tree: Create deploy link to DTBMark Hatle2021-09-271-1/+16
| | | | | | | Bootbin support requires the dtb to be available in the deploydir as 'system.dtb'. This matches existing meta-xilinx-tools behavior. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* extract-cdo: Move from meta-xilinx-toolsMark Hatle2021-09-271-0/+34
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* Enabling bootbin wiring for decoupling flow for zynqmp and versalJaewon Lee2021-09-2710-131/+98
| | | | Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
* Adding bootbin as is from xilinx-toolsJaewon Lee2021-09-275-0/+363
| | | | Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
* Update the lop file as per new cpu cluster namingNaga Sureshkumar Relli2021-09-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are changes in microblaze cpu cluster node_name and node_labels. so update the lop file accordingly to generate microblaze tune macros. Previously the microblaze.conf is generated like below For Versal: AVAILTUNES += "microblaze-cpu2" TUNE_FEATURES_tune-microblaze-cpu2 = " microblaze v10.0 barrel-shift pattern-compare reorder multiply-high divide-hard fpu-soft" PACKAGE_EXTRA_ARCHS_tune-microblaze-cpu2 = "${TUNE_PKGARCH}" TUNE_FEATURES_tune-pmc-microblaze = ${TUNE_FEATURES_tune-microblaze-cpu2} AVAILTUNES += "microblaze-cpu3" TUNE_FEATURES_tune-microblaze-cpu3 = " microblaze v10.0 barrel-shift pattern-compare reorder multiply-high divide-hard fpu-soft" PACKAGE_EXTRA_ARCHS_tune-microblaze-cpu3 = "${TUNE_PKGARCH}" TUNE_FEATURES_tune-psm-microblaze = ${TUNE_FEATURES_tune-microblaze-cpu3} For Zynqmp: AVAILTUNES += "microblaze-cpu0" TUNE_FEATURES_tune-microblaze-cpu0 = " microblaze v9.2 barrel-shift pattern-compare reorder fpu-soft" PACKAGE_EXTRA_ARCHS_tune-microblaze-cpu0 = "${TUNE_PKGARCH}" TUNE_FEATURES_tune-pmu-microblaze = "${TUNE_FEATURES_tune-microblaze-cpu0}" With the new changes the microblaze.conf is generated like below For Versal: AVAILTUNES += "microblaze-cpu0" TUNE_FEATURES_tune-microblaze-cpu0 = " microblaze v10.0 barrel-shift pattern-compare reorder multiply-high divide-hard fpu-soft" PACKAGE_EXTRA_ARCHS_tune-microblaze-cpu0 = "${TUNE_PKGARCH}" TUNE_FEATURES_tune-pmc-microblaze = "${TUNE_FEATURES_tune-microblaze-cpu0}" AVAILTUNES += "microblaze-cpu1" TUNE_FEATURES_tune-microblaze-cpu1 = " microblaze v10.0 barrel-shift pattern-compare reorder multiply-high divide-hard fpu-soft" PACKAGE_EXTRA_ARCHS_tune-microblaze-cpu1 = "${TUNE_PKGARCH}" TUNE_FEATURES_tune-psm-microblaze = "${TUNE_FEATURES_tune-microblaze-cpu1}" For Zynqmp: No change the cpu index is changed because the cpu@0 for cpus_microblaze is same for both pmc and psm, hence for better readability we updated the lop file to generate cpu0 for pmc and cpu1 for psm. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
* lopper: Move to master-next branchMark Hatle2021-09-272-1/+3
| | | | | | | | Master-next fixes some issues we were having. The new version also now requires the python 'humanfriendly' modules, so bbappend this to make it available to nativesdk and native. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* xilinx-lops: Fix missing " (quote)Mark Hatle2021-09-271-1/+1
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* xilinx-lops: Update to tag firmware microblaze configsMark Hatle2021-09-271-224/+178
| | | | Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
* lop-microblaze-yocto.dts: Adjust to current DTB formatMark Hatle2021-09-271-32/+45
| | | | | | Add support for PLM, PMU and PSM. Only ZynqMP processing currently works. Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-23 14:17:00 +0000