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* meta-xilinx-core: Bring in a copy of wic from pokyMark Hatle2025-03-3038-0/+11892
| | | | | | | Import a copy of wic and lib/oe as of poky commit: 8f74fa4073d4b2ba8e0d9559aa654f3cafcf373a Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* boot-jtag: Fix fpga-overlay typoSandeep Gundlupet Raju2025-01-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | boot-jtag script had a type for fpga-overlay and due to this it fails to build with below errors when fpga-overlay is enabled for zynqmp or versal devices. $ MACHINE=zynqmp-zcu104-sdt-full devtool boot-jtag --image core-image-full-cmdline --hw_server zcu104-5 NOTE: Starting bitbake server... NOTE: Started PRServer with DBfile: /scratch/sandeep/yocto/2024.2/yp-dev/build-yp-native/cache/prserv.sqlite3, Address: 127.0.0.1:33765, PID: 1586408 NOTE: Reconnecting to bitbake server... NOTE: Retrying server connection (#1)... (09:43:24.858854) NOTE: Started PRServer with DBfile: /scratch/sandeep/yocto/2024.2/yp-dev/build-yp-native/cache/prserv.sqlite3, Address: 127.0.0.1:35749, PID: 1586439 Loading cache: 100% |###############################################################################################################################################################################| Time: 0:00:06 Loaded 26502 entries from dependency cache. Parsing recipes: 100% |#############################################################################################################################################################################| Time: 0:00:02 Parsing of 18552 .bb files complete (18543 cached, 9 parsed). 26511 targets, 13521 skipped, 81 masked, 0 errors. INFO: HW_SERVER Connected to: zcu104-5 INFO: Using DISTRO IMAGE: core-image-full-cmdline INFO: SOC FAMILY: zynqmp INFO: MACHINE: zynqmp-zcu104-sdt-full INFO: fpga-overlay MACHINE_FEATURES is not enabled, Hence PL bitstream or PDI will be loaded at initial boot. Traceback (most recent call last): File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/scripts/devtool", line 350, in <module> ret = main() File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/scripts/devtool", line 337, in main ret = args.func(args, config, basepath, workspace) File "/scratch/sandeep/yocto/2024.2/yp-dev/sources/poky/../meta-xilinx/meta-xilinx-core/lib/devtool/boot-jtag.py", line 82, in bootjtag data['bit'] = glob.glob(os.path.join(deploy_dir, '*' + machine + '.bit'))[0] IndexError: list index out of range Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* boot-jtag.py: Add IMAGE_NAME_SUFFIX to tclSandeep Gundlupet Raju2024-08-161-1/+2
| | | | | | | | | | In scarthgap release, By default IMAGE_NAME_SUFFIX=".rootfs" set in image-artifact-name.bbclass, Due to this boot-jtag script doesn't include rootfs in .tcl script. Hence add IMAGE_NAME_SUFFIX to tcl script. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* boot-jtag.py: Remove stale importsAlain Péteut2024-06-201-10/+7
| | | | | | | | | | | | | | | | | Based on github Pull Request #61. 1. `yaml` is imported but not used. This may cause issues as `yaml` is not a standard library module. 2. Remove trailing newlines. Signed-off-by: Alain Péteut <alain.peteut@spacetek.ch> Update commit message and added PR number in commit message. Also update import list order. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* various: Remove SOC_VARIANT, split versal and versal-net, add machine_featuresMark Hatle2024-06-041-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY configuration. The defined families are: zynq, zynqmp, versal and versal-net. Our decision of breaking up versal-net from versal, is based on the SoC CPU changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a different SoC family. In order to capture the individual capabilities that we used to handle via SOC_VARIANT, we have defined the following features (some may have been previously defined): - mali400 (zynqmp eg and ev) - vcu (zynqmp ev) - rfsoc (zynqmp dr RF capabiltiies) - aie - (versal ai & premium) - vdu - (versal ai) SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by MACHINE_ARCH. This is based on the guideline that any recipes that use MACHINE_FEATURES should be MACHINE_ARCH specific. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* boot-jtag.py: Add devtool script for jtag boot modeSandeep Gundlupet Raju2024-03-151-0/+272
This script uses devtool and creates a boot-jtag.tcl script in ${DEPLOY_DIR_IMAGE} directory. This script is executed by xsdb tool to boot yocto generated images on HW via jtag boot mode. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>