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| * | | u-boot-xlnx-scr: add DEVICETREE_ADDRESS_SD variable in boot scriptSwagath Gadde2023-10-132-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to load the different DTB load address in SD boot mode using the DEVICETREE_ADDRESS_SD variable in generic boot script. use case: When TF-A is doing some runtime memory reservation and that can be hand-off to kernel by u-boot. so satisy that case in SD boot mode we should load kernel dtb at different address so that it dont override dtb packed in BOOT.BIN. Signed-off-by: Swagath Gadde <swagath.gadde@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | | u-boot-xlnx : Updated SRCREV for 2024.1_7279Sivaprasad Addepalli2023-10-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64: zynqmp: Remove kv260 PL overlays test: py: tests: Add test case to write and read multiple files from MMC test: py: tests: Extend i2c test to cover all buses spi: cadence_qspi: Fix versal ospi indirect write timed out issue configs: zynq: Disable the config CONFIG_SPI_FLASH_USE_4K_SECTORS spi: cadence_ospi_versal: Add support for 64-bit address arm64: zynqmp: Remove unused xlnx,phy-type DT property net: phy: xilinx_phy: Get rid of using property xlnx, phy-type Revert "arm64: zynqmp: Add the fclk node" arm64: versal-net: Add missing xlnx,versal-firmware string arm64: zynqmp: Add output-enable pins to SOM KD240 arm64: versal-net: Append xlnx,versal-clk to clock node arm64: zynqmp: Enable uart0 with pinctrl description arm64: zynqmp: Add support for K26 rev2 boards arm64: zynqmp: Setup default si570 frequency to 156.25MHz Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | | u-boot-xlnx : Updated SRCREV for 2024.1_3663Sivaprasad Addepalli2023-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | net: zynq_gem: Update the MDC clock divisor in the probe function Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | | u-boot-xlnx : Updated SRCREV for 2024.1_2411Sivaprasad Addepalli2023-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | net: phy: xilinx-gmii2rgmii: Removed hardcoded phy address 0 for bridge Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | | u-boot-xlnx : Updated SRCREV for 2023.2_2643Sivaprasad Addepalli2023-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64: versal-net: Add dts files for mini u-boot qspi and ospi configurations mtd: spi-nor: Update block protection flags for spansion flash Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | | u-boot-xlnx : Updated SRCREV for 2023.2_2883Sivaprasad Addepalli2023-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mtd: spi-nor: Fix the issi_get_locked_range api arm64: zynqmp: Add output-enable pins to SOMs cmd: sf: Fix the flash_is_unlocked api size parameter mtd: spi-nor: Fix the giga_get_locked_range api Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | | u-boot-xlnx-2024.1.inc: Update branch and SRCREV for 2024.1Sandeep Gundlupet Raju2023-09-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Branche xlnx_rebase_v2023.01 and master content are same but commit id's are different. Hence no change logs are added in commit message. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
| * | | boot.cmd.generic.root: Add kernel command line param supportSandeep Gundlupet Raju2023-09-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add kernel command line parameters support in boot.scr, With this user can append additional kernel command line parameters to existing bootargs. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | | u-boot-xlnx : Updated SRCREV for 2023.2_1791Sivaprasad Addepalli2023-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | arm64: versal-net: Fix sysmon interrupt number Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | | u-boot: Branch recipe for 2024.1 integrationMark Hatle2023-08-293-0/+42
| | | | | | | | | | | | | | | | Signed-off-by: Mark Hatle <mark.hatle@amd.com>
* | | | Merge remote-tracking branch 'github/rel-v2023.2' into master-nextMark Hatle2024-03-211-1/+1
|\ \ \ \ | | |_|/ | |/| | | | | | Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | | u-boot-xlnx : Updated SRCREV for 2023.2_3039Sivaprasad Addepalli2023-12-131-1/+1
| | |/ | |/| | | | | | | | | | misc: usb5744: Prevent the HUB from suspend mode Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
* | | Merge remote-tracking branch 'origin/rel-v2023.2' into nanbieldMark Hatle2023-10-238-30/+86
|\| | | | | | | | | | | Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | u-boot-xlnx : Updated SRCREV for 2023.2_3243Sivaprasad Addepalli2023-09-221-1/+1
| | | | | | | | | | | | | | | net: zynq_gem: Update the MDC clock divisor in the probe function Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | u-boot-xlnx : Updated SRCREV for 2023.2_8535Sivaprasad Addepalli2023-09-191-1/+1
| | | | | | | | | | | | | | | net: phy: xilinx-gmii2rgmii: Removed hardcoded phy address 0 for bridge Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | u-boot-xlnx : Updated SRCREV for 2023.2_2643Sivaprasad Addepalli2023-09-141-1/+1
| | | | | | | | | | | | | | | | | | arm64: versal-net: Add dts files for mini u-boot qspi and ospi configurations mtd: spi-nor: Update block protection flags for spansion flash Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | u-boot-xlnx : Updated SRCREV for 2023.2_2883Sivaprasad Addepalli2023-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | mtd: spi-nor: Fix the issi_get_locked_range api arm64: zynqmp: Add output-enable pins to SOMs cmd: sf: Fix the flash_is_unlocked api size parameter mtd: spi-nor: Fix the giga_get_locked_range api Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * | boot.cmd.generic.root: Add kernel command line param supportSandeep Gundlupet Raju2023-09-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add kernel command line parameters support in boot.scr, With this user can append additional kernel command line parameters to existing bootargs. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * | u-boot-xlnx : Updated SRCREV for 2023.2_1791Sivaprasad Addepalli2023-09-051-1/+1
| |/ | | | | | | | | arm64: versal-net: Fix sysmon interrupt number Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_3579Sivaprasad Addepalli2023-08-241-1/+1
| | | | | | | | | | arm64: zynqmp: Enable the config CMD_KASLRSEED Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_4615Sivaprasad Addepalli2023-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64:versal_net: Add jedec compatible string for SPI flash spi: spi-uclass: Add dev_read_u32() if reg property is not an array arm64: zynqmp: Update ECAM size to discover up to 256 buses dm: core: ofnode: Change the log message to debug clk: versal: Fix the function versal_clock_ref pinctrl: zynqmp: Add support for output-enable and bias-high-impedance pinctrl: zynqmp: Add version check for TRISTATE configuration firmware: zynqmp: Add support to check feature arm64: versal_net: Disable the lock option for mini ospi and qspi arm64: zynqmp: Disable the lock option for mini qspi arm64: versal: Disable the lock option for mini ospi and qspi mtd: spi-nor: Add spi flash lock config option spi: zynq: Clear flags to get updated value spi: zynqmp_qspi: Clear flag to get updated value Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx-scr: Refactor boot scr variables to make it easier to overrideSandeep Gundlupet Raju2023-08-191-15/+3
| | | | | | | | | | | | | | | | | | | | With the previous version by default xen variables are included in non xen use case, it would have been possible for kernel and devicetree offset can be override from meta-virtualization layer. With the new version add variables as addendum. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_3191Addepalli, Siva2023-08-181-1/+1
| | | | | | | | | | | | dm: core: ofnode: Change the log message to debug clk: versal: Fix the function versal_clock_ref Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| * u-boot-xlnx-scr: Add variables for xen bootSandeep Gundlupet Raju2023-08-141-0/+16
| | | | | | | | | | | | | | | | | | | | Add variables for xen u-boot script and define in meta-virtualization dynamic layer bbapends. Variables are set wtih weak default assignment. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx-scr: Set weak assignment for variablesSandeep Gundlupet Raju2023-08-141-101/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Variables set from dynamic layer bbappends will not take effect due softer assignment defined in u-boot-xlnx-scr.bb. Hence weak assignment should be set for variables in u-boot-xlnx-scr.bb file so that pre-expansion values are properly handled. This way variable value can be changed from dynamic layer bbapends or local.conf. Also fix indentation. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_8499Addepalli, Siva2023-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | pinctrl: zynqmp: Add support for output-enable and bias-high-impedance pinctrl: zynqmp: Add version check for TRISTATE configuration firmware: zynqmp: Add support to check feature arm64: versal_net: Disable the lock option for mini ospi and qspi arm64: zynqmp: Disable the lock option for mini qspi arm64: versal: Disable the lock option for mini ospi and qspi mtd: spi-nor: Add spi flash lock config option Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_3819Addepalli, Siva2023-08-081-1/+1
| | | | | | | | | | | | | | | | spi: zynq: Clear flags to get updated value spi: zynqmp_qspi: Clear flag to get updated value xilinx: board: Add support to pick bootscr flash offset/size from DT dm: core: ofnode: Add ofnode_read_bootscript_flash() Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_6015Addepalli, Siva2023-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi: zynqmp_qpsi: Enable invalidate_cache for ZynqMP and Versal xilinx: board: Add support to pick bootscr address from DT dm: core: ofnode: Add ofnode_read_bootscript_address() Revert "arm64: xilinx: Replace _ from clock node names by -" arm64: zynqmp: Get clock node name back with _ arm64: versal: Increase the number of DRAM banks to 36 spi: zynq: Configure lqspi register based on memory configuration arm64: versal-net: Add sysmon node entry xilinx: zynqmp: Do not setup boot_targets if driver is not enabled xilinx: versal: Do not setup boot_targets if driver is not enabled xilinx: versal-net: Do not setup boot_targets if driver is not enabled arm64: xilinx: Do not use _ in DT node names arm64: zynqmp: Use s/gtr_sel/gtr-sel/ for DT node name arm64: zynqmp: Use s/heartbeat_led/heartbeat-led/ for DT node name arm64: xilinx: Replace _ from clock node names by - arm64: zynqmp: Rename xlnx,mio_bank to xlnx,mio-bank for DLC21 arm64: versal-net: Remove xlnx,device_id property from VNX arm64: versal-net: Remove ref_clk node from VNX board mtd: spi-nor: Update block protection flags for flash parts net: zynq_gem: Add missing newline (upstream sync) xilinx: versal-net: Remove additional newline in board.c spi: spi-uclass: Dont return error for single cs spi: spi-uclass: Move restricting multi_cs_cap code dm: core: Remove debug print from of_read_u64_index mtd: spi-nor: Add support for locking on Spansion nor flashes mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes mtd: spi-nor: Add support for locking on ISSI nor flashes mtd: spi-nor: Add support for locking on Macronix nor flashes clk: zynqmp: Add gem rx and tsu clocks to return register clk: zynqmp: Add set_rate support for gem rx and tsu clks arm64: zynqmp: Add resets property for CAN nodes spi: zynq: Add support for parallel-memories and stacked-memories spi: zynqmp_qspi: Add parallel memories support in GQSPI driver spi: spi-uclass: Read chipselect and restrict capabilities mtd: spi-nor: Add parallel and stacked memories support in spi-nor dm: core: support reading a single indexed u64 value Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
| * u-boot-xlnx-scr: Add PRE_BOOTENV variable for boot cmd filesSandeep Gundlupet Raju2023-07-254-0/+8
| | | | | | | | | | | | | | | | | | Based on github Pull Request #34. While that pull request is no longer valid with other changes, the actual bug still exists. Originally reported by Felix S(ubfx). Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
| * Add a check for uboot-device-tree dtbTejas Bhumkar2023-07-251-2/+2
| | | | | | | | | | | | | | | | | | Added below changes: 1)Updated operator in if condition from `==` to `=` as it is used for string comparison in both Bash and Dash, making the script compatible with both shells. 2)Checking for uboot-device-tree.dtb file in RECIPE_SYSROOT path before applying fdtoverlay. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_2183Sivaprasad Addepalli2023-07-141-1/+1
| | | | | | | | | | | | | | arm64: zynqmp: Remove USB description from SC revB/C test: py: tests: Add qspi negative tests test: py: tests: Add qspi flash lock/unlock test Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_5375Sivaprasad Addepalli2023-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | clk: Dont return error when assigned-clocks is empty or missing xilinx: zynq: Enable fdt apply utility for zynq env: Fix default environment saving issue zynqmp: config: Add proper dependencies for USB cmd: thordown: Add proper dependency for CMD_THOR_DOWNLOAD dfu: Add proper dependency for CONFIG_DFU_MMC usb: xhci: Fix the missing return statement Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx-scr: Add support to use uboot env variable at builtRaju Kumar Pothuraju2023-07-051-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current boot.scr recipe implementation supports the fixed offsets. Add support to use the uboot env variables to load the images. If offsets starts from '$' sign considering it as a uboot env. Example for SC BSPs(using fitblob) uboot will redirect the dtb to $fdtcontroladdr, so our boot script DT address also should point to the same. In .conf: DEVICETREE_OFFSET:<soc> = "$fdtcontroladdr" In boot.scr: <bootcmd> 0x00200000 0x04000000 $fdtcontroladdr Remove the DEVICETREE_OVERLAY_ADDRESS dependency with DEVICETREE_ADDRESS as it may fail if you point uboot env variables(reserved memory). Adding new variables DEVICETREE_OVERLAY_OFFSET - To specify DTB overlay offset which will add to DDR base address. DEVICETREE_OVERLAY_PADSIZE - To specify the offset from overlay_offset to load dtbo file. Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_1639Sivaprasad Addepalli2023-07-051-1/+1
| | | | | | | | | | | | arm64: versal-net: add usb-wakeup interrupt in dwc3 core arm64: versal: Add no-wp DT property in OSPI flash node Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * boot.cmd.generic: Update bootargs with launch_ramdisk_initRaju Kumar Pothuraju2023-06-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Map uboot env variable launch_ramdisk_init with bootargs to stop at tiny rootfs. If user specified bootargs at uboot skip appending auto bootargs. Using fdtcontroladdr uboot variable instead of hardcoded value in boot.scr. If DTB loads from FAT to DDR from uboot fdtcontroladdr points to old dtb(loaded from boot.bin or uboot.elf) so updating it with the dtb load address. Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx : Updated SRCREV for 2023.2_1551Sivaprasad Addepalli2023-06-261-1/+1
| | | | | | | | | | | | arm64: versal_net: Update SPI node for se7 mtd: spi-nor: Add support for w25q256jwm Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_8771Sivaprasad Addepalli2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | net: zynq_gem: Don't hardcode the MDC clock divisor spi: zynqmp_qspi: Workaround for small data cache issue spi: zynqmp_qspi: Change flush cache to invalidate cache arm64: versal-net: Add LPD-WWDT to versal-net.dtsi include: dt-bindings: power: Add TCM,RPU nodes for Versal NET arm64: versal: Add DT description for CPM5 Root port for Versal Premium arm64: versal: Add missing DT properties to cpm_pciea arm64: versal: rename CPM interrupt-controller arm64: versal-net: Add support for VNX board arm64: versal: Switch to new wwdt DT binding Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx-scr: Add KERNEL_COMMAND_APPENDJohn Toomey2023-06-191-0/+4
| | | | | | | | | | | | | | Allow appending to the kernel command line in boot.scr Signed-off-by: John Toomey <john.toomey@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_5419Sivaprasad Addepalli2023-06-141-1/+1
| | | | | | | | | | | | | | | | | | watchdog: versal: Use new compatible xlnx,versal-wwdt arm64: zynqmp: In sc-revB dts add mtd partition for secure OS storage area mtd: spi-nor: Send write enable cmd before write to SR2 usb: xhci: Workaround to fix the USB halted endpoint issues arm64: dts: zynqmp: make hw-ecc as the default ecc mode Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_6275Sivaprasad Addepalli2023-06-081-1/+1
| | | | | | | | | | | | | | arm64: zynqmp: Fix lockstep mode cpu release functionality arm64: zynqmp: Fix tcminit mode param arm64: versal-net: spi: Update boot sequence dynamically Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_5115Sivaprasad Addepalli2023-06-061-1/+1
| | | | | | | | | | | | | | test: py: tests: Add test case for loading RPU apps test: py: tests: Add test case for saveenv command arm64: zynqmp: Fix the memory node for k26/k24 kria som boards Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx-blob: Error if CC_DTBS_DUP file missingJohn Toomey2023-06-011-0/+2
| | | | | | | | | | | | | | | | When processing all of the entries in CC_DTBS_DUP an error should be thrown if the target dtb file is not found. Signed-off-by: John Toomey <john.toomey@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_8447Sivaprasad Addepalli2023-05-311-1/+1
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_6211Sivaprasad Addepalli2023-05-311-1/+1
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_4071Sivaprasad Addepalli2023-05-301-1/+1
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * Updated SRCREV of u-boot-xlnx for 2023.2_2199Sivaprasad Addepalli2023-05-271-1/+1
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * u-boot-xlnx: Move to 2023.2 rebase branchMark Hatle2023-05-241-2/+2
| | | | | | | | Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * Updated SRCREV for 2023.2_3567Sivaprasad Addepalli2023-05-191-1/+1
| | | | | | | | Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| * meta-xilinx-core:boot.cmd.generic: update boot script.Swagath Gadde2023-05-171-1/+1
| | | | | | | | | | | | | | update the generic boot script to support xspi1 for versal-net platform. Signed-off-by: Swagath Gadde <swagath.gadde@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| * u-boot-xlnx: Rename DTB_NAME to DTB_FILE_NAMEMark Hatle2023-05-132-7/+7
| | | | | | | | | | | | | | Match the variable naming used in device-tree recipe, functionality remains the same. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-24 03:18:15 +0000