| Commit message (Collapse) | Author | Age | Files | Lines |
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The merge commit, 2bbe53c463daf01de661a905e08461231b6ad8f1, accidently 'renamed' the 2023.1
version instead of just adding the new 2024.1 version. Restore, unmodified, the last
2023.1 version.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
fixed the incorrect sysfs path (#8182) (#8184)
Signed-off-by: saumya garg <saumya.garg@amd.com>
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Changelog:
Fix for CR-1182821: AIE Status was unable to get good data and was outputting empty files (#8178) (#8181)
enablign rtp updates from alias name also (#8167) (#8168)
Signed-off-by: saumya garg <saumya.garg@amd.com>
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Changelog:
fixing reserved memory logic (#8164) (#8165)
Fixed rw_shared flag for user managed kernel (#8158) (#8162)
Add instructions for installation of xrt package on Alma Linux (#8156) (#8159)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Updated commit message
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Revert "configs: versal: Enable CONFIG_LTO for mini qspi/ospi"
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Changelog:
Run on centos 8.1 tests (#8151)
Fix for CR-1178294: XRT AIE Status .json file does not include tile information for a tile where only memory is used (#8147) (#8150)
giving default value for event column (#8144) (#8146)
CR-1199552: Fixing mem-bw test for RAVE (#8123) (#8130)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
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Changelog:
replacing DMA events for PLIO in profiling (#8132)
fixing issue in adf::event crash (#8119) (#8120)
cover all stream switch port events (#8118)
ZOCL version adjusted to 2.17 for 2024.1 (#8114) (#8115)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
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Changelog:
lopper: assists: Add num-insts to rfdc node
lopper: Update check to adjust DDR start and size address
lopper: fix incorrect warning log
lopper: assists: baremetallinker: Adjust heap size for microblaze lmb_bram designs having size less than 8k
Signed-off-by: Conall O'Griofa <conall.ogriofa@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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driver: src: io_backend: Disabled shim reset bit in _XAie_PrivilegeRstPartShims API.
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driver: src: timer: Setup two broadcast channels for timer sync.
driver:src:Fixed some softpartition getting isolated wrongly.
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apps: zynqmp_r5: zynqmp: Update #ifndef wrappings for RPU1
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Updated latest branch commit id
Signed-off-by: Ramya Darapuneni <ramya.darapuneni@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
master pipeline for 2024.1 (#8087)
CR-1186952 (#8111)
Removing unnecessary include file that was causing problems on non-edge builds (#8107)
XRT Support for EEMI based PMC SRST (system reset) CR-1183722 (#8096)
CR-1189791 Update OS Support in XRT Docs (#8097)
Fix GeMM coverity (#8104)
CR-1194229: Removed json file dependency for the AIE-PL test (#8095)
Move dmatest.h dependency to fix build issues (#8103)
Enhancing mem-bw testcase to print individual bank name and throughput. (#8101)
fixing rw_shared configuration in xgq based flow (#8102)
fix to select both channels as default (#8082)
GeMM testcase (#8058)
reduce the number of iterations for throughput test to 1000 (#8091)
fixing an ISR issue in ctrl_none case (#8094)
Fixing extraction logic (#8100)
fix for centos78 issue (#8099)
using right column for broadcasting start core (#8092)
Remove MaxPower from electrical report for Ryzen (#8088)
Silence C++ [[nodiscard]] warning (#8090)
More clang-tidy cleanups of HIP code and a major bug in new PDI transform error handling path (#8086)
integrate aie-pdi-transform into xclbinutil (#8011)
Manticfixes (#8084)
CR-1197359: Modifying XRT codebase to send absolute tile column value to AIE driver (#8080)
Client AIE improvements (#8056)
aie core tile status report fix due to relative values of column in xclbin (#8081)
Temporarily disable telemetry report for RyzenAI (#8078)
VITIS-11824 Consolidate examine and platform reports (#8077)
Building Hip in XRT as part of Ubuntu 2204 (#8079)
VITIS-11639 Small Enhancements to xbutil validate description (#8075)
Fix for CR:1194572-XRT stop_profiling API error (#8074)
Completed HIP Command Related Functions (#8041)
Non-client AIE improvements (#8055)
Add missing include (#8068)
VITIS-11112 HIP Binding: Memory Management. (#8050)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Move to xlnx_rel_v2024.1 Branch.
Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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drivers: crypto: xilinx: Add support for do_one_request
mtd: spi-nor: gigadevice: Disable 16bit SR operation for gd25lx256e flash
mtd: spi-nor: Fix RX tuning failure for OSPI flashes connected in stacked mode
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drivers: crypto: xilinx: Fix the request size
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driver: src: Added StarCol in XAie_GetTileBitPosFromLoc for non-zero partition and correction in SetColumnClk for set & cleat Bitmap.
driver: src: Remove resource files from CMake
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phy: xilinx-xhdmiphy: Add support for FRL 6G 3-lane mode
phy: xilinx-xhdmiphy: Fix bug in xhdmiphy_rpll_param function
phy: xilinx-xhdmiphy: Fix configuring retimer chip in HDMI 2.1 mode
phy: xilinx-xhdmiphy: Clear all the config flags after being served
phy: xilinx-xhdmiphy: Select FRL clock source after configuring in HDMI 2.1 mode
firmware: xilinx: Fix feature check for crypto drivers
usb: udc: remove warning when queue disabled ep
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Fixed buildpath QA warning
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mtd: spi-nor: Fix OSPI probe issue in stacked mode.
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fal: src: Fix combo event resource ID
driver: src: io_backend: Clear TileInUse Bitmap _XAie_PrivilegeInitPart API
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misc: rsmu: add rsmu cdev driver
ptp: 82p33: move register definitions out of ptp folder
mfd: rsmu: add FemtoClock3 support
mfd: rsmu: support I2C SMBus access
ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h
ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO]
ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns
ptp: clockmatrix: set write phase timer to 0 when not in PCW mode
ptp: clockmatrix: support 32-bit address space
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Revert "Revert "lmb: consider EFI memory map""
common: fdt: replace error prints to debug
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The hard coded PV = '3.3' does not match the recipe version which is 3.5.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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drivers: mailbox: handle SGI for shared IPI
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spi: cadence_qspi: Fix OSPI probe issue when the prescaler is set to 2
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Removed Warning related obsolete licenses GPLv2
WARNING: kernel-module-vdu-1.0.0-xilinx-v2024.1+gitAUTOINC+25773344ce-r0
do_package_qa: QA Issue:
Recipe LICENSE includes obsolete licenses GPLv2 [obsolete-license]
Signed-off-by: Virendra Nakaskar <Virendra.Nakaskar2@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
driver: src: io_backend: Request tiles before gating clocks
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
Fix to handle input_ports_details and output_ports_details Interface tiles metric for PLIO designs (#8064)
Changing a copy to a move for when profiling samples are written (#8065)
VITIS-11806 Command-chaining: XRT C++ Command List (#8063)
VITIS-11832 - Support transaction buffer patching in XRT (#8059)
fix printing logs on windows (#8062)
using the correct workspace path for windows (#8061)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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microblaze: Change TLB mapping and free space allocation
arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
arm64: zynqmp: Disable Tri-state for SDIO
arm64: dts: zynqmp: make hw-ecc as the default ecc mode
mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOCs
mailbox: zynqmp: Move buffered IPI setup to of_match selected routine
mailbox: zynqmp: Move of_match structure closer to usage
phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate
video/hdmi: Add support for version 3 AVI Infoframe
phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode
drm: xlnx: hdmi: Set wait event flag for TMDS mode
drm: xlnx: hdmi: Fix TMDS clock calculation for RGB YUV422 YUV444 formats
phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5
drm: xlnx: hdmi: Fix overwriting the max_frl_rate variable
drm: xlnx: hdmi: Downgrade the FRL rate when sink requests
drm: xlnx: hdmi: Fix lts2 state machine
drm: xlnx: hdmi: Implement xlnx_hdmi_frl_config function
drm: xlnx: hdmi: Implement streamdown callback function
drm: xlnx: hdmi: Add support for all FRL line rates
drm: xlnx: hdmi: Implement streamup callback function
drm: xlnx: hdmi: Implement connect callback function
drm: xlnx: hdmi: Set wait event flag in ltsp state
drm: xlnx: hdmi: Fix FRL link and video clock values
drm: xlnx: hdmi: Fix VTC macros as per the IP specification
phy: xilinx-xhdmiphy: Fix MMCM parameter values for GTYE5/GTYP
drm: xlnx: hdmi: Optimize phy configuration function calls
firmware: xilinx: Dont send linux address to get fpga config get status
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fdt_generic_devices: Add phy aliases
arm_generic_fdt: Create ethernet phy in postinit
fdt_generic_util: Add a postinit call back
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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30bed2b openamp: xlnx: Add vc-p and vn-p models
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
Cleanup clangtidy warnings (#8057)
Providing a work-around to allocate instruction buffer in HIP (#8047)
SC warning fix on RAVE and xsabin extension warning fix on Versal (#8053)
aie-status reports fix (#8051)
VITIS-11503 - Dump instruction bo created from Elf so verification can be done (#8043)
VITIS-11503 - change elf section name from mc_code to control-packet (#8054)
Defining Mailbox Macro for QDMA to fix APU crash on RAVE (#8052)
revert sdr changes (#8049)
ML Timeline Plugin should read timestamp data before AIE Profile/Debug (#8045)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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openamp: xlnx: versal: match model parsing same as VNET
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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net: axienet: Correct tx_buff size when DRE is not enabled
clk: clocking-wizard: calculate dividers fractional parts
v4l: xilinx: dprxss: Fix xhdcp1x_rx_init() function declaration
v4l: xilinx: dprxss: Fix gcc warning
staging: xilinx_hdcp: Fix gcc warning
mtd: spi-nor: Use same bit mask macro in spi & spi-nor core
Revert "drivers: clk: zynqmp: add hack to use old algorithm for divider round rate"
fpga: Fix the reset handling
remoteproc: zynqmp_r5: Clean up support for Versal NET CTCM
mtd: spi-nor: Add support for BP3 at SR bit 5
mtd: spi-nor: Use params->size for flash size info
mtd: spi-nor: Avoid writing EAR register for flashes less than 16MB
mtd: spi-nor: Use nor->info->id[0] for manufacturer id
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driver:src:Softpartition boundary Isolation fixed
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VEK280 SDT QEMU doesn't come up with PLM, this to default
QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for
VEK280 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vek280.dtb and also adjust the QB_MEM to 12GB
to match with board dtsi file, we need set same in QB_MEM
for QEMU boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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VHK158 SDT QEMU doesn't come up with PLM, this to default
QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for
VHK158 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vmk158.dtb and also adjust the QB_MEM to 32GB
as versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM
for QEMU boot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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The SRCREV update contains below commits:
assists: generate_config_object: Enable user-driven customization of library options
assists: generate_config_object: Addressed the scenario where, not all masters are reset masters
lopper:assists:baremetallinker: Do not consider linear SPIs for memory tests
lopper:assists:gen_domain_dts: Remove axi_noc and noc_ddr4 IPs from linux ignore list
base: add expression to clock phandle description
Signed-off-by: Onkar Harsh <onkar.harsh@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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QEMU PLM error code are observed as shown below.
[13422.262]****************************************
[13422.490]Xilinx Versal Platform Loader and Manager
[13422.508]Release 2024.1 Mar 30 2024 - 14:13:53
[13422.562]Platform Version: v0.0 PMC: v0.0, PS: v0.0
[13422.588]BOOTMODE: 0x5, MULTIBOOT: 0xF0000000
[13422.608]****************************************
[13427.899]Non Secure Boot
[13441.028]PLM Initialization Time
[13441.090]***********Boot PDI Load: Started***********
[13441.191]Loading PDI from SD1
[13441.218]Monolithic/Master Device
[14850.660]1409.510 ms: PDI initialization time
[14850.719]+++Loading Image#: 0x1, Name: lpd, Id: 0x04210002
[14850.755]---Loading Partition#: 0x1, Id: 0xC
[14892.625] 41.831 ms for Partition#: 0x1, Size: 11360 Bytes
[14893.706]---Loading Partition#: 0x2, Id: 0x0
[14902.163] 7.679 ms for Partition#: 0x2, Size: 65104 Bytes
PSM Firmware version: 2024.1 [Build: Mar 30 2024 14:13:53 ]
[15013.595]+++Loading Image#: 0x2, Name: pl_cfi, Id: 0x18700000
[15014.589]---Loading Partition#: 0x3, Id: 0x3
[21947.779]Polling 0xF11A0000 Mask: 0xFFFFFFFF ExpectedValue: 0x14CAA093
[21949.039]MaskPoll: Addr: 0x0F11A0000, Mask: 0xFFFFFFFF, ExpVal: 0x14CAA093, Timeout: 1000000, RegVal: 0x14CA8093 ...ERROR
[21951.067]CMD: 0x00040101 execute failed, Processed Cdo Length 0x84
[21952.260]CMD Payload START, Len:0x00000004
0x00000000F20000A8: 0xF11A0000 0xFFFFFFFF 0x14CAA093 0x00000001
0x00000000F20000B4:
[21954.516]CMD Payload END
[21955.035]Error loading PL data:
CFU_ISR: 0x00000000, CFU_STATUS: 0x0000080C
PMC ERR1: 0x00000000, PMC ERR2: 0x00000000
[21957.810]PLM Error Status: 0x21010001
[21958.489]============Register Dump============
[21959.269]PMC_TAP_IDCODE: 0x14CA8093
[21959.887]EFUSE_CACHE_IP_DISABLE_0(EXTENDED IDCODE): 0x00004000
[21960.901]PMC_TAP_VERSION: 0x03000000
[21961.516]CRP_BOOT_MODE_USER: 0x00000005
[21962.179]CRP_BOOT_MODE_POR: 0x00000005
[21962.823]CRP_RESET_REASON: 0x00000202
[21963.462]PMC_GLOBAL_PMC_MULTI_BOOT: 0xF0000000
[21964.242]PMC_GLOBAL_PWR_STATUS: 0x00000000
[21964.946]PMC_GLOBAL_PMC_GSW_ERR: 0x00000000
[21965.666]PMC_GLOBAL_PLM_ERR: 0x00000000
[21966.342]PMC_GLOBAL_PMC_ERR1_STATUS: 0x00000000
[21967.136]PMC_GLOBAL_PMC_ERR2_STATUS: 0x00000000
[21967.917]PMC_GLOBAL_GICP0_IRQ_STATUS: 0x20000000
[21968.713]PMC_GLOBAL_GICP1_IRQ_STATUS: 0x00000000
[21969.507]PMC_GLOBAL_GICP2_IRQ_STATUS: 0x00000000
[21970.307]PMC_GLOBAL_GICP3_IRQ_STATUS: 0x00000000
[21971.113]PMC_GLOBAL_GICP4_IRQ_STATUS: 0x00000000
[21971.921]PMC_GLOBAL_GICP_PMC_IRQ_STATUS: 0x00000000
[21972.767]============Register Dump============
This is due to default QEMU_HW_DTB_PS used from versal-generic.conf
file doesn't work for VMK180 machine conf file.
Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to
board-versal-ps-vmk180.dtb.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Update QEMU_HW_DTB_PMC to use board-versal-pmc-virt.dtb instead of
board-versal-pmc-vc-p-a2197-00.dtb as board-versal-pmc-vc-p-a2197-00.dtb
dtb targets tenzing board.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts
mtd: spi-nor: Remove SPI_NOR_OCTAL_READ flag
soc: zynqmp: Add the IDcode for TEG variant
zlib: Remove incorrect ZLIB_VERSION
zlib: Port fix for CVE-2016-9841 to U-Boot
zlib: Rename write variable to wnext (window write index)
zlib: Rename this variable to here (current decoding table entry)
configs: versal: Disable the config for spansion flash
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m25p80: Consider 4byte address for octal ddr mode
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vck190: Add 2g OSPI flash
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versal: Add support for xqvm1102, xqve2102, xqvp2502, xqvp1052 and xqve2302
versal: Add support for xave2602 and xave2802
versal: SE variants support
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versal: Add support for the SE variant of xcvp1002
versal: Add support for the SE variant of xcvm2152
versal: Add support for xcvm2152
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1. Make bit or bin or pdi as required input for firmware recipes. If bit
or bin or pdi of respective soc_family is not included then raise
bitbake parse skip recipe errors.
2. Check for absolute dtbo/bin/bit path if any of these files exits
in SRC_URI.
3. Skip recipe if both dtbo and dts/dtsi found in SRC_URI.
4. Fix logic to convert from bit to bin for zynqmp or zynq soc family.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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