| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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usb: misc: usb5744: prevent the HUB from suspend mode
versal-net-*: matching node names with platform dtsi
xilinx: Convert MODULE_LICENSE GPL v2 to GPL
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versal-net-*: matching node names with platform dtsi
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mtd: spi-nor: winbond: Add flash lock/unlock support to w25q256jwm
Revert "arm64: zynqmp: Add the fclk node"
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Update send-email.yml
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog:
Remove use of typeid (#7808)
Fix divide by zero exception when collecting usage metrics (#7805)
VITIS-10045 - add prototype (#7790)
CR-1181478 Fix reports for AIE and AIESHIM (#7801)
VITIS-9941 Separate Alveo and Ryzen reports (#7784)
Fix for call repo mirror worflow (#7804)
PR to trigger enterprise XRT pipeline using github actions (#7794)
Fix coverity scan issues (#7797)
Add hybrid access to xrt::fence for cross-adapter sharing (#7800)
Changes to XDP Plugin metadata parsing (#7798)
VITIS-9991 - Removing boost::any (#7795)
Add hybrid access to xrt::ext:bo (#7796)
VITIS-10034 Add Usage metrics for all XRT objects (#7788)
AIE profile/trace updates (#7781)
remove 1x4.xclbin dependency (#7792)
Amend #7773 to add back missing include (#7793)
Adding a flag o and m (#7791)
Add inline specifier to xrt::ini::set(const string&, unsigned int) (#7789)
Moving petalinux to 2024.1 version (#7786)
VITIS-9909 Bundle AIE microbenchmarks with xbutil validate (#7770)
VITIS-9987 xbutil : IPU specific enhancements (#7773)
Feature/mariner updates to 202220 2 14 354 (#7775) (#7783)
VTITIS-9990 - Removing boost::filesystem P4 (#7785)
VTITIS-9990 - Removing boost::filesystem P3 (#7782)
VTITIS-9990 - Removing boost::filesystem P2 (#7780)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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dfx_mgr: allow symbolic links to firmware dir
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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w1: Add AXI 1-wire host driver for AMD programmable logic IP core
dt-bindings: w1: Add AMD AXI w1 host and MAINTAINERS entry
mtd: spi-nor: issi: Add support for is25lp02g
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misc: usb5744: Prevent the HUB from suspend mode
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yocto_machine.py: adding template dt machine
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Merge "docs(changelog): changelog for v2.10 release" into integration
docs(changelog): changelog for v2.10 release
Merge "Revert "docs(changelog): changelog for v2.10 release"" into integration
Revert "docs(changelog): changelog for v2.10 release"
Merge "docs(threat-model): add a threat model for TF-A with Arm CCA" into integration
Merge "refactor(tc): deprecate Arm TC1 FVP platform" into integration
Merge "docs(changelog): changelog for v2.10 release" into integration
refactor(tc): deprecate Arm TC1 FVP platform
docs(changelog): changelog for v2.10 release
Merge changes from topic "hm/rt-instr" into integration
Merge "docs: add a section for experimental build options" into integration
docs: add a section for experimental build options
docs(juno): update PSCI instrumentation data
docs(n1sdp): update N1SDP PSCI instrumentation data
docs(threat-model): add a threat model for TF-A with Arm CCA
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dmaengine: xilinx: use correct enum for dma_data_direction
Revert "spi: increase timeout value for spi transfers"
Revert "arm: zynq: Suspend support"
firmware: xilinx: Export function to use in other module
Revert "usb: xhci: wait for at least 1ms after exiting U3"
Revert "usb: dwc3: Fix the broken suspend/resume functionality in dwc3"
dt-bindings: net: cdns,macb: Remove cdns,versal-gem compatible string
Revert "dt-bindings: clock: versal: Correct example dts"
Revert "fpga: zynq: Fix incorrect variable type"
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Deprecate fpgamanager_custom.bbclass and this bbclass functionality
is available in new dfx_user_dts.bbclass and going forward user should
be using dfx_user_dts.bbclass.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Move all libdrm patches from meta-petalinux to meta-xilinx
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Move the pulseaudio patch from meta-petalinux to meta-xilinx
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Move the two v4l2apps from meta-petalinux to meta-xilinx
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Below are the updates
lopper: lops: Keep the status disabled nodes in the pruned tree
lopper: assists: xlnx_overlay_dt: Remove amba_pl references
assists:baremetal_xparameters_xlnx: Correct the string macros in xparameters
openamp: xlnx: Add new module flags for role, host and remote
lopper: assists: bmcmake_metadata_xlnx: Don't include IP subcores in the hw metadata
openamp: xlnx: Update output file
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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test/py: test: Remove test cases for test command
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Merge "docs(fvp): update model version documentation" into integration
Merge "fix(docs): update maintainers list" into integration
fix(docs): update maintainers list
docs(fvp): update model version documentation
Merge "refactor(qemu): change way how we enable cpu features" into integration
refactor(qemu): change way how we enable cpu features
Merge changes from topic "od/hf-doc-migration" into integration
Merge "docs(threat-model): cover threats inherent to receiving data over UART" into integration
docs(threat-model): cover threats inherent to receiving data over UART
docs(spm-mm): remove reference to SEL2 SPMC
docs: remove SEL2 SPMC threat model
docs: remove unused SPM related diagrams
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Kconfig.part:Update menuconfig for enabling the DT aliases
hw-description.tcl: Update help for serial settings
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Current gcc requires cstdint for C types
chore: update to revision d20230901
fix: add missing ToString
feat(app): add device selection
chore: update to revision d20230724
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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chore: update to revision d20230901
chore: update to revision d20230724
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Header File cstdin Added
fix: avc lookahead buffers count
chore: update to revision d20230901
fix: add missing mask
chore: update to revision d20230724
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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chore: align xilinx-private and master-allegro
Fix compilation issue
fix: xilinx implementation of add_memory
refacto setup_dma
reformat
feat: Use the macro defined by the kernel to initialize dmabuf export informations.
Move constant in al_constants.h
small fixes
cdev refacto
Revert Revert Add support for reserved memory with start address not aligned on 2GB
feat: getter/setter encode/decode
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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dfx_mgr: remove internal names in listIRbuf output
dfx_mgr: scan for new firmware before loading
README.md: /var/run and Vivado UID/PID
dfx_mgr: move server socket to /var/run
dfx_mgr: detect zeros in PID, UID compare
README.md: AIE and graph notes
README.md: add libdfx, XRT, kria-dfx-hw links
dfx_mgr: avoid reading Clear-On-Read register
client: API to set Data-Mover configuration
client: list or set Data-Mover configuration
dfx_mgr: display or configure Data-Movers
dfx-mgr: get Inter-RP address from shell.json
accel: Use sbustring match to get VA address
dfx-mgrd: add uid, pid checks
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Merge "build(mbedtls): add deprecation notice" into integration
Merge "refactor(auth): remove return_if_error() macro" into integration
refactor(auth): remove return_if_error() macro
build(mbedtls): add deprecation notice
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Update send-email.yml
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Merge "fix(arm): correct the SPMC_AT_EL3 condition" into integration
Merge "fix(xlat): set MAX_PHYS_ADDR to total mapped physical region" into integration
Merge "fix(intel): update boot scratch cold register to use cold 8" into integration
Merge changes from topic "sb/remove-cryptocell" into integration
Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration
Merge "build(qemu): use xlat tables v2 directly" into integration
chore(npcm845x): remove CryptoCell-712/713 support
build(qemu): use xlat tables v2 directly
docs(qemu): mention a55 in list of v8.2 cores
fix(arm): correct the SPMC_AT_EL3 condition
chore(auth)!: remove CryptoCell-712/713 support
Merge "build(qemu-sbsa): it is GICv3 platform" into integration
Merge changes Ia72b2542,I1eba5671 into integration
Merge "chore(libfdt): update header files to v1.7.0 tag" into integration
Merge "refactor(cm): introduce INIT_UNUSED_NS_EL2 macro" into integration
Merge "fix(el3-spmc): remove experimental flag" into integration
Merge changes from topic "ns/spmc_at_el3" into integration
Merge "fix(smccc): ensure that mpidr passed through SMC is valid" into integration
fix(el3-spmc): remove experimental flag
feat(sgi): increase sp memmap size
feat(build): include plat header in fdt build
feat(docs): save BL32 image base and size in entry point info
feat(arm): save BL32 image base and size in entry point info
refactor(cm): introduce INIT_UNUSED_NS_EL2 macro
chore(compiler-rt): update compiler-rt source files
chore(zlib): update zlib to version 1.3
chore(libfdt): update header files to v1.7.0 tag
fix(smccc): ensure that mpidr passed through SMC is valid
build(qemu-sbsa): it is GICv3 platform
Merge "fix(sdei): ensure that interrupt ID is valid" into integration
Merge changes from topic "enable_assertion" into integration
Merge changes from topic "errata" into integration
Merge "fix(ti): release lock in all TI-SCI xfer return paths" into integration
Merge "feat(xilinx): switch boot console to runtime" into integration
Merge "docs: add TF-A version numbering information" into integration
Merge "feat(zynqmp): remove pm_ioctl_set_sgmii_mode api" into integration
fix(ti): release lock in all TI-SCI xfer return paths
fix(intel): update boot scratch cold register to use cold 8
fix(xlat): set MAX_PHYS_ADDR to total mapped physical region
docs: add TF-A version numbering information
feat(zynqmp): remove pm_ioctl_set_sgmii_mode api
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround for Neoverse N2 erratum 2340933
fix(cpus): workaround for Neoverse N2 erratum 2346952
fix(sdei): ensure that interrupt ID is valid
feat(zynqmp): enable assertion
feat(versal-net): enable assertion
feat(versal): enable assertion
feat(xilinx): switch boot console to runtime
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ipinfo.yaml: Add available memory banks for versal-net
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Update send-email.yml
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Changelog:
Fixed tile information printed to the screen (#7779)
Adjust trace points (#7778)
VTITIS-9990 - Removing boost::filesystem P1 (#7777)
Update coverity.yml
Configuration of AIE not needed in ML Timeline Plugin (#7776)
Remove multiple printout of early access message (#7774)
Updates to AIE Profile Client Plugin (#7772)
VITIS-9943 Improve help menu to use JSON file (#7766)
Amend #7752 to default error out if ERT FW cannot be built (#7769)
CR-1179639 Add early access label for Ryzen AI (#7754)
effective filtering of the unsorted events (#7763)
CR-1178667 Remove device specification restriction (#7750)
change ipu name (#7768)
Use write buffer for AIE Profile, AIE Debug Plugins in Client Device (#7757)
Fix for XRT_IPU build break (#7762)
Update CHANGELOG to reflect minimum gcc requirement
Add platform specific repository for xclbins (#7712)
VITIS-10045 - Fix a crash in xclbinUtil on windows platform (#7756)
Exclude version file generation when running AMD promotion build (#7755)
update mb-gcc path for building ERT (#7751)
ML Timeline Plugin for extracting layer-by-layer timestamps for ML designs (#7753)
Add build.sh option to force error if ERT FW cannot be build (#7752)
Update trace logging to support Linux (#7745)
Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Changelog since xlnx_rel_v2023.2
examples: linux: include utilities.h
Revert commits with unclear upstream plan
Signed-off-by: Sergei Korneichuk <sergei.korneichuk@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Adds support for Rev2 boards
Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Update send-email.yml
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Revert "firmware: xilinx: xilinx: Add IOCTL ids for probe counter"
mailbox: Explicitly include correct DT includes
mailbox: zynqmp: Fix IPI isr handling
mailbox: zynqmp: Fix counts of child nodes
Revert "dt-bindings: zynqmp: Add new PD_PL macro"
Revert "firmware: xilinx: Add zynqmp SGMII firmware support"
Revert "dt-bindings: usb: host: ehci-xilinx: Add binding doc"
arm64: xilinx: Sync defconfigs with the latest Kconfig layout
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Update send-email.yml
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post_process_config.py: Fix for nfs boot configurations
gen-machineconf: Add SKIP_BBPATH_SEARCH variable
sdt_flow.py:xsct_flow.py: Add Layers before conf files
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Merge changes from topic "morello/firmware-revision" into integration
Merge changes from topic "xlnx_tsp_feat" into integration
feat(morello): add TF-A version string to NT_FW_CONFIG
feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version
Merge "fix(rmmd): enable sme using sme_enable_per_world" into integration
fix(rmmd): enable sme using sme_enable_per_world
Merge "fix(build): remove duplicated include order" into integration
Merge changes from topic "mp/exceptions" into integration
Merge "docs: deletion of a few deprecated platforms not yet confirmed" into integration
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
fix(build): remove duplicated include order
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths
docs: deletion of a few deprecated platforms not yet confirmed
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driver: src: Fixed misra warning
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fix libmetal shimdma issue
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fal:src: Fixed AIE baremetal app compilation fail in rigel flow
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mtd: spi-nor: Fix the issi_flash_lock api
mtd: spi-nor: Enhance block protection support for micron flashes
mtd: spi-nor: Update block protection flags for ospi flash parts
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arm64: xilinx: Enable KASLR in defconfig
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Merge changes from topic "fw-caps" into integration
Merge "fix(tegra): return correct error code for plat_core_pos_by_mpidr" into integration
fix(tegra): return correct error code for plat_core_pos_by_mpidr
Merge changes from topic "hst/cs1k-add-gpt-support" into integration
Merge "feat(cpufeat): add memory retention bit define for CLUSTERPWRDN" into integration
feat(bl2): add gpt support
fix(corstone-1000): modify boot device dependencies
Merge "refactor(cm): move EL3 registers to global context" into integration
Merge "fix(build): remove handling of mandatory options" into integration
Merge changes from topic "hm/mpam" into integration
fix(build): convert tabs and ifdef comparisons
Merge "refactor(fvp): do not use RSS platform token and attestation key APIs" into integration
fix(build): disable ENABLE_FEAT_MPAM for Aarch32
fix(corstone-1000): removing the signature area
Merge changes from topic "hm/post-image" into integration
refactor(cm): move EL3 registers to global context
Merge "feat(rmm): update RMI VERSION command as per EAC5" into integration
feat(rmm): update RMI VERSION command as per EAC5
Merge "fix(versal): type cast addresses to fix integer overflow" into integration
fix(build): remove handling of mandatory options
Merge changes from topic "gr/build_refactor" into integration
build(refactor): avoid ifdef comparison
refactor(build): avoid using values for comparison
refactor(build): reorder arch features handling
build(n1sdp): add ARM_ARCH_MAJOR.ARM_ARCH_MINOR
refactor(build): reorder platform Makefile evaluation
Merge changes from topic "mb/psa-crypto-ecdsa" into integration
fix(versal): type cast addresses to fix integer overflow
refactor(fvp): move image handling into generic procedure
refactor(bl2): make post image handling platform-specific
Merge "fix(ast2700): add device mapping for coherent memory" into integration
fix(ast2700): add device mapping for coherent memory
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove extra core counts in cluster 2 and 3
refactor(fvp): do not use RSS platform token and attestation key APIs
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(mbedtls-psa): mbedTLS PSA Crypto with ECDSA
feat(cpufeat): add memory retention bit define for CLUSTERPWRDN
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arm64: zynqmp: Remove description for 8T49N240
arm64: versal: Switch to new xlnx,versal-ddrmc compatible string
arm64: versal: Update SE5 Ethernet PHY RGMII properties
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xlnx-efuse: versal: zynqmp: Switch to upstreamed eFuse models
zynqmp: PUF: Use upstream Xilinx eFuse model
versal: PUF: Use upstream Xilinx eFuse model
versal: pmc-sysmon: Use upstream Xilinx eFuse model
versal: pmc-global: Use upstream Xilinx eFuse model
versal: pmx: Use upstream Xilinx eFuse model
hw/nvram: zynqmp-efuse: Implement the get_puf abstraction
hw/nvram: zynqmp-efuse: Add key delivery to AES engine
hw/nvram: zynqmp-efuse: Kconfig: Exclude eFUSE from ZynqMP PMU
hw/nvram: zynqmp-efuse: Remove checking of a never-true condition
hw/nvram: versal-efuse: Implement the get_* abstraction
hw/nvram: versal-efuse: Add key delivery to AES engine
hw/nvram: xlnx-efuse: Zeroing data for the get_sysmon abstraction
hw/nvram: xlnx-efuse: Expand the data for the get_puf abstraction.
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Revert "firmware: xilinx: Open MMIO read/write interface via debugfs"
Revert "include: dt-bindings: Add mscc-vsc8531 RGMII clock delay definitions"
Revert "firmware: xilinx: add support for sd/usb/gem config"
arm: dts: xilinx: Remove redundant is-dual and is-stacked DT properties
Revert "firmware: xilinx: Add ULPI reset support"
misc: Get OPEN_DICE/VCPU_STALL_DETECTOR back
Revert "remoteproc: Add support for peek from remote and acking kick from remote"
Revert "uartlite: Update the default for the parameter"
dt-bindings: misc: Remove description for xlnx,fclk
clocking-wizard: Sync internal driver with v7 version
dt-bindings: clock: xilinx: add versal compatible
clocking-wizard: Sync valuem/d/o names with upstream version
Revert "clocking-wizard: Add versal clocking wizard support"
Revert "dt-bindings: Add versal clocking wizard"
arm64: versal: Switch to new xlnx,versal-ddrmc compatible string
EDAC/versal: Move driver to its final location
edac: zynqmp_edac: Moved driver to new location
Revert "i2c: mux: pca954x: write to mux channel always"
arm64: versal: Update SE5 Ethernet PHY RGMII properties
net: phy: mscc: fix packet loss due to RGMII delays
phy: mscc: Add support for RGMII delay configuration
phy: mscc: Use PHY_ID_MATCH_VENDOR to minimize PHY ID table
net: phy: mscc: enable VSC8501/2 RGMII RX clock
net: phy: mscc: remove unnecessary phydev locking
Revert "phy: mscc: Add support for VSC8531_02 with RGMII tuning"
Revert "dt-bindings: mscc: Add RGMII RX and TX delay tuning"
Revert "edac: Add documentation for cortexa53 edac sysfs"
soc: xilinx: Remove XPM_NODETYPE_ macro prefix
dt-bindings: i2c: xiic: Sync up with upstream
Revert "irqchip: xilinx: Make per cpu primary controller entries"
Revert "irqchip: xilinx: Move early initialization to own function"
Revert "irqchip: xilinx: Add support for sw interrupts"
Revert "irqchip: xilinx: Support only LE/BE irqc by the same driver"
Revert "irqchip: xilinx: Add support for cpu hotplug"
Revert "irqchip: xilinx: Add support for Microblaze SMP"
Revert "irqchip: xilinx: Change level for cpu-id warning"
Revert "edac: add support for ARM PL310 L2 cache parity"
Revert "microblaze: timer: Dont use cpu timer setting"
Revert "microblaze: timer: Separate clocksource timer from clockevent one"
Revert "microblaze: timer: Pass timer freq via parameter"
Revert "microblaze: timer: Squash clocksource code together"
Revert "microblaze: timer: Covert timer to use cpu hotplug"
Revert "microblaze: timer: Move irq code to clockevent function"
Revert "microblaze: timer: Create per cpu clockevent device"
Revert "microblaze: timer: Remove global variables"
Revert "microblaze: timer: Make sure that clockevent timer is initialized properly"
Revert "microblaze: timer: Group clockevent setting together"
Revert "microblaze: timer: Detect cpu_id from DT"
Revert "microblaze: timer: Change timer initialization setting"
Revert "microblaze: timer: Make timer SMP aware"
Revert "microblaze: timer: Add condition to check return value"
Revert "microblaze: timer: Fix incompatible parameters passed to the function"
Revert "microblaze: Change TLB mapping and free space allocation"
Revert "microblaze: Define SMP safe bit operations"
Revert "microblaze: Make cpuinfo structure SMP aware"
Revert "microblaze: Add SMP implementation of xchg and cmpxchg"
Revert "microblaze: Remove disabling IRQ while pte_update() run"
Revert "microblaze: Implement architecture spinlock"
Revert "microblaze: Do atomic operations by using exclusive"
Revert "microblaze: Prepare entry.S for SMP implementation"
Revert "microblaze: Rework mmu context management to prepare"
Revert "microblaze: Enable experimental SMP functionality"
Revert "microblaze: Add defconfig and DT for SMP design"
Revert "clk: Add ccf driver for IDT 8T49N24x UFT"
Revert "dt-bindings: Add binding for IDT 8T49N24x UFT"
arm64: zynqmp: Remove description for 8T49N240
Revert "Xilinx: ARM: Devcfg and SLCR drivers updated to support reconfiguration."
arm64: versal-net: Add missing xlnx,versal-firmware string
arm64: versal-net: Append xlnx,versal-clk to clock node
arm64: zynqmp: Remove unused xlnx,phy-type DT property
arm64: zynqmp: Add output-enable pins to SOM KD240
arm64: zynqmp: Enable uart0 with pinctrl description
arm64: zynqmp: Add support for K26 rev2 boards
arm64: zynqmp: Setup default si570 frequency to 156.25MHz
arm: dts: xilinx: Remove redundant is-dual and is-stacked DT properties
Revert "watchdog: xilinx_wwdt: Add "xlnx,versal-wwdt-1.0" compatible"
Revert "dt-bindings: watchdog: xlnx,versal-wwdt: Add "xlnx,versal-wwdt-1.0" compatible"
fpga: bridge: make fpga_bridge_class a static const structure
fpga: bridge: return errors in the show() method of the "state" attribute
fpga: bridge: properly initialize bridge device before populating children
fpga: bridge: fix kernel-doc parameter description
fpga: bridge: fix kernel-doc
edac: Remove the cortex cache edac driver
Revert "edac: Update device tree bindings for cortex_arm64"
drm: xlnx: hdmitx: Add HDCP1X support
dt-bindings: display: xlnx: hdmitx: Add HDCP1X key management support
drm: xlnx: hdcp: Add HDMI supportive HDCP1X functionalities
drm: xlnx: hdcp: Add HDMI supportive HDCP Secure hashing algorithm
staging: xilinx_hdcp: Remove unused XBYTES_PER_DIGIT #define
staging: xlnx_hdcp1x: Add HDMI supportive functionality
staging: xlnx_hdcp1x: Fix kernel-doc errors
firmware: xilinx: fix enum mismatch
Revert "uas: Add US_FL_NO_ATA_1X for linux tcm_usb_gadget"
Revert "serial: uartps: Fix stuck ISR if RX disabled with non-empty FIFO"
i2c: xiic: Correct return value check for xiic_reinit()
Revert "drivers: clk: zynqmp: Add versal-net compatible string"
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Below are the updates
lopper: lops: lop-domain-linux-a72-prune: prune symbol node
lopper: lops: lop-domain-a72-prune: Don't delete pl nodes
lopper: assists: xlnx_overlay_dt: Migrate the DT overlays to sugar syntax
lopper:assists:xparams: Provide an option to configure the xparam prefix
lopper:assists:xparams: Replace the node label name with the IP name in canonical entries
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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yocto_machine.py: update kernel load address for microblaze
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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