| Commit message (Collapse) | Author | Age | Files | Lines |
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xilpm: versal_net: server: fix gcc warnings
sw_services:xilnvm:Fix bug in reading PUF secure control bits
bsp: standalone: Fixed source code-format issue.
zynqmp_rpu_bsp: Fix standalone coverity static analysis
sw_services: xilmailbox: Updated XIpiPs_PollforDone logic to improve AES client performance
sw_services: xilsecure:Fixed MISRA C violation for Rule 10.3
sw_services: xilsecure:Fixed MISRA C violation for Rule 12.2
sw_services: xilsecure:Fixed MISRA C violation for Rule 2.5
sw_services: xilsecure:Fixed MISRA C violation for Rule 12.1
sw_services: xilsecure:Fixed MISRA C violation for Rule 8.3
csudma: examples: Add support for system device-tree flow
csudma: Format examples using checkpatch
scugic: Initialize priority of SGI and PPI interrupts
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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sw_services: xilloader: Redundancy check implemented incorrectly
xilloader: versal_net: Added support for cluster flags in ATF handoff params
xilpm: versal_net: server: add PMC_GPIO device in pre-alloc list
xilplmi: Update default WDT timeout for VERSAL_NET
sw_services:xilsecure:Fix xilsecure sha client example failure
csudma: Fix Assert condition in XCsuDma_Transfer for VERSAL_NET
lib: bsp: standalone: Update R5 ZyqnMP CMakeLists.txt as per latest soucre file
xilplmi: versal_net: Fix PMC IRO frequency logic
zynqmp_pmufw: Remove API ID enum
xilpm: versal: common: Remove API ID enum
xilpm: versal_net: common: Remove API ID enum
xilpm: zynqmp: client: Remove API ID enum
lib: bsp: standalone: Move API ID enum to common place
prd: Increment driver version, copyright and addtogroup version
prc: Increment driver version, copyright and addtogroup version
dfxasm: Increment driver version, copyright and addtogroup version
devcfg: Increment driver version, copyright and addtogroup version
sw_apps: img_rcvry: Added support for kd240 boards
lib: sw_apps: freertos: Enable lwip examples for Versal-Net
lib: sw_apps: Enable lwip standalone examples for Versal-Net.
lwip213: Add Versal-Net support for PS GEM.
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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sw_services:xilloader:Add partial pdi loading from Image Store
BSP: cortexr5: Separate out CortexR52 MPU APIs
asm_vectors: fix kernel boot header
sw_apps: zynqmp_pmufw: Add support of parallel build
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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lib: bsp: standalone: Include bspconfig.h in boot.S for system device-tree flow
lib: bsp: standalone: Use XScuGic_LookupConfigBaseAddr() API for xsct flow
Update addtogroup to Overview and AMD copyright
versal_rpu_bsp: Fixed some MISRA-C violations.
xilpm: versal_net: client: add idle call back support
zynqmp_pmufw: bypass smmu during suspend
Updated change logs for plm & its libraries
lib: sw_services: xiltimer: Fix ifdef check in the microblaze_sleep.c
lib: bsp: standalone: Fix race conditions in the versal r5 mpu.c
lib: bsp: standalone: Fix race conditions in the A72 translation table
update Embedded SW license file for 2023.1
Revert "XilinxProcessorIPLib: drivers: aiengine: Add support for system device-tree flow"
freertos: gicv3: check group 1 IAR in NS EL1 irq handler
iomodule: Updated data types for few variables.
iomodule: Typecasting condition expressions with bool.
iomodule: Added parentheses to Expressions.
iomodule: Added U to Numericals.
sw_services: xilplmi: Address third party review comments
sw_services: xilplmi: Fix third party review comments
xilsem: Add support for psxl IP name
sw_services:xilloader:updated examples to support versalnet
XilNvm:Voltage, Temp Monitoring before efuse program
lib: sw_apps: freertos_hello_world: Add support for system device-tree flow
ThirdParty: bsp: freertos10_xilinx: Add support for system device-tree flow
lib: sw_apps: memory_tests: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: iomodule: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: ipipsu: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: common: Add meta-data required for system device-tree flow
XilinxProcessorIPLib: drivers: tmrctr: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: scugic: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: csudma: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: ttcps: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: uartpsv: Add support for system device-tree flow
XilinxProcessorIPLib: drivers: uartps: Add support for system device-tree flow
lib: sw_services: xiltimer: Add support for system device-tree flow
scripts: Add linker template and processor spec files
cmake: Add required cmake meta-data
lib: bsp: standalone: src: common: Much needed improvements in xinterrupt_wrap.c
lib: bsp: standalone: Add meta-data for the system device-tree flow
lib: bsp: standalone: Update common code to support system device-tree flow
lib: bsp: standalone: Add support for microblaze in system device-tree flow
lib: bsp: standalone: Add support for cortexr5 in system device-tree flow
lib: bsp: standalone: Add support for ARMv8 in system device-tree flow
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
(cherry picked from commit 2ba0c89b9aae7459b3d9e3c328c1db3fea4dc617)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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rfdc: Enable workaround for a specific version of libidn.so needed by cmake
XilinxProcessorIPLib: drivers: aiengine: Add support for system device-tree flow
plm: versal: Remove xplm_modules from PPU1 RAM
XilinxProcessorIPLib: drivers: CMakeLists.txt: Add required cmake meta-data for libxil
xilpuf: Fix PUF auxiliary convergence error
versal_psmfw: versal_net: reduce partition count
xilpm: versal: server: Update BFR-B pre-config sequence
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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versal_psmfw: versal_net: set local power state at last
emacps: example: Fix GEM1 base address check.
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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dfeofdm: Update documentation
lib: sw_apps: memory_tests: Update copyright year
lib: bsp: Added support to- use ttc as sleeptimer for cortexR52
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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sdps: Fix doxygen warnings
freertos10_xilinx: ARM_CR5: Use group 1 interrupts for CortexR52
scugic: Use IRQ for CortexR52 interrupts by default
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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updated for xilsem changelog
xilpm: versal_net: server: add power rail checks for LPD domain
xilpm: versal_net: server: add power rail checks for FPD domain
xilpm: versal_net: server: add power rail checks for pl domain
xilpm: versal_net: server: add power rail checks for np domain
xilpm: versal_net: server: add power rail checks for cpm domain
xilpm: versal_net: server: Update rail status for PMC
xilpm: versal_net: server: add support to check and control power rail status
xilpm: versal_net: server: Add pmc global and sysmon registers
xilpm: server: Remove unnecessary validation of arguments
xilpm: versal_commom: server: Add power rail support for Versal NET
Updated changelog
updated for license and copyright
Doxygen fixes - xilpdi
Doxygen fixes - xilplmi
Doxygen fixes - xilloader
Doxygen fixes - versal_plm
xilplmi: updated algorithm & return values
xilloader: updated algorithm & return values
xilpdi: updated algorithm & return values
xilpm:versal_net: enable isolation during system reset
xilpki: Update examples notes description
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
(cherry picked from commit d5e7e01ca6979d0ce1d8f5158bcffbf565a56c65)
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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reverting as we still need to continue to use xlnx_rel_v2023.1-next branch
This reverts commit 84bcd7a4dc5ba55fa74bec1bee0786ce45c049ee.
Conflicts:
meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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reverting as we still need to continue to use xlnx_rel_v2023.1-next branch
This reverts commit 84bcd7a4dc5ba55fa74bec1bee0786ce45c049ee.
Conflicts:
meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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This reverts commit aee55354756be9514c61f5e768dfa0370bdf8de0.
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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