From 0ad4c88146cc71c48da9b04da9b2b5a6982a0187 Mon Sep 17 00:00:00 2001 From: Manjukumar Matha Date: Fri, 10 Aug 2018 13:06:43 -0700 Subject: Update recipes for Xilinx v2018.3 release Update the arm-trusted-firmware, u-boot-xlnx, linux-xlnx, qemu-xilinx and qemu-devicetrees recipes for 2018.3 release Signed-off-by: Manjukumar Matha --- .../arm-trusted-firmware/arm-trusted-firmware.inc | 2 +- .../arm-trusted-firmware_2018.1.bb | 7 - .../arm-trusted-firmware_2018.3.bb | 7 + ...aze-kc705-Convert-microblaze-generic-to-k.patch | 1168 -------------------- ...aze-kc705-Convert-microblaze-generic-to-k.patch | 1168 ++++++++++++++++++++ .../recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb | 27 - .../recipes-bsp/u-boot/u-boot-xlnx_2018.3.bb | 27 + .../recipes-devtools/qemu/files/memfd.patch | 57 - .../qemu/qemu-devicetrees_2018.1.bb | 6 - .../qemu/qemu-devicetrees_2018.3.bb | 6 + .../recipes-devtools/qemu/qemu-xilinx.inc | 4 +- .../recipes-devtools/qemu/qemu-xilinx_2018.1.bb | 6 - .../recipes-devtools/qemu/qemu-xilinx_2018.3.bb | 6 + .../recipes-kernel/linux/linux-xlnx_2018.1.bb | 7 - .../recipes-kernel/linux/linux-xlnx_2018.3.bb | 7 + ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 302 ----- ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 ---------- ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 - .../v2018.1/0004-minized-wifi-bluetooth.cfg | 33 - ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 302 +++++ ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 ++++++++++ ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 + .../v2018.3/0004-minized-wifi-bluetooth.cfg | 33 + .../linux/linux-xlnx_2018.1.bbappend | 9 - .../linux/linux-xlnx_2018.3.bbappend | 9 + 25 files changed, 2228 insertions(+), 2287 deletions(-) delete mode 100644 meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb create mode 100644 meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.3.bb delete mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch create mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch delete mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb create mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.3.bb delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.3.bb delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.3.bb delete mode 100644 meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb create mode 100644 meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.3.bb delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0004-minized-wifi-bluetooth.cfg create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0004-minized-wifi-bluetooth.cfg delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.1.bbappend create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.3.bbappend diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 6830c9d0..b00af117 100644 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -1,7 +1,7 @@ DESCRIPTION = "ARM Trusted Firmware" LICENSE = "BSD" -LIC_FILES_CHKSUM = "file://license.rst;md5=33065335ea03d977d0569f270b39603e" +LIC_FILES_CHKSUM = "file://license.rst;md5=e927e02bca647e14efd87e9e914b2443" PROVIDES = "virtual/arm-trusted-firmware" diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb deleted file mode 100644 index 6a9eea68..00000000 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.1.bb +++ /dev/null @@ -1,7 +0,0 @@ -ATF_VERSION = "1.4" -XILINX_RELEASE_VERSION = "v2018.1" -BRANCH ?= "master" -SRCREV ?= "df4a7e97d57494c7d79de51b1e0e450d982cea98" - -include arm-trusted-firmware.inc - diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.3.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.3.bb new file mode 100644 index 00000000..8c8a5d00 --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2018.3.bb @@ -0,0 +1,7 @@ +ATF_VERSION = "1.5" +XILINX_RELEASE_VERSION = "v2018.3" +BRANCH ?= "master" +SRCREV ?= "08560c36ea5b6f48b962cb4bd9a79b35bb3d95ce" + +include arm-trusted-firmware.inc + diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch deleted file mode 100644 index ce8771f8..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch +++ /dev/null @@ -1,1168 +0,0 @@ -From 539838b4fe4afecd9b6874c5ac397ab7f5b343d4 Mon Sep 17 00:00:00 2001 -From: Manjukumar Matha -Date: Tue, 10 Apr 2018 18:34:45 -0700 -Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to - kc705-microblazeel - -This is an update to earlier kc705-trd patch done by Nathan Rossi. -Starting from v2016.1, KC705 will no longer refer to deprecated KC705 -TRD application. - -Change the microblaze-generic board to match the kc705-microblazeel. -This patch is not intended for upstream and serves as an intermediate -solution until OF support in upstream u-boot allows for easy support for -custom microblaze boards. - -Signed-off-by: Manjukumar Matha -Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific] ---- - arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++- - board/xilinx/microblaze-generic/config.mk | 30 +- - configs/microblaze-generic_defconfig | 57 ++- - include/configs/microblaze-generic.h | 396 ++++++++----------- - 4 files changed, 782 insertions(+), 291 deletions(-) - -diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts -index 08a1396..f8e616b 100644 ---- a/arch/microblaze/dts/microblaze-generic.dts -+++ b/arch/microblaze/dts/microblaze-generic.dts -@@ -1,9 +1,587 @@ - /dts-v1/; -+ - / { -- #address-cells = <1>; -- #size-cells = <1>; -- aliases { -- } ; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ compatible = "xlnx,microblaze"; -+ model = "Xilinx MicroBlaze"; -+ hard-reset-gpios = <0x1 0x0 0x1>; -+ -+ cpus { -+ #address-cells = <0x1>; -+ #cpus = <0x1>; -+ #size-cells = <0x0>; -+ -+ cpu@0 { -+ bus-handle = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clocks = <0x3>; -+ compatible = "xlnx,microblaze-10.0"; -+ d-cache-baseaddr = <0x80000000>; -+ d-cache-highaddr = <0xbfffffff>; -+ d-cache-line-size = <0x20>; -+ d-cache-size = <0x4000>; -+ device_type = "cpu"; -+ i-cache-baseaddr = <0x80000000>; -+ i-cache-highaddr = <0xbfffffff>; -+ i-cache-line-size = <0x10>; -+ i-cache-size = <0x4000>; -+ interrupt-handle = <0x4>; -+ model = "microblaze,10.0"; -+ timebase-frequency = <0xbebc200>; -+ xlnx,addr-size = <0x20>; -+ xlnx,addr-tag-bits = <0x10>; -+ xlnx,allow-dcache-wr = <0x1>; -+ xlnx,allow-icache-wr = <0x1>; -+ xlnx,area-optimized = <0x0>; -+ xlnx,async-interrupt = <0x1>; -+ xlnx,async-wakeup = <0x3>; -+ xlnx,avoid-primitives = <0x0>; -+ xlnx,base-vectors = <0x0>; -+ xlnx,branch-target-cache-size = <0x0>; -+ xlnx,cache-byte-size = <0x4000>; -+ xlnx,d-axi = <0x1>; -+ xlnx,d-lmb = <0x1>; -+ xlnx,d-lmb-mon = <0x0>; -+ xlnx,daddr-size = <0x20>; -+ xlnx,data-size = <0x20>; -+ xlnx,dc-axi-mon = <0x0>; -+ xlnx,dcache-addr-tag = <0x10>; -+ xlnx,dcache-always-used = <0x1>; -+ xlnx,dcache-byte-size = <0x4000>; -+ xlnx,dcache-data-width = <0x0>; -+ xlnx,dcache-force-tag-lutram = <0x0>; -+ xlnx,dcache-line-len = <0x8>; -+ xlnx,dcache-use-writeback = <0x0>; -+ xlnx,dcache-victims = <0x0>; -+ xlnx,debug-counter-width = <0x20>; -+ xlnx,debug-enabled = <0x1>; -+ xlnx,debug-event-counters = <0x5>; -+ xlnx,debug-external-trace = <0x0>; -+ xlnx,debug-interface = <0x0>; -+ xlnx,debug-latency-counters = <0x1>; -+ xlnx,debug-profile-size = <0x0>; -+ xlnx,debug-trace-async-reset = <0x0>; -+ xlnx,debug-trace-size = <0x2000>; -+ xlnx,div-zero-exception = <0x1>; -+ xlnx,dp-axi-mon = <0x0>; -+ xlnx,dynamic-bus-sizing = <0x0>; -+ xlnx,ecc-use-ce-exception = <0x0>; -+ xlnx,edge-is-positive = <0x1>; -+ xlnx,enable-discrete-ports = <0x0>; -+ xlnx,endianness = <0x1>; -+ xlnx,fault-tolerant = <0x0>; -+ xlnx,fpu-exception = <0x0>; -+ xlnx,freq = <0xbebc200>; -+ xlnx,fsl-exception = <0x0>; -+ xlnx,fsl-links = <0x0>; -+ xlnx,i-axi = <0x0>; -+ xlnx,i-lmb = <0x1>; -+ xlnx,i-lmb-mon = <0x0>; -+ xlnx,iaddr-size = <0x20>; -+ xlnx,ic-axi-mon = <0x0>; -+ xlnx,icache-always-used = <0x1>; -+ xlnx,icache-data-width = <0x0>; -+ xlnx,icache-force-tag-lutram = <0x0>; -+ xlnx,icache-line-len = <0x4>; -+ xlnx,icache-streams = <0x1>; -+ xlnx,icache-victims = <0x8>; -+ xlnx,ill-opcode-exception = <0x1>; -+ xlnx,imprecise-exceptions = <0x0>; -+ xlnx,instr-size = <0x20>; -+ xlnx,interconnect = <0x2>; -+ xlnx,interrupt-is-edge = <0x0>; -+ xlnx,interrupt-mon = <0x0>; -+ xlnx,ip-axi-mon = <0x0>; -+ xlnx,lockstep-master = <0x0>; -+ xlnx,lockstep-select = <0x0>; -+ xlnx,lockstep-slave = <0x0>; -+ xlnx,mmu-dtlb-size = <0x4>; -+ xlnx,mmu-itlb-size = <0x2>; -+ xlnx,mmu-privileged-instr = <0x0>; -+ xlnx,mmu-tlb-access = <0x3>; -+ xlnx,mmu-zones = <0x2>; -+ xlnx,num-sync-ff-clk = <0x2>; -+ xlnx,num-sync-ff-clk-debug = <0x2>; -+ xlnx,num-sync-ff-clk-irq = <0x1>; -+ xlnx,num-sync-ff-dbg-clk = <0x1>; -+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>; -+ xlnx,number-of-pc-brk = <0x1>; -+ xlnx,number-of-rd-addr-brk = <0x0>; -+ xlnx,number-of-wr-addr-brk = <0x0>; -+ xlnx,opcode-0x0-illegal = <0x1>; -+ xlnx,optimization = <0x0>; -+ xlnx,pc-width = <0x20>; -+ xlnx,piaddr-size = <0x20>; -+ xlnx,pvr = <0x2>; -+ xlnx,pvr-user1 = <0x0>; -+ xlnx,pvr-user2 = <0x0>; -+ xlnx,reset-msr = <0x0>; -+ xlnx,reset-msr-bip = <0x0>; -+ xlnx,reset-msr-dce = <0x0>; -+ xlnx,reset-msr-ee = <0x0>; -+ xlnx,reset-msr-eip = <0x0>; -+ xlnx,reset-msr-ice = <0x0>; -+ xlnx,reset-msr-ie = <0x0>; -+ xlnx,sco = <0x0>; -+ xlnx,trace = <0x0>; -+ xlnx,unaligned-exceptions = <0x1>; -+ xlnx,use-barrel = <0x1>; -+ xlnx,use-branch-target-cache = <0x0>; -+ xlnx,use-config-reset = <0x0>; -+ xlnx,use-dcache = <0x1>; -+ xlnx,use-div = <0x1>; -+ xlnx,use-ext-brk = <0x0>; -+ xlnx,use-ext-nm-brk = <0x0>; -+ xlnx,use-extended-fsl-instr = <0x0>; -+ xlnx,use-fpu = <0x0>; -+ xlnx,use-hw-mul = <0x2>; -+ xlnx,use-icache = <0x1>; -+ xlnx,use-interrupt = <0x2>; -+ xlnx,use-mmu = <0x3>; -+ xlnx,use-msr-instr = <0x1>; -+ xlnx,use-non-secure = <0x0>; -+ xlnx,use-pcmp-instr = <0x1>; -+ xlnx,use-reorder-instr = <0x1>; -+ xlnx,use-stack-protection = <0x0>; -+ }; -+ }; -+ -+ clocks { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ -+ clk_cpu@0 { -+ #clock-cells = <0x0>; -+ clock-frequency = <0xbebc200>; -+ clock-output-names = "clk_cpu"; -+ compatible = "fixed-clock"; -+ reg = <0x0>; -+ linux,phandle = <0x3>; -+ phandle = <0x3>; -+ }; -+ -+ clk_bus_0@1 { -+ #clock-cells = <0x0>; -+ clock-frequency = <0xbebc200>; -+ clock-output-names = "clk_bus_0"; -+ compatible = "fixed-clock"; -+ reg = <0x1>; -+ linux,phandle = <0x8>; -+ phandle = <0x8>; -+ }; -+ }; -+ -+ amba_pl { -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ compatible = "simple-bus"; -+ ranges; -+ linux,phandle = <0x2>; -+ phandle = <0x2>; -+ -+ ethernet@40c00000 { -+ axistream-connected = <0x5>; -+ axistream-control-connected = <0x5>; -+ clock-frequency = <0x5f5e100>; -+ compatible = "xlnx,axi-ethernet-1.00.a"; -+ device_type = "network"; -+ interrupt-names = "interrupt"; -+ interrupt-parent = <0x4>; -+ interrupts = <0x4 0x2>; -+ phy-mode = "gmii"; -+ reg = <0x40c00000 0x40000>; -+ xlnx = <0x0>; -+ xlnx,axiliteclkrate = <0x0>; -+ xlnx,axisclkrate = <0x0>; -+ xlnx,clockselection = <0x0>; -+ xlnx,enableasyncsgmii = <0x0>; -+ xlnx,gt-type = <0x0>; -+ xlnx,gtinex = <0x0>; -+ xlnx,gtlocation = <0x0>; -+ xlnx,gtrefclksrc = <0x0>; -+ xlnx,include-dre; -+ xlnx,instantiatebitslice0 = <0x0>; -+ xlnx,phy-type = <0x1>; -+ xlnx,phyaddr = <0x1>; -+ xlnx,rable = <0x0>; -+ xlnx,rxcsum = <0x0>; -+ xlnx,rxlane0-placement = <0x0>; -+ xlnx,rxlane1-placement = <0x0>; -+ xlnx,rxmem = <0x1000>; -+ xlnx,rxnibblebitslice0used = <0x0>; -+ xlnx,tx-in-upper-nibble = <0x1>; -+ xlnx,txcsum = <0x0>; -+ xlnx,txlane0-placement = <0x0>; -+ xlnx,txlane1-placement = <0x0>; -+ phy-handle = <0x6>; -+ local-mac-address = [00 0a 35 00 22 01]; -+ linux,phandle = <0x7>; -+ phandle = <0x7>; -+ -+ mdio { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ -+ phy@7 { -+ device_type = "ethernet-phy"; -+ reg = <0x7>; -+ linux,phandle = <0x6>; -+ phandle = <0x6>; -+ }; -+ }; -+ }; -+ -+ dma@41e00000 { -+ #dma-cells = <0x1>; -+ axistream-connected = <0x7>; -+ axistream-control-connected = <0x7>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_lite_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,eth-dma"; -+ interrupt-names = "mm2s_introut", "s2mm_introut"; -+ interrupt-parent = <0x4>; -+ interrupts = <0x3 0x2 0x2 0x2>; -+ reg = <0x41e00000 0x10000>; -+ xlnx,include-dre; -+ linux,phandle = <0x5>; -+ phandle = <0x5>; -+ }; -+ -+ timer@41c00000 { -+ clock-frequency = <0xbebc200>; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-timer-1.00.a"; -+ interrupt-names = "interrupt"; -+ interrupt-parent = <0x4>; -+ interrupts = <0x5 0x2>; -+ reg = <0x41c00000 0x10000>; -+ xlnx,count-width = <0x20>; -+ xlnx,gen0-assert = <0x1>; -+ xlnx,gen1-assert = <0x1>; -+ xlnx,one-timer-only = <0x0>; -+ xlnx,trig0-assert = <0x1>; -+ xlnx,trig1-assert = <0x1>; -+ }; -+ -+ gpio@40010000 { -+ #gpio-cells = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-gpio-1.00.a"; -+ gpio-controller; -+ reg = <0x40010000 0x10000>; -+ xlnx,all-inputs = <0x1>; -+ xlnx,all-inputs-2 = <0x0>; -+ xlnx,all-outputs = <0x0>; -+ xlnx,all-outputs-2 = <0x0>; -+ xlnx,dout-default = <0x0>; -+ xlnx,dout-default-2 = <0x0>; -+ xlnx,gpio-width = <0x1>; -+ xlnx,gpio2-width = <0x20>; -+ xlnx,interrupt-present = <0x0>; -+ xlnx,is-dual = <0x0>; -+ xlnx,tri-default = <0xffffffff>; -+ xlnx,tri-default-2 = <0xffffffff>; -+ }; -+ -+ gpio@40020000 { -+ #gpio-cells = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-gpio-1.00.a"; -+ gpio-controller; -+ reg = <0x40020000 0x10000>; -+ xlnx,all-inputs = <0x1>; -+ xlnx,all-inputs-2 = <0x0>; -+ xlnx,all-outputs = <0x0>; -+ xlnx,all-outputs-2 = <0x0>; -+ xlnx,dout-default = <0x0>; -+ xlnx,dout-default-2 = <0x0>; -+ xlnx,gpio-width = <0x4>; -+ xlnx,gpio2-width = <0x20>; -+ xlnx,interrupt-present = <0x0>; -+ xlnx,is-dual = <0x0>; -+ xlnx,tri-default = <0xffffffff>; -+ xlnx,tri-default-2 = <0xffffffff>; -+ }; -+ -+ i2c@40800000 { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ clock-frequency = <0xbebc200>; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-iic-2.00.a"; -+ interrupt-names = "iic2intc_irpt"; -+ interrupt-parent = <0x4>; -+ interrupts = <0x1 0x2>; -+ reg = <0x40800000 0x10000>; -+ -+ i2cswitch@74 { -+ compatible = "nxp,pca9548"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ reg = <0x74>; -+ -+ i2c@0 { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ reg = <0x0>; -+ -+ clock-generator@5d { -+ #clock-cells = <0x0>; -+ compatible = "silabs,si570"; -+ temperature-stability = <0x32>; -+ reg = <0x5d>; -+ factory-fout = <0x9502f90>; -+ clock-frequency = <0x8d9ee20>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ reg = <0x3>; -+ -+ eeprom@54 { -+ compatible = "at,24c08"; -+ reg = <0x54>; -+ }; -+ }; -+ }; -+ }; -+ -+ gpio@40030000 { -+ #gpio-cells = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-gpio-1.00.a"; -+ gpio-controller; -+ reg = <0x40030000 0x10000>; -+ xlnx,all-inputs = <0x0>; -+ xlnx,all-inputs-2 = <0x0>; -+ xlnx,all-outputs = <0x1>; -+ xlnx,all-outputs-2 = <0x0>; -+ xlnx,dout-default = <0x0>; -+ xlnx,dout-default-2 = <0x0>; -+ xlnx,gpio-width = <0x8>; -+ xlnx,gpio2-width = <0x20>; -+ xlnx,interrupt-present = <0x0>; -+ xlnx,is-dual = <0x0>; -+ xlnx,tri-default = <0xffffffff>; -+ xlnx,tri-default-2 = <0xffffffff>; -+ }; -+ -+ flash@60000000 { -+ bank-width = <0x2>; -+ compatible = "cfi-flash"; -+ reg = <0x60000000 0x8000000>; -+ xlnx,axi-clk-period-ps = <0x1388>; -+ xlnx,include-datawidth-matching-0 = <0x1>; -+ xlnx,include-datawidth-matching-1 = <0x1>; -+ xlnx,include-datawidth-matching-2 = <0x1>; -+ xlnx,include-datawidth-matching-3 = <0x1>; -+ xlnx,include-negedge-ioregs = <0x0>; -+ xlnx,lflash-period-ps = <0x1388>; -+ xlnx,linear-flash-sync-burst = <0x0>; -+ xlnx,max-mem-width = <0x10>; -+ xlnx,mem-a-lsb = <0x0>; -+ xlnx,mem-a-msb = <0x1f>; -+ xlnx,mem0-type = <0x2>; -+ xlnx,mem0-width = <0x10>; -+ xlnx,mem1-type = <0x0>; -+ xlnx,mem1-width = <0x10>; -+ xlnx,mem2-type = <0x0>; -+ xlnx,mem2-width = <0x10>; -+ xlnx,mem3-type = <0x0>; -+ xlnx,mem3-width = <0x10>; -+ xlnx,num-banks-mem = <0x1>; -+ xlnx,page-size = <0x10>; -+ xlnx,parity-type-mem-0 = <0x0>; -+ xlnx,parity-type-mem-1 = <0x0>; -+ xlnx,parity-type-mem-2 = <0x0>; -+ xlnx,parity-type-mem-3 = <0x0>; -+ xlnx,port-diff = <0x0>; -+ xlnx,s-axi-en-reg = <0x0>; -+ xlnx,s-axi-mem-addr-width = <0x20>; -+ xlnx,s-axi-mem-data-width = <0x20>; -+ xlnx,s-axi-mem-id-width = <0x1>; -+ xlnx,s-axi-reg-addr-width = <0x5>; -+ xlnx,s-axi-reg-data-width = <0x20>; -+ xlnx,synch-pipedelay-0 = <0x1>; -+ xlnx,synch-pipedelay-1 = <0x1>; -+ xlnx,synch-pipedelay-2 = <0x1>; -+ xlnx,synch-pipedelay-3 = <0x1>; -+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>; -+ xlnx,tavdv-ps-mem-1 = <0x3a98>; -+ xlnx,tavdv-ps-mem-2 = <0x3a98>; -+ xlnx,tavdv-ps-mem-3 = <0x3a98>; -+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>; -+ xlnx,tcedv-ps-mem-1 = <0x3a98>; -+ xlnx,tcedv-ps-mem-2 = <0x3a98>; -+ xlnx,tcedv-ps-mem-3 = <0x3a98>; -+ xlnx,thzce-ps-mem-0 = <0x88b8>; -+ xlnx,thzce-ps-mem-1 = <0x1b58>; -+ xlnx,thzce-ps-mem-2 = <0x1b58>; -+ xlnx,thzce-ps-mem-3 = <0x1b58>; -+ xlnx,thzoe-ps-mem-0 = <0x1b58>; -+ xlnx,thzoe-ps-mem-1 = <0x1b58>; -+ xlnx,thzoe-ps-mem-2 = <0x1b58>; -+ xlnx,thzoe-ps-mem-3 = <0x1b58>; -+ xlnx,tlzwe-ps-mem-0 = <0xc350>; -+ xlnx,tlzwe-ps-mem-1 = <0x0>; -+ xlnx,tlzwe-ps-mem-2 = <0x0>; -+ xlnx,tlzwe-ps-mem-3 = <0x0>; -+ xlnx,tpacc-ps-flash-0 = <0x61a8>; -+ xlnx,tpacc-ps-flash-1 = <0x61a8>; -+ xlnx,tpacc-ps-flash-2 = <0x61a8>; -+ xlnx,tpacc-ps-flash-3 = <0x61a8>; -+ xlnx,twc-ps-mem-0 = <0x11170>; -+ xlnx,twc-ps-mem-1 = <0x3a98>; -+ xlnx,twc-ps-mem-2 = <0x3a98>; -+ xlnx,twc-ps-mem-3 = <0x3a98>; -+ xlnx,twp-ps-mem-0 = <0x13880>; -+ xlnx,twp-ps-mem-1 = <0x2ee0>; -+ xlnx,twp-ps-mem-2 = <0x2ee0>; -+ xlnx,twp-ps-mem-3 = <0x2ee0>; -+ xlnx,twph-ps-mem-0 = <0x13880>; -+ xlnx,twph-ps-mem-1 = <0x2ee0>; -+ xlnx,twph-ps-mem-2 = <0x2ee0>; -+ xlnx,twph-ps-mem-3 = <0x2ee0>; -+ xlnx,use-startup = <0x0>; -+ xlnx,use-startup-int = <0x0>; -+ xlnx,wr-rec-time-mem-0 = <0x186a0>; -+ xlnx,wr-rec-time-mem-1 = <0x6978>; -+ xlnx,wr-rec-time-mem-2 = <0x6978>; -+ xlnx,wr-rec-time-mem-3 = <0x6978>; -+ #address-cells = <0x1>; -+ #size-cells = <0x1>; -+ -+ partition@0x00000000 { -+ label = "fpga"; -+ reg = <0x0 0xb00000>; -+ }; -+ -+ partition@0x00b00000 { -+ label = "boot"; -+ reg = <0xb00000 0x80000>; -+ }; -+ -+ partition@0x00b80000 { -+ label = "bootenv"; -+ reg = <0xb80000 0x20000>; -+ }; -+ -+ partition@0x00ba0000 { -+ label = "kernel"; -+ reg = <0xba0000 0xc00000>; -+ }; -+ -+ partition@0x017a0000 { -+ label = "spare"; -+ reg = <0x17a0000 0x0>; -+ }; -+ }; -+ -+ interrupt-controller@41200000 { -+ #interrupt-cells = <0x2>; -+ compatible = "xlnx,xps-intc-1.00.a"; -+ interrupt-controller; -+ reg = <0x41200000 0x10000>; -+ xlnx,kind-of-intr = <0x0>; -+ xlnx,num-intr-inputs = <0x6>; -+ linux,phandle = <0x4>; -+ phandle = <0x4>; -+ }; -+ -+ gpio@40040000 { -+ #gpio-cells = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-gpio-1.00.a"; -+ gpio-controller; -+ reg = <0x40040000 0x10000>; -+ xlnx,all-inputs = <0x1>; -+ xlnx,all-inputs-2 = <0x0>; -+ xlnx,all-outputs = <0x0>; -+ xlnx,all-outputs-2 = <0x0>; -+ xlnx,dout-default = <0x0>; -+ xlnx,dout-default-2 = <0x0>; -+ xlnx,gpio-width = <0x5>; -+ xlnx,gpio2-width = <0x20>; -+ xlnx,interrupt-present = <0x0>; -+ xlnx,is-dual = <0x0>; -+ xlnx,tri-default = <0xffffffff>; -+ xlnx,tri-default-2 = <0xffffffff>; -+ }; -+ -+ gpio@40000000 { -+ #gpio-cells = <0x2>; -+ clock-frequency = <0xbebc200>; -+ clock-names = "s_axi_aclk"; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-gpio-1.00.a"; -+ gpio-controller; -+ reg = <0x40000000 0x10000>; -+ xlnx,all-inputs = <0x0>; -+ xlnx,all-inputs-2 = <0x0>; -+ xlnx,all-outputs = <0x1>; -+ xlnx,all-outputs-2 = <0x0>; -+ xlnx,dout-default = <0x0>; -+ xlnx,dout-default-2 = <0x0>; -+ xlnx,gpio-width = <0x1>; -+ xlnx,gpio2-width = <0x20>; -+ xlnx,interrupt-present = <0x0>; -+ xlnx,is-dual = <0x0>; -+ xlnx,tri-default = <0xffffffff>; -+ xlnx,tri-default-2 = <0xffffffff>; -+ linux,phandle = <0x1>; -+ phandle = <0x1>; -+ }; -+ -+ serial@44a00000 { -+ clock-frequency = <0xbebc200>; -+ clocks = <0x8>; -+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; -+ current-speed = <0x1c200>; -+ device_type = "serial"; -+ interrupt-names = "ip2intc_irpt"; -+ interrupt-parent = <0x4>; -+ interrupts = <0x0 0x2>; -+ port-number = <0x0>; -+ reg = <0x44a00000 0x10000>; -+ reg-offset = <0x1000>; -+ reg-shift = <0x2>; -+ xlnx,external-xin-clk-hz = <0x17d7840>; -+ xlnx,external-xin-clk-hz-d = <0x19>; -+ xlnx,has-external-rclk = <0x0>; -+ xlnx,has-external-xin = <0x0>; -+ xlnx,is-a-16550 = <0x1>; -+ xlnx,s-axi-aclk-freq-hz-d = "200.0"; -+ xlnx,use-modem-ports = <0x1>; -+ xlnx,use-user-ports = <0x1>; -+ }; -+ }; -+ - chosen { -- } ; --} ; -+ bootargs = "console=ttyS0,115200 earlyprintk"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ ethernet0 = "/amba_pl/ethernet@40c00000"; -+ i2c0 = "/amba_pl/i2c@40800000"; -+ serial0 = "/amba_pl/serial@44a00000"; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x80000000 0x40000000>; -+ }; -+}; -+ -diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk -index 1dee2d6..cb75fde 100644 ---- a/board/xilinx/microblaze-generic/config.mk -+++ b/board/xilinx/microblaze-generic/config.mk -@@ -1,20 +1,10 @@ --# --# (C) Copyright 2007 - 2016 Michal Simek --# --# Michal SIMEK --# --# SPDX-License-Identifier: GPL-2.0+ --# -- --CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER)) -- --# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support. --CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high --CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul --CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div --CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift --CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare -- --CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER)) -- --PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2) -+TEXT_BASE = 0x80400000 -+CONFIG_SYS_TEXT_BASE = 0x80400000 -+ -+PLATFORM_CPPFLAGS += -mxl-barrel-shift -+PLATFORM_CPPFLAGS += -mno-xl-soft-div -+PLATFORM_CPPFLAGS += -mxl-pattern-compare -+PLATFORM_CPPFLAGS += -mxl-multiply-high -+PLATFORM_CPPFLAGS += -mno-xl-soft-mul -+PLATFORM_CPPFLAGS += -mcpu=v10.0 -+PLATFORM_CPPFLAGS += -fgnu89-inline -diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig -index 08d99f2..bac6939 100644 ---- a/configs/microblaze-generic_defconfig -+++ b/configs/microblaze-generic_defconfig -@@ -1,5 +1,4 @@ - CONFIG_MICROBLAZE=y --CONFIG_SYS_TEXT_BASE=0x29000000 - CONFIG_SPL_LIBCOMMON_SUPPORT=y - CONFIG_SPL_LIBGENERIC_SUPPORT=y - CONFIG_SPL_SERIAL_SUPPORT=y -@@ -8,50 +7,50 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 - CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 - CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 - CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 -+CONFIG_SYS_TEXT_BASE=0x80400000 - CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y --CONFIG_BOOTDELAY=-1 --CONFIG_USE_BOOTARGS=y --CONFIG_BOOTARGS="root=romfs" -+CONFIG_BOOTDELAY=4 - CONFIG_SYS_CONSOLE_IS_IN_ENV=y --CONFIG_SPL=y --CONFIG_SPL_BOARD_INIT=y --CONFIG_SPL_SYS_MALLOC_SIMPLE=y - CONFIG_SPL_NOR_SUPPORT=y - CONFIG_SPL_OS_BOOT=y - CONFIG_SYS_OS_BASE=0x2c060000 - CONFIG_HUSH_PARSER=y --CONFIG_SYS_PROMPT="U-Boot-mONStR> " --CONFIG_CMD_IMLS=y --CONFIG_CMD_SPL=y -+CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_ASKENV=y --CONFIG_CMD_GPIO=y - CONFIG_CMD_SAVES=y - # CONFIG_CMD_SETEXPR is not set --CONFIG_CMD_TFTPPUT=y -+CONFIG_SYS_ENET=y -+CONFIG_NET=y -+CONFIG_NETDEVICES=y -+CONFIG_CMD_NET=y - CONFIG_CMD_DHCP=y -+CONFIG_CMD_NFS=y - CONFIG_CMD_MII=y - CONFIG_CMD_PING=y - CONFIG_CMD_JFFS2=y --CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_EMBED=y --CONFIG_ENV_IS_IN_FLASH=y --CONFIG_NETCONSOLE=y --CONFIG_SPL_DM=y --CONFIG_MTD_NOR_FLASH=y --CONFIG_PHY_ATHEROS=y --CONFIG_PHY_BROADCOM=y --CONFIG_PHY_DAVICOM=y --CONFIG_PHY_LXT=y --CONFIG_PHY_MARVELL=y --CONFIG_PHY_MICREL=y --CONFIG_PHY_MICREL_KSZ90X1=y --CONFIG_PHY_NATSEMI=y --CONFIG_PHY_REALTEK=y --CONFIG_PHY_VITESSE=y - CONFIG_DM_ETH=y -+CONFIG_SYS_MALLOC_F=y -+CONFIG_SYS_GENERIC_BOARD=y - CONFIG_XILINX_AXIEMAC=y --CONFIG_XILINX_EMACLITE=y - CONFIG_SYS_NS16550=y --CONFIG_XILINX_UARTLITE=y -+CONFIG_CMD_FLASH=y -+CONFIG_MTD_NOR_FLASH=y -+CONFIG_CMD_IMLS=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_TFTPPUT=y -+CONFIG_NETCONSOLE=y -+CONFIG_XILINX_FSL_LINKS=0 -+CONFIG_PHY_GIGE=y -+CONFIG_ENV_IS_IN_FLASH=y -+CONFIG_PHY_MICREL=y -+CONFIG_PHY_MICREL_KSZ90X1=y -+CONFIG_SPL_DM_SERIAL=y -+CONFIG_SPL_OF_LIBFDT=y -+CONFIG_PHY_XILINX=y -+# CONFIG_SPL is not set -+# CONFIG_CMD_EEPROM is not set -+# CONFIG_BOOTARGS is not set -+# CONFIG_USE_BOOTARGS is not set -diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h -index 16481cb..1377c5e 100644 ---- a/include/configs/microblaze-generic.h -+++ b/include/configs/microblaze-generic.h -@@ -1,254 +1,178 @@ --/* -- * (C) Copyright 2007-2010 Michal Simek -- * -- * Michal SIMEK -- * -- * SPDX-License-Identifier: GPL-2.0+ -- */ -- - #ifndef __CONFIG_H - #define __CONFIG_H - --#include "../board/xilinx/microblaze-generic/xparameters.h" -- --/* MicroBlaze CPU */ --#define MICROBLAZE_V5 1 -- --/* linear and spi flash memory */ --#ifdef XILINX_FLASH_START --#define FLASH --#undef SPIFLASH --#undef RAMENV /* hold environment in flash */ --#else --#ifdef XILINX_SPI_FLASH_BASEADDR --#undef FLASH --#define SPIFLASH --#undef RAMENV /* hold environment in flash */ --#else --#undef FLASH --#undef SPIFLASH --#define RAMENV /* hold environment in RAM */ --#endif --#endif -- --/* uart */ --/* The following table includes the supported baudrates */ --# define CONFIG_SYS_BAUDRATE_TABLE \ -- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -- --/* setting reset address */ --/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -- --/* gpio */ --#ifdef XILINX_GPIO_BASEADDR --# define CONFIG_XILINX_GPIO --# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR --#endif -- --/* watchdog */ --#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) --# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR --# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ --# ifndef CONFIG_SPL_BUILD --# define CONFIG_HW_WATCHDOG --# define CONFIG_XILINX_TB_WATCHDOG --# endif --#endif -- --#define CONFIG_SYS_MALLOC_LEN 0xC0000 -- --/* Stack location before relocation */ --#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ -- CONFIG_SYS_MALLOC_F_LEN) -- --/* -- * CFI flash memory layout - Example -- * CONFIG_SYS_FLASH_BASE = 0x2200_0000; -- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB -- * -- * SECT_SIZE = 0x20000; 128kB is one sector -- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store -- * -- * 0x2200_0000 CONFIG_SYS_FLASH_BASE -- * FREE 256kB -- * 0x2204_0000 CONFIG_ENV_ADDR -- * ENV_AREA 128kB -- * 0x2206_0000 -- * FREE -- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE -- * -- */ -- --#ifdef FLASH --# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START --# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE --# define CONFIG_SYS_FLASH_CFI 1 --# define CONFIG_FLASH_CFI_DRIVER 1 --/* ?empty sector */ --# define CONFIG_SYS_FLASH_EMPTY_INFO 1 --/* max number of memory banks */ --# define CONFIG_SYS_MAX_FLASH_BANKS 1 --/* max number of sectors on one chip */ --# define CONFIG_SYS_MAX_FLASH_SECT 512 --/* hardware flash protection */ --# define CONFIG_SYS_FLASH_PROTECTION --/* use buffered writes (20x faster) */ --# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 --# ifdef RAMENV --# define CONFIG_ENV_SIZE 0x1000 --# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -- --# else /* FLASH && !RAMENV */ --/* 128K(one sector) for env */ --# define CONFIG_ENV_SECT_SIZE 0x20000 --# define CONFIG_ENV_ADDR \ -- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) --# define CONFIG_ENV_SIZE 0x20000 --# endif /* FLASH && !RAMBOOT */ --#else /* !FLASH */ -- --#ifdef SPIFLASH --# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR --# define CONFIG_SPI 1 --# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 --# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ --# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS -- --# ifdef RAMENV --# define CONFIG_ENV_SIZE 0x1000 --# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -- --# else /* SPIFLASH && !RAMENV */ --# define CONFIG_ENV_SPI_MODE SPI_MODE_3 --# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED --# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS --/* 128K(two sectors) for env */ --# define CONFIG_ENV_SECT_SIZE 0x10000 --# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) --/* Warning: adjust the offset in respect of other flash content and size */ --# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ --# endif /* SPIFLASH && !RAMBOOT */ --#else /* !SPIFLASH */ -- --/* ENV in RAM */ --# define CONFIG_ENV_SIZE 0x1000 --# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) --#endif /* !SPIFLASH */ --#endif /* !FLASH */ -- --#if defined(XILINX_USE_ICACHE) --# define CONFIG_ICACHE --#else --# undef CONFIG_ICACHE --#endif -- --#if defined(XILINX_USE_DCACHE) --# define CONFIG_DCACHE --#else --# undef CONFIG_DCACHE --#endif -- --#ifndef XILINX_DCACHE_BYTE_SIZE --#define XILINX_DCACHE_BYTE_SIZE 32768 --#endif -- --/* -- * BOOTP options -- */ -+#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } -+ -+/* processor - microblaze_0 */ -+#define XILINX_USE_MSR_INSTR 1 -+#define XILINX_USE_ICACHE 1 -+#define XILINX_USE_DCACHE 1 -+#define XILINX_DCACHE_BYTE_SIZE 16384 -+#define XILINX_PVR 2 -+#define MICROBLAZE_V5 -+#define CONFIG_CMD_IRQ -+#define CONFIG_DCACHE -+#define CONFIG_ICACHE -+ -+/* main_memory - ddr3_sdram */ -+ -+ -+/* uart - rs232_uart */ -+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) -+#define CONFIG_SYS_NS16550_REG_SIZE -4 -+#define CONSOLE_ARG "console=console=ttyS0,115200\0" -+#define CONFIG_SYS_NS16550_SERIAL -+#define CONFIG_CONS_INDEX 1 -+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0" -+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" -+#define CONFIG_SYS_NS16550_CLK 200000000 -+#define CONFIG_BAUDRATE 115200 -+ -+/* ethernet - axi_ethernet */ -+#define CONFIG_PHY_XILINX -+#define CONFIG_MII -+#define CONFIG_PHY_MARVELL -+#define CONFIG_PHY_NATSEMI -+#define CONFIG_NET_MULTI -+#define CONFIG_PHY_REALTEK -+#define CONFIG_NETCONSOLE 1 -+#define CONFIG_SERVERIP 172.25.229.115 -+#define CONFIG_IPADDR -+ -+/* nor_flash - linear_flash */ -+#define CONFIG_SYS_FLASH_BASE 0x60000000 -+#define CONFIG_FLASH_END 0x68000000 -+#define CONFIG_SYS_MAX_FLASH_SECT 2048 -+#define CONFIG_SYS_FLASH_PROTECTION -+#define CONFIG_SYS_FLASH_EMPTY_INFO -+#define CONFIG_SYS_FLASH_CFI -+#define CONFIG_FLASH_CFI_DRIVER -+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -+#define CONFIG_SYS_MAX_FLASH_BANKS 1 -+ -+/* timer - axi_timer_0 */ -+ -+/* gpio - reset_gpio */ -+#define XILINX_GPIO_BASEADDR 0x40000000 -+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000 -+#define CONFIG_XILINX_GPIO -+ -+/* intc - microblaze_0_axi_intc */ -+ -+/* FPGA */ -+ -+/* Memory testing handling */ -+#define CONFIG_SYS_MEMTEST_START 0x80000000 -+#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000) -+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */ -+ -+/* global pointer options */ -+#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE) -+ -+/* Size of malloc() pool */ -+#define SIZE 0x100000 -+#define CONFIG_SYS_MALLOC_LEN SIZE -+#define CONFIG_SYS_MONITOR_LEN SIZE -+#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) -+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -+ -+/* stack */ -+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN) -+ -+/* No of_control support yet*/ -+ -+/* BOOTP options */ -+#define CONFIG_BOOTP_SERVERIP - #define CONFIG_BOOTP_BOOTFILESIZE - #define CONFIG_BOOTP_BOOTPATH - #define CONFIG_BOOTP_GATEWAY - #define CONFIG_BOOTP_HOSTNAME -+#define CONFIG_BOOTP_MAY_FAIL -+#define CONFIG_BOOTP_DNS -+#define CONFIG_BOOTP_SUBNETMASK -+#define CONFIG_BOOTP_PXE - --#if defined(CONFIG_CMD_JFFS2) --# define CONFIG_MTD_PARTITIONS --#endif -- --#if defined(CONFIG_CMD_UBI) --# define CONFIG_MTD_PARTITIONS --#endif -- --#if defined(CONFIG_MTD_PARTITIONS) --/* MTD partitions */ --#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ --#define CONFIG_FLASH_CFI_MTD -- --/* default mtd partition table */ --#endif -- --/* size of console buffer */ --#define CONFIG_SYS_CBSIZE 512 --/* max number of command args */ --#define CONFIG_SYS_MAXARGS 15 --#define CONFIG_SYS_LONGHELP --/* default load address */ --#define CONFIG_SYS_LOAD_ADDR 0 -- --#define CONFIG_HOSTNAME XILINX_BOARD_NAME --#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -- --/* architecture dependent code */ --#define CONFIG_SYS_USR_EXCEP /* user exception */ -- --#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" -- --#ifndef CONFIG_EXTRA_ENV_SETTINGS --#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ -- "nor0=flash-0\0"\ -- "mtdparts=mtdparts=flash-0:"\ -- "256k(u-boot),256k(env),3m(kernel),"\ -- "1m(romfs),1m(cramfs),-(jffs2)\0"\ -- "nc=setenv stdout nc;"\ -- "setenv stdin nc\0" \ -- "serial=setenv stdout serial;"\ -- "setenv stdin serial\0" --#endif -- -+/*Command line configuration.*/ - #define CONFIG_CMDLINE_EDITING -+#define CONFIG_AUTO_COMPLETE - --/* Enable flat device tree support */ --#define CONFIG_LMB 1 -- --#if defined(CONFIG_XILINX_AXIEMAC) --# define CONFIG_MII 1 --# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 --#else --# undef CONFIG_MII --#endif -- --/* SPL part */ --#define CONFIG_SPL_FRAMEWORK -+/* Miscellaneous configurable options */ -+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */ -+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - --#ifdef CONFIG_SYS_FLASH_BASE --# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE --#endif -- --/* for booting directly linux */ - --#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ -- 0x40000) --#define CONFIG_SYS_FDT_SIZE (16<<10) --#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ -- 0x1000000) -+/* Use the HUSH parser */ -+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - --/* SP location before relocation, must use scratch RAM */ --/* BRAM start */ --#define CONFIG_SYS_INIT_RAM_ADDR 0x0 --/* BRAM size - will be generated */ --#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -+#define CONFIG_ENV_VARS_UBOOT_CONFIG -+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ - --# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ -- CONFIG_SYS_INIT_RAM_SIZE - \ -- CONFIG_SYS_MALLOC_F_LEN) -+#define CONFIG_LMB - --/* Just for sure that there is a space for stack */ --#define CONFIG_SPL_STACK_SIZE 0x100 -+/* FDT support */ -+#define CONFIG_DISPLAY_BOARDINFO_LATE - --#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE - --#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ -- CONFIG_SYS_INIT_RAM_ADDR - \ -- CONFIG_SYS_MALLOC_F_LEN - \ -- CONFIG_SPL_STACK_SIZE) -+/* architecture dependent code */ -+#define CONFIG_SYS_USR_EXCEP /* user exception */ -+#define CONFIG_SYS_HZ 1000 -+ -+/* Boot Argument Buffer Size */ -+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -+#define CONFIG_SYS_LONGHELP -+/* Initial memory map for Linux */ -+#define CONFIG_SYS_BOOTMAPSZ 0x8000000 -+ -+/* Environment settings*/ -+#define CONFIG_ENV_ADDR 0x60b80000 -+#define CONFIG_ENV_SIZE 0x20000 -+#define CONFIG_ENV_SECT_SIZE 0x20000 -+/* PREBOOT */ -+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp" -+ -+/* Extra U-Boot Env settings */ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ SERIAL_MULTI \ -+ CONSOLE_ARG \ -+ ESERIAL0 \ -+ "nc=setenv stdout nc;setenv stdin nc;\0" \ -+ "ethaddr=00:0a:35:00:22:01\0" \ -+ "autoload=no\0" \ -+ "sdbootdev=0\0" \ -+ "clobstart=0x81000000\0" \ -+ "netstart=0x81000000\0" \ -+ "dtbnetstart=0x82800000\0" \ -+ "loadaddr=0x81000000\0" \ -+ "bootsize=0x80000\0" \ -+ "bootstart=0x60b00000\0" \ -+ "boot_img=u-boot-s.bin\0" \ -+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \ -+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \ -+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \ -+ "bootenvsize=0x20000\0" \ -+ "bootenvstart=0x60b80000\0" \ -+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \ -+ "kernelsize=0xc00000\0" \ -+ "kernelstart=0x60ba0000\0" \ -+ "kernel_img=image.ub\0" \ -+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ -+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \ -+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \ -+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \ -+ "fpgasize=0xb00000\0" \ -+ "fpgastart=0x60000000\0" \ -+ "fpga_img=system.bit.bin\0" \ -+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \ -+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \ -+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \ -+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ -+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ -+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ -+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ -+ "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ -+"" -+/* BOOTCOMMAND */ -+#define CONFIG_BOOTCOMMAND "run default_bootcmd" - --#endif /* __CONFIG_H */ -+#endif --- -2.7.4 - diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch new file mode 100644 index 00000000..ce8771f8 --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch @@ -0,0 +1,1168 @@ +From 539838b4fe4afecd9b6874c5ac397ab7f5b343d4 Mon Sep 17 00:00:00 2001 +From: Manjukumar Matha +Date: Tue, 10 Apr 2018 18:34:45 -0700 +Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to + kc705-microblazeel + +This is an update to earlier kc705-trd patch done by Nathan Rossi. +Starting from v2016.1, KC705 will no longer refer to deprecated KC705 +TRD application. + +Change the microblaze-generic board to match the kc705-microblazeel. +This patch is not intended for upstream and serves as an intermediate +solution until OF support in upstream u-boot allows for easy support for +custom microblaze boards. + +Signed-off-by: Manjukumar Matha +Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific] +--- + arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++- + board/xilinx/microblaze-generic/config.mk | 30 +- + configs/microblaze-generic_defconfig | 57 ++- + include/configs/microblaze-generic.h | 396 ++++++++----------- + 4 files changed, 782 insertions(+), 291 deletions(-) + +diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts +index 08a1396..f8e616b 100644 +--- a/arch/microblaze/dts/microblaze-generic.dts ++++ b/arch/microblaze/dts/microblaze-generic.dts +@@ -1,9 +1,587 @@ + /dts-v1/; ++ + / { +- #address-cells = <1>; +- #size-cells = <1>; +- aliases { +- } ; ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ compatible = "xlnx,microblaze"; ++ model = "Xilinx MicroBlaze"; ++ hard-reset-gpios = <0x1 0x0 0x1>; ++ ++ cpus { ++ #address-cells = <0x1>; ++ #cpus = <0x1>; ++ #size-cells = <0x0>; ++ ++ cpu@0 { ++ bus-handle = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clocks = <0x3>; ++ compatible = "xlnx,microblaze-10.0"; ++ d-cache-baseaddr = <0x80000000>; ++ d-cache-highaddr = <0xbfffffff>; ++ d-cache-line-size = <0x20>; ++ d-cache-size = <0x4000>; ++ device_type = "cpu"; ++ i-cache-baseaddr = <0x80000000>; ++ i-cache-highaddr = <0xbfffffff>; ++ i-cache-line-size = <0x10>; ++ i-cache-size = <0x4000>; ++ interrupt-handle = <0x4>; ++ model = "microblaze,10.0"; ++ timebase-frequency = <0xbebc200>; ++ xlnx,addr-size = <0x20>; ++ xlnx,addr-tag-bits = <0x10>; ++ xlnx,allow-dcache-wr = <0x1>; ++ xlnx,allow-icache-wr = <0x1>; ++ xlnx,area-optimized = <0x0>; ++ xlnx,async-interrupt = <0x1>; ++ xlnx,async-wakeup = <0x3>; ++ xlnx,avoid-primitives = <0x0>; ++ xlnx,base-vectors = <0x0>; ++ xlnx,branch-target-cache-size = <0x0>; ++ xlnx,cache-byte-size = <0x4000>; ++ xlnx,d-axi = <0x1>; ++ xlnx,d-lmb = <0x1>; ++ xlnx,d-lmb-mon = <0x0>; ++ xlnx,daddr-size = <0x20>; ++ xlnx,data-size = <0x20>; ++ xlnx,dc-axi-mon = <0x0>; ++ xlnx,dcache-addr-tag = <0x10>; ++ xlnx,dcache-always-used = <0x1>; ++ xlnx,dcache-byte-size = <0x4000>; ++ xlnx,dcache-data-width = <0x0>; ++ xlnx,dcache-force-tag-lutram = <0x0>; ++ xlnx,dcache-line-len = <0x8>; ++ xlnx,dcache-use-writeback = <0x0>; ++ xlnx,dcache-victims = <0x0>; ++ xlnx,debug-counter-width = <0x20>; ++ xlnx,debug-enabled = <0x1>; ++ xlnx,debug-event-counters = <0x5>; ++ xlnx,debug-external-trace = <0x0>; ++ xlnx,debug-interface = <0x0>; ++ xlnx,debug-latency-counters = <0x1>; ++ xlnx,debug-profile-size = <0x0>; ++ xlnx,debug-trace-async-reset = <0x0>; ++ xlnx,debug-trace-size = <0x2000>; ++ xlnx,div-zero-exception = <0x1>; ++ xlnx,dp-axi-mon = <0x0>; ++ xlnx,dynamic-bus-sizing = <0x0>; ++ xlnx,ecc-use-ce-exception = <0x0>; ++ xlnx,edge-is-positive = <0x1>; ++ xlnx,enable-discrete-ports = <0x0>; ++ xlnx,endianness = <0x1>; ++ xlnx,fault-tolerant = <0x0>; ++ xlnx,fpu-exception = <0x0>; ++ xlnx,freq = <0xbebc200>; ++ xlnx,fsl-exception = <0x0>; ++ xlnx,fsl-links = <0x0>; ++ xlnx,i-axi = <0x0>; ++ xlnx,i-lmb = <0x1>; ++ xlnx,i-lmb-mon = <0x0>; ++ xlnx,iaddr-size = <0x20>; ++ xlnx,ic-axi-mon = <0x0>; ++ xlnx,icache-always-used = <0x1>; ++ xlnx,icache-data-width = <0x0>; ++ xlnx,icache-force-tag-lutram = <0x0>; ++ xlnx,icache-line-len = <0x4>; ++ xlnx,icache-streams = <0x1>; ++ xlnx,icache-victims = <0x8>; ++ xlnx,ill-opcode-exception = <0x1>; ++ xlnx,imprecise-exceptions = <0x0>; ++ xlnx,instr-size = <0x20>; ++ xlnx,interconnect = <0x2>; ++ xlnx,interrupt-is-edge = <0x0>; ++ xlnx,interrupt-mon = <0x0>; ++ xlnx,ip-axi-mon = <0x0>; ++ xlnx,lockstep-master = <0x0>; ++ xlnx,lockstep-select = <0x0>; ++ xlnx,lockstep-slave = <0x0>; ++ xlnx,mmu-dtlb-size = <0x4>; ++ xlnx,mmu-itlb-size = <0x2>; ++ xlnx,mmu-privileged-instr = <0x0>; ++ xlnx,mmu-tlb-access = <0x3>; ++ xlnx,mmu-zones = <0x2>; ++ xlnx,num-sync-ff-clk = <0x2>; ++ xlnx,num-sync-ff-clk-debug = <0x2>; ++ xlnx,num-sync-ff-clk-irq = <0x1>; ++ xlnx,num-sync-ff-dbg-clk = <0x1>; ++ xlnx,num-sync-ff-dbg-trace-clk = <0x2>; ++ xlnx,number-of-pc-brk = <0x1>; ++ xlnx,number-of-rd-addr-brk = <0x0>; ++ xlnx,number-of-wr-addr-brk = <0x0>; ++ xlnx,opcode-0x0-illegal = <0x1>; ++ xlnx,optimization = <0x0>; ++ xlnx,pc-width = <0x20>; ++ xlnx,piaddr-size = <0x20>; ++ xlnx,pvr = <0x2>; ++ xlnx,pvr-user1 = <0x0>; ++ xlnx,pvr-user2 = <0x0>; ++ xlnx,reset-msr = <0x0>; ++ xlnx,reset-msr-bip = <0x0>; ++ xlnx,reset-msr-dce = <0x0>; ++ xlnx,reset-msr-ee = <0x0>; ++ xlnx,reset-msr-eip = <0x0>; ++ xlnx,reset-msr-ice = <0x0>; ++ xlnx,reset-msr-ie = <0x0>; ++ xlnx,sco = <0x0>; ++ xlnx,trace = <0x0>; ++ xlnx,unaligned-exceptions = <0x1>; ++ xlnx,use-barrel = <0x1>; ++ xlnx,use-branch-target-cache = <0x0>; ++ xlnx,use-config-reset = <0x0>; ++ xlnx,use-dcache = <0x1>; ++ xlnx,use-div = <0x1>; ++ xlnx,use-ext-brk = <0x0>; ++ xlnx,use-ext-nm-brk = <0x0>; ++ xlnx,use-extended-fsl-instr = <0x0>; ++ xlnx,use-fpu = <0x0>; ++ xlnx,use-hw-mul = <0x2>; ++ xlnx,use-icache = <0x1>; ++ xlnx,use-interrupt = <0x2>; ++ xlnx,use-mmu = <0x3>; ++ xlnx,use-msr-instr = <0x1>; ++ xlnx,use-non-secure = <0x0>; ++ xlnx,use-pcmp-instr = <0x1>; ++ xlnx,use-reorder-instr = <0x1>; ++ xlnx,use-stack-protection = <0x0>; ++ }; ++ }; ++ ++ clocks { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ ++ clk_cpu@0 { ++ #clock-cells = <0x0>; ++ clock-frequency = <0xbebc200>; ++ clock-output-names = "clk_cpu"; ++ compatible = "fixed-clock"; ++ reg = <0x0>; ++ linux,phandle = <0x3>; ++ phandle = <0x3>; ++ }; ++ ++ clk_bus_0@1 { ++ #clock-cells = <0x0>; ++ clock-frequency = <0xbebc200>; ++ clock-output-names = "clk_bus_0"; ++ compatible = "fixed-clock"; ++ reg = <0x1>; ++ linux,phandle = <0x8>; ++ phandle = <0x8>; ++ }; ++ }; ++ ++ amba_pl { ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ compatible = "simple-bus"; ++ ranges; ++ linux,phandle = <0x2>; ++ phandle = <0x2>; ++ ++ ethernet@40c00000 { ++ axistream-connected = <0x5>; ++ axistream-control-connected = <0x5>; ++ clock-frequency = <0x5f5e100>; ++ compatible = "xlnx,axi-ethernet-1.00.a"; ++ device_type = "network"; ++ interrupt-names = "interrupt"; ++ interrupt-parent = <0x4>; ++ interrupts = <0x4 0x2>; ++ phy-mode = "gmii"; ++ reg = <0x40c00000 0x40000>; ++ xlnx = <0x0>; ++ xlnx,axiliteclkrate = <0x0>; ++ xlnx,axisclkrate = <0x0>; ++ xlnx,clockselection = <0x0>; ++ xlnx,enableasyncsgmii = <0x0>; ++ xlnx,gt-type = <0x0>; ++ xlnx,gtinex = <0x0>; ++ xlnx,gtlocation = <0x0>; ++ xlnx,gtrefclksrc = <0x0>; ++ xlnx,include-dre; ++ xlnx,instantiatebitslice0 = <0x0>; ++ xlnx,phy-type = <0x1>; ++ xlnx,phyaddr = <0x1>; ++ xlnx,rable = <0x0>; ++ xlnx,rxcsum = <0x0>; ++ xlnx,rxlane0-placement = <0x0>; ++ xlnx,rxlane1-placement = <0x0>; ++ xlnx,rxmem = <0x1000>; ++ xlnx,rxnibblebitslice0used = <0x0>; ++ xlnx,tx-in-upper-nibble = <0x1>; ++ xlnx,txcsum = <0x0>; ++ xlnx,txlane0-placement = <0x0>; ++ xlnx,txlane1-placement = <0x0>; ++ phy-handle = <0x6>; ++ local-mac-address = [00 0a 35 00 22 01]; ++ linux,phandle = <0x7>; ++ phandle = <0x7>; ++ ++ mdio { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ ++ phy@7 { ++ device_type = "ethernet-phy"; ++ reg = <0x7>; ++ linux,phandle = <0x6>; ++ phandle = <0x6>; ++ }; ++ }; ++ }; ++ ++ dma@41e00000 { ++ #dma-cells = <0x1>; ++ axistream-connected = <0x7>; ++ axistream-control-connected = <0x7>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_lite_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,eth-dma"; ++ interrupt-names = "mm2s_introut", "s2mm_introut"; ++ interrupt-parent = <0x4>; ++ interrupts = <0x3 0x2 0x2 0x2>; ++ reg = <0x41e00000 0x10000>; ++ xlnx,include-dre; ++ linux,phandle = <0x5>; ++ phandle = <0x5>; ++ }; ++ ++ timer@41c00000 { ++ clock-frequency = <0xbebc200>; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-timer-1.00.a"; ++ interrupt-names = "interrupt"; ++ interrupt-parent = <0x4>; ++ interrupts = <0x5 0x2>; ++ reg = <0x41c00000 0x10000>; ++ xlnx,count-width = <0x20>; ++ xlnx,gen0-assert = <0x1>; ++ xlnx,gen1-assert = <0x1>; ++ xlnx,one-timer-only = <0x0>; ++ xlnx,trig0-assert = <0x1>; ++ xlnx,trig1-assert = <0x1>; ++ }; ++ ++ gpio@40010000 { ++ #gpio-cells = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-gpio-1.00.a"; ++ gpio-controller; ++ reg = <0x40010000 0x10000>; ++ xlnx,all-inputs = <0x1>; ++ xlnx,all-inputs-2 = <0x0>; ++ xlnx,all-outputs = <0x0>; ++ xlnx,all-outputs-2 = <0x0>; ++ xlnx,dout-default = <0x0>; ++ xlnx,dout-default-2 = <0x0>; ++ xlnx,gpio-width = <0x1>; ++ xlnx,gpio2-width = <0x20>; ++ xlnx,interrupt-present = <0x0>; ++ xlnx,is-dual = <0x0>; ++ xlnx,tri-default = <0xffffffff>; ++ xlnx,tri-default-2 = <0xffffffff>; ++ }; ++ ++ gpio@40020000 { ++ #gpio-cells = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-gpio-1.00.a"; ++ gpio-controller; ++ reg = <0x40020000 0x10000>; ++ xlnx,all-inputs = <0x1>; ++ xlnx,all-inputs-2 = <0x0>; ++ xlnx,all-outputs = <0x0>; ++ xlnx,all-outputs-2 = <0x0>; ++ xlnx,dout-default = <0x0>; ++ xlnx,dout-default-2 = <0x0>; ++ xlnx,gpio-width = <0x4>; ++ xlnx,gpio2-width = <0x20>; ++ xlnx,interrupt-present = <0x0>; ++ xlnx,is-dual = <0x0>; ++ xlnx,tri-default = <0xffffffff>; ++ xlnx,tri-default-2 = <0xffffffff>; ++ }; ++ ++ i2c@40800000 { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ clock-frequency = <0xbebc200>; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-iic-2.00.a"; ++ interrupt-names = "iic2intc_irpt"; ++ interrupt-parent = <0x4>; ++ interrupts = <0x1 0x2>; ++ reg = <0x40800000 0x10000>; ++ ++ i2cswitch@74 { ++ compatible = "nxp,pca9548"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ reg = <0x74>; ++ ++ i2c@0 { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ reg = <0x0>; ++ ++ clock-generator@5d { ++ #clock-cells = <0x0>; ++ compatible = "silabs,si570"; ++ temperature-stability = <0x32>; ++ reg = <0x5d>; ++ factory-fout = <0x9502f90>; ++ clock-frequency = <0x8d9ee20>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ reg = <0x3>; ++ ++ eeprom@54 { ++ compatible = "at,24c08"; ++ reg = <0x54>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio@40030000 { ++ #gpio-cells = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-gpio-1.00.a"; ++ gpio-controller; ++ reg = <0x40030000 0x10000>; ++ xlnx,all-inputs = <0x0>; ++ xlnx,all-inputs-2 = <0x0>; ++ xlnx,all-outputs = <0x1>; ++ xlnx,all-outputs-2 = <0x0>; ++ xlnx,dout-default = <0x0>; ++ xlnx,dout-default-2 = <0x0>; ++ xlnx,gpio-width = <0x8>; ++ xlnx,gpio2-width = <0x20>; ++ xlnx,interrupt-present = <0x0>; ++ xlnx,is-dual = <0x0>; ++ xlnx,tri-default = <0xffffffff>; ++ xlnx,tri-default-2 = <0xffffffff>; ++ }; ++ ++ flash@60000000 { ++ bank-width = <0x2>; ++ compatible = "cfi-flash"; ++ reg = <0x60000000 0x8000000>; ++ xlnx,axi-clk-period-ps = <0x1388>; ++ xlnx,include-datawidth-matching-0 = <0x1>; ++ xlnx,include-datawidth-matching-1 = <0x1>; ++ xlnx,include-datawidth-matching-2 = <0x1>; ++ xlnx,include-datawidth-matching-3 = <0x1>; ++ xlnx,include-negedge-ioregs = <0x0>; ++ xlnx,lflash-period-ps = <0x1388>; ++ xlnx,linear-flash-sync-burst = <0x0>; ++ xlnx,max-mem-width = <0x10>; ++ xlnx,mem-a-lsb = <0x0>; ++ xlnx,mem-a-msb = <0x1f>; ++ xlnx,mem0-type = <0x2>; ++ xlnx,mem0-width = <0x10>; ++ xlnx,mem1-type = <0x0>; ++ xlnx,mem1-width = <0x10>; ++ xlnx,mem2-type = <0x0>; ++ xlnx,mem2-width = <0x10>; ++ xlnx,mem3-type = <0x0>; ++ xlnx,mem3-width = <0x10>; ++ xlnx,num-banks-mem = <0x1>; ++ xlnx,page-size = <0x10>; ++ xlnx,parity-type-mem-0 = <0x0>; ++ xlnx,parity-type-mem-1 = <0x0>; ++ xlnx,parity-type-mem-2 = <0x0>; ++ xlnx,parity-type-mem-3 = <0x0>; ++ xlnx,port-diff = <0x0>; ++ xlnx,s-axi-en-reg = <0x0>; ++ xlnx,s-axi-mem-addr-width = <0x20>; ++ xlnx,s-axi-mem-data-width = <0x20>; ++ xlnx,s-axi-mem-id-width = <0x1>; ++ xlnx,s-axi-reg-addr-width = <0x5>; ++ xlnx,s-axi-reg-data-width = <0x20>; ++ xlnx,synch-pipedelay-0 = <0x1>; ++ xlnx,synch-pipedelay-1 = <0x1>; ++ xlnx,synch-pipedelay-2 = <0x1>; ++ xlnx,synch-pipedelay-3 = <0x1>; ++ xlnx,tavdv-ps-mem-0 = <0x1fbd0>; ++ xlnx,tavdv-ps-mem-1 = <0x3a98>; ++ xlnx,tavdv-ps-mem-2 = <0x3a98>; ++ xlnx,tavdv-ps-mem-3 = <0x3a98>; ++ xlnx,tcedv-ps-mem-0 = <0x1fbd0>; ++ xlnx,tcedv-ps-mem-1 = <0x3a98>; ++ xlnx,tcedv-ps-mem-2 = <0x3a98>; ++ xlnx,tcedv-ps-mem-3 = <0x3a98>; ++ xlnx,thzce-ps-mem-0 = <0x88b8>; ++ xlnx,thzce-ps-mem-1 = <0x1b58>; ++ xlnx,thzce-ps-mem-2 = <0x1b58>; ++ xlnx,thzce-ps-mem-3 = <0x1b58>; ++ xlnx,thzoe-ps-mem-0 = <0x1b58>; ++ xlnx,thzoe-ps-mem-1 = <0x1b58>; ++ xlnx,thzoe-ps-mem-2 = <0x1b58>; ++ xlnx,thzoe-ps-mem-3 = <0x1b58>; ++ xlnx,tlzwe-ps-mem-0 = <0xc350>; ++ xlnx,tlzwe-ps-mem-1 = <0x0>; ++ xlnx,tlzwe-ps-mem-2 = <0x0>; ++ xlnx,tlzwe-ps-mem-3 = <0x0>; ++ xlnx,tpacc-ps-flash-0 = <0x61a8>; ++ xlnx,tpacc-ps-flash-1 = <0x61a8>; ++ xlnx,tpacc-ps-flash-2 = <0x61a8>; ++ xlnx,tpacc-ps-flash-3 = <0x61a8>; ++ xlnx,twc-ps-mem-0 = <0x11170>; ++ xlnx,twc-ps-mem-1 = <0x3a98>; ++ xlnx,twc-ps-mem-2 = <0x3a98>; ++ xlnx,twc-ps-mem-3 = <0x3a98>; ++ xlnx,twp-ps-mem-0 = <0x13880>; ++ xlnx,twp-ps-mem-1 = <0x2ee0>; ++ xlnx,twp-ps-mem-2 = <0x2ee0>; ++ xlnx,twp-ps-mem-3 = <0x2ee0>; ++ xlnx,twph-ps-mem-0 = <0x13880>; ++ xlnx,twph-ps-mem-1 = <0x2ee0>; ++ xlnx,twph-ps-mem-2 = <0x2ee0>; ++ xlnx,twph-ps-mem-3 = <0x2ee0>; ++ xlnx,use-startup = <0x0>; ++ xlnx,use-startup-int = <0x0>; ++ xlnx,wr-rec-time-mem-0 = <0x186a0>; ++ xlnx,wr-rec-time-mem-1 = <0x6978>; ++ xlnx,wr-rec-time-mem-2 = <0x6978>; ++ xlnx,wr-rec-time-mem-3 = <0x6978>; ++ #address-cells = <0x1>; ++ #size-cells = <0x1>; ++ ++ partition@0x00000000 { ++ label = "fpga"; ++ reg = <0x0 0xb00000>; ++ }; ++ ++ partition@0x00b00000 { ++ label = "boot"; ++ reg = <0xb00000 0x80000>; ++ }; ++ ++ partition@0x00b80000 { ++ label = "bootenv"; ++ reg = <0xb80000 0x20000>; ++ }; ++ ++ partition@0x00ba0000 { ++ label = "kernel"; ++ reg = <0xba0000 0xc00000>; ++ }; ++ ++ partition@0x017a0000 { ++ label = "spare"; ++ reg = <0x17a0000 0x0>; ++ }; ++ }; ++ ++ interrupt-controller@41200000 { ++ #interrupt-cells = <0x2>; ++ compatible = "xlnx,xps-intc-1.00.a"; ++ interrupt-controller; ++ reg = <0x41200000 0x10000>; ++ xlnx,kind-of-intr = <0x0>; ++ xlnx,num-intr-inputs = <0x6>; ++ linux,phandle = <0x4>; ++ phandle = <0x4>; ++ }; ++ ++ gpio@40040000 { ++ #gpio-cells = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-gpio-1.00.a"; ++ gpio-controller; ++ reg = <0x40040000 0x10000>; ++ xlnx,all-inputs = <0x1>; ++ xlnx,all-inputs-2 = <0x0>; ++ xlnx,all-outputs = <0x0>; ++ xlnx,all-outputs-2 = <0x0>; ++ xlnx,dout-default = <0x0>; ++ xlnx,dout-default-2 = <0x0>; ++ xlnx,gpio-width = <0x5>; ++ xlnx,gpio2-width = <0x20>; ++ xlnx,interrupt-present = <0x0>; ++ xlnx,is-dual = <0x0>; ++ xlnx,tri-default = <0xffffffff>; ++ xlnx,tri-default-2 = <0xffffffff>; ++ }; ++ ++ gpio@40000000 { ++ #gpio-cells = <0x2>; ++ clock-frequency = <0xbebc200>; ++ clock-names = "s_axi_aclk"; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-gpio-1.00.a"; ++ gpio-controller; ++ reg = <0x40000000 0x10000>; ++ xlnx,all-inputs = <0x0>; ++ xlnx,all-inputs-2 = <0x0>; ++ xlnx,all-outputs = <0x1>; ++ xlnx,all-outputs-2 = <0x0>; ++ xlnx,dout-default = <0x0>; ++ xlnx,dout-default-2 = <0x0>; ++ xlnx,gpio-width = <0x1>; ++ xlnx,gpio2-width = <0x20>; ++ xlnx,interrupt-present = <0x0>; ++ xlnx,is-dual = <0x0>; ++ xlnx,tri-default = <0xffffffff>; ++ xlnx,tri-default-2 = <0xffffffff>; ++ linux,phandle = <0x1>; ++ phandle = <0x1>; ++ }; ++ ++ serial@44a00000 { ++ clock-frequency = <0xbebc200>; ++ clocks = <0x8>; ++ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; ++ current-speed = <0x1c200>; ++ device_type = "serial"; ++ interrupt-names = "ip2intc_irpt"; ++ interrupt-parent = <0x4>; ++ interrupts = <0x0 0x2>; ++ port-number = <0x0>; ++ reg = <0x44a00000 0x10000>; ++ reg-offset = <0x1000>; ++ reg-shift = <0x2>; ++ xlnx,external-xin-clk-hz = <0x17d7840>; ++ xlnx,external-xin-clk-hz-d = <0x19>; ++ xlnx,has-external-rclk = <0x0>; ++ xlnx,has-external-xin = <0x0>; ++ xlnx,is-a-16550 = <0x1>; ++ xlnx,s-axi-aclk-freq-hz-d = "200.0"; ++ xlnx,use-modem-ports = <0x1>; ++ xlnx,use-user-ports = <0x1>; ++ }; ++ }; ++ + chosen { +- } ; +-} ; ++ bootargs = "console=ttyS0,115200 earlyprintk"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ ethernet0 = "/amba_pl/ethernet@40c00000"; ++ i2c0 = "/amba_pl/i2c@40800000"; ++ serial0 = "/amba_pl/serial@44a00000"; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x80000000 0x40000000>; ++ }; ++}; ++ +diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk +index 1dee2d6..cb75fde 100644 +--- a/board/xilinx/microblaze-generic/config.mk ++++ b/board/xilinx/microblaze-generic/config.mk +@@ -1,20 +1,10 @@ +-# +-# (C) Copyright 2007 - 2016 Michal Simek +-# +-# Michal SIMEK +-# +-# SPDX-License-Identifier: GPL-2.0+ +-# +- +-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER)) +- +-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support. +-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high +-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul +-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div +-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift +-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare +- +-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER)) +- +-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2) ++TEXT_BASE = 0x80400000 ++CONFIG_SYS_TEXT_BASE = 0x80400000 ++ ++PLATFORM_CPPFLAGS += -mxl-barrel-shift ++PLATFORM_CPPFLAGS += -mno-xl-soft-div ++PLATFORM_CPPFLAGS += -mxl-pattern-compare ++PLATFORM_CPPFLAGS += -mxl-multiply-high ++PLATFORM_CPPFLAGS += -mno-xl-soft-mul ++PLATFORM_CPPFLAGS += -mcpu=v10.0 ++PLATFORM_CPPFLAGS += -fgnu89-inline +diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig +index 08d99f2..bac6939 100644 +--- a/configs/microblaze-generic_defconfig ++++ b/configs/microblaze-generic_defconfig +@@ -1,5 +1,4 @@ + CONFIG_MICROBLAZE=y +-CONFIG_SYS_TEXT_BASE=0x29000000 + CONFIG_SPL_LIBCOMMON_SUPPORT=y + CONFIG_SPL_LIBGENERIC_SUPPORT=y + CONFIG_SPL_SERIAL_SUPPORT=y +@@ -8,50 +7,50 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 + CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 + CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 + CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1 ++CONFIG_SYS_TEXT_BASE=0x80400000 + CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-CONFIG_BOOTDELAY=-1 +-CONFIG_USE_BOOTARGS=y +-CONFIG_BOOTARGS="root=romfs" ++CONFIG_BOOTDELAY=4 + CONFIG_SYS_CONSOLE_IS_IN_ENV=y +-CONFIG_SPL=y +-CONFIG_SPL_BOARD_INIT=y +-CONFIG_SPL_SYS_MALLOC_SIMPLE=y + CONFIG_SPL_NOR_SUPPORT=y + CONFIG_SPL_OS_BOOT=y + CONFIG_SYS_OS_BASE=0x2c060000 + CONFIG_HUSH_PARSER=y +-CONFIG_SYS_PROMPT="U-Boot-mONStR> " +-CONFIG_CMD_IMLS=y +-CONFIG_CMD_SPL=y ++CONFIG_SYS_PROMPT="U-Boot> " + CONFIG_CMD_ASKENV=y +-CONFIG_CMD_GPIO=y + CONFIG_CMD_SAVES=y + # CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_TFTPPUT=y ++CONFIG_SYS_ENET=y ++CONFIG_NET=y ++CONFIG_NETDEVICES=y ++CONFIG_CMD_NET=y + CONFIG_CMD_DHCP=y ++CONFIG_CMD_NFS=y + CONFIG_CMD_MII=y + CONFIG_CMD_PING=y + CONFIG_CMD_JFFS2=y +-CONFIG_SPL_OF_CONTROL=y + CONFIG_OF_EMBED=y +-CONFIG_ENV_IS_IN_FLASH=y +-CONFIG_NETCONSOLE=y +-CONFIG_SPL_DM=y +-CONFIG_MTD_NOR_FLASH=y +-CONFIG_PHY_ATHEROS=y +-CONFIG_PHY_BROADCOM=y +-CONFIG_PHY_DAVICOM=y +-CONFIG_PHY_LXT=y +-CONFIG_PHY_MARVELL=y +-CONFIG_PHY_MICREL=y +-CONFIG_PHY_MICREL_KSZ90X1=y +-CONFIG_PHY_NATSEMI=y +-CONFIG_PHY_REALTEK=y +-CONFIG_PHY_VITESSE=y + CONFIG_DM_ETH=y ++CONFIG_SYS_MALLOC_F=y ++CONFIG_SYS_GENERIC_BOARD=y + CONFIG_XILINX_AXIEMAC=y +-CONFIG_XILINX_EMACLITE=y + CONFIG_SYS_NS16550=y +-CONFIG_XILINX_UARTLITE=y ++CONFIG_CMD_FLASH=y ++CONFIG_MTD_NOR_FLASH=y ++CONFIG_CMD_IMLS=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_TFTPPUT=y ++CONFIG_NETCONSOLE=y ++CONFIG_XILINX_FSL_LINKS=0 ++CONFIG_PHY_GIGE=y ++CONFIG_ENV_IS_IN_FLASH=y ++CONFIG_PHY_MICREL=y ++CONFIG_PHY_MICREL_KSZ90X1=y ++CONFIG_SPL_DM_SERIAL=y ++CONFIG_SPL_OF_LIBFDT=y ++CONFIG_PHY_XILINX=y ++# CONFIG_SPL is not set ++# CONFIG_CMD_EEPROM is not set ++# CONFIG_BOOTARGS is not set ++# CONFIG_USE_BOOTARGS is not set +diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h +index 16481cb..1377c5e 100644 +--- a/include/configs/microblaze-generic.h ++++ b/include/configs/microblaze-generic.h +@@ -1,254 +1,178 @@ +-/* +- * (C) Copyright 2007-2010 Michal Simek +- * +- * Michal SIMEK +- * +- * SPDX-License-Identifier: GPL-2.0+ +- */ +- + #ifndef __CONFIG_H + #define __CONFIG_H + +-#include "../board/xilinx/microblaze-generic/xparameters.h" +- +-/* MicroBlaze CPU */ +-#define MICROBLAZE_V5 1 +- +-/* linear and spi flash memory */ +-#ifdef XILINX_FLASH_START +-#define FLASH +-#undef SPIFLASH +-#undef RAMENV /* hold environment in flash */ +-#else +-#ifdef XILINX_SPI_FLASH_BASEADDR +-#undef FLASH +-#define SPIFLASH +-#undef RAMENV /* hold environment in flash */ +-#else +-#undef FLASH +-#undef SPIFLASH +-#define RAMENV /* hold environment in RAM */ +-#endif +-#endif +- +-/* uart */ +-/* The following table includes the supported baudrates */ +-# define CONFIG_SYS_BAUDRATE_TABLE \ +- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +- +-/* setting reset address */ +-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ +- +-/* gpio */ +-#ifdef XILINX_GPIO_BASEADDR +-# define CONFIG_XILINX_GPIO +-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR +-#endif +- +-/* watchdog */ +-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) +-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR +-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ +-# ifndef CONFIG_SPL_BUILD +-# define CONFIG_HW_WATCHDOG +-# define CONFIG_XILINX_TB_WATCHDOG +-# endif +-#endif +- +-#define CONFIG_SYS_MALLOC_LEN 0xC0000 +- +-/* Stack location before relocation */ +-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ +- CONFIG_SYS_MALLOC_F_LEN) +- +-/* +- * CFI flash memory layout - Example +- * CONFIG_SYS_FLASH_BASE = 0x2200_0000; +- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB +- * +- * SECT_SIZE = 0x20000; 128kB is one sector +- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store +- * +- * 0x2200_0000 CONFIG_SYS_FLASH_BASE +- * FREE 256kB +- * 0x2204_0000 CONFIG_ENV_ADDR +- * ENV_AREA 128kB +- * 0x2206_0000 +- * FREE +- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE +- * +- */ +- +-#ifdef FLASH +-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START +-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE +-# define CONFIG_SYS_FLASH_CFI 1 +-# define CONFIG_FLASH_CFI_DRIVER 1 +-/* ?empty sector */ +-# define CONFIG_SYS_FLASH_EMPTY_INFO 1 +-/* max number of memory banks */ +-# define CONFIG_SYS_MAX_FLASH_BANKS 1 +-/* max number of sectors on one chip */ +-# define CONFIG_SYS_MAX_FLASH_SECT 512 +-/* hardware flash protection */ +-# define CONFIG_SYS_FLASH_PROTECTION +-/* use buffered writes (20x faster) */ +-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +-# ifdef RAMENV +-# define CONFIG_ENV_SIZE 0x1000 +-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +- +-# else /* FLASH && !RAMENV */ +-/* 128K(one sector) for env */ +-# define CONFIG_ENV_SECT_SIZE 0x20000 +-# define CONFIG_ENV_ADDR \ +- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) +-# define CONFIG_ENV_SIZE 0x20000 +-# endif /* FLASH && !RAMBOOT */ +-#else /* !FLASH */ +- +-#ifdef SPIFLASH +-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR +-# define CONFIG_SPI 1 +-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ +-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS +- +-# ifdef RAMENV +-# define CONFIG_ENV_SIZE 0x1000 +-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +- +-# else /* SPIFLASH && !RAMENV */ +-# define CONFIG_ENV_SPI_MODE SPI_MODE_3 +-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +-/* 128K(two sectors) for env */ +-# define CONFIG_ENV_SECT_SIZE 0x10000 +-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) +-/* Warning: adjust the offset in respect of other flash content and size */ +-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ +-# endif /* SPIFLASH && !RAMBOOT */ +-#else /* !SPIFLASH */ +- +-/* ENV in RAM */ +-# define CONFIG_ENV_SIZE 0x1000 +-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +-#endif /* !SPIFLASH */ +-#endif /* !FLASH */ +- +-#if defined(XILINX_USE_ICACHE) +-# define CONFIG_ICACHE +-#else +-# undef CONFIG_ICACHE +-#endif +- +-#if defined(XILINX_USE_DCACHE) +-# define CONFIG_DCACHE +-#else +-# undef CONFIG_DCACHE +-#endif +- +-#ifndef XILINX_DCACHE_BYTE_SIZE +-#define XILINX_DCACHE_BYTE_SIZE 32768 +-#endif +- +-/* +- * BOOTP options +- */ ++#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } ++ ++/* processor - microblaze_0 */ ++#define XILINX_USE_MSR_INSTR 1 ++#define XILINX_USE_ICACHE 1 ++#define XILINX_USE_DCACHE 1 ++#define XILINX_DCACHE_BYTE_SIZE 16384 ++#define XILINX_PVR 2 ++#define MICROBLAZE_V5 ++#define CONFIG_CMD_IRQ ++#define CONFIG_DCACHE ++#define CONFIG_ICACHE ++ ++/* main_memory - ddr3_sdram */ ++ ++ ++/* uart - rs232_uart */ ++#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) ++#define CONFIG_SYS_NS16550_REG_SIZE -4 ++#define CONSOLE_ARG "console=console=ttyS0,115200\0" ++#define CONFIG_SYS_NS16550_SERIAL ++#define CONFIG_CONS_INDEX 1 ++#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0" ++#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" ++#define CONFIG_SYS_NS16550_CLK 200000000 ++#define CONFIG_BAUDRATE 115200 ++ ++/* ethernet - axi_ethernet */ ++#define CONFIG_PHY_XILINX ++#define CONFIG_MII ++#define CONFIG_PHY_MARVELL ++#define CONFIG_PHY_NATSEMI ++#define CONFIG_NET_MULTI ++#define CONFIG_PHY_REALTEK ++#define CONFIG_NETCONSOLE 1 ++#define CONFIG_SERVERIP 172.25.229.115 ++#define CONFIG_IPADDR ++ ++/* nor_flash - linear_flash */ ++#define CONFIG_SYS_FLASH_BASE 0x60000000 ++#define CONFIG_FLASH_END 0x68000000 ++#define CONFIG_SYS_MAX_FLASH_SECT 2048 ++#define CONFIG_SYS_FLASH_PROTECTION ++#define CONFIG_SYS_FLASH_EMPTY_INFO ++#define CONFIG_SYS_FLASH_CFI ++#define CONFIG_FLASH_CFI_DRIVER ++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++ ++/* timer - axi_timer_0 */ ++ ++/* gpio - reset_gpio */ ++#define XILINX_GPIO_BASEADDR 0x40000000 ++#define CONFIG_SYS_GPIO_0_ADDR 0x40000000 ++#define CONFIG_XILINX_GPIO ++ ++/* intc - microblaze_0_axi_intc */ ++ ++/* FPGA */ ++ ++/* Memory testing handling */ ++#define CONFIG_SYS_MEMTEST_START 0x80000000 ++#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000) ++#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */ ++ ++/* global pointer options */ ++#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE) ++ ++/* Size of malloc() pool */ ++#define SIZE 0x100000 ++#define CONFIG_SYS_MALLOC_LEN SIZE ++#define CONFIG_SYS_MONITOR_LEN SIZE ++#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE) ++#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) ++ ++/* stack */ ++#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN) ++ ++/* No of_control support yet*/ ++ ++/* BOOTP options */ ++#define CONFIG_BOOTP_SERVERIP + #define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_BOOTP_BOOTPATH + #define CONFIG_BOOTP_GATEWAY + #define CONFIG_BOOTP_HOSTNAME ++#define CONFIG_BOOTP_MAY_FAIL ++#define CONFIG_BOOTP_DNS ++#define CONFIG_BOOTP_SUBNETMASK ++#define CONFIG_BOOTP_PXE + +-#if defined(CONFIG_CMD_JFFS2) +-# define CONFIG_MTD_PARTITIONS +-#endif +- +-#if defined(CONFIG_CMD_UBI) +-# define CONFIG_MTD_PARTITIONS +-#endif +- +-#if defined(CONFIG_MTD_PARTITIONS) +-/* MTD partitions */ +-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +-#define CONFIG_FLASH_CFI_MTD +- +-/* default mtd partition table */ +-#endif +- +-/* size of console buffer */ +-#define CONFIG_SYS_CBSIZE 512 +-/* max number of command args */ +-#define CONFIG_SYS_MAXARGS 15 +-#define CONFIG_SYS_LONGHELP +-/* default load address */ +-#define CONFIG_SYS_LOAD_ADDR 0 +- +-#define CONFIG_HOSTNAME XILINX_BOARD_NAME +-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +- +-/* architecture dependent code */ +-#define CONFIG_SYS_USR_EXCEP /* user exception */ +- +-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" +- +-#ifndef CONFIG_EXTRA_ENV_SETTINGS +-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ +- "nor0=flash-0\0"\ +- "mtdparts=mtdparts=flash-0:"\ +- "256k(u-boot),256k(env),3m(kernel),"\ +- "1m(romfs),1m(cramfs),-(jffs2)\0"\ +- "nc=setenv stdout nc;"\ +- "setenv stdin nc\0" \ +- "serial=setenv stdout serial;"\ +- "setenv stdin serial\0" +-#endif +- ++/*Command line configuration.*/ + #define CONFIG_CMDLINE_EDITING ++#define CONFIG_AUTO_COMPLETE + +-/* Enable flat device tree support */ +-#define CONFIG_LMB 1 +- +-#if defined(CONFIG_XILINX_AXIEMAC) +-# define CONFIG_MII 1 +-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +-#else +-# undef CONFIG_MII +-#endif +- +-/* SPL part */ +-#define CONFIG_SPL_FRAMEWORK ++/* Miscellaneous configurable options */ ++#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */ ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +-#ifdef CONFIG_SYS_FLASH_BASE +-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +-#endif +- +-/* for booting directly linux */ + +-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ +- 0x40000) +-#define CONFIG_SYS_FDT_SIZE (16<<10) +-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ +- 0x1000000) ++/* Use the HUSH parser */ ++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +-/* SP location before relocation, must use scratch RAM */ +-/* BRAM start */ +-#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +-/* BRAM size - will be generated */ +-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 ++#define CONFIG_ENV_VARS_UBOOT_CONFIG ++#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ + +-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +- CONFIG_SYS_INIT_RAM_SIZE - \ +- CONFIG_SYS_MALLOC_F_LEN) ++#define CONFIG_LMB + +-/* Just for sure that there is a space for stack */ +-#define CONFIG_SPL_STACK_SIZE 0x100 ++/* FDT support */ ++#define CONFIG_DISPLAY_BOARDINFO_LATE + +-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ +- CONFIG_SYS_INIT_RAM_ADDR - \ +- CONFIG_SYS_MALLOC_F_LEN - \ +- CONFIG_SPL_STACK_SIZE) ++/* architecture dependent code */ ++#define CONFIG_SYS_USR_EXCEP /* user exception */ ++#define CONFIG_SYS_HZ 1000 ++ ++/* Boot Argument Buffer Size */ ++#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ ++#define CONFIG_SYS_LONGHELP ++/* Initial memory map for Linux */ ++#define CONFIG_SYS_BOOTMAPSZ 0x8000000 ++ ++/* Environment settings*/ ++#define CONFIG_ENV_ADDR 0x60b80000 ++#define CONFIG_ENV_SIZE 0x20000 ++#define CONFIG_ENV_SECT_SIZE 0x20000 ++/* PREBOOT */ ++#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp" ++ ++/* Extra U-Boot Env settings */ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ SERIAL_MULTI \ ++ CONSOLE_ARG \ ++ ESERIAL0 \ ++ "nc=setenv stdout nc;setenv stdin nc;\0" \ ++ "ethaddr=00:0a:35:00:22:01\0" \ ++ "autoload=no\0" \ ++ "sdbootdev=0\0" \ ++ "clobstart=0x81000000\0" \ ++ "netstart=0x81000000\0" \ ++ "dtbnetstart=0x82800000\0" \ ++ "loadaddr=0x81000000\0" \ ++ "bootsize=0x80000\0" \ ++ "bootstart=0x60b00000\0" \ ++ "boot_img=u-boot-s.bin\0" \ ++ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \ ++ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \ ++ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \ ++ "bootenvsize=0x20000\0" \ ++ "bootenvstart=0x60b80000\0" \ ++ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \ ++ "kernelsize=0xc00000\0" \ ++ "kernelstart=0x60ba0000\0" \ ++ "kernel_img=image.ub\0" \ ++ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ ++ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \ ++ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \ ++ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \ ++ "fpgasize=0xb00000\0" \ ++ "fpgastart=0x60000000\0" \ ++ "fpga_img=system.bit.bin\0" \ ++ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \ ++ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \ ++ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \ ++ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ ++ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ ++ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ ++ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ ++ "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ ++"" ++/* BOOTCOMMAND */ ++#define CONFIG_BOOTCOMMAND "run default_bootcmd" + +-#endif /* __CONFIG_H */ ++#endif +-- +2.7.4 + diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb deleted file mode 100644 index fb2c618c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb +++ /dev/null @@ -1,27 +0,0 @@ -UBOOT_VERSION = "v2018.01" -XILINX_RELEASE_VERSION = "v2018.1" - -UBRANCH ?= "master" - -SRCREV ?= "949e5cb9a736bac32ea8886e3953da55bdd30754" - -include u-boot-xlnx.inc -include u-boot-spl-zynq-init.inc - -SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch" - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" - -# u-boot-xlnx has support for these -HAS_PLATFORM_INIT ?= " \ - zynq_microzed_config \ - zynq_zed_config \ - zynq_zc702_config \ - zynq_zc706_config \ - zynq_zybo_config \ - xilinx_zynqmp_zcu102_rev1_0_config \ - xilinx_zynqmp_zcu106_revA_config \ - xilinx_zynqmp_zcu104_revC_config \ - " - diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.3.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.3.bb new file mode 100644 index 00000000..c9442fa6 --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.3.bb @@ -0,0 +1,27 @@ +UBOOT_VERSION = "v2018.01" +XILINX_RELEASE_VERSION = "v2018.3" + +UBRANCH ?= "master" + +SRCREV ?= "d8fc4b3b70bccf1577dab69f6ddfd4ada9a93bac" + +include u-boot-xlnx.inc +include u-boot-spl-zynq-init.inc + +SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch" + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" + +# u-boot-xlnx has support for these +HAS_PLATFORM_INIT ?= " \ + zynq_microzed_config \ + zynq_zed_config \ + zynq_zc702_config \ + zynq_zc706_config \ + zynq_zybo_config \ + xilinx_zynqmp_zcu102_rev1_0_config \ + xilinx_zynqmp_zcu106_revA_config \ + xilinx_zynqmp_zcu104_revC_config \ + " + diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch b/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch deleted file mode 100644 index 62e8d380..00000000 --- a/meta-xilinx-bsp/recipes-devtools/qemu/files/memfd.patch +++ /dev/null @@ -1,57 +0,0 @@ -Upstream-Status: Backport -Signed-off-by: Ross Burton - -From 75e5b70e6b5dcc4f2219992d7cffa462aa406af0 Mon Sep 17 00:00:00 2001 -From: Paolo Bonzini -Date: Tue, 28 Nov 2017 11:51:27 +0100 -Subject: [PATCH] memfd: fix configure test -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Recent glibc added memfd_create in sys/mman.h. This conflicts with -the definition in util/memfd.c: - - /builddir/build/BUILD/qemu-2.11.0-rc1/util/memfd.c:40:12: error: static declaration of memfd_create follows non-static declaration - -Fix the configure test, and remove the sys/memfd.h inclusion since the -file actually does not exist---it is a typo in the memfd_create(2) man -page. - -Cc: Marc-André Lureau -Signed-off-by: Paolo Bonzini ---- - configure | 2 +- - util/memfd.c | 4 +--- - 2 files changed, 2 insertions(+), 4 deletions(-) - -diff --git a/configure b/configure -index 9c8aa5a98b..99ccc1725a 100755 ---- a/configure -+++ b/configure -@@ -3923,7 +3923,7 @@ fi - # check if memfd is supported - memfd=no - cat > $TMPC << EOF --#include -+#include - - int main(void) - { -diff --git a/util/memfd.c b/util/memfd.c -index 4571d1aba8..412e94a405 100644 ---- a/util/memfd.c -+++ b/util/memfd.c -@@ -31,9 +31,7 @@ - - #include "qemu/memfd.h" - --#ifdef CONFIG_MEMFD --#include --#elif defined CONFIG_LINUX -+#if defined CONFIG_LINUX && !defined CONFIG_MEMFD - #include - #include - --- -2.11.0 diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb deleted file mode 100644 index a73b9e57..00000000 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.1.bb +++ /dev/null @@ -1,6 +0,0 @@ -require qemu-devicetrees.inc - -XILINX_RELEASE_VERSION = "v2018.1" - -BRANCH ?= "master" -SRCREV ?= "d5017f8119b6493d8b2fcdfd5caa4e8b16580877" diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.3.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.3.bb new file mode 100644 index 00000000..6f8eda2f --- /dev/null +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2018.3.bb @@ -0,0 +1,6 @@ +require qemu-devicetrees.inc + +XILINX_RELEASE_VERSION = "v2018.3" + +BRANCH ?= "master" +SRCREV ?= "e3e40b8829894a479c7d7380fc8137886645dda8" diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc index b6c5dee5..daff5ffc 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc @@ -17,9 +17,7 @@ BRANCH ?= "" REPO ?= "git://github.com/Xilinx/qemu.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG} \ - file://memfd.patch \ - " +SRC_URI = "${REPO};${BRANCHARG}" S = "${WORKDIR}/git" diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb deleted file mode 100644 index 1d6697cd..00000000 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.1.bb +++ /dev/null @@ -1,6 +0,0 @@ -require qemu-xilinx.inc - -XILINX_RELEASE_VERSION = "v2018.1" -XILINX_QEMU_VERSION ?= "v2.11.0" -BRANCH ?= "master" -SRCREV ?= "1d5516986ea296d91a599ac23252e302a4003914" diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.3.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.3.bb new file mode 100644 index 00000000..57547dff --- /dev/null +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2018.3.bb @@ -0,0 +1,6 @@ +require qemu-xilinx.inc + +XILINX_RELEASE_VERSION = "v2018.3" +XILINX_QEMU_VERSION ?= "v2.11.0" +BRANCH ?= "master" +SRCREV ?= "f70bd86859c7a1a075ac864b4765168f821f1aae" diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb deleted file mode 100644 index c3a8f764..00000000 --- a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.1.bb +++ /dev/null @@ -1,7 +0,0 @@ -LINUX_VERSION = "4.14" -XILINX_RELEASE_VERSION = "v2018.1" -KBRANCH ?= "xlnx_rebase_v4.14" -SRCREV ?= "4ac76ffacb54712b0361e51d0b7156e53d062e3c" - -include linux-xlnx.inc - diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.3.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.3.bb new file mode 100644 index 00000000..ade13e32 --- /dev/null +++ b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2018.3.bb @@ -0,0 +1,7 @@ +LINUX_VERSION = "4.14" +XILINX_RELEASE_VERSION = "v2018.3" +KBRANCH ?= "xlnx_rebase_v4.14" +SRCREV ?= "eeab73d1207d6fc2082776c954eb19fd7290bfbe" + +include linux-xlnx.inc + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch deleted file mode 100644 index b8ba70ea..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch +++ /dev/null @@ -1,302 +0,0 @@ -From c1bf9e8c50baa237b514715dcb9c8fd367694c93 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:14:13 +1000 -Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards - -Add the dglnt_encoder driver that enables DRM support for the VGA and -HDMI output ports found on many Digilent boards. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ - drivers/gpu/drm/xilinx/Kconfig | 6 + - drivers/gpu/drm/xilinx/Makefile | 1 + - drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ - 4 files changed, 247 insertions(+) - create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt - create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c - -diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -new file mode 100644 -index 0000000000..242b24e482 ---- /dev/null -+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -@@ -0,0 +1,23 @@ -+Device-Tree bindings for Digilent DRM Encoder Slave -+ -+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. -+The VGA or HDMI port must be connected to a Xilinx display pipeline via an -+axi2vid IP core. -+ -+Required properties: -+ - compatible: Should be "digilent,drm-encoder". -+ -+Optional properties: -+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video -+ connector. This is used to obtain the supported resolutions -+ of an attached monitor. If not defined, then a default -+ set of resolutions is used and the display will initialize -+ to 720p. Note most VGA connectors on Digilent boards do -+ not have the DDC bus routed out. -+ -+Example: -+ -+ encoder_0: digilent_encoder { -+ compatible = "digilent,drm-encoder"; -+ dglnt,edid-i2c = <&i2c1>; -+ }; -diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig -index 12b548c2a9..c3e2562e53 100644 ---- a/drivers/gpu/drm/xilinx/Kconfig -+++ b/drivers/gpu/drm/xilinx/Kconfig -@@ -57,3 +57,9 @@ config DRM_XILINX_SDI - depends on DRM_XILINX - help - DRM driver for Xilinx Display Port Subsystem. -+ -+config DRM_DIGILENT_ENCODER -+ tristate "Digilent VGA/HDMI DRM Encoder Driver" -+ depends on DRM_XILINX -+ help -+ DRM slave encoder for Video-out on Digilent boards. -diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile -index 19bc1541ca..c2717e40ea 100644 ---- a/drivers/gpu/drm/xilinx/Makefile -+++ b/drivers/gpu/drm/xilinx/Makefile -@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ - xilinx_drm_plane.o - xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o - -+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o - obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o - obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o - obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o -diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c -new file mode 100644 -index 0000000000..26a23986f9 ---- /dev/null -+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c -@@ -0,0 +1,217 @@ -+/* -+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. -+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DGLNT_ENC_MAX_FREQ 150000 -+#define DGLNT_ENC_MAX_H 1920 -+#define DGLNT_ENC_MAX_V 1080 -+#define DGLNT_ENC_PREF_H 1280 -+#define DGLNT_ENC_PREF_V 720 -+ -+struct dglnt_encoder { -+ struct drm_encoder *encoder; -+ struct i2c_adapter *i2c_bus; -+ bool i2c_present; -+}; -+ -+static inline struct dglnt_encoder *to_dglnt_encoder( -+ struct drm_encoder *encoder) -+{ -+ return to_encoder_slave(encoder)->slave_priv; -+} -+ -+static bool dglnt_mode_fixup(struct drm_encoder *encoder, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+ return true; -+} -+ -+static void dglnt_encoder_mode_set(struct drm_encoder *encoder, -+ struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+} -+ -+static void -+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) -+{ -+} -+ -+static void dglnt_encoder_save(struct drm_encoder *encoder) -+{ -+} -+ -+static void dglnt_encoder_restore(struct drm_encoder *encoder) -+{ -+} -+ -+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, -+ struct drm_display_mode *mode) -+{ -+ if (mode && -+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | -+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && -+ (mode->clock <= DGLNT_ENC_MAX_FREQ) && -+ (mode->hdisplay <= DGLNT_ENC_MAX_H) && -+ (mode->vdisplay <= DGLNT_ENC_MAX_V)) -+ return MODE_OK; -+ return MODE_BAD; -+} -+ -+static int dglnt_encoder_get_modes(struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ struct edid *edid; -+ int num_modes = 0; -+ -+ if (dglnt->i2c_present) { -+ edid = drm_get_edid(connector, dglnt->i2c_bus); -+ drm_mode_connector_update_edid_property(connector, edid); -+ if (edid) { -+ num_modes = drm_add_edid_modes(connector, edid); -+ kfree(edid); -+ } -+ } else { -+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, -+ DGLNT_ENC_MAX_V); -+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, -+ DGLNT_ENC_PREF_V); -+ } -+ return num_modes; -+} -+ -+static enum drm_connector_status dglnt_encoder_detect( -+ struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ -+ if (dglnt->i2c_present) { -+ if (drm_probe_ddc(dglnt->i2c_bus)) -+ return connector_status_connected; -+ return connector_status_disconnected; -+ } else -+ return connector_status_unknown; -+} -+ -+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { -+ .dpms = dglnt_encoder_dpms, -+ .save = dglnt_encoder_save, -+ .restore = dglnt_encoder_restore, -+ .mode_fixup = dglnt_mode_fixup, -+ .mode_valid = dglnt_encoder_mode_valid, -+ .mode_set = dglnt_encoder_mode_set, -+ .detect = dglnt_encoder_detect, -+ .get_modes = dglnt_encoder_get_modes, -+}; -+ -+static int dglnt_encoder_encoder_init(struct platform_device *pdev, -+ struct drm_device *dev, -+ struct drm_encoder_slave *encoder) -+{ -+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); -+ struct device_node *sub_node; -+ -+ encoder->slave_priv = dglnt; -+ encoder->slave_funcs = &dglnt_encoder_slave_funcs; -+ -+ dglnt->encoder = &encoder->base; -+ -+ /* get i2c adapter for edid */ -+ dglnt->i2c_present = false; -+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); -+ if (sub_node) { -+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); -+ if (!dglnt->i2c_bus) -+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); -+ else -+ dglnt->i2c_present = true; -+ of_node_put(sub_node); -+ } -+ -+ return 0; -+} -+ -+static int dglnt_encoder_probe(struct platform_device *pdev) -+{ -+ struct dglnt_encoder *dglnt; -+ -+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); -+ if (!dglnt) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, dglnt); -+ -+ return 0; -+} -+ -+static int dglnt_encoder_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+static const struct of_device_id dglnt_encoder_of_match[] = { -+ { .compatible = "digilent,drm-encoder", }, -+ { /* end of table */ }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); -+ -+static struct drm_platform_encoder_driver dglnt_encoder_driver = { -+ .platform_driver = { -+ .probe = dglnt_encoder_probe, -+ .remove = dglnt_encoder_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "dglnt-drm-enc", -+ .of_match_table = dglnt_encoder_of_match, -+ }, -+ }, -+ -+ .encoder_init = dglnt_encoder_encoder_init, -+}; -+ -+static int __init dglnt_encoder_init(void) -+{ -+ return platform_driver_register(&dglnt_encoder_driver.platform_driver); -+} -+ -+static void __exit dglnt_encoder_exit(void) -+{ -+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); -+} -+ -+module_init(dglnt_encoder_init); -+module_exit(dglnt_encoder_exit); -+ -+MODULE_AUTHOR("Digilent, Inc."); -+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); -+MODULE_LICENSE("GPL v2"); --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch deleted file mode 100644 index 9b6229db..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch +++ /dev/null @@ -1,607 +0,0 @@ -From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:16:06 +1000 -Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core - -Add support for the axi_dynclk IP Core available from Digilent. This IP -core dynamically configures the clock resources inside a Xilinx FPGA to -generate a clock with a software programmable frequency. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - drivers/clk/Kconfig | 8 + - drivers/clk/Makefile | 1 + - drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 556 insertions(+) - create mode 100644 drivers/clk/clk-dglnt-dynclk.c - -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index dccb111100..7fe65a702b 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -148,6 +148,14 @@ config CLK_QORIQ - This adds the clock driver support for Freescale QorIQ platforms - using common clock framework. - -+config COMMON_CLK_DGLNT_DYNCLK -+ tristate "Digilent axi_dynclk Driver" -+ depends on ARCH_ZYNQ || MICROBLAZE -+ help -+ ---help--- -+ Support for the Digilent AXI Dynamic Clock core for Xilinx -+ FPGAs. -+ - config COMMON_CLK_XGENE - bool "Clock driver for APM XGene SoC" - default y -diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index 0760449dde..45ce97d053 100644 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o - obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o - obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o - obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o -+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o - obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o - obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o - obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o -diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c -new file mode 100644 -index 0000000000..496ad5fc90 ---- /dev/null -+++ b/drivers/clk/clk-dglnt-dynclk.c -@@ -0,0 +1,547 @@ -+/* -+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLK_BIT_WEDGE 13 -+#define CLK_BIT_NOCOUNT 12 -+ -+/* This value is used to signal an error */ -+#define ERR_CLKCOUNTCALC 0xFFFFFFFF -+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) -+ -+#define DYNCLK_DIV_1_REGMASK 0x1041 -+/* 25 MHz (125 KHz / 5) */ -+#define DYNCLK_DEFAULT_FREQ 125000 -+ -+#define MMCM_FREQ_VCOMIN 600000 -+#define MMCM_FREQ_VCOMAX 1200000 -+#define MMCM_FREQ_PFDMIN 10000 -+#define MMCM_FREQ_PFDMAX 450000 -+#define MMCM_FREQ_OUTMIN 4000 -+#define MMCM_FREQ_OUTMAX 800000 -+#define MMCM_DIV_MAX 106 -+#define MMCM_FB_MIN 2 -+#define MMCM_FB_MAX 64 -+#define MMCM_CLKDIV_MAX 128 -+#define MMCM_CLKDIV_MIN 1 -+ -+#define OFST_DISPLAY_CTRL 0x0 -+#define OFST_DISPLAY_STATUS 0x4 -+#define OFST_DISPLAY_CLK_L 0x8 -+#define OFST_DISPLAY_FB_L 0x0C -+#define OFST_DISPLAY_FB_H_CLK_H 0x10 -+#define OFST_DISPLAY_DIV 0x14 -+#define OFST_DISPLAY_LOCK_L 0x18 -+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C -+ -+static const u64 lock_lookup[64] = { -+ 0b0011000110111110100011111010010000000001, -+ 0b0011000110111110100011111010010000000001, -+ 0b0100001000111110100011111010010000000001, -+ 0b0101101011111110100011111010010000000001, -+ 0b0111001110111110100011111010010000000001, -+ 0b1000110001111110100011111010010000000001, -+ 0b1001110011111110100011111010010000000001, -+ 0b1011010110111110100011111010010000000001, -+ 0b1100111001111110100011111010010000000001, -+ 0b1110011100111110100011111010010000000001, -+ 0b1111111111111000010011111010010000000001, -+ 0b1111111111110011100111111010010000000001, -+ 0b1111111111101110111011111010010000000001, -+ 0b1111111111101011110011111010010000000001, -+ 0b1111111111101000101011111010010000000001, -+ 0b1111111111100111000111111010010000000001, -+ 0b1111111111100011111111111010010000000001, -+ 0b1111111111100010011011111010010000000001, -+ 0b1111111111100000110111111010010000000001, -+ 0b1111111111011111010011111010010000000001, -+ 0b1111111111011101101111111010010000000001, -+ 0b1111111111011100001011111010010000000001, -+ 0b1111111111011010100111111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111010111011111111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001 -+}; -+ -+static const u32 filter_lookup_low[64] = { -+ 0b0001011111, -+ 0b0001010111, -+ 0b0001111011, -+ 0b0001011011, -+ 0b0001101011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0010110011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011 -+}; -+ -+struct dglnt_dynclk_reg; -+struct dglnt_dynclk_mode; -+struct dglnt_dynclk; -+ -+struct dglnt_dynclk_reg { -+ u32 clk0L; -+ u32 clkFBL; -+ u32 clkFBH_clk0H; -+ u32 divclk; -+ u32 lockL; -+ u32 fltr_lockH; -+}; -+ -+struct dglnt_dynclk_mode { -+ u32 freq; -+ u32 fbmult; -+ u32 clkdiv; -+ u32 maindiv; -+}; -+ -+struct dglnt_dynclk { -+ void __iomem *base; -+ struct clk_hw clk_hw; -+ unsigned long freq; -+}; -+ -+u32 dglnt_dynclk_divider(u32 divide) -+{ -+ u32 output = 0; -+ u32 highTime = 0; -+ u32 lowTime = 0; -+ -+ if ((divide < 1) || (divide > 128)) -+ return ERR_CLKDIVIDER; -+ -+ if (divide == 1) -+ return DYNCLK_DIV_1_REGMASK; -+ -+ highTime = divide / 2; -+ /* if divide is odd */ -+ if (divide & 0x1) { -+ lowTime = highTime + 1; -+ output = 1 << CLK_BIT_WEDGE; -+ } else { -+ lowTime = highTime; -+ } -+ -+ output |= 0x03F & lowTime; -+ output |= 0xFC0 & (highTime << 6); -+ return output; -+} -+ -+u32 dglnt_dynclk_count_calc(u32 divide) -+{ -+ u32 output = 0; -+ u32 divCalc = 0; -+ -+ divCalc = dglnt_dynclk_divider(divide); -+ if (divCalc == ERR_CLKDIVIDER) -+ output = ERR_CLKCOUNTCALC; -+ else -+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); -+ return output; -+} -+ -+ -+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, -+ struct dglnt_dynclk_mode *clkParams) -+{ -+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) -+ return -EINVAL; -+ -+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); -+ if (regValues->clk0L == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); -+ if (regValues->clkFBL == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBH_clk0H = 0; -+ -+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); -+ if (regValues->divclk == ERR_CLKDIVIDER) -+ return -EINVAL; -+ -+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & -+ 0xFFFFFFFF); -+ -+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> -+ 32) & 0x000000FF); -+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << -+ 16) & 0x03FF0000); -+ -+ return 0; -+} -+ -+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, -+ void __iomem *baseaddr) -+{ -+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); -+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); -+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); -+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); -+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); -+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); -+} -+ -+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, -+ struct dglnt_dynclk_mode *bestPick) -+{ -+ u32 bestError = MMCM_FREQ_OUTMAX; -+ u32 curError; -+ u32 curClkMult; -+ u32 curFreq; -+ u32 divVal; -+ u32 curFb, curClkDiv; -+ u32 minFb = 0; -+ u32 maxFb = 0; -+ u32 curDiv = 1; -+ u32 maxDiv; -+ bool freq_found = false; -+ -+ bestPick->freq = 0; -+ if (parentFreq == 0) -+ return 0; -+ -+ /* minimum frequency is actually dictated by VCOmin */ -+ if (freq < MMCM_FREQ_OUTMIN) -+ freq = MMCM_FREQ_OUTMIN; -+ if (freq > MMCM_FREQ_OUTMAX) -+ freq = MMCM_FREQ_OUTMAX; -+ -+ if (parentFreq > MMCM_FREQ_PFDMAX) -+ curDiv = 2; -+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; -+ if (maxDiv > MMCM_DIV_MAX) -+ maxDiv = MMCM_DIV_MAX; -+ -+ while (curDiv <= maxDiv && !freq_found) { -+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); -+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); -+ if (maxFb > MMCM_FB_MAX) -+ maxFb = MMCM_FB_MAX; -+ if (minFb < MMCM_FB_MIN) -+ minFb = MMCM_FB_MIN; -+ -+ divVal = curDiv * freq; -+ /* -+ * This multiplier is used to find the best clkDiv value for -+ * each FB value -+ */ -+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; -+ -+ curFb = minFb; -+ while (curFb <= maxFb && !freq_found) { -+ curClkDiv = ((curClkMult * curFb) + 500) / 1000; -+ if (curClkDiv > MMCM_CLKDIV_MAX) -+ curClkDiv = MMCM_CLKDIV_MAX; -+ if (curClkDiv < MMCM_CLKDIV_MIN) -+ curClkDiv = MMCM_CLKDIV_MIN; -+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); -+ if (curFreq >= freq) -+ curError = curFreq - freq; -+ else -+ curError = freq - curFreq; -+ if (curError < bestError) { -+ bestError = curError; -+ bestPick->clkdiv = curClkDiv; -+ bestPick->fbmult = curFb; -+ bestPick->maindiv = curDiv; -+ bestPick->freq = curFreq; -+ } -+ if (!curError) -+ freq_found = true; -+ curFb++; -+ } -+ curDiv++; -+ } -+ return bestPick->freq; -+} -+ -+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) -+{ -+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); -+} -+ -+ -+static int dglnt_dynclk_enable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ unsigned int clock_state; -+ -+ if (dglnt_dynclk->freq) { -+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+ do { -+ clock_state = readl(dglnt_dynclk->base + -+ OFST_DISPLAY_STATUS); -+ } while (!clock_state); -+ } -+ return 0; -+} -+ -+static void dglnt_dynclk_disable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+} -+ -+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, -+ unsigned long rate, unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ struct dglnt_dynclk_reg clkReg; -+ struct dglnt_dynclk_mode clkMode; -+ -+ if (parent_rate == 0 || rate == 0) -+ return -EINVAL; -+ if (rate == dglnt_dynclk->freq) -+ return 0; -+ -+ /* -+ * Convert from Hz to KHz, then multiply by five to account for -+ * BUFR division -+ */ -+ rate = (rate + 100) / 200; -+ /* convert from Hz to KHz */ -+ parent_rate = (parent_rate + 500) / 1000; -+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) -+ return -EINVAL; -+ -+ /* -+ * Write to the PLL dynamic configuration registers to configure it -+ * with the calculated parameters. -+ */ -+ dglnt_dynclk_find_reg(&clkReg, &clkMode); -+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); -+ dglnt_dynclk->freq = clkMode.freq * 200; -+ dglnt_dynclk_disable(clk_hw); -+ dglnt_dynclk_enable(clk_hw); -+ -+ return 0; -+} -+ -+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ struct dglnt_dynclk_mode clkMode; -+ -+ dglnt_dynclk_find_mode(((rate + 100) / 200), -+ ((*parent_rate) + 500) / 1000, &clkMode); -+ -+ return (clkMode.freq * 200); -+} -+ -+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, -+ unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ return dglnt_dynclk->freq; -+} -+ -+ -+static const struct clk_ops dglnt_dynclk_ops = { -+ .recalc_rate = dglnt_dynclk_recalc_rate, -+ .round_rate = dglnt_dynclk_round_rate, -+ .set_rate = dglnt_dynclk_set_rate, -+ .enable = dglnt_dynclk_enable, -+ .disable = dglnt_dynclk_disable, -+}; -+ -+static const struct of_device_id dglnt_dynclk_ids[] = { -+ { .compatible = "digilent,axi-dynclk", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); -+ -+static int dglnt_dynclk_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *id; -+ struct dglnt_dynclk *dglnt_dynclk; -+ struct clk_init_data init; -+ const char *parent_name; -+ const char *clk_name; -+ struct resource *mem; -+ struct clk *clk; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); -+ if (!id) -+ return -ENODEV; -+ -+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), -+ GFP_KERNEL); -+ if (!dglnt_dynclk) -+ return -ENOMEM; -+ -+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); -+ if (IS_ERR(dglnt_dynclk->base)) -+ return PTR_ERR(dglnt_dynclk->base); -+ -+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); -+ if (!parent_name) -+ return -EINVAL; -+ -+ clk_name = pdev->dev.of_node->name; -+ of_property_read_string(pdev->dev.of_node, "clock-output-names", -+ &clk_name); -+ -+ init.name = clk_name; -+ init.ops = &dglnt_dynclk_ops; -+ init.flags = 0; -+ init.parent_names = &parent_name; -+ init.num_parents = 1; -+ -+ dglnt_dynclk->freq = 0; -+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); -+ -+ dglnt_dynclk->clk_hw.init = &init; -+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, -+ clk); -+} -+ -+static int dglnt_dynclk_remove(struct platform_device *pdev) -+{ -+ of_clk_del_provider(pdev->dev.of_node); -+ -+ return 0; -+} -+ -+static struct platform_driver dglnt_dynclk_driver = { -+ .driver = { -+ .name = "dglnt-dynclk", -+ .owner = THIS_MODULE, -+ .of_match_table = dglnt_dynclk_ids, -+ }, -+ .probe = dglnt_dynclk_probe, -+ .remove = dglnt_dynclk_remove, -+}; -+module_platform_driver(dglnt_dynclk_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Sam Bobrowicz "); -+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch deleted file mode 100644 index a98d84c5..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 -From: Nathan Rossi -Date: Mon, 2 May 2016 23:46:42 +1000 -Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on - -Fix the issues where the VTC is reset (losing its timing config). - -Also fix the issue where the plane destroys its DMA descriptors and -marks the DMA channels as inactive but never recreates the descriptors -and never updates the active state when turning DPMS back on. - -Signed-off-by: Nathan Rossi -Upstream-Status: Pending [This is a workaround] ---- - drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - - drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -index 631d35b921..93dbd4b58a 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) - default: - if (crtc->vtc) { - xilinx_vtc_disable(crtc->vtc); -- xilinx_vtc_reset(crtc->vtc); - } - if (crtc->cresample) { - xilinx_cresample_disable(crtc->cresample); -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -index 6a248b72d4..d2518a4bdf 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { - struct xilinx_drm_plane_dma *dma = &plane->dma[i]; - -- if (dma->chan && dma->is_active) { -+ if (dma->chan) { - flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; - desc = dmaengine_prep_interleaved_dma(dma->chan, - &dma->xt, -@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - dmaengine_submit(desc); - - dma_async_issue_pending(dma->chan); -+ dma->is_active = true; - } - } - } --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0004-minized-wifi-bluetooth.cfg deleted file mode 100644 index f71e53ab..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.1/0004-minized-wifi-bluetooth.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# -# Bluetooth config -# -CONFIG_BT=y -CONFIG_BT_BREDR=y -CONFIG_BT_HS=y -CONFIG_BT_LE=y -CONFIG_BT_BCM=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HIDP=y -CONFIG_CFG80211=y -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_CRDA_SUPPORT=y -CONFIG_BRCMUTIL=y -CONFIG_BRCMFMAC=y -CONFIG_BRCMFMAC_PROTO_BCDC=y -CONFIG_BRCMFMAC_SDIO=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_SHA256=y - -# -# Regulator config -# -CONFIG_REGMAP_IRQ=y -CONFIG_I2C_XILINX=y -CONFIG_MFD_DA9062=y -CONFIG_REGULATOR_DA9062=y - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch new file mode 100644 index 00000000..b8ba70ea --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch @@ -0,0 +1,302 @@ +From c1bf9e8c50baa237b514715dcb9c8fd367694c93 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:14:13 +1000 +Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards + +Add the dglnt_encoder driver that enables DRM support for the VGA and +HDMI output ports found on many Digilent boards. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ + drivers/gpu/drm/xilinx/Kconfig | 6 + + drivers/gpu/drm/xilinx/Makefile | 1 + + drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ + 4 files changed, 247 insertions(+) + create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt + create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c + +diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +new file mode 100644 +index 0000000000..242b24e482 +--- /dev/null ++++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +@@ -0,0 +1,23 @@ ++Device-Tree bindings for Digilent DRM Encoder Slave ++ ++This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. ++The VGA or HDMI port must be connected to a Xilinx display pipeline via an ++axi2vid IP core. ++ ++Required properties: ++ - compatible: Should be "digilent,drm-encoder". ++ ++Optional properties: ++ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video ++ connector. This is used to obtain the supported resolutions ++ of an attached monitor. If not defined, then a default ++ set of resolutions is used and the display will initialize ++ to 720p. Note most VGA connectors on Digilent boards do ++ not have the DDC bus routed out. ++ ++Example: ++ ++ encoder_0: digilent_encoder { ++ compatible = "digilent,drm-encoder"; ++ dglnt,edid-i2c = <&i2c1>; ++ }; +diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig +index 12b548c2a9..c3e2562e53 100644 +--- a/drivers/gpu/drm/xilinx/Kconfig ++++ b/drivers/gpu/drm/xilinx/Kconfig +@@ -57,3 +57,9 @@ config DRM_XILINX_SDI + depends on DRM_XILINX + help + DRM driver for Xilinx Display Port Subsystem. ++ ++config DRM_DIGILENT_ENCODER ++ tristate "Digilent VGA/HDMI DRM Encoder Driver" ++ depends on DRM_XILINX ++ help ++ DRM slave encoder for Video-out on Digilent boards. +diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile +index 19bc1541ca..c2717e40ea 100644 +--- a/drivers/gpu/drm/xilinx/Makefile ++++ b/drivers/gpu/drm/xilinx/Makefile +@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ + xilinx_drm_plane.o + xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o + ++obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o + obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o + obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o + obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o +diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c +new file mode 100644 +index 0000000000..26a23986f9 +--- /dev/null ++++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c +@@ -0,0 +1,217 @@ ++/* ++ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. ++ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DGLNT_ENC_MAX_FREQ 150000 ++#define DGLNT_ENC_MAX_H 1920 ++#define DGLNT_ENC_MAX_V 1080 ++#define DGLNT_ENC_PREF_H 1280 ++#define DGLNT_ENC_PREF_V 720 ++ ++struct dglnt_encoder { ++ struct drm_encoder *encoder; ++ struct i2c_adapter *i2c_bus; ++ bool i2c_present; ++}; ++ ++static inline struct dglnt_encoder *to_dglnt_encoder( ++ struct drm_encoder *encoder) ++{ ++ return to_encoder_slave(encoder)->slave_priv; ++} ++ ++static bool dglnt_mode_fixup(struct drm_encoder *encoder, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++static void dglnt_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++} ++ ++static void ++dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) ++{ ++} ++ ++static void dglnt_encoder_save(struct drm_encoder *encoder) ++{ ++} ++ ++static void dglnt_encoder_restore(struct drm_encoder *encoder) ++{ ++} ++ ++static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, ++ struct drm_display_mode *mode) ++{ ++ if (mode && ++ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | ++ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && ++ (mode->clock <= DGLNT_ENC_MAX_FREQ) && ++ (mode->hdisplay <= DGLNT_ENC_MAX_H) && ++ (mode->vdisplay <= DGLNT_ENC_MAX_V)) ++ return MODE_OK; ++ return MODE_BAD; ++} ++ ++static int dglnt_encoder_get_modes(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ struct edid *edid; ++ int num_modes = 0; ++ ++ if (dglnt->i2c_present) { ++ edid = drm_get_edid(connector, dglnt->i2c_bus); ++ drm_mode_connector_update_edid_property(connector, edid); ++ if (edid) { ++ num_modes = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ } else { ++ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, ++ DGLNT_ENC_MAX_V); ++ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, ++ DGLNT_ENC_PREF_V); ++ } ++ return num_modes; ++} ++ ++static enum drm_connector_status dglnt_encoder_detect( ++ struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ ++ if (dglnt->i2c_present) { ++ if (drm_probe_ddc(dglnt->i2c_bus)) ++ return connector_status_connected; ++ return connector_status_disconnected; ++ } else ++ return connector_status_unknown; ++} ++ ++static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { ++ .dpms = dglnt_encoder_dpms, ++ .save = dglnt_encoder_save, ++ .restore = dglnt_encoder_restore, ++ .mode_fixup = dglnt_mode_fixup, ++ .mode_valid = dglnt_encoder_mode_valid, ++ .mode_set = dglnt_encoder_mode_set, ++ .detect = dglnt_encoder_detect, ++ .get_modes = dglnt_encoder_get_modes, ++}; ++ ++static int dglnt_encoder_encoder_init(struct platform_device *pdev, ++ struct drm_device *dev, ++ struct drm_encoder_slave *encoder) ++{ ++ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); ++ struct device_node *sub_node; ++ ++ encoder->slave_priv = dglnt; ++ encoder->slave_funcs = &dglnt_encoder_slave_funcs; ++ ++ dglnt->encoder = &encoder->base; ++ ++ /* get i2c adapter for edid */ ++ dglnt->i2c_present = false; ++ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); ++ if (sub_node) { ++ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); ++ if (!dglnt->i2c_bus) ++ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); ++ else ++ dglnt->i2c_present = true; ++ of_node_put(sub_node); ++ } ++ ++ return 0; ++} ++ ++static int dglnt_encoder_probe(struct platform_device *pdev) ++{ ++ struct dglnt_encoder *dglnt; ++ ++ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); ++ if (!dglnt) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, dglnt); ++ ++ return 0; ++} ++ ++static int dglnt_encoder_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static const struct of_device_id dglnt_encoder_of_match[] = { ++ { .compatible = "digilent,drm-encoder", }, ++ { /* end of table */ }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); ++ ++static struct drm_platform_encoder_driver dglnt_encoder_driver = { ++ .platform_driver = { ++ .probe = dglnt_encoder_probe, ++ .remove = dglnt_encoder_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "dglnt-drm-enc", ++ .of_match_table = dglnt_encoder_of_match, ++ }, ++ }, ++ ++ .encoder_init = dglnt_encoder_encoder_init, ++}; ++ ++static int __init dglnt_encoder_init(void) ++{ ++ return platform_driver_register(&dglnt_encoder_driver.platform_driver); ++} ++ ++static void __exit dglnt_encoder_exit(void) ++{ ++ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); ++} ++ ++module_init(dglnt_encoder_init); ++module_exit(dglnt_encoder_exit); ++ ++MODULE_AUTHOR("Digilent, Inc."); ++MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); ++MODULE_LICENSE("GPL v2"); +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch new file mode 100644 index 00000000..9b6229db --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch @@ -0,0 +1,607 @@ +From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:16:06 +1000 +Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core + +Add support for the axi_dynclk IP Core available from Digilent. This IP +core dynamically configures the clock resources inside a Xilinx FPGA to +generate a clock with a software programmable frequency. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + drivers/clk/Kconfig | 8 + + drivers/clk/Makefile | 1 + + drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 556 insertions(+) + create mode 100644 drivers/clk/clk-dglnt-dynclk.c + +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index dccb111100..7fe65a702b 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -148,6 +148,14 @@ config CLK_QORIQ + This adds the clock driver support for Freescale QorIQ platforms + using common clock framework. + ++config COMMON_CLK_DGLNT_DYNCLK ++ tristate "Digilent axi_dynclk Driver" ++ depends on ARCH_ZYNQ || MICROBLAZE ++ help ++ ---help--- ++ Support for the Digilent AXI Dynamic Clock core for Xilinx ++ FPGAs. ++ + config COMMON_CLK_XGENE + bool "Clock driver for APM XGene SoC" + default y +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index 0760449dde..45ce97d053 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o + obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o ++obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o + obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o + obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o + obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c +new file mode 100644 +index 0000000000..496ad5fc90 +--- /dev/null ++++ b/drivers/clk/clk-dglnt-dynclk.c +@@ -0,0 +1,547 @@ ++/* ++ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLK_BIT_WEDGE 13 ++#define CLK_BIT_NOCOUNT 12 ++ ++/* This value is used to signal an error */ ++#define ERR_CLKCOUNTCALC 0xFFFFFFFF ++#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) ++ ++#define DYNCLK_DIV_1_REGMASK 0x1041 ++/* 25 MHz (125 KHz / 5) */ ++#define DYNCLK_DEFAULT_FREQ 125000 ++ ++#define MMCM_FREQ_VCOMIN 600000 ++#define MMCM_FREQ_VCOMAX 1200000 ++#define MMCM_FREQ_PFDMIN 10000 ++#define MMCM_FREQ_PFDMAX 450000 ++#define MMCM_FREQ_OUTMIN 4000 ++#define MMCM_FREQ_OUTMAX 800000 ++#define MMCM_DIV_MAX 106 ++#define MMCM_FB_MIN 2 ++#define MMCM_FB_MAX 64 ++#define MMCM_CLKDIV_MAX 128 ++#define MMCM_CLKDIV_MIN 1 ++ ++#define OFST_DISPLAY_CTRL 0x0 ++#define OFST_DISPLAY_STATUS 0x4 ++#define OFST_DISPLAY_CLK_L 0x8 ++#define OFST_DISPLAY_FB_L 0x0C ++#define OFST_DISPLAY_FB_H_CLK_H 0x10 ++#define OFST_DISPLAY_DIV 0x14 ++#define OFST_DISPLAY_LOCK_L 0x18 ++#define OFST_DISPLAY_FLTR_LOCK_H 0x1C ++ ++static const u64 lock_lookup[64] = { ++ 0b0011000110111110100011111010010000000001, ++ 0b0011000110111110100011111010010000000001, ++ 0b0100001000111110100011111010010000000001, ++ 0b0101101011111110100011111010010000000001, ++ 0b0111001110111110100011111010010000000001, ++ 0b1000110001111110100011111010010000000001, ++ 0b1001110011111110100011111010010000000001, ++ 0b1011010110111110100011111010010000000001, ++ 0b1100111001111110100011111010010000000001, ++ 0b1110011100111110100011111010010000000001, ++ 0b1111111111111000010011111010010000000001, ++ 0b1111111111110011100111111010010000000001, ++ 0b1111111111101110111011111010010000000001, ++ 0b1111111111101011110011111010010000000001, ++ 0b1111111111101000101011111010010000000001, ++ 0b1111111111100111000111111010010000000001, ++ 0b1111111111100011111111111010010000000001, ++ 0b1111111111100010011011111010010000000001, ++ 0b1111111111100000110111111010010000000001, ++ 0b1111111111011111010011111010010000000001, ++ 0b1111111111011101101111111010010000000001, ++ 0b1111111111011100001011111010010000000001, ++ 0b1111111111011010100111111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111010111011111111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001 ++}; ++ ++static const u32 filter_lookup_low[64] = { ++ 0b0001011111, ++ 0b0001010111, ++ 0b0001111011, ++ 0b0001011011, ++ 0b0001101011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0010110011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011 ++}; ++ ++struct dglnt_dynclk_reg; ++struct dglnt_dynclk_mode; ++struct dglnt_dynclk; ++ ++struct dglnt_dynclk_reg { ++ u32 clk0L; ++ u32 clkFBL; ++ u32 clkFBH_clk0H; ++ u32 divclk; ++ u32 lockL; ++ u32 fltr_lockH; ++}; ++ ++struct dglnt_dynclk_mode { ++ u32 freq; ++ u32 fbmult; ++ u32 clkdiv; ++ u32 maindiv; ++}; ++ ++struct dglnt_dynclk { ++ void __iomem *base; ++ struct clk_hw clk_hw; ++ unsigned long freq; ++}; ++ ++u32 dglnt_dynclk_divider(u32 divide) ++{ ++ u32 output = 0; ++ u32 highTime = 0; ++ u32 lowTime = 0; ++ ++ if ((divide < 1) || (divide > 128)) ++ return ERR_CLKDIVIDER; ++ ++ if (divide == 1) ++ return DYNCLK_DIV_1_REGMASK; ++ ++ highTime = divide / 2; ++ /* if divide is odd */ ++ if (divide & 0x1) { ++ lowTime = highTime + 1; ++ output = 1 << CLK_BIT_WEDGE; ++ } else { ++ lowTime = highTime; ++ } ++ ++ output |= 0x03F & lowTime; ++ output |= 0xFC0 & (highTime << 6); ++ return output; ++} ++ ++u32 dglnt_dynclk_count_calc(u32 divide) ++{ ++ u32 output = 0; ++ u32 divCalc = 0; ++ ++ divCalc = dglnt_dynclk_divider(divide); ++ if (divCalc == ERR_CLKDIVIDER) ++ output = ERR_CLKCOUNTCALC; ++ else ++ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); ++ return output; ++} ++ ++ ++int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, ++ struct dglnt_dynclk_mode *clkParams) ++{ ++ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) ++ return -EINVAL; ++ ++ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); ++ if (regValues->clk0L == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); ++ if (regValues->clkFBL == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBH_clk0H = 0; ++ ++ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); ++ if (regValues->divclk == ERR_CLKDIVIDER) ++ return -EINVAL; ++ ++ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & ++ 0xFFFFFFFF); ++ ++ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> ++ 32) & 0x000000FF); ++ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << ++ 16) & 0x03FF0000); ++ ++ return 0; ++} ++ ++void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, ++ void __iomem *baseaddr) ++{ ++ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); ++ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); ++ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); ++ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); ++ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); ++ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); ++} ++ ++u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, ++ struct dglnt_dynclk_mode *bestPick) ++{ ++ u32 bestError = MMCM_FREQ_OUTMAX; ++ u32 curError; ++ u32 curClkMult; ++ u32 curFreq; ++ u32 divVal; ++ u32 curFb, curClkDiv; ++ u32 minFb = 0; ++ u32 maxFb = 0; ++ u32 curDiv = 1; ++ u32 maxDiv; ++ bool freq_found = false; ++ ++ bestPick->freq = 0; ++ if (parentFreq == 0) ++ return 0; ++ ++ /* minimum frequency is actually dictated by VCOmin */ ++ if (freq < MMCM_FREQ_OUTMIN) ++ freq = MMCM_FREQ_OUTMIN; ++ if (freq > MMCM_FREQ_OUTMAX) ++ freq = MMCM_FREQ_OUTMAX; ++ ++ if (parentFreq > MMCM_FREQ_PFDMAX) ++ curDiv = 2; ++ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; ++ if (maxDiv > MMCM_DIV_MAX) ++ maxDiv = MMCM_DIV_MAX; ++ ++ while (curDiv <= maxDiv && !freq_found) { ++ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); ++ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); ++ if (maxFb > MMCM_FB_MAX) ++ maxFb = MMCM_FB_MAX; ++ if (minFb < MMCM_FB_MIN) ++ minFb = MMCM_FB_MIN; ++ ++ divVal = curDiv * freq; ++ /* ++ * This multiplier is used to find the best clkDiv value for ++ * each FB value ++ */ ++ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; ++ ++ curFb = minFb; ++ while (curFb <= maxFb && !freq_found) { ++ curClkDiv = ((curClkMult * curFb) + 500) / 1000; ++ if (curClkDiv > MMCM_CLKDIV_MAX) ++ curClkDiv = MMCM_CLKDIV_MAX; ++ if (curClkDiv < MMCM_CLKDIV_MIN) ++ curClkDiv = MMCM_CLKDIV_MIN; ++ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); ++ if (curFreq >= freq) ++ curError = curFreq - freq; ++ else ++ curError = freq - curFreq; ++ if (curError < bestError) { ++ bestError = curError; ++ bestPick->clkdiv = curClkDiv; ++ bestPick->fbmult = curFb; ++ bestPick->maindiv = curDiv; ++ bestPick->freq = curFreq; ++ } ++ if (!curError) ++ freq_found = true; ++ curFb++; ++ } ++ curDiv++; ++ } ++ return bestPick->freq; ++} ++ ++static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) ++{ ++ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); ++} ++ ++ ++static int dglnt_dynclk_enable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ unsigned int clock_state; ++ ++ if (dglnt_dynclk->freq) { ++ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++ do { ++ clock_state = readl(dglnt_dynclk->base + ++ OFST_DISPLAY_STATUS); ++ } while (!clock_state); ++ } ++ return 0; ++} ++ ++static void dglnt_dynclk_disable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++} ++ ++static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ struct dglnt_dynclk_reg clkReg; ++ struct dglnt_dynclk_mode clkMode; ++ ++ if (parent_rate == 0 || rate == 0) ++ return -EINVAL; ++ if (rate == dglnt_dynclk->freq) ++ return 0; ++ ++ /* ++ * Convert from Hz to KHz, then multiply by five to account for ++ * BUFR division ++ */ ++ rate = (rate + 100) / 200; ++ /* convert from Hz to KHz */ ++ parent_rate = (parent_rate + 500) / 1000; ++ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) ++ return -EINVAL; ++ ++ /* ++ * Write to the PLL dynamic configuration registers to configure it ++ * with the calculated parameters. ++ */ ++ dglnt_dynclk_find_reg(&clkReg, &clkMode); ++ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); ++ dglnt_dynclk->freq = clkMode.freq * 200; ++ dglnt_dynclk_disable(clk_hw); ++ dglnt_dynclk_enable(clk_hw); ++ ++ return 0; ++} ++ ++static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct dglnt_dynclk_mode clkMode; ++ ++ dglnt_dynclk_find_mode(((rate + 100) / 200), ++ ((*parent_rate) + 500) / 1000, &clkMode); ++ ++ return (clkMode.freq * 200); ++} ++ ++static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, ++ unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ return dglnt_dynclk->freq; ++} ++ ++ ++static const struct clk_ops dglnt_dynclk_ops = { ++ .recalc_rate = dglnt_dynclk_recalc_rate, ++ .round_rate = dglnt_dynclk_round_rate, ++ .set_rate = dglnt_dynclk_set_rate, ++ .enable = dglnt_dynclk_enable, ++ .disable = dglnt_dynclk_disable, ++}; ++ ++static const struct of_device_id dglnt_dynclk_ids[] = { ++ { .compatible = "digilent,axi-dynclk", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); ++ ++static int dglnt_dynclk_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct dglnt_dynclk *dglnt_dynclk; ++ struct clk_init_data init; ++ const char *parent_name; ++ const char *clk_name; ++ struct resource *mem; ++ struct clk *clk; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); ++ if (!id) ++ return -ENODEV; ++ ++ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), ++ GFP_KERNEL); ++ if (!dglnt_dynclk) ++ return -ENOMEM; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); ++ if (IS_ERR(dglnt_dynclk->base)) ++ return PTR_ERR(dglnt_dynclk->base); ++ ++ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); ++ if (!parent_name) ++ return -EINVAL; ++ ++ clk_name = pdev->dev.of_node->name; ++ of_property_read_string(pdev->dev.of_node, "clock-output-names", ++ &clk_name); ++ ++ init.name = clk_name; ++ init.ops = &dglnt_dynclk_ops; ++ init.flags = 0; ++ init.parent_names = &parent_name; ++ init.num_parents = 1; ++ ++ dglnt_dynclk->freq = 0; ++ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); ++ ++ dglnt_dynclk->clk_hw.init = &init; ++ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, ++ clk); ++} ++ ++static int dglnt_dynclk_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver dglnt_dynclk_driver = { ++ .driver = { ++ .name = "dglnt-dynclk", ++ .owner = THIS_MODULE, ++ .of_match_table = dglnt_dynclk_ids, ++ }, ++ .probe = dglnt_dynclk_probe, ++ .remove = dglnt_dynclk_remove, ++}; ++module_platform_driver(dglnt_dynclk_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Sam Bobrowicz "); ++MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch new file mode 100644 index 00000000..a98d84c5 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch @@ -0,0 +1,54 @@ +From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 +From: Nathan Rossi +Date: Mon, 2 May 2016 23:46:42 +1000 +Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on + +Fix the issues where the VTC is reset (losing its timing config). + +Also fix the issue where the plane destroys its DMA descriptors and +marks the DMA channels as inactive but never recreates the descriptors +and never updates the active state when turning DPMS back on. + +Signed-off-by: Nathan Rossi +Upstream-Status: Pending [This is a workaround] +--- + drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - + drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +index 631d35b921..93dbd4b58a 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) + default: + if (crtc->vtc) { + xilinx_vtc_disable(crtc->vtc); +- xilinx_vtc_reset(crtc->vtc); + } + if (crtc->cresample) { + xilinx_cresample_disable(crtc->cresample); +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +index 6a248b72d4..d2518a4bdf 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { + struct xilinx_drm_plane_dma *dma = &plane->dma[i]; + +- if (dma->chan && dma->is_active) { ++ if (dma->chan) { + flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + desc = dmaengine_prep_interleaved_dma(dma->chan, + &dma->xt, +@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + dmaengine_submit(desc); + + dma_async_issue_pending(dma->chan); ++ dma->is_active = true; + } + } + } +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0004-minized-wifi-bluetooth.cfg new file mode 100644 index 00000000..f71e53ab --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2018.3/0004-minized-wifi-bluetooth.cfg @@ -0,0 +1,33 @@ +# +# Bluetooth config +# +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_BCM=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HIDP=y +CONFIG_CFG80211=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_BRCMUTIL=y +CONFIG_BRCMFMAC=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA256=y + +# +# Regulator config +# +CONFIG_REGMAP_IRQ=y +CONFIG_I2C_XILINX=y +CONFIG_MFD_DA9062=y +CONFIG_REGULATOR_DA9062=y + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.1.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.1.bbappend deleted file mode 100644 index 535fbb26..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.1.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -FILESEXTRAPATHS_prepend := "${THISDIR}/linux-xlnx:" - -SRC_URI_append_zybo-linux-bd-zynq7 = " \ - file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ - file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ - file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ - " - -SRC_URI_append_minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.3.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.3.bbappend new file mode 100644 index 00000000..535fbb26 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2018.3.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/linux-xlnx:" + +SRC_URI_append_zybo-linux-bd-zynq7 = " \ + file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ + file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ + file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ + " + +SRC_URI_append_minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" -- cgit v1.2.3-54-g00ecf