From 7d8ebf6923ef5405acb8778aeb266b9c8189d8fb Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Sat, 5 Feb 2022 09:55:11 -0800 Subject: xlnx-embeddedsw: Add 2022.2 branch Signed-off-by: Mark Hatle --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index caf3095e..3d9b207f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -10,6 +10,7 @@ ESW_BRANCH[2020.2] = "master-rel-2020.2" ESW_BRANCH[2021.1] = "xlnx_rel_v2021.1" ESW_BRANCH[2021.2] = "xlnx_rel_v2021.2" ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1-next" +ESW_BRANCH[2022.2] = "master-next" ESW_BRANCH[git] = "master-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" @@ -20,6 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "2a4cab4ccf38e0d7cc59270ad4de69b8e73c1835" +ESW_REV[2022.2] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" @@ -34,7 +36,7 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1-next] = '87cee16dbcd2c2f7ceef30163838056e' -LIC_FILES_CHKSUM[master-next] = '87cee16dbcd2c2f7ceef30163838056e' +LIC_FILES_CHKSUM[master-next] = '593ba3fb8be51271097ddaa4b9c65cde' LIC_FILES_CHKSUM[master] = '593ba3fb8be51271097ddaa4b9c65cde' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" -- cgit v1.2.3-54-g00ecf From e941e10d9f22e5f7dbbdc293dc7f6e59ff63b8f0 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 4 Feb 2022 13:10:22 -0800 Subject: various: Move from 2022.1 to 2022.2 Signed-off-by: Mark Hatle --- .../reference-design/kc705-bitstream_2022.1.bb | 48 -- .../reference-design/kc705-bitstream_2022.2.bb | 48 ++ meta-xilinx-contrib/conf/layer.conf | 2 +- ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 305 ----------- ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 --------------------- ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 -- .../v2022.1/0004-minized-wifi-bluetooth.cfg | 33 -- ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 305 +++++++++++ ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 +++++++++++++++++++++ ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 ++ .../v2022.2/0004-minized-wifi-bluetooth.cfg | 33 ++ .../linux/linux-xlnx_2022.1.bbappend | 9 - .../linux/linux-xlnx_2022.2.bbappend | 9 + meta-xilinx-core/README.qemu.md | 2 +- meta-xilinx-core/conf/layer.conf | 2 +- meta-xilinx-core/conf/local.conf.sample | 4 +- .../arm-trusted-firmware_2022.1.bb | 8 - .../arm-trusted-firmware_2022.2.bb | 8 + .../pmu-firmware/pmu-rom-native_2022.1.bb | 27 - .../pmu-firmware/pmu-rom-native_2022.2.bb | 27 + .../recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb | 19 - .../recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 19 + .../qemu/qemu-devicetrees_2022.1.bb | 5 - .../qemu/qemu-devicetrees_2022.2.bb | 5 + .../qemu/qemu-xilinx-native_2022.1.bb | 7 - .../qemu/qemu-xilinx-native_2022.2.bb | 7 + .../qemu/qemu-xilinx-system-native_2022.1.bb | 18 - .../qemu/qemu-xilinx-system-native_2022.2.bb | 18 + .../recipes-devtools/qemu/qemu-xilinx_2022.1.bb | 17 - .../recipes-devtools/qemu/qemu-xilinx_2022.2.bb | 17 + .../recipes-kernel/linux/linux-xlnx_2022.1.bb | 9 - .../recipes-kernel/linux/linux-xlnx_2022.2.bb | 9 + meta-xilinx-standalone/conf/layer.conf | 2 +- .../recipes-bsp/embeddedsw/fsbl-firmware_2022.2.bb | 11 + .../recipes-bsp/embeddedsw/plm-firmware_2022.2.bb | 16 + .../recipes-bsp/embeddedsw/pmu-firmware_2022.2.bb | 16 + .../recipes-bsp/embeddedsw/psm-firmware_2022.2.bb | 16 + 37 files changed, 1231 insertions(+), 1172 deletions(-) delete mode 100644 meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb create mode 100644 meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.2.bb delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0004-minized-wifi-bluetooth.cfg delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend delete mode 100644 meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb create mode 100644 meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.1.bb create mode 100644 meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb create mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb create mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.1.bb create mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.1.bb create mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.1.bb create mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb create mode 100644 meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.2.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.2.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.2.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.2.bb diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb deleted file mode 100644 index e512777c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb +++ /dev/null @@ -1,48 +0,0 @@ -SUMMARY = "KC705 Pre-built Bitstream" -DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -# The BSP package does not include any license information. -LICENSE = "Proprietary" -LICENSE_FLAGS = "xilinx" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" - -COMPATIBLE_MACHINE = "kc705-microblazeel" - -inherit deploy -inherit xilinx-fetch-restricted - -BSP_NAME = "xilinx-kc705" -BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" -SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" -SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" -SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" - -PROVIDES = "virtual/bitstream" - -FILES:${PN} += "/boot/download.bit" - -INHIBIT_DEFAULT_DEPS = "1" -PACKAGE_ARCH = "${MACHINE_ARCH}" - -# deps needed to extract content from the .bsp file -DEPENDS += "tar-native gzip-native" - -do_compile() { - # Extract the bitstream into workdir - tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} - # move the bit file to ${S}/ as it is in a subdir in the tar file - for i in $(find -type f -name download.bit); do mv $i ${S}; done -} - -do_install() { - install -D ${S}/download.bit ${D}/boot/download.bit -} - -do_deploy () { - install -D ${S}/download.bit ${DEPLOYDIR}/download.bit -} - -addtask deploy before do_build after do_install - diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.2.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.2.bb new file mode 100644 index 00000000..e512777c --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.2.bb @@ -0,0 +1,48 @@ +SUMMARY = "KC705 Pre-built Bitstream" +DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." +HOMEPAGE = "http://www.xilinx.com" +SECTION = "bsp" + +# The BSP package does not include any license information. +LICENSE = "Proprietary" +LICENSE_FLAGS = "xilinx" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" + +COMPATIBLE_MACHINE = "kc705-microblazeel" + +inherit deploy +inherit xilinx-fetch-restricted + +BSP_NAME = "xilinx-kc705" +BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" +SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" +SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" +SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" + +PROVIDES = "virtual/bitstream" + +FILES:${PN} += "/boot/download.bit" + +INHIBIT_DEFAULT_DEPS = "1" +PACKAGE_ARCH = "${MACHINE_ARCH}" + +# deps needed to extract content from the .bsp file +DEPENDS += "tar-native gzip-native" + +do_compile() { + # Extract the bitstream into workdir + tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} + # move the bit file to ${S}/ as it is in a subdir in the tar file + for i in $(find -type f -name download.bit); do mv $i ${S}; done +} + +do_install() { + install -D ${S}/download.bit ${D}/boot/download.bit +} + +do_deploy () { + install -D ${S}/download.bit ${DEPLOYDIR}/download.bit +} + +addtask deploy before do_build after do_install + diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf index 026d79d2..253d64d1 100644 --- a/meta-xilinx-contrib/conf/layer.conf +++ b/meta-xilinx-contrib/conf/layer.conf @@ -14,4 +14,4 @@ LAYERDEPENDS_xilinx-contrib = "xilinx" LAYERSERIES_COMPAT_xilinx-contrib = "honister" -XILINX_RELEASE_VERSION = "v2022.1" +XILINX_RELEASE_VERSION = "v2022.2" diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch deleted file mode 100644 index 660bc218..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch +++ /dev/null @@ -1,305 +0,0 @@ -From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:14:13 +1000 -Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards - -Add the dglnt_encoder driver that enables DRM support for the VGA and -HDMI output ports found on many Digilent boards. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ - drivers/gpu/drm/xilinx/Kconfig | 6 + - drivers/gpu/drm/xilinx/Makefile | 1 + - drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ - 4 files changed, 247 insertions(+) - create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt - create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c - -diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -new file mode 100644 -index 0000000..242b24e ---- /dev/null -+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -@@ -0,0 +1,23 @@ -+Device-Tree bindings for Digilent DRM Encoder Slave -+ -+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. -+The VGA or HDMI port must be connected to a Xilinx display pipeline via an -+axi2vid IP core. -+ -+Required properties: -+ - compatible: Should be "digilent,drm-encoder". -+ -+Optional properties: -+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video -+ connector. This is used to obtain the supported resolutions -+ of an attached monitor. If not defined, then a default -+ set of resolutions is used and the display will initialize -+ to 720p. Note most VGA connectors on Digilent boards do -+ not have the DDC bus routed out. -+ -+Example: -+ -+ encoder_0: digilent_encoder { -+ compatible = "digilent,drm-encoder"; -+ dglnt,edid-i2c = <&i2c1>; -+ }; -diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig -index 57e18a9..d9ecff2 100644 ---- a/drivers/gpu/drm/xilinx/Kconfig -+++ b/drivers/gpu/drm/xilinx/Kconfig -@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB - help - DRM driver for Xilinx Display Port Subsystem. - -+config DRM_DIGILENT_ENCODER -+ tristate "Digilent VGA/HDMI DRM Encoder Driver" -+ depends on DRM_XILINX -+ help -+ DRM slave encoder for Video-out on Digilent boards. -+ - config DRM_XILINX_DP_SUB_DEBUG_FS - bool "Xilinx DRM DPSUB debugfs" - depends on DEBUG_FS && DRM_XILINX_DP_SUB -diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile -index 19bc154..c2717e40 100644 ---- a/drivers/gpu/drm/xilinx/Makefile -+++ b/drivers/gpu/drm/xilinx/Makefile -@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ - xilinx_drm_plane.o - xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o - -+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o - obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o - obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o - obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o -diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c -new file mode 100644 -index 0000000..cb9fc7d ---- /dev/null -+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c -@@ -0,0 +1,217 @@ -+/* -+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. -+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DGLNT_ENC_MAX_FREQ 150000 -+#define DGLNT_ENC_MAX_H 1920 -+#define DGLNT_ENC_MAX_V 1080 -+#define DGLNT_ENC_PREF_H 1280 -+#define DGLNT_ENC_PREF_V 720 -+ -+struct dglnt_encoder { -+ struct drm_encoder *encoder; -+ struct i2c_adapter *i2c_bus; -+ bool i2c_present; -+}; -+ -+static inline struct dglnt_encoder *to_dglnt_encoder( -+ struct drm_encoder *encoder) -+{ -+ return to_encoder_slave(encoder)->slave_priv; -+} -+ -+static bool dglnt_mode_fixup(struct drm_encoder *encoder, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+ return true; -+} -+ -+static void dglnt_encoder_mode_set(struct drm_encoder *encoder, -+ struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+} -+ -+static void -+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) -+{ -+} -+ -+static void dglnt_encoder_save(struct drm_encoder *encoder) -+{ -+} -+ -+static void dglnt_encoder_restore(struct drm_encoder *encoder) -+{ -+} -+ -+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, -+ struct drm_display_mode *mode) -+{ -+ if (mode && -+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | -+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && -+ (mode->clock <= DGLNT_ENC_MAX_FREQ) && -+ (mode->hdisplay <= DGLNT_ENC_MAX_H) && -+ (mode->vdisplay <= DGLNT_ENC_MAX_V)) -+ return MODE_OK; -+ return MODE_BAD; -+} -+ -+static int dglnt_encoder_get_modes(struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ struct edid *edid; -+ int num_modes = 0; -+ -+ if (dglnt->i2c_present) { -+ edid = drm_get_edid(connector, dglnt->i2c_bus); -+ drm_connector_update_edid_property(connector, edid); -+ if (edid) { -+ num_modes = drm_add_edid_modes(connector, edid); -+ kfree(edid); -+ } -+ } else { -+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, -+ DGLNT_ENC_MAX_V); -+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, -+ DGLNT_ENC_PREF_V); -+ } -+ return num_modes; -+} -+ -+static enum drm_connector_status dglnt_encoder_detect( -+ struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ -+ if (dglnt->i2c_present) { -+ if (drm_probe_ddc(dglnt->i2c_bus)) -+ return connector_status_connected; -+ return connector_status_disconnected; -+ } else -+ return connector_status_unknown; -+} -+ -+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { -+ .dpms = dglnt_encoder_dpms, -+ .save = dglnt_encoder_save, -+ .restore = dglnt_encoder_restore, -+ .mode_fixup = dglnt_mode_fixup, -+ .mode_valid = dglnt_encoder_mode_valid, -+ .mode_set = dglnt_encoder_mode_set, -+ .detect = dglnt_encoder_detect, -+ .get_modes = dglnt_encoder_get_modes, -+}; -+ -+static int dglnt_encoder_encoder_init(struct platform_device *pdev, -+ struct drm_device *dev, -+ struct drm_encoder_slave *encoder) -+{ -+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); -+ struct device_node *sub_node; -+ -+ encoder->slave_priv = dglnt; -+ encoder->slave_funcs = &dglnt_encoder_slave_funcs; -+ -+ dglnt->encoder = &encoder->base; -+ -+ /* get i2c adapter for edid */ -+ dglnt->i2c_present = false; -+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); -+ if (sub_node) { -+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); -+ if (!dglnt->i2c_bus) -+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); -+ else -+ dglnt->i2c_present = true; -+ of_node_put(sub_node); -+ } -+ -+ return 0; -+} -+ -+static int dglnt_encoder_probe(struct platform_device *pdev) -+{ -+ struct dglnt_encoder *dglnt; -+ -+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); -+ if (!dglnt) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, dglnt); -+ -+ return 0; -+} -+ -+static int dglnt_encoder_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+static const struct of_device_id dglnt_encoder_of_match[] = { -+ { .compatible = "digilent,drm-encoder", }, -+ { /* end of table */ }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); -+ -+static struct drm_platform_encoder_driver dglnt_encoder_driver = { -+ .platform_driver = { -+ .probe = dglnt_encoder_probe, -+ .remove = dglnt_encoder_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "dglnt-drm-enc", -+ .of_match_table = dglnt_encoder_of_match, -+ }, -+ }, -+ -+ .encoder_init = dglnt_encoder_encoder_init, -+}; -+ -+static int __init dglnt_encoder_init(void) -+{ -+ return platform_driver_register(&dglnt_encoder_driver.platform_driver); -+} -+ -+static void __exit dglnt_encoder_exit(void) -+{ -+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); -+} -+ -+module_init(dglnt_encoder_init); -+module_exit(dglnt_encoder_exit); -+ -+MODULE_AUTHOR("Digilent, Inc."); -+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); -+MODULE_LICENSE("GPL v2"); --- -2.7.4 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch deleted file mode 100644 index 9b6229db..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch +++ /dev/null @@ -1,607 +0,0 @@ -From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:16:06 +1000 -Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core - -Add support for the axi_dynclk IP Core available from Digilent. This IP -core dynamically configures the clock resources inside a Xilinx FPGA to -generate a clock with a software programmable frequency. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - drivers/clk/Kconfig | 8 + - drivers/clk/Makefile | 1 + - drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 556 insertions(+) - create mode 100644 drivers/clk/clk-dglnt-dynclk.c - -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index dccb111100..7fe65a702b 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -148,6 +148,14 @@ config CLK_QORIQ - This adds the clock driver support for Freescale QorIQ platforms - using common clock framework. - -+config COMMON_CLK_DGLNT_DYNCLK -+ tristate "Digilent axi_dynclk Driver" -+ depends on ARCH_ZYNQ || MICROBLAZE -+ help -+ ---help--- -+ Support for the Digilent AXI Dynamic Clock core for Xilinx -+ FPGAs. -+ - config COMMON_CLK_XGENE - bool "Clock driver for APM XGene SoC" - default y -diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index 0760449dde..45ce97d053 100644 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o - obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o - obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o - obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o -+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o - obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o - obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o - obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o -diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c -new file mode 100644 -index 0000000000..496ad5fc90 ---- /dev/null -+++ b/drivers/clk/clk-dglnt-dynclk.c -@@ -0,0 +1,547 @@ -+/* -+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLK_BIT_WEDGE 13 -+#define CLK_BIT_NOCOUNT 12 -+ -+/* This value is used to signal an error */ -+#define ERR_CLKCOUNTCALC 0xFFFFFFFF -+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) -+ -+#define DYNCLK_DIV_1_REGMASK 0x1041 -+/* 25 MHz (125 KHz / 5) */ -+#define DYNCLK_DEFAULT_FREQ 125000 -+ -+#define MMCM_FREQ_VCOMIN 600000 -+#define MMCM_FREQ_VCOMAX 1200000 -+#define MMCM_FREQ_PFDMIN 10000 -+#define MMCM_FREQ_PFDMAX 450000 -+#define MMCM_FREQ_OUTMIN 4000 -+#define MMCM_FREQ_OUTMAX 800000 -+#define MMCM_DIV_MAX 106 -+#define MMCM_FB_MIN 2 -+#define MMCM_FB_MAX 64 -+#define MMCM_CLKDIV_MAX 128 -+#define MMCM_CLKDIV_MIN 1 -+ -+#define OFST_DISPLAY_CTRL 0x0 -+#define OFST_DISPLAY_STATUS 0x4 -+#define OFST_DISPLAY_CLK_L 0x8 -+#define OFST_DISPLAY_FB_L 0x0C -+#define OFST_DISPLAY_FB_H_CLK_H 0x10 -+#define OFST_DISPLAY_DIV 0x14 -+#define OFST_DISPLAY_LOCK_L 0x18 -+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C -+ -+static const u64 lock_lookup[64] = { -+ 0b0011000110111110100011111010010000000001, -+ 0b0011000110111110100011111010010000000001, -+ 0b0100001000111110100011111010010000000001, -+ 0b0101101011111110100011111010010000000001, -+ 0b0111001110111110100011111010010000000001, -+ 0b1000110001111110100011111010010000000001, -+ 0b1001110011111110100011111010010000000001, -+ 0b1011010110111110100011111010010000000001, -+ 0b1100111001111110100011111010010000000001, -+ 0b1110011100111110100011111010010000000001, -+ 0b1111111111111000010011111010010000000001, -+ 0b1111111111110011100111111010010000000001, -+ 0b1111111111101110111011111010010000000001, -+ 0b1111111111101011110011111010010000000001, -+ 0b1111111111101000101011111010010000000001, -+ 0b1111111111100111000111111010010000000001, -+ 0b1111111111100011111111111010010000000001, -+ 0b1111111111100010011011111010010000000001, -+ 0b1111111111100000110111111010010000000001, -+ 0b1111111111011111010011111010010000000001, -+ 0b1111111111011101101111111010010000000001, -+ 0b1111111111011100001011111010010000000001, -+ 0b1111111111011010100111111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111010111011111111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001 -+}; -+ -+static const u32 filter_lookup_low[64] = { -+ 0b0001011111, -+ 0b0001010111, -+ 0b0001111011, -+ 0b0001011011, -+ 0b0001101011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0010110011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011 -+}; -+ -+struct dglnt_dynclk_reg; -+struct dglnt_dynclk_mode; -+struct dglnt_dynclk; -+ -+struct dglnt_dynclk_reg { -+ u32 clk0L; -+ u32 clkFBL; -+ u32 clkFBH_clk0H; -+ u32 divclk; -+ u32 lockL; -+ u32 fltr_lockH; -+}; -+ -+struct dglnt_dynclk_mode { -+ u32 freq; -+ u32 fbmult; -+ u32 clkdiv; -+ u32 maindiv; -+}; -+ -+struct dglnt_dynclk { -+ void __iomem *base; -+ struct clk_hw clk_hw; -+ unsigned long freq; -+}; -+ -+u32 dglnt_dynclk_divider(u32 divide) -+{ -+ u32 output = 0; -+ u32 highTime = 0; -+ u32 lowTime = 0; -+ -+ if ((divide < 1) || (divide > 128)) -+ return ERR_CLKDIVIDER; -+ -+ if (divide == 1) -+ return DYNCLK_DIV_1_REGMASK; -+ -+ highTime = divide / 2; -+ /* if divide is odd */ -+ if (divide & 0x1) { -+ lowTime = highTime + 1; -+ output = 1 << CLK_BIT_WEDGE; -+ } else { -+ lowTime = highTime; -+ } -+ -+ output |= 0x03F & lowTime; -+ output |= 0xFC0 & (highTime << 6); -+ return output; -+} -+ -+u32 dglnt_dynclk_count_calc(u32 divide) -+{ -+ u32 output = 0; -+ u32 divCalc = 0; -+ -+ divCalc = dglnt_dynclk_divider(divide); -+ if (divCalc == ERR_CLKDIVIDER) -+ output = ERR_CLKCOUNTCALC; -+ else -+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); -+ return output; -+} -+ -+ -+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, -+ struct dglnt_dynclk_mode *clkParams) -+{ -+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) -+ return -EINVAL; -+ -+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); -+ if (regValues->clk0L == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); -+ if (regValues->clkFBL == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBH_clk0H = 0; -+ -+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); -+ if (regValues->divclk == ERR_CLKDIVIDER) -+ return -EINVAL; -+ -+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & -+ 0xFFFFFFFF); -+ -+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> -+ 32) & 0x000000FF); -+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << -+ 16) & 0x03FF0000); -+ -+ return 0; -+} -+ -+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, -+ void __iomem *baseaddr) -+{ -+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); -+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); -+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); -+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); -+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); -+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); -+} -+ -+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, -+ struct dglnt_dynclk_mode *bestPick) -+{ -+ u32 bestError = MMCM_FREQ_OUTMAX; -+ u32 curError; -+ u32 curClkMult; -+ u32 curFreq; -+ u32 divVal; -+ u32 curFb, curClkDiv; -+ u32 minFb = 0; -+ u32 maxFb = 0; -+ u32 curDiv = 1; -+ u32 maxDiv; -+ bool freq_found = false; -+ -+ bestPick->freq = 0; -+ if (parentFreq == 0) -+ return 0; -+ -+ /* minimum frequency is actually dictated by VCOmin */ -+ if (freq < MMCM_FREQ_OUTMIN) -+ freq = MMCM_FREQ_OUTMIN; -+ if (freq > MMCM_FREQ_OUTMAX) -+ freq = MMCM_FREQ_OUTMAX; -+ -+ if (parentFreq > MMCM_FREQ_PFDMAX) -+ curDiv = 2; -+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; -+ if (maxDiv > MMCM_DIV_MAX) -+ maxDiv = MMCM_DIV_MAX; -+ -+ while (curDiv <= maxDiv && !freq_found) { -+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); -+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); -+ if (maxFb > MMCM_FB_MAX) -+ maxFb = MMCM_FB_MAX; -+ if (minFb < MMCM_FB_MIN) -+ minFb = MMCM_FB_MIN; -+ -+ divVal = curDiv * freq; -+ /* -+ * This multiplier is used to find the best clkDiv value for -+ * each FB value -+ */ -+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; -+ -+ curFb = minFb; -+ while (curFb <= maxFb && !freq_found) { -+ curClkDiv = ((curClkMult * curFb) + 500) / 1000; -+ if (curClkDiv > MMCM_CLKDIV_MAX) -+ curClkDiv = MMCM_CLKDIV_MAX; -+ if (curClkDiv < MMCM_CLKDIV_MIN) -+ curClkDiv = MMCM_CLKDIV_MIN; -+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); -+ if (curFreq >= freq) -+ curError = curFreq - freq; -+ else -+ curError = freq - curFreq; -+ if (curError < bestError) { -+ bestError = curError; -+ bestPick->clkdiv = curClkDiv; -+ bestPick->fbmult = curFb; -+ bestPick->maindiv = curDiv; -+ bestPick->freq = curFreq; -+ } -+ if (!curError) -+ freq_found = true; -+ curFb++; -+ } -+ curDiv++; -+ } -+ return bestPick->freq; -+} -+ -+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) -+{ -+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); -+} -+ -+ -+static int dglnt_dynclk_enable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ unsigned int clock_state; -+ -+ if (dglnt_dynclk->freq) { -+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+ do { -+ clock_state = readl(dglnt_dynclk->base + -+ OFST_DISPLAY_STATUS); -+ } while (!clock_state); -+ } -+ return 0; -+} -+ -+static void dglnt_dynclk_disable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+} -+ -+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, -+ unsigned long rate, unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ struct dglnt_dynclk_reg clkReg; -+ struct dglnt_dynclk_mode clkMode; -+ -+ if (parent_rate == 0 || rate == 0) -+ return -EINVAL; -+ if (rate == dglnt_dynclk->freq) -+ return 0; -+ -+ /* -+ * Convert from Hz to KHz, then multiply by five to account for -+ * BUFR division -+ */ -+ rate = (rate + 100) / 200; -+ /* convert from Hz to KHz */ -+ parent_rate = (parent_rate + 500) / 1000; -+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) -+ return -EINVAL; -+ -+ /* -+ * Write to the PLL dynamic configuration registers to configure it -+ * with the calculated parameters. -+ */ -+ dglnt_dynclk_find_reg(&clkReg, &clkMode); -+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); -+ dglnt_dynclk->freq = clkMode.freq * 200; -+ dglnt_dynclk_disable(clk_hw); -+ dglnt_dynclk_enable(clk_hw); -+ -+ return 0; -+} -+ -+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ struct dglnt_dynclk_mode clkMode; -+ -+ dglnt_dynclk_find_mode(((rate + 100) / 200), -+ ((*parent_rate) + 500) / 1000, &clkMode); -+ -+ return (clkMode.freq * 200); -+} -+ -+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, -+ unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ return dglnt_dynclk->freq; -+} -+ -+ -+static const struct clk_ops dglnt_dynclk_ops = { -+ .recalc_rate = dglnt_dynclk_recalc_rate, -+ .round_rate = dglnt_dynclk_round_rate, -+ .set_rate = dglnt_dynclk_set_rate, -+ .enable = dglnt_dynclk_enable, -+ .disable = dglnt_dynclk_disable, -+}; -+ -+static const struct of_device_id dglnt_dynclk_ids[] = { -+ { .compatible = "digilent,axi-dynclk", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); -+ -+static int dglnt_dynclk_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *id; -+ struct dglnt_dynclk *dglnt_dynclk; -+ struct clk_init_data init; -+ const char *parent_name; -+ const char *clk_name; -+ struct resource *mem; -+ struct clk *clk; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); -+ if (!id) -+ return -ENODEV; -+ -+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), -+ GFP_KERNEL); -+ if (!dglnt_dynclk) -+ return -ENOMEM; -+ -+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); -+ if (IS_ERR(dglnt_dynclk->base)) -+ return PTR_ERR(dglnt_dynclk->base); -+ -+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); -+ if (!parent_name) -+ return -EINVAL; -+ -+ clk_name = pdev->dev.of_node->name; -+ of_property_read_string(pdev->dev.of_node, "clock-output-names", -+ &clk_name); -+ -+ init.name = clk_name; -+ init.ops = &dglnt_dynclk_ops; -+ init.flags = 0; -+ init.parent_names = &parent_name; -+ init.num_parents = 1; -+ -+ dglnt_dynclk->freq = 0; -+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); -+ -+ dglnt_dynclk->clk_hw.init = &init; -+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, -+ clk); -+} -+ -+static int dglnt_dynclk_remove(struct platform_device *pdev) -+{ -+ of_clk_del_provider(pdev->dev.of_node); -+ -+ return 0; -+} -+ -+static struct platform_driver dglnt_dynclk_driver = { -+ .driver = { -+ .name = "dglnt-dynclk", -+ .owner = THIS_MODULE, -+ .of_match_table = dglnt_dynclk_ids, -+ }, -+ .probe = dglnt_dynclk_probe, -+ .remove = dglnt_dynclk_remove, -+}; -+module_platform_driver(dglnt_dynclk_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Sam Bobrowicz "); -+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch deleted file mode 100644 index a98d84c5..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 -From: Nathan Rossi -Date: Mon, 2 May 2016 23:46:42 +1000 -Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on - -Fix the issues where the VTC is reset (losing its timing config). - -Also fix the issue where the plane destroys its DMA descriptors and -marks the DMA channels as inactive but never recreates the descriptors -and never updates the active state when turning DPMS back on. - -Signed-off-by: Nathan Rossi -Upstream-Status: Pending [This is a workaround] ---- - drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - - drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -index 631d35b921..93dbd4b58a 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) - default: - if (crtc->vtc) { - xilinx_vtc_disable(crtc->vtc); -- xilinx_vtc_reset(crtc->vtc); - } - if (crtc->cresample) { - xilinx_cresample_disable(crtc->cresample); -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -index 6a248b72d4..d2518a4bdf 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { - struct xilinx_drm_plane_dma *dma = &plane->dma[i]; - -- if (dma->chan && dma->is_active) { -+ if (dma->chan) { - flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; - desc = dmaengine_prep_interleaved_dma(dma->chan, - &dma->xt, -@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - dmaengine_submit(desc); - - dma_async_issue_pending(dma->chan); -+ dma->is_active = true; - } - } - } --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg deleted file mode 100644 index f71e53ab..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# -# Bluetooth config -# -CONFIG_BT=y -CONFIG_BT_BREDR=y -CONFIG_BT_HS=y -CONFIG_BT_LE=y -CONFIG_BT_BCM=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HIDP=y -CONFIG_CFG80211=y -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_CRDA_SUPPORT=y -CONFIG_BRCMUTIL=y -CONFIG_BRCMFMAC=y -CONFIG_BRCMFMAC_PROTO_BCDC=y -CONFIG_BRCMFMAC_SDIO=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_SHA256=y - -# -# Regulator config -# -CONFIG_REGMAP_IRQ=y -CONFIG_I2C_XILINX=y -CONFIG_MFD_DA9062=y -CONFIG_REGULATOR_DA9062=y - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch new file mode 100644 index 00000000..660bc218 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch @@ -0,0 +1,305 @@ +From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:14:13 +1000 +Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards + +Add the dglnt_encoder driver that enables DRM support for the VGA and +HDMI output ports found on many Digilent boards. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ + drivers/gpu/drm/xilinx/Kconfig | 6 + + drivers/gpu/drm/xilinx/Makefile | 1 + + drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ + 4 files changed, 247 insertions(+) + create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt + create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c + +diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +new file mode 100644 +index 0000000..242b24e +--- /dev/null ++++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +@@ -0,0 +1,23 @@ ++Device-Tree bindings for Digilent DRM Encoder Slave ++ ++This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. ++The VGA or HDMI port must be connected to a Xilinx display pipeline via an ++axi2vid IP core. ++ ++Required properties: ++ - compatible: Should be "digilent,drm-encoder". ++ ++Optional properties: ++ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video ++ connector. This is used to obtain the supported resolutions ++ of an attached monitor. If not defined, then a default ++ set of resolutions is used and the display will initialize ++ to 720p. Note most VGA connectors on Digilent boards do ++ not have the DDC bus routed out. ++ ++Example: ++ ++ encoder_0: digilent_encoder { ++ compatible = "digilent,drm-encoder"; ++ dglnt,edid-i2c = <&i2c1>; ++ }; +diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig +index 57e18a9..d9ecff2 100644 +--- a/drivers/gpu/drm/xilinx/Kconfig ++++ b/drivers/gpu/drm/xilinx/Kconfig +@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB + help + DRM driver for Xilinx Display Port Subsystem. + ++config DRM_DIGILENT_ENCODER ++ tristate "Digilent VGA/HDMI DRM Encoder Driver" ++ depends on DRM_XILINX ++ help ++ DRM slave encoder for Video-out on Digilent boards. ++ + config DRM_XILINX_DP_SUB_DEBUG_FS + bool "Xilinx DRM DPSUB debugfs" + depends on DEBUG_FS && DRM_XILINX_DP_SUB +diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile +index 19bc154..c2717e40 100644 +--- a/drivers/gpu/drm/xilinx/Makefile ++++ b/drivers/gpu/drm/xilinx/Makefile +@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ + xilinx_drm_plane.o + xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o + ++obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o + obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o + obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o + obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o +diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c +new file mode 100644 +index 0000000..cb9fc7d +--- /dev/null ++++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c +@@ -0,0 +1,217 @@ ++/* ++ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. ++ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DGLNT_ENC_MAX_FREQ 150000 ++#define DGLNT_ENC_MAX_H 1920 ++#define DGLNT_ENC_MAX_V 1080 ++#define DGLNT_ENC_PREF_H 1280 ++#define DGLNT_ENC_PREF_V 720 ++ ++struct dglnt_encoder { ++ struct drm_encoder *encoder; ++ struct i2c_adapter *i2c_bus; ++ bool i2c_present; ++}; ++ ++static inline struct dglnt_encoder *to_dglnt_encoder( ++ struct drm_encoder *encoder) ++{ ++ return to_encoder_slave(encoder)->slave_priv; ++} ++ ++static bool dglnt_mode_fixup(struct drm_encoder *encoder, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++static void dglnt_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++} ++ ++static void ++dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) ++{ ++} ++ ++static void dglnt_encoder_save(struct drm_encoder *encoder) ++{ ++} ++ ++static void dglnt_encoder_restore(struct drm_encoder *encoder) ++{ ++} ++ ++static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, ++ struct drm_display_mode *mode) ++{ ++ if (mode && ++ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | ++ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && ++ (mode->clock <= DGLNT_ENC_MAX_FREQ) && ++ (mode->hdisplay <= DGLNT_ENC_MAX_H) && ++ (mode->vdisplay <= DGLNT_ENC_MAX_V)) ++ return MODE_OK; ++ return MODE_BAD; ++} ++ ++static int dglnt_encoder_get_modes(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ struct edid *edid; ++ int num_modes = 0; ++ ++ if (dglnt->i2c_present) { ++ edid = drm_get_edid(connector, dglnt->i2c_bus); ++ drm_connector_update_edid_property(connector, edid); ++ if (edid) { ++ num_modes = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ } else { ++ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, ++ DGLNT_ENC_MAX_V); ++ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, ++ DGLNT_ENC_PREF_V); ++ } ++ return num_modes; ++} ++ ++static enum drm_connector_status dglnt_encoder_detect( ++ struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ ++ if (dglnt->i2c_present) { ++ if (drm_probe_ddc(dglnt->i2c_bus)) ++ return connector_status_connected; ++ return connector_status_disconnected; ++ } else ++ return connector_status_unknown; ++} ++ ++static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { ++ .dpms = dglnt_encoder_dpms, ++ .save = dglnt_encoder_save, ++ .restore = dglnt_encoder_restore, ++ .mode_fixup = dglnt_mode_fixup, ++ .mode_valid = dglnt_encoder_mode_valid, ++ .mode_set = dglnt_encoder_mode_set, ++ .detect = dglnt_encoder_detect, ++ .get_modes = dglnt_encoder_get_modes, ++}; ++ ++static int dglnt_encoder_encoder_init(struct platform_device *pdev, ++ struct drm_device *dev, ++ struct drm_encoder_slave *encoder) ++{ ++ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); ++ struct device_node *sub_node; ++ ++ encoder->slave_priv = dglnt; ++ encoder->slave_funcs = &dglnt_encoder_slave_funcs; ++ ++ dglnt->encoder = &encoder->base; ++ ++ /* get i2c adapter for edid */ ++ dglnt->i2c_present = false; ++ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); ++ if (sub_node) { ++ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); ++ if (!dglnt->i2c_bus) ++ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); ++ else ++ dglnt->i2c_present = true; ++ of_node_put(sub_node); ++ } ++ ++ return 0; ++} ++ ++static int dglnt_encoder_probe(struct platform_device *pdev) ++{ ++ struct dglnt_encoder *dglnt; ++ ++ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); ++ if (!dglnt) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, dglnt); ++ ++ return 0; ++} ++ ++static int dglnt_encoder_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static const struct of_device_id dglnt_encoder_of_match[] = { ++ { .compatible = "digilent,drm-encoder", }, ++ { /* end of table */ }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); ++ ++static struct drm_platform_encoder_driver dglnt_encoder_driver = { ++ .platform_driver = { ++ .probe = dglnt_encoder_probe, ++ .remove = dglnt_encoder_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "dglnt-drm-enc", ++ .of_match_table = dglnt_encoder_of_match, ++ }, ++ }, ++ ++ .encoder_init = dglnt_encoder_encoder_init, ++}; ++ ++static int __init dglnt_encoder_init(void) ++{ ++ return platform_driver_register(&dglnt_encoder_driver.platform_driver); ++} ++ ++static void __exit dglnt_encoder_exit(void) ++{ ++ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); ++} ++ ++module_init(dglnt_encoder_init); ++module_exit(dglnt_encoder_exit); ++ ++MODULE_AUTHOR("Digilent, Inc."); ++MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); ++MODULE_LICENSE("GPL v2"); +-- +2.7.4 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch new file mode 100644 index 00000000..9b6229db --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch @@ -0,0 +1,607 @@ +From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:16:06 +1000 +Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core + +Add support for the axi_dynclk IP Core available from Digilent. This IP +core dynamically configures the clock resources inside a Xilinx FPGA to +generate a clock with a software programmable frequency. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + drivers/clk/Kconfig | 8 + + drivers/clk/Makefile | 1 + + drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 556 insertions(+) + create mode 100644 drivers/clk/clk-dglnt-dynclk.c + +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index dccb111100..7fe65a702b 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -148,6 +148,14 @@ config CLK_QORIQ + This adds the clock driver support for Freescale QorIQ platforms + using common clock framework. + ++config COMMON_CLK_DGLNT_DYNCLK ++ tristate "Digilent axi_dynclk Driver" ++ depends on ARCH_ZYNQ || MICROBLAZE ++ help ++ ---help--- ++ Support for the Digilent AXI Dynamic Clock core for Xilinx ++ FPGAs. ++ + config COMMON_CLK_XGENE + bool "Clock driver for APM XGene SoC" + default y +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index 0760449dde..45ce97d053 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o + obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o ++obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o + obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o + obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o + obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c +new file mode 100644 +index 0000000000..496ad5fc90 +--- /dev/null ++++ b/drivers/clk/clk-dglnt-dynclk.c +@@ -0,0 +1,547 @@ ++/* ++ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLK_BIT_WEDGE 13 ++#define CLK_BIT_NOCOUNT 12 ++ ++/* This value is used to signal an error */ ++#define ERR_CLKCOUNTCALC 0xFFFFFFFF ++#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) ++ ++#define DYNCLK_DIV_1_REGMASK 0x1041 ++/* 25 MHz (125 KHz / 5) */ ++#define DYNCLK_DEFAULT_FREQ 125000 ++ ++#define MMCM_FREQ_VCOMIN 600000 ++#define MMCM_FREQ_VCOMAX 1200000 ++#define MMCM_FREQ_PFDMIN 10000 ++#define MMCM_FREQ_PFDMAX 450000 ++#define MMCM_FREQ_OUTMIN 4000 ++#define MMCM_FREQ_OUTMAX 800000 ++#define MMCM_DIV_MAX 106 ++#define MMCM_FB_MIN 2 ++#define MMCM_FB_MAX 64 ++#define MMCM_CLKDIV_MAX 128 ++#define MMCM_CLKDIV_MIN 1 ++ ++#define OFST_DISPLAY_CTRL 0x0 ++#define OFST_DISPLAY_STATUS 0x4 ++#define OFST_DISPLAY_CLK_L 0x8 ++#define OFST_DISPLAY_FB_L 0x0C ++#define OFST_DISPLAY_FB_H_CLK_H 0x10 ++#define OFST_DISPLAY_DIV 0x14 ++#define OFST_DISPLAY_LOCK_L 0x18 ++#define OFST_DISPLAY_FLTR_LOCK_H 0x1C ++ ++static const u64 lock_lookup[64] = { ++ 0b0011000110111110100011111010010000000001, ++ 0b0011000110111110100011111010010000000001, ++ 0b0100001000111110100011111010010000000001, ++ 0b0101101011111110100011111010010000000001, ++ 0b0111001110111110100011111010010000000001, ++ 0b1000110001111110100011111010010000000001, ++ 0b1001110011111110100011111010010000000001, ++ 0b1011010110111110100011111010010000000001, ++ 0b1100111001111110100011111010010000000001, ++ 0b1110011100111110100011111010010000000001, ++ 0b1111111111111000010011111010010000000001, ++ 0b1111111111110011100111111010010000000001, ++ 0b1111111111101110111011111010010000000001, ++ 0b1111111111101011110011111010010000000001, ++ 0b1111111111101000101011111010010000000001, ++ 0b1111111111100111000111111010010000000001, ++ 0b1111111111100011111111111010010000000001, ++ 0b1111111111100010011011111010010000000001, ++ 0b1111111111100000110111111010010000000001, ++ 0b1111111111011111010011111010010000000001, ++ 0b1111111111011101101111111010010000000001, ++ 0b1111111111011100001011111010010000000001, ++ 0b1111111111011010100111111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111010111011111111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001 ++}; ++ ++static const u32 filter_lookup_low[64] = { ++ 0b0001011111, ++ 0b0001010111, ++ 0b0001111011, ++ 0b0001011011, ++ 0b0001101011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0010110011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011 ++}; ++ ++struct dglnt_dynclk_reg; ++struct dglnt_dynclk_mode; ++struct dglnt_dynclk; ++ ++struct dglnt_dynclk_reg { ++ u32 clk0L; ++ u32 clkFBL; ++ u32 clkFBH_clk0H; ++ u32 divclk; ++ u32 lockL; ++ u32 fltr_lockH; ++}; ++ ++struct dglnt_dynclk_mode { ++ u32 freq; ++ u32 fbmult; ++ u32 clkdiv; ++ u32 maindiv; ++}; ++ ++struct dglnt_dynclk { ++ void __iomem *base; ++ struct clk_hw clk_hw; ++ unsigned long freq; ++}; ++ ++u32 dglnt_dynclk_divider(u32 divide) ++{ ++ u32 output = 0; ++ u32 highTime = 0; ++ u32 lowTime = 0; ++ ++ if ((divide < 1) || (divide > 128)) ++ return ERR_CLKDIVIDER; ++ ++ if (divide == 1) ++ return DYNCLK_DIV_1_REGMASK; ++ ++ highTime = divide / 2; ++ /* if divide is odd */ ++ if (divide & 0x1) { ++ lowTime = highTime + 1; ++ output = 1 << CLK_BIT_WEDGE; ++ } else { ++ lowTime = highTime; ++ } ++ ++ output |= 0x03F & lowTime; ++ output |= 0xFC0 & (highTime << 6); ++ return output; ++} ++ ++u32 dglnt_dynclk_count_calc(u32 divide) ++{ ++ u32 output = 0; ++ u32 divCalc = 0; ++ ++ divCalc = dglnt_dynclk_divider(divide); ++ if (divCalc == ERR_CLKDIVIDER) ++ output = ERR_CLKCOUNTCALC; ++ else ++ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); ++ return output; ++} ++ ++ ++int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, ++ struct dglnt_dynclk_mode *clkParams) ++{ ++ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) ++ return -EINVAL; ++ ++ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); ++ if (regValues->clk0L == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); ++ if (regValues->clkFBL == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBH_clk0H = 0; ++ ++ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); ++ if (regValues->divclk == ERR_CLKDIVIDER) ++ return -EINVAL; ++ ++ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & ++ 0xFFFFFFFF); ++ ++ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> ++ 32) & 0x000000FF); ++ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << ++ 16) & 0x03FF0000); ++ ++ return 0; ++} ++ ++void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, ++ void __iomem *baseaddr) ++{ ++ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); ++ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); ++ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); ++ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); ++ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); ++ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); ++} ++ ++u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, ++ struct dglnt_dynclk_mode *bestPick) ++{ ++ u32 bestError = MMCM_FREQ_OUTMAX; ++ u32 curError; ++ u32 curClkMult; ++ u32 curFreq; ++ u32 divVal; ++ u32 curFb, curClkDiv; ++ u32 minFb = 0; ++ u32 maxFb = 0; ++ u32 curDiv = 1; ++ u32 maxDiv; ++ bool freq_found = false; ++ ++ bestPick->freq = 0; ++ if (parentFreq == 0) ++ return 0; ++ ++ /* minimum frequency is actually dictated by VCOmin */ ++ if (freq < MMCM_FREQ_OUTMIN) ++ freq = MMCM_FREQ_OUTMIN; ++ if (freq > MMCM_FREQ_OUTMAX) ++ freq = MMCM_FREQ_OUTMAX; ++ ++ if (parentFreq > MMCM_FREQ_PFDMAX) ++ curDiv = 2; ++ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; ++ if (maxDiv > MMCM_DIV_MAX) ++ maxDiv = MMCM_DIV_MAX; ++ ++ while (curDiv <= maxDiv && !freq_found) { ++ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); ++ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); ++ if (maxFb > MMCM_FB_MAX) ++ maxFb = MMCM_FB_MAX; ++ if (minFb < MMCM_FB_MIN) ++ minFb = MMCM_FB_MIN; ++ ++ divVal = curDiv * freq; ++ /* ++ * This multiplier is used to find the best clkDiv value for ++ * each FB value ++ */ ++ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; ++ ++ curFb = minFb; ++ while (curFb <= maxFb && !freq_found) { ++ curClkDiv = ((curClkMult * curFb) + 500) / 1000; ++ if (curClkDiv > MMCM_CLKDIV_MAX) ++ curClkDiv = MMCM_CLKDIV_MAX; ++ if (curClkDiv < MMCM_CLKDIV_MIN) ++ curClkDiv = MMCM_CLKDIV_MIN; ++ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); ++ if (curFreq >= freq) ++ curError = curFreq - freq; ++ else ++ curError = freq - curFreq; ++ if (curError < bestError) { ++ bestError = curError; ++ bestPick->clkdiv = curClkDiv; ++ bestPick->fbmult = curFb; ++ bestPick->maindiv = curDiv; ++ bestPick->freq = curFreq; ++ } ++ if (!curError) ++ freq_found = true; ++ curFb++; ++ } ++ curDiv++; ++ } ++ return bestPick->freq; ++} ++ ++static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) ++{ ++ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); ++} ++ ++ ++static int dglnt_dynclk_enable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ unsigned int clock_state; ++ ++ if (dglnt_dynclk->freq) { ++ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++ do { ++ clock_state = readl(dglnt_dynclk->base + ++ OFST_DISPLAY_STATUS); ++ } while (!clock_state); ++ } ++ return 0; ++} ++ ++static void dglnt_dynclk_disable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++} ++ ++static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ struct dglnt_dynclk_reg clkReg; ++ struct dglnt_dynclk_mode clkMode; ++ ++ if (parent_rate == 0 || rate == 0) ++ return -EINVAL; ++ if (rate == dglnt_dynclk->freq) ++ return 0; ++ ++ /* ++ * Convert from Hz to KHz, then multiply by five to account for ++ * BUFR division ++ */ ++ rate = (rate + 100) / 200; ++ /* convert from Hz to KHz */ ++ parent_rate = (parent_rate + 500) / 1000; ++ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) ++ return -EINVAL; ++ ++ /* ++ * Write to the PLL dynamic configuration registers to configure it ++ * with the calculated parameters. ++ */ ++ dglnt_dynclk_find_reg(&clkReg, &clkMode); ++ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); ++ dglnt_dynclk->freq = clkMode.freq * 200; ++ dglnt_dynclk_disable(clk_hw); ++ dglnt_dynclk_enable(clk_hw); ++ ++ return 0; ++} ++ ++static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct dglnt_dynclk_mode clkMode; ++ ++ dglnt_dynclk_find_mode(((rate + 100) / 200), ++ ((*parent_rate) + 500) / 1000, &clkMode); ++ ++ return (clkMode.freq * 200); ++} ++ ++static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, ++ unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ return dglnt_dynclk->freq; ++} ++ ++ ++static const struct clk_ops dglnt_dynclk_ops = { ++ .recalc_rate = dglnt_dynclk_recalc_rate, ++ .round_rate = dglnt_dynclk_round_rate, ++ .set_rate = dglnt_dynclk_set_rate, ++ .enable = dglnt_dynclk_enable, ++ .disable = dglnt_dynclk_disable, ++}; ++ ++static const struct of_device_id dglnt_dynclk_ids[] = { ++ { .compatible = "digilent,axi-dynclk", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); ++ ++static int dglnt_dynclk_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct dglnt_dynclk *dglnt_dynclk; ++ struct clk_init_data init; ++ const char *parent_name; ++ const char *clk_name; ++ struct resource *mem; ++ struct clk *clk; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); ++ if (!id) ++ return -ENODEV; ++ ++ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), ++ GFP_KERNEL); ++ if (!dglnt_dynclk) ++ return -ENOMEM; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); ++ if (IS_ERR(dglnt_dynclk->base)) ++ return PTR_ERR(dglnt_dynclk->base); ++ ++ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); ++ if (!parent_name) ++ return -EINVAL; ++ ++ clk_name = pdev->dev.of_node->name; ++ of_property_read_string(pdev->dev.of_node, "clock-output-names", ++ &clk_name); ++ ++ init.name = clk_name; ++ init.ops = &dglnt_dynclk_ops; ++ init.flags = 0; ++ init.parent_names = &parent_name; ++ init.num_parents = 1; ++ ++ dglnt_dynclk->freq = 0; ++ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); ++ ++ dglnt_dynclk->clk_hw.init = &init; ++ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, ++ clk); ++} ++ ++static int dglnt_dynclk_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver dglnt_dynclk_driver = { ++ .driver = { ++ .name = "dglnt-dynclk", ++ .owner = THIS_MODULE, ++ .of_match_table = dglnt_dynclk_ids, ++ }, ++ .probe = dglnt_dynclk_probe, ++ .remove = dglnt_dynclk_remove, ++}; ++module_platform_driver(dglnt_dynclk_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Sam Bobrowicz "); ++MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch new file mode 100644 index 00000000..a98d84c5 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch @@ -0,0 +1,54 @@ +From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 +From: Nathan Rossi +Date: Mon, 2 May 2016 23:46:42 +1000 +Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on + +Fix the issues where the VTC is reset (losing its timing config). + +Also fix the issue where the plane destroys its DMA descriptors and +marks the DMA channels as inactive but never recreates the descriptors +and never updates the active state when turning DPMS back on. + +Signed-off-by: Nathan Rossi +Upstream-Status: Pending [This is a workaround] +--- + drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - + drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +index 631d35b921..93dbd4b58a 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) + default: + if (crtc->vtc) { + xilinx_vtc_disable(crtc->vtc); +- xilinx_vtc_reset(crtc->vtc); + } + if (crtc->cresample) { + xilinx_cresample_disable(crtc->cresample); +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +index 6a248b72d4..d2518a4bdf 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { + struct xilinx_drm_plane_dma *dma = &plane->dma[i]; + +- if (dma->chan && dma->is_active) { ++ if (dma->chan) { + flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + desc = dmaengine_prep_interleaved_dma(dma->chan, + &dma->xt, +@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + dmaengine_submit(desc); + + dma_async_issue_pending(dma->chan); ++ dma->is_active = true; + } + } + } +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0004-minized-wifi-bluetooth.cfg new file mode 100644 index 00000000..f71e53ab --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.2/0004-minized-wifi-bluetooth.cfg @@ -0,0 +1,33 @@ +# +# Bluetooth config +# +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_BCM=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HIDP=y +CONFIG_CFG80211=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_BRCMUTIL=y +CONFIG_BRCMFMAC=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA256=y + +# +# Regulator config +# +CONFIG_REGMAP_IRQ=y +CONFIG_I2C_XILINX=y +CONFIG_MFD_DA9062=y +CONFIG_REGULATOR_DA9062=y + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend deleted file mode 100644 index 2ce919ac..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" - -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ - file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ - file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ - " - -SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend new file mode 100644 index 00000000..2ce919ac --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" + +SRC_URI:append:zybo-linux-bd-zynq7 = " \ + file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ + file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ + file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ + " + +SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-core/README.qemu.md b/meta-xilinx-core/README.qemu.md index d0040b09..d3a02a90 100644 --- a/meta-xilinx-core/README.qemu.md +++ b/meta-xilinx-core/README.qemu.md @@ -12,7 +12,7 @@ to make this available: pmu-rom-native. The license on the software is Xilinx proprietary, so you may be required to enable the approprate LICENSE_FLAGS_WHITELIST to trigger the download. The license itself is available within the download at the URL referred to in -meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.1.bb. +meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.2.bb. Add the following to your local.conf to acknowledge you accept the proprietary xilinx license. diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf index 8588b988..bb2c5de7 100644 --- a/meta-xilinx-core/conf/layer.conf +++ b/meta-xilinx-core/conf/layer.conf @@ -42,6 +42,6 @@ SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS += " \ *->xserver-xorg \ " -XILINX_RELEASE_VERSION = "v2022.1" +XILINX_RELEASE_VERSION = "v2022.2" HOSTTOOLS += "xxd" diff --git a/meta-xilinx-core/conf/local.conf.sample b/meta-xilinx-core/conf/local.conf.sample index a7173fb8..b907b072 100644 --- a/meta-xilinx-core/conf/local.conf.sample +++ b/meta-xilinx-core/conf/local.conf.sample @@ -206,11 +206,11 @@ BB_DISKMON_DIRS ??= "\ #file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \ #file://.* file:///some/local/dir/sstate/PATH" -XILINX_VER_MAIN = "2022.1" +XILINX_VER_MAIN = "2022.2" # Uncomment below lines to provide path for custom xsct trim # -#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2022.1_xsct_daily_latest" +#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2022.2_xsct_daily_latest" #VALIDATE_XSCT_CHECKSUM = '0' # diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb deleted file mode 100644 index 34008ea5..00000000 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb +++ /dev/null @@ -1,8 +0,0 @@ -ATF_VERSION = "2.6" -SRCREV = "e678d5ddc475f34dea8f5004fb6ebde118621784" -BRANCH = "xlnx_rebase_v2.6" -LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" - - -include arm-trusted-firmware.inc - diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb new file mode 100644 index 00000000..34008ea5 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -0,0 +1,8 @@ +ATF_VERSION = "2.6" +SRCREV = "e678d5ddc475f34dea8f5004fb6ebde118621784" +BRANCH = "xlnx_rebase_v2.6" +LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" + + +include arm-trusted-firmware.inc + diff --git a/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.1.bb b/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.1.bb deleted file mode 100644 index 44ad9368..00000000 --- a/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.1.bb +++ /dev/null @@ -1,27 +0,0 @@ -SUMMARY = "PMU ROM for QEMU" -DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation" -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -LICENSE = "Proprietary" -LICENSE_FLAGS = "xilinx" -LIC_FILES_CHKSUM = "file://PMU_ROM-LICENSE.txt;md5=d43d49bc1eb1c907fc6f4ea75abafdfc" - -SRC_URI = "https://www.xilinx.com/bin/public/openDownload?filename=PMU_ROM.tar.gz" -SRC_URI[sha256sum] = "f9a450ef960979463ea0a87a35fafb4a5b62d3a741de30cbcef04c8edc22a7cf" - -S = "${WORKDIR}/PMU_ROM" - -inherit deploy native - -INHIBIT_DEFAULT_DEPS = "1" - -do_configure[noexec] = "1" -do_compile[noexec] = "1" -do_install[noexec] = "1" - -do_deploy () { - install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf -} - -addtask deploy before do_build after do_install diff --git a/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.2.bb b/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.2.bb new file mode 100644 index 00000000..44ad9368 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom-native_2022.2.bb @@ -0,0 +1,27 @@ +SUMMARY = "PMU ROM for QEMU" +DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation" +HOMEPAGE = "http://www.xilinx.com" +SECTION = "bsp" + +LICENSE = "Proprietary" +LICENSE_FLAGS = "xilinx" +LIC_FILES_CHKSUM = "file://PMU_ROM-LICENSE.txt;md5=d43d49bc1eb1c907fc6f4ea75abafdfc" + +SRC_URI = "https://www.xilinx.com/bin/public/openDownload?filename=PMU_ROM.tar.gz" +SRC_URI[sha256sum] = "f9a450ef960979463ea0a87a35fafb4a5b62d3a741de30cbcef04c8edc22a7cf" + +S = "${WORKDIR}/PMU_ROM" + +inherit deploy native + +INHIBIT_DEFAULT_DEPS = "1" + +do_configure[noexec] = "1" +do_compile[noexec] = "1" +do_install[noexec] = "1" + +do_deploy () { + install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf +} + +addtask deploy before do_build after do_install diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb deleted file mode 100644 index c8b8c14c..00000000 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb +++ /dev/null @@ -1,19 +0,0 @@ -UBOOT_VERSION = "v2021.01" - -UBRANCH ?= "master" - -SRCREV = "6aca2a543eaa68f543c54a93cb1eed2f0bbaa96f" - -include u-boot-xlnx.inc -include u-boot-spl-zynq-init.inc - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" - -# u-boot-xlnx has support for these -HAS_PLATFORM_INIT ?= " \ - xilinx_zynqmp_virt_config \ - xilinx_zynq_virt_defconfig \ - xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ - " - diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb new file mode 100644 index 00000000..c8b8c14c --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -0,0 +1,19 @@ +UBOOT_VERSION = "v2021.01" + +UBRANCH ?= "master" + +SRCREV = "6aca2a543eaa68f543c54a93cb1eed2f0bbaa96f" + +include u-boot-xlnx.inc +include u-boot-spl-zynq-init.inc + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" + +# u-boot-xlnx has support for these +HAS_PLATFORM_INIT ?= " \ + xilinx_zynqmp_virt_config \ + xilinx_zynq_virt_defconfig \ + xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ + " + diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb deleted file mode 100644 index 2c8b3ffb..00000000 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb +++ /dev/null @@ -1,5 +0,0 @@ - -require qemu-devicetrees.inc - -BRANCH ?= "master" -SRCREV ?= "922daa6a36abd2392f9c31e3222f7a38d548e981" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb new file mode 100644 index 00000000..2c8b3ffb --- /dev/null +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -0,0 +1,5 @@ + +require qemu-devicetrees.inc + +BRANCH ?= "master" +SRCREV ?= "922daa6a36abd2392f9c31e3222f7a38d548e981" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.1.bb deleted file mode 100644 index 5e6c2d28..00000000 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.1.bb +++ /dev/null @@ -1,7 +0,0 @@ -require qemu-xilinx-native.inc -BPN = "qemu-xilinx" - -EXTRA_OECONF:append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent" - -PROVIDES = "qemu-native" -PACKAGECONFIG ??= "pie" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.2.bb new file mode 100644 index 00000000..5e6c2d28 --- /dev/null +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2022.2.bb @@ -0,0 +1,7 @@ +require qemu-xilinx-native.inc +BPN = "qemu-xilinx" + +EXTRA_OECONF:append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent" + +PROVIDES = "qemu-native" +PACKAGECONFIG ??= "pie" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.1.bb deleted file mode 100644 index f5b89f05..00000000 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.1.bb +++ /dev/null @@ -1,18 +0,0 @@ -require qemu-xilinx-native.inc - -EXTRA_OECONF:append = " --target-list=${@get_qemu_system_target_list(d)}" - -PACKAGECONFIG ??= "fdt alsa kvm pie" - -PACKAGECONFIG:remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}" - -DEPENDS += "pixman-native qemu-xilinx-native bison-native ninja-native meson-native" - -do_install:append() { - # The following is also installed by qemu-native - rm -f ${D}${datadir}/qemu/trace-events-all - rm -rf ${D}${datadir}/qemu/keymaps - rm -rf ${D}${datadir}/icons - rm -rf ${D}${includedir}/qemu-plugin.h -} - diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb new file mode 100644 index 00000000..f5b89f05 --- /dev/null +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb @@ -0,0 +1,18 @@ +require qemu-xilinx-native.inc + +EXTRA_OECONF:append = " --target-list=${@get_qemu_system_target_list(d)}" + +PACKAGECONFIG ??= "fdt alsa kvm pie" + +PACKAGECONFIG:remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}" + +DEPENDS += "pixman-native qemu-xilinx-native bison-native ninja-native meson-native" + +do_install:append() { + # The following is also installed by qemu-native + rm -f ${D}${datadir}/qemu/trace-events-all + rm -rf ${D}${datadir}/qemu/keymaps + rm -rf ${D}${datadir}/icons + rm -rf ${D}${includedir}/qemu-plugin.h +} + diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.1.bb deleted file mode 100644 index 4983b4df..00000000 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.1.bb +++ /dev/null @@ -1,17 +0,0 @@ -require recipes-devtools/qemu/qemu.inc -require qemu-xilinx.inc - -BBCLASSEXTEND = "nativesdk" - -RDEPENDS:${PN}:class-target += "bash" - -PROVIDES:class-nativesdk = "nativesdk-qemu" -RPROVIDES:${PN}:class-nativesdk = "nativesdk-qemu" - -EXTRA_OECONF:append:class-target = " --target-list=${@get_qemu_target_list(d)}" -EXTRA_OECONF:append:class-nativesdk = " --target-list=${@get_qemu_target_list(d)}" -EXTRA_OECONF:append:class-target:mipsarcho32 = "${@bb.utils.contains('BBEXTENDCURR', 'multilib', ' --disable-capstone', '', d)}" - -do_install:append:class-nativesdk() { - ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} -} diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.2.bb new file mode 100644 index 00000000..4983b4df --- /dev/null +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2022.2.bb @@ -0,0 +1,17 @@ +require recipes-devtools/qemu/qemu.inc +require qemu-xilinx.inc + +BBCLASSEXTEND = "nativesdk" + +RDEPENDS:${PN}:class-target += "bash" + +PROVIDES:class-nativesdk = "nativesdk-qemu" +RPROVIDES:${PN}:class-nativesdk = "nativesdk-qemu" + +EXTRA_OECONF:append:class-target = " --target-list=${@get_qemu_target_list(d)}" +EXTRA_OECONF:append:class-nativesdk = " --target-list=${@get_qemu_target_list(d)}" +EXTRA_OECONF:append:class-target:mipsarcho32 = "${@bb.utils.contains('BBEXTENDCURR', 'multilib', ' --disable-capstone', '', d)}" + +do_install:append:class-nativesdk() { + ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} +} diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb deleted file mode 100644 index c1cda51c..00000000 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb +++ /dev/null @@ -1,9 +0,0 @@ -LINUX_VERSION = "5.15" -KBRANCH="master" -SRCREV = "5296e6841df2b46132a9e5a3b7c5218f58486195" - -KCONF_AUDIT_LEVEL="0" - -include linux-xlnx.inc - -FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb new file mode 100644 index 00000000..c1cda51c --- /dev/null +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -0,0 +1,9 @@ +LINUX_VERSION = "5.15" +KBRANCH="master" +SRCREV = "5296e6841df2b46132a9e5a3b7c5218f58486195" + +KCONF_AUDIT_LEVEL="0" + +include linux-xlnx.inc + +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" diff --git a/meta-xilinx-standalone/conf/layer.conf b/meta-xilinx-standalone/conf/layer.conf index f7ebaca4..79997d24 100644 --- a/meta-xilinx-standalone/conf/layer.conf +++ b/meta-xilinx-standalone/conf/layer.conf @@ -16,4 +16,4 @@ LAYERDEPENDS_xilinx-standalone = "core xilinx" LAYERRECOMMENDS_xilinx-standalone = "xilinx-microblaze" LAYERSERIES_COMPAT_xilinx-standalone = "honister" -XILINX_RELEASE_VERSION = "v2022.1" +XILINX_RELEASE_VERSION = "v2022.2" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.2.bb new file mode 100644 index 00000000..3f9740a0 --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.2.bb @@ -0,0 +1,11 @@ +require fsbl-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://fsbl-fixups.patch \ + " + +# This version does not build for zynq +COMPATIBLE_MACHINE:zynq = "none" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.2.bb new file mode 100644 index 00000000..cc810241 --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.2.bb @@ -0,0 +1,16 @@ +require plm-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-versal_fw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.2.bb new file mode 100644 index 00000000..2c554d6d --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.2.bb @@ -0,0 +1,16 @@ +require pmu-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-zynqmp_pmufw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.2.bb new file mode 100644 index 00000000..d861fb1c --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.2.bb @@ -0,0 +1,16 @@ +require psm-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-versal_fw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} -- cgit v1.2.3-54-g00ecf From 5ff3d8ad926de27a11f12e9ab18845fe81747b90 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Sat, 5 Feb 2022 07:41:51 -0800 Subject: kernel-module-dp: Update to latest SRCREV Changelog: xfmc: Correct the mcdp6000_reset_cr_path function xfmc: Fix mcdp6000_read_reg and mcdp6000_modify_reg functions xfmc: Add support for different MCDP6000 revisions xfmc: Fix retimer function pointer sequence xfmc: implement mcdp6000 functions xfmc: Implement retimer configuration functions vphy: Implement prbs mode enable/disable function xvphy: update the direction flag of RX/TX instances xfmc: Add changes to Make xilinx-vfmc driver xfmc: remove fmc calls from video phy driver Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb index 1ecab893..88a2876d 100755 --- a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb +++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb @@ -11,7 +11,7 @@ S = "${WORKDIR}/git" BRANCH ?= "master" REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" -SRCREV ?= "a2e918016fa22902d58c862afe4a76efe09c6610" +SRCREV ?= "c57b2ce95ee6c86f35caecbc7007644ff8f6d337" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 79622852f55bbbeb30ebd23c480c17df57861e07 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 8 Feb 2022 13:16:59 +0530 Subject: Updated SRCREV for 2022 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3d9b207f..9426c121 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -20,7 +20,7 @@ ESW_REV[2020.1] = "338150ab3628a1ea6b06e964b16e712b131882dd" ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" -ESW_REV[2022.1] = "2a4cab4ccf38e0d7cc59270ad4de69b8e73c1835" +ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" ESW_REV[2022.2] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 5cfc8e5808b022ff34a7d3605cad94c4a51fe219 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 10 Feb 2022 19:00:40 -0800 Subject: libvcu-xlnx: Update SRCREV Changelog: fix(dec): check vui timing info present before using them Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb index 8d48e023..348f9dec 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb @@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV = "0c2921d91c94fc041cfb07ae92ab033fff87be51" +SRCREV = "9c5170fb3fa9239ed915f40f61761cc9873425ce" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 2b4b9cc0bb694f7437c99a2a93ae3b2ed4b00bca Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 9 Feb 2022 08:32:43 -0800 Subject: gcc standalone: Add workaround for microblaze -Os bug Remove -enable-target-optspace, which forces -Os when building various internal libraries. Signed-off-by: Mark Hatle --- meta-xilinx-standalone/recipes-devtools/gcc/gcc-runtime_%.bbappend | 1 - meta-xilinx-standalone/recipes-devtools/gcc/gcc-xilinx-standalone.inc | 1 - 2 files changed, 2 deletions(-) diff --git a/meta-xilinx-standalone/recipes-devtools/gcc/gcc-runtime_%.bbappend b/meta-xilinx-standalone/recipes-devtools/gcc/gcc-runtime_%.bbappend index d2a174d5..cbf43008 100644 --- a/meta-xilinx-standalone/recipes-devtools/gcc/gcc-runtime_%.bbappend +++ b/meta-xilinx-standalone/recipes-devtools/gcc/gcc-runtime_%.bbappend @@ -37,7 +37,6 @@ EXTRA_OECONF:append:xilinx-standalone:armv8r:class-target = " \ " EXTRA_OECONF:append:xilinx-standalone:microblaze:class-target = " \ - --enable-target-optspace \ --without-long-double-128 \ " diff --git a/meta-xilinx-standalone/recipes-devtools/gcc/gcc-xilinx-standalone.inc b/meta-xilinx-standalone/recipes-devtools/gcc/gcc-xilinx-standalone.inc index ec76d518..ca14529c 100644 --- a/meta-xilinx-standalone/recipes-devtools/gcc/gcc-xilinx-standalone.inc +++ b/meta-xilinx-standalone/recipes-devtools/gcc/gcc-xilinx-standalone.inc @@ -32,6 +32,5 @@ EXTRA_OECONF:append:xilinx-standalone:armv8r = " \ " EXTRA_OECONF:append:xilinx-standalone:microblaze = " \ - --enable-target-optspace \ --without-long-double-128 \ " -- cgit v1.2.3-54-g00ecf From ec05838b438ac630fe39d8aca54af2b7904648c4 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Feb 2022 20:36:33 -0800 Subject: meta-microblaze: Fix glibc issues related to select/pselect *) Select syscall is not implemented on microblaze, newselect should be used instead, but commit 4c3df0eba5e8fe98f0de917ade9b2ebba6951c5f from glibc removed this behavior. Presumably by accident. *) When the code path that doesn't use select, but instead uses pselect32 is used, microblaze provides it's own implementation but this implementation is only available when ASSUME_PSELECT is disabled. We need to fallback to the default Linux implementation. Signed-off-by: Mark Hatle --- ...Add-missing-implementation-when-__ASSUME_.patch | 61 ++++++++++++++++++++++ .../glibc/files/select-use-newselect-syscall.patch | 50 ++++++++++++++++++ .../recipes-core/glibc/glibc_2.34.bbappend | 4 ++ .../recipes-core/glibc/microblaze-glibc.inc | 7 +++ 4 files changed, 122 insertions(+) create mode 100644 meta-microblaze/recipes-core/glibc/files/0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch create mode 100644 meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch create mode 100644 meta-microblaze/recipes-core/glibc/glibc_2.34.bbappend create mode 100644 meta-microblaze/recipes-core/glibc/microblaze-glibc.inc diff --git a/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch b/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch new file mode 100644 index 00000000..5c0dc42a --- /dev/null +++ b/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch @@ -0,0 +1,61 @@ +From c75aa9246a8cfc814d99cf5f58229177bd69fc4f Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 28 Dec 2021 09:09:49 -0300 +Subject: [PATCH] microblaze: Add missing implementation when + !__ASSUME_TIME64_SYSCALLS + +In commit a92f4e6299fe0e3cb6f77e79de00817aece501ce ("linux: Add time64 +pselect support"), a Microblaze specific implementation of +__pselect32() was added to cover the case of kernels < 3.15 which lack +the pselect6 system call. + +This new file sysdeps/unix/sysv/linux/microblaze/pselect32.c takes +precedence over the default implementation +sysdeps/unix/sysv/linux/pselect32.c. + +However sysdeps/unix/sysv/linux/pselect32.c provides an implementation +of __pselect32() which is needed when __ASSUME_TIME64_SYSCALLS is not +defined. On Microblaze, which is a 32-bit architecture, +__ASSUME_TIME64_SYSCALLS is only true for kernels >= 5.1. + +Due to sysdeps/unix/sysv/linux/microblaze/pselect32.c taking +precedence over sysdeps/unix/sysv/linux/pselect32.c, it means that +when we are with a kernel >= 3.15 but < 5.1, we need a __pselect32() +implementation, but sysdeps/unix/sysv/linux/microblaze/pselect32.c +doesn't provide it, and sysdeps/unix/sysv/linux/pselect32.c which +would provide it is not compiled in. + +This causes the following build failure on Microblaze with for example +Linux kernel headers 4.9: + +[...]/build/libc_pic.os: in function `__pselect64': +(.text+0x120b44): undefined reference to `__pselect32' +collect2: error: ld returned 1 exit status + +Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=c75aa9246a8cfc814d99cf5f58229177bd69fc4f] + +Signed-off-by: Thomas Petazzoni +Reviewed-by: Adhemerval Zanella +Signed-off-by: Mark Hatle +--- + sysdeps/unix/sysv/linux/microblaze/pselect32.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/sysdeps/unix/sysv/linux/microblaze/pselect32.c b/sysdeps/unix/sysv/linux/microblaze/pselect32.c +index 70b7b52a48..dd9d56ba29 100644 +--- a/sysdeps/unix/sysv/linux/microblaze/pselect32.c ++++ b/sysdeps/unix/sysv/linux/microblaze/pselect32.c +@@ -22,7 +22,9 @@ + #include + #include + +-#ifndef __ASSUME_PSELECT ++#ifndef __ASSUME_TIME64_SYSCALL ++#include ++#elif !defined __ASSUME_PSELECT + int + __pselect32 (int nfds, fd_set *readfds, fd_set *writefds, + fd_set *exceptfds, const struct __timespec64 *timeout, +-- +2.17.1 + diff --git a/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch b/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch new file mode 100644 index 00000000..04231f0a --- /dev/null +++ b/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch @@ -0,0 +1,50 @@ +Restore newselect syscall override of select syscall + +Commit 4c3df0eba5e8fe98f0de917ade9b2ebba6951c5f removed the check and override +of select syscall with newselect if newselect was defined. + +This code path, using select instead of pselect is only executed when +ASSUME_PSELECT is not enabled. This happens on microblaze when the +kernel version is set below 3.15. + +On Microblaze select is not implemented, only newselect is. So this automatic +conversion from select to newselect syscall is expected. The original +implementation of the select to newselect syscall was part of: + + commit 26f28fd73d20df8847d93f88b6e2a7bd3bd9bf51 + Author: Adhemerval Zanella + Date: Fri Nov 18 14:27:03 2016 -0200 + + Consolidate Linux select implementation + + This patch consolidates the select Linux syscall implementation on + sysdeps/unix/sysv/linux/select.c. The changes are: + + 1. Remove select from auto-generation syscalls.list on the architecture + that uses __NR_select. + 2. Remove generic implementation add a default one that handle all + current cases (with the expection of alpha) + The new default implementation will either use __NR_select if + available of fallback to __NR_pselect6 otherwise. + 3. Add a alpha outlier implementation which requires old compatibility + symbols. + +Upstream-Status: Submitted [https://sourceware.org/bugzilla/show_bug.cgi?id=28883] + +Signed-off-by: Mark Hatle + +diff --git a/sysdeps/unix/sysv/linux/select.c b/sysdeps/unix/sysv/linux/select.c +index da25b4b4cfe..0f4c67aa29e 100644 +--- a/sysdeps/unix/sysv/linux/select.c ++++ b/sysdeps/unix/sysv/linux/select.c +@@ -101,6 +116,10 @@ __select64 (int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, + TIMESPEC_TO_TIMEVAL (timeout, pts32); + return r; + # else ++# ifdef __NR__newselect ++# undef __NR_select ++# define __NR_select __NR__newselect ++# endif + struct timeval tv32, *ptv32 = NULL; + if (pts64 != NULL) + { diff --git a/meta-microblaze/recipes-core/glibc/glibc_2.34.bbappend b/meta-microblaze/recipes-core/glibc/glibc_2.34.bbappend new file mode 100644 index 00000000..ab93a9b5 --- /dev/null +++ b/meta-microblaze/recipes-core/glibc/glibc_2.34.bbappend @@ -0,0 +1,4 @@ +MB_INC_FILE = "" +MB_INC_FILE:microblaze = "microblaze-glibc.inc" + +require ${MB_INC_FILE} diff --git a/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc b/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc new file mode 100644 index 00000000..f7820f24 --- /dev/null +++ b/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc @@ -0,0 +1,7 @@ +# Workaround for microblaze being unable to boot +FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/files" + +SRC_URI:append:microblaze = " \ + file://select-use-newselect-syscall.patch \ + file://0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch \ +" -- cgit v1.2.3-54-g00ecf From 496bf61b5f9301f3a8d373ba6653e15bdcbcf0c2 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 11 Feb 2022 15:33:11 -0800 Subject: meta-microblaze: Set OLDEST_KERNEL version is 3.15 Version 3.15 is required to enable pselect instead of (new)select syscall when using the select function. Signed-off-by: Mark Hatle --- meta-microblaze/conf/layer.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meta-microblaze/conf/layer.conf b/meta-microblaze/conf/layer.conf index 9a4a9cb2..68ee3a2b 100644 --- a/meta-microblaze/conf/layer.conf +++ b/meta-microblaze/conf/layer.conf @@ -15,3 +15,5 @@ LAYERSERIES_COMPAT_xilinx-microblaze = "honister" # Microblaze does not support stack-protector! SECURITY_STACK_PROTECTOR:microblaze = "" + +OLDEST_KERNEL:microblaze = "3.15" -- cgit v1.2.3-54-g00ecf From 9aeaacf9545649c169176eedc6b16b9cedc616e6 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 16 Feb 2022 21:52:01 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 9426c121..a9312b1c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" +ESW_REV[2022.2] = "9e33eecb879c6272c9be4d57cee081ff5247f05b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" @@ -36,8 +36,8 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1-next] = '87cee16dbcd2c2f7ceef30163838056e' -LIC_FILES_CHKSUM[master-next] = '593ba3fb8be51271097ddaa4b9c65cde' -LIC_FILES_CHKSUM[master] = '593ba3fb8be51271097ddaa4b9c65cde' +LIC_FILES_CHKSUM[master-next] = '87cee16dbcd2c2f7ceef30163838056e' +LIC_FILES_CHKSUM[master] = '87cee16dbcd2c2f7ceef30163838056e' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" -- cgit v1.2.3-54-g00ecf From f4e11dfebe4d9e7838d2083ca1ced1e0a3acb082 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 17 Feb 2022 07:23:40 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 34008ea5..1e764acf 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "e678d5ddc475f34dea8f5004fb6ebde118621784" +SRCREV = "21ecf9ed6da67118787129bde6f871592274eefa" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index c8b8c14c..53aaab75 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "6aca2a543eaa68f543c54a93cb1eed2f0bbaa96f" +SRCREV = "88d33539cfc49540194363e27f3eb221e62ae18c" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c1cda51c..ec5990f8 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "5296e6841df2b46132a9e5a3b7c5218f58486195" +SRCREV = "9e2b4d5f785c5246f5c069680371226e47b9f636" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 71f56b11e0b0418f62c608026aded96ef1b9ed00 Mon Sep 17 00:00:00 2001 From: RamyaSree Date: Thu, 27 Jan 2022 16:48:00 +0530 Subject: Update to bootgen SRCREV to point to latest commit. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb index d9676eca..8f89200d 100644 --- a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb @@ -11,7 +11,7 @@ RDEPENDS:${PN} += "openssl" REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" BRANCH ?= "master" -SRCREV = "0a6c53b6a057879c236e7194e5f818d146cf3461" +SRCREV = "2b8859218defc9983b6d312c8be48d0c08070ca1" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 8fc8dd7cb87faae0e84a81ffc93a0e5b7290456d Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 16 Feb 2022 13:27:30 -0800 Subject: meta-microblaze: Move to glibc backport Move to a backport of the official fix for glibc BZ #28883. Signed-off-by: Mark Hatle --- ...e-Use-the-correct-select-syscall-BZ-28883.patch | 34 +++++++++++++++ .../glibc/files/select-use-newselect-syscall.patch | 50 ---------------------- .../recipes-core/glibc/microblaze-glibc.inc | 2 +- 3 files changed, 35 insertions(+), 51 deletions(-) create mode 100644 meta-microblaze/recipes-core/glibc/files/0001-microblaze-Use-the-correct-select-syscall-BZ-28883.patch delete mode 100644 meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch diff --git a/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Use-the-correct-select-syscall-BZ-28883.patch b/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Use-the-correct-select-syscall-BZ-28883.patch new file mode 100644 index 00000000..aaaa0fc1 --- /dev/null +++ b/meta-microblaze/recipes-core/glibc/files/0001-microblaze-Use-the-correct-select-syscall-BZ-28883.patch @@ -0,0 +1,34 @@ +From bbe199b27aa52fc407db3372af00c3e9ffa20d1d Mon Sep 17 00:00:00 2001 +From: Adhemerval Zanella +Date: Wed, 16 Feb 2022 13:51:42 -0300 +Subject: [PATCH] microblaze: Use the correct select syscall (BZ #28883) + +On Microblaze only __NR_newselect is implemented, even though kernel +advertise __NR_select on asm/unistd.h. Since microblaze is the +only architecture that undef __ASSUME_PSELECT, the generic code +change is simpler than chaging the architecture syscall number. + +Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=bbe199b27aa52fc407db3372af00c3e9ffa20d1d] + +Acked-by: Mark Hatle +Signed-off-by: Mark Hatle +--- + sysdeps/unix/sysv/linux/select.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sysdeps/unix/sysv/linux/select.c b/sysdeps/unix/sysv/linux/select.c +index 3bc8b0cc3d..a3f0a2eba7 100644 +--- a/sysdeps/unix/sysv/linux/select.c ++++ b/sysdeps/unix/sysv/linux/select.c +@@ -108,7 +108,7 @@ __select64 (int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, + ptv32 = &tv32; + } + +- int r = SYSCALL_CANCEL (select, nfds, readfds, writefds, exceptfds, ptv32); ++ int r = SYSCALL_CANCEL (_newselect, nfds, readfds, writefds, exceptfds, ptv32); + if (timeout != NULL) + *timeout = valid_timeval_to_timeval64 (tv32); + return r; +-- +2.17.1 + diff --git a/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch b/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch deleted file mode 100644 index 04231f0a..00000000 --- a/meta-microblaze/recipes-core/glibc/files/select-use-newselect-syscall.patch +++ /dev/null @@ -1,50 +0,0 @@ -Restore newselect syscall override of select syscall - -Commit 4c3df0eba5e8fe98f0de917ade9b2ebba6951c5f removed the check and override -of select syscall with newselect if newselect was defined. - -This code path, using select instead of pselect is only executed when -ASSUME_PSELECT is not enabled. This happens on microblaze when the -kernel version is set below 3.15. - -On Microblaze select is not implemented, only newselect is. So this automatic -conversion from select to newselect syscall is expected. The original -implementation of the select to newselect syscall was part of: - - commit 26f28fd73d20df8847d93f88b6e2a7bd3bd9bf51 - Author: Adhemerval Zanella - Date: Fri Nov 18 14:27:03 2016 -0200 - - Consolidate Linux select implementation - - This patch consolidates the select Linux syscall implementation on - sysdeps/unix/sysv/linux/select.c. The changes are: - - 1. Remove select from auto-generation syscalls.list on the architecture - that uses __NR_select. - 2. Remove generic implementation add a default one that handle all - current cases (with the expection of alpha) - The new default implementation will either use __NR_select if - available of fallback to __NR_pselect6 otherwise. - 3. Add a alpha outlier implementation which requires old compatibility - symbols. - -Upstream-Status: Submitted [https://sourceware.org/bugzilla/show_bug.cgi?id=28883] - -Signed-off-by: Mark Hatle - -diff --git a/sysdeps/unix/sysv/linux/select.c b/sysdeps/unix/sysv/linux/select.c -index da25b4b4cfe..0f4c67aa29e 100644 ---- a/sysdeps/unix/sysv/linux/select.c -+++ b/sysdeps/unix/sysv/linux/select.c -@@ -101,6 +116,10 @@ __select64 (int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, - TIMESPEC_TO_TIMEVAL (timeout, pts32); - return r; - # else -+# ifdef __NR__newselect -+# undef __NR_select -+# define __NR_select __NR__newselect -+# endif - struct timeval tv32, *ptv32 = NULL; - if (pts64 != NULL) - { diff --git a/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc b/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc index f7820f24..1dbb0a64 100644 --- a/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc +++ b/meta-microblaze/recipes-core/glibc/microblaze-glibc.inc @@ -2,6 +2,6 @@ FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/files" SRC_URI:append:microblaze = " \ - file://select-use-newselect-syscall.patch \ + file://0001-microblaze-Use-the-correct-select-syscall-BZ-28883.patch \ file://0001-microblaze-Add-missing-implementation-when-__ASSUME_.patch \ " -- cgit v1.2.3-54-g00ecf From 33992fde1eb0369ed2070cbee38ecdf04c562e49 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 17 Feb 2022 13:16:29 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 53aaab75..37dbcd3f 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "88d33539cfc49540194363e27f3eb221e62ae18c" +SRCREV = "8ed6b9e3bc17f4ce7530fed6f4968bb937b413fa" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From 3ef6f51bd426c670827d7a144f7e5cb2c6f614ed Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 18 Feb 2022 13:16:37 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index ec5990f8..6625775c 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "9e2b4d5f785c5246f5c069680371226e47b9f636" +SRCREV = "0293811d1fb48202f60d63799ec58c3e44f83a55" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From a0c18df44f81874c0c999c0bef1deda3e1303f3e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 21 Feb 2022 13:18:03 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 2c8b3ffb..f3ed45a0 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "922daa6a36abd2392f9c31e3222f7a38d548e981" +SRCREV ?= "e87376ce9ef6a386844e7c5d1f52f41348f18986" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index bf92208b..f8778ebd 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "e353d497d8aff64b42575fa4799a2f43555e0502" +SRCREV = "7da7251ad605d4bc7e0fae5cb2bd927d1b7d6dea" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -- cgit v1.2.3-54-g00ecf From a2da8479e3bedeba42b20eaf2fa32a262a7c3c5e Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 17 Feb 2022 08:48:58 -0800 Subject: linux-xlnx: Move default branch to latest LTS New default branch is xlnx_rebase_5.15_LTS. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc index 429eccbf..adefabea 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc @@ -4,7 +4,7 @@ LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" PV = "${LINUX_VERSION}+git${SRCPV}" # Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits -KBRANCH ?= "xlnx_rebase_v5.15" +KBRANCH ?= "xlnx_rebase_v5.15_LTS" SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}" FILESOVERRIDES:append = ":${XILINX_RELEASE_VERSION}" -- cgit v1.2.3-54-g00ecf From 3b22c9780f299581430058eca64c0cf6a49392ac Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 23 Feb 2022 20:48:36 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index a9312b1c..2adb620f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "9e33eecb879c6272c9be4d57cee081ff5247f05b" +ESW_REV[2022.2] = "b2cbd53471063c6653e35fe5a14ac72b0c7d6606" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From b82f968e65b90ff25393fdda4ee791aad91c3fe0 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 24 Feb 2022 13:16:47 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 1e764acf..388d71cc 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "21ecf9ed6da67118787129bde6f871592274eefa" +SRCREV = "6d400d0aac6def2495d92176d26b2fbecc7fd703" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" -- cgit v1.2.3-54-g00ecf From 09b25b908a60c030c1e374e3aa090283d71002e8 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 22 Feb 2022 19:13:28 -0700 Subject: lopper: Update SRCREV to upstream master 1. Update SRCREV to upstream master commit id. 2. Update do_install based on new directory structure in source. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-kernel/lopper/lopper.bbappend | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index aa552fe5..034dce2d 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -22,28 +22,27 @@ RDEPENDS:${PN} += " \ " SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master" -SRCREV = "4fc085c4be031996e7f48dcaf03d0782989c8d58" +SRCREV = "17350a773a73c426a826e32e4e093effc718ecf5" do_install() { install -d "${D}/${bindir}" install -d "${D}/${datadir}/${BPN}" - install -m 0644 "${S}/README" "${D}/${datadir}/${BPN}" - install -m 0644 "${S}/README-architecture.txt" "${D}/${datadir}/${BPN}" + install -m 0644 "${S}/README.md" "${D}/${datadir}/${BPN}" + install -m 0644 "${S}/README-architecture.md" "${D}/${datadir}/${BPN}" install -m 0644 "${S}/README.pydoc" "${D}/${datadir}/${BPN}" install -m 0644 "${S}/LICENSE.md" "${D}/${datadir}/${BPN}" install -d "${D}/${datadir}/${BPN}/assists" - #install -m 0644 "${S}/assists/"* "${D}/${datadir}/${BPN}/assists/" - cp -r "${S}/assists/"* "${D}/${datadir}/${BPN}/assists/" + cp -r "${S}/lopper/assists/"* "${D}/${datadir}/${BPN}/assists/" install -d "${D}/${datadir}/${BPN}/lops" - install -m 0644 "${S}/lops/"* "${D}/${datadir}/${BPN}/lops/" + install -m 0644 "${S}/lopper/lops/"* "${D}/${datadir}/${BPN}/lops/" install -d "${D}/${datadir}/${BPN}/device-trees" install -m 0644 "${S}/device-trees/"* "${D}/${datadir}/${BPN}/device-trees/" - install -m 0644 "${S}/"lopper.ini "${D}/${datadir}/${BPN}/" + install -m 0644 "${S}/lopper/"lopper.ini "${D}/${datadir}/${BPN}/" install -m 0755 "${S}/"lopper*.py "${D}/${datadir}/${BPN}/" sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' ${D}/${datadir}/${BPN}/lopper.py -- cgit v1.2.3-54-g00ecf From da6dee12e254bd22d2756cca247f5cafb6c2ff9c Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 22 Feb 2022 19:13:29 -0700 Subject: embeddedsw: Update fsbl image name Update FSBL_IMAGE_NAME to align with expected file name to be fsbl-${MACHINE}. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware.inc | 2 +- meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-fw-cfg.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware.inc b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware.inc index 99101d09..dd87ff31 100644 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware.inc +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware.inc @@ -57,7 +57,7 @@ do_install() { PACKAGES = "" # This is the default in most BSPs. A MACHINE.conf can override this! -FSBL_IMAGE_NAME ??= "fsbl" +FSBL_IMAGE_NAME ??= "fsbl-${MACHINE}" inherit image-artifact-names diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-fw-cfg.inc b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-fw-cfg.inc index 5499befd..ebd9e00a 100644 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-fw-cfg.inc +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-fw-cfg.inc @@ -4,4 +4,4 @@ FSBL_DEPENDS ?= "" FSBL_MCDEPENDS ?= "mc::fsbl-fw:fsbl-firmware:do_deploy" FSBL_DEPLOY_DIR ?= "${TOPDIR}/tmp-fsbl-fw/deploy/images/${MACHINE}" -FSBL_IMAGE_NAME ?= "fsbl" +FSBL_IMAGE_NAME ?= "fsbl-${MACHINE}" -- cgit v1.2.3-54-g00ecf From 299550b94abee3c8653fbcbc4f2e1f94fae7741e Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Tue, 22 Feb 2022 19:09:33 -0800 Subject: dfx-mgr: fix systemd service file Fix ExecStart and Description. Add Documentation and comments. Fix warnings during systemd start-up. Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service | 11 +++++++++-- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service index af21f3c1..12239266 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service @@ -1,8 +1,15 @@ +# SPDX-License-Identifier: MIT +# +# DFX manager daemon is used to demonstrate Dynamic Function eXchange (DFX) +# or partial reconfiguration feature on Xilinx Zynq UltraScale+ and newer. +# See: UG909 "Vivado Design Suite User Guide Dynamic Function eXchange" + [Unit] -Description=dfx-mgr +Description=dfx-mgrd Dynamic Function eXchange +Documentation=https://github.com/Xilinx/dfx-mgr [Service] -ExecStart=/usr/bin/dfx-mgr.sh & +ExecStart=/usr/bin/dfx-mgrd [Install] WantedBy=multi-user.target diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 5e40785c..5bba168c 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -62,7 +62,7 @@ do_install(){ install -m 0755 ${S}/src/dfx-mgr.sh ${D}${bindir}/ install -d ${D}${systemd_system_unitdir} - install -m 0755 ${WORKDIR}/dfx-mgr.service ${D}${systemd_system_unitdir} + install -m 0644 ${WORKDIR}/dfx-mgr.service ${D}${systemd_system_unitdir} } PACKAGES =+ "libdfx-mgr libdfxgraph" -- cgit v1.2.3-54-g00ecf From 410587c6f3209205a921ec49166aaca3aa9fd60a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 26 Feb 2022 13:16:47 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 37dbcd3f..482db95f 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "8ed6b9e3bc17f4ce7530fed6f4968bb937b413fa" +SRCREV = "754eb0b1401bb361dcd33ef2f2942785d802c7d1" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 6625775c..42785a27 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "0293811d1fb48202f60d63799ec58c3e44f83a55" +SRCREV = "e7f54e8fcc4f5ee50288e843cf509353cdf1a89e" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 81dcb9770253c668d87ca73ad0a4d9a7d2e3519f Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 28 Feb 2022 13:16:59 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 482db95f..c51013bc 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "754eb0b1401bb361dcd33ef2f2942785d802c7d1" +SRCREV = "12f54fa56ef24ee7b1d6e73299931d95dbd7f125" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From 091a36ab03c04b5b507e8d862372c4e4d21a9814 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Thu, 24 Feb 2022 16:56:26 +0530 Subject: fpgamanager_custom: Split SRC_URI with space Splitting with file:// is not extracting the file name when git path is in between (Ex: file://rp.xsa git://devicetree-xlnx.git file://base.tcl) with above example the xsa path will be "rp.xsa git://devicetree-xlnx.git" which is not proper. To fix this splitting the SRC_URI with space and removes the prefix 'file://'. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/classes/fpgamanager_custom.bbclass | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/classes/fpgamanager_custom.bbclass b/meta-xilinx-core/classes/fpgamanager_custom.bbclass index 0b5fa249..848727fb 100644 --- a/meta-xilinx-core/classes/fpgamanager_custom.bbclass +++ b/meta-xilinx-core/classes/fpgamanager_custom.bbclass @@ -30,13 +30,13 @@ python (){ or d.getVar("SRC_URI").count("shell.json") != 1: raise bb.parse.SkipRecipe("Need one '.dtsi', one '.bit' and one 'shell.json' file added to SRC_URI") - d.setVar("DTSI_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.dtsi' in a][0])) - d.setVar("BIT_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.bit' in a][0])) - d.setVar("JSON_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if 'shell.json' in a][0])) + d.setVar("DTSI_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split() if '.dtsi' in a][0].lstrip('file://'))) + d.setVar("BIT_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split() if '.bit' in a][0].lstrip('file://'))) + d.setVar("JSON_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split() if 'shell.json' in a][0].lstrip('file://'))) #optional input if '.xclbin' in d.getVar("SRC_URI"): - d.setVar("XCL_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.xclbin' in a][0])) + d.setVar("XCL_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split() if '.xclbin' in a][0].lstrip('file://'))) } python do_configure() { import glob, re, shutil -- cgit v1.2.3-54-g00ecf From 5f4842d6a800897bfed271dc6eda9bf2a783c9ae Mon Sep 17 00:00:00 2001 From: Swagath Gadde Date: Thu, 24 Feb 2022 23:25:19 +0530 Subject: pmu-firmware_%.bbappend:enable build flags for dynamic MIO configuration. This patch will enable the below pmufw build flags to support dynamic MIO configuration. which is required for SOM use case. ENABLE_IOCTL ENABLE_DYNAMIC_MIO_CONFIG Signed-off-by: Swagath Gadde Signed-off-by: Mark Hatle --- .../meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend index 93caf4e4..56cede1a 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend @@ -1,4 +1,4 @@ ULTRA96_VERSION ?= "1" YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" -YAML_COMPILER_FLAGS:append:k26 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 -DENABLE_EM -DENABLE_MOD_OVERTEMP -DOVERTEMP_DEGC=90.0 " +YAML_COMPILER_FLAGS:append:k26 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 -DENABLE_EM -DENABLE_MOD_OVERTEMP -DOVERTEMP_DEGC=90.0 -DENABLE_DYNAMIC_MIO_CONFIG -DENABLE_IOCTL" -- cgit v1.2.3-54-g00ecf From e68f5cd04e868787cc7331542c13a8dc1794fa4d Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Fri, 25 Feb 2022 03:34:23 +0100 Subject: weston-init: Use 644 permission for ini file Use 644 permission for the Xilinx ini file which matches the default ini file permissions from upstream. This allows non-root users to also load this ini file. Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend b/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend index ba570d44..3b2b17fd 100644 --- a/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend +++ b/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend @@ -3,5 +3,5 @@ FILESEXTRAPATHS:prepend:zynqmp := "${THISDIR}/files:" SRC_URI:append:zynqmp = " file://weston.ini" do_install:append:zynqmp() { - install -Dm 0700 ${WORKDIR}/weston.ini ${D}/${sysconfdir}/xdg/weston/weston.ini + install -D -p -m0644 ${WORKDIR}/weston.ini ${D}/${sysconfdir}/xdg/weston/weston.ini } -- cgit v1.2.3-54-g00ecf From dbf773c58d3f0771fbd5f7bca8b77e1279ea6628 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Fri, 25 Feb 2022 03:34:24 +0100 Subject: weston-init: Copy init and service file from openembedded-core Current as of honister commits e09625b31c6dbe7121665a554e26e267b809beb1 and a849f29bcbd85c6d30d2ef4e061ef332ea555450 Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- .../recipes-graphics/wayland/files/init | 54 ++++++++++++++++ .../recipes-graphics/wayland/files/weston.service | 71 ++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 meta-xilinx-core/recipes-graphics/wayland/files/init create mode 100644 meta-xilinx-core/recipes-graphics/wayland/files/weston.service diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/init b/meta-xilinx-core/recipes-graphics/wayland/files/init new file mode 100644 index 00000000..a849f29b --- /dev/null +++ b/meta-xilinx-core/recipes-graphics/wayland/files/init @@ -0,0 +1,54 @@ +#!/bin/sh +# +### BEGIN INIT INFO +# Provides: weston +# Required-Start: $local_fs $remote_fs +# Required-Stop: $local_fs $remote_fs +# Default-Start: 2 3 4 5 +# Default-Stop: 0 1 6 +### END INIT INFO + +if test -e /etc/default/weston ; then + . /etc/default/weston +fi + +killproc() { + pid=`/bin/pidof $1` + [ "$pid" != "" ] && kill $pid +} + +read CMDLINE < /proc/cmdline +for x in $CMDLINE; do + case $x in + weston=false) + echo "Weston disabled" + exit 0; + ;; + esac +done + +case "$1" in + start) + . /etc/profile + export HOME=ROOTHOME + + weston-start -- $OPTARGS + ;; + + stop) + echo "Stopping Weston" + killproc weston + ;; + + restart) + $0 stop + sleep 1 + $0 start + ;; + + *) + echo "usage: $0 { start | stop | restart }" + ;; +esac + +exit 0 diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/weston.service b/meta-xilinx-core/recipes-graphics/wayland/files/weston.service new file mode 100644 index 00000000..e09625b3 --- /dev/null +++ b/meta-xilinx-core/recipes-graphics/wayland/files/weston.service @@ -0,0 +1,71 @@ +# This is a system unit for launching Weston with auto-login as the +# user configured here. +# +# Weston must be built with systemd support, and your weston.ini must load +# the plugin systemd-notify.so. +[Unit] +Description=Weston, a Wayland compositor, as a system service +Documentation=man:weston(1) man:weston.ini(5) +Documentation=http://wayland.freedesktop.org/ + +# Make sure we are started after logins are permitted. +Requires=systemd-user-sessions.service +After=systemd-user-sessions.service + +# If Plymouth is used, we want to start when it is on its way out. +After=plymouth-quit-wait.service + +# D-Bus is necessary for contacting logind. Logind is required. +Wants=dbus.socket +After=dbus.socket + +# Ensure the socket is present +Requires=weston.socket + +# Since we are part of the graphical session, make sure we are started before +# it is complete. +Before=graphical.target + +# Prevent starting on systems without virtual consoles, Weston requires one +# for now. +ConditionPathExists=/dev/tty0 + +[Service] +# Requires systemd-notify.so Weston plugin. +Type=notify +EnvironmentFile=/etc/default/weston +ExecStart=/usr/bin/weston --modules=systemd-notify.so + +# Optional watchdog setup +TimeoutStartSec=60 +WatchdogSec=20 + +# The user to run Weston as. +User=weston +Group=weston + +# Make sure the working directory is the users home directory +WorkingDirectory=/home/weston + +# Set up a full user session for the user, required by Weston. +PAMName=weston-autologin + +# A virtual terminal is needed. +TTYPath=/dev/tty7 +TTYReset=yes +TTYVHangup=yes +TTYVTDisallocate=yes + +# Fail to start if not controlling the tty. +StandardInput=tty-fail +StandardOutput=journal +StandardError=journal + +# Log this user with utmp, letting it show up with commands 'w' and 'who'. +UtmpIdentifier=tty7 +UtmpMode=user + +[Install] +# Note: If you only want weston to start on-demand, remove this line with a +# service drop file +WantedBy=graphical.target -- cgit v1.2.3-54-g00ecf From bb7439368c6a1fc17ccb32731471d9e6c5661ba6 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Fri, 25 Feb 2022 03:34:25 +0100 Subject: weston-init: Pass --continue-without-input when launching weston This ensures that we do not need keyboard/mouse or other input system Weston's default behavior is to not open if input devices are not found, but we may not always have input devices connected for systems running weston in field. Signed-off-by: Khem Raj Signed-off-by: Richard Purdie This commit is based on 762a20b493cc219a46d9ac188fe4895a111ee7b4 from meta-openembedded-core. It was later reverted in master because it breaks the fbdev backend. At Xilinx, we are using the drm backend so it is safe to add this. Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-graphics/wayland/files/init | 2 +- meta-xilinx-core/recipes-graphics/wayland/files/weston.service | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/init b/meta-xilinx-core/recipes-graphics/wayland/files/init index a849f29b..f74ac8b1 100644 --- a/meta-xilinx-core/recipes-graphics/wayland/files/init +++ b/meta-xilinx-core/recipes-graphics/wayland/files/init @@ -32,7 +32,7 @@ case "$1" in . /etc/profile export HOME=ROOTHOME - weston-start -- $OPTARGS + weston-start -- --continue-without-input $OPTARGS ;; stop) diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/weston.service b/meta-xilinx-core/recipes-graphics/wayland/files/weston.service index e09625b3..c7583e92 100644 --- a/meta-xilinx-core/recipes-graphics/wayland/files/weston.service +++ b/meta-xilinx-core/recipes-graphics/wayland/files/weston.service @@ -34,7 +34,7 @@ ConditionPathExists=/dev/tty0 # Requires systemd-notify.so Weston plugin. Type=notify EnvironmentFile=/etc/default/weston -ExecStart=/usr/bin/weston --modules=systemd-notify.so +ExecStart=/usr/bin/weston --continue-without-input --modules=systemd-notify.so # Optional watchdog setup TimeoutStartSec=60 -- cgit v1.2.3-54-g00ecf From 83233e145de6107692e0c90ebbdff975dca1c34e Mon Sep 17 00:00:00 2001 From: rbramand Date: Fri, 25 Feb 2022 11:14:50 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 615e69ce..b9466b63 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "bbaea8fb0024cadc2de19000c800cfdb93a4c3d7" +SRCREV= "bb871e556f9b8f6a57cbbac7d6b14c60b96422a2" PV = "202210.2.13.0" diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index f73d3d2b..7cb9b185 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -36,6 +36,7 @@ FILES_SOLIBSDEV = "" FILES:${PN} += "\ ${libdir}/lib*.so \ ${libdir}/lib*.so.* \ + ${libdir}/ps_kernels_lib \ /lib/*.so* " INSANE_SKIP:${PN} += "dev-so" -- cgit v1.2.3-54-g00ecf From d5a4926047c28a0c3448d68961d7f749c4555253 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 1 Mar 2022 13:16:56 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 42785a27..9a9906c5 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "e7f54e8fcc4f5ee50288e843cf509353cdf1a89e" +SRCREV = "6a58fcf9a9592faeab019a3b55ce1f49ecfb91ea" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 55e47ae13bdfc94e95ec0d7edb01d3df4cd09e90 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 3 Mar 2022 06:01:09 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 388d71cc..acfc1e7c 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "6d400d0aac6def2495d92176d26b2fbecc7fd703" +SRCREV = "5de5e3b5501ac5aa2a7bc5670c97b5dff2c7366f" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 9a9906c5..b6aef22a 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "6a58fcf9a9592faeab019a3b55ce1f49ecfb91ea" +SRCREV = "71427a49117cac96dbfe9101bdc06005121c8c52" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 71ca272cf8c96ddd6a7182729a225adf19f933c0 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 1 Mar 2022 16:38:11 -0700 Subject: kernel-module-vcu: Add vcu rules to video group Adding vcu rules file changing permissions and ownership group to video so that any new user added to video groups can run allegro vcu encoder and decoder devices. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-multimedia/vcu/files/99-vcu-enc-dec.rules | 7 +++++++ .../recipes-multimedia/vcu/kernel-module-vcu.bb | 14 +++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/files/99-vcu-enc-dec.rules diff --git a/meta-xilinx-core/recipes-multimedia/vcu/files/99-vcu-enc-dec.rules b/meta-xilinx-core/recipes-multimedia/vcu/files/99-vcu-enc-dec.rules new file mode 100644 index 00000000..4643ad37 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/files/99-vcu-enc-dec.rules @@ -0,0 +1,7 @@ +# Allegro VCU Encode, Decoder module drivers +SUBSYSTEM=="allegro_encode_class", KERNEL=="allegroIP", MODE="0660", GROUP="video" +SUBSYSTEM=="allegro_decode_class", KERNEL=="allegroDecodeIP", MODE="0660", GROUP="video" + +# Xilinx Video DMA driver +SUBSYSTEM=="char", KERNEL=="dmaproxy", MODE="0660", GROUP="video" + diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb index 816b7517..505b54db 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb @@ -9,12 +9,17 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" S = "${WORKDIR}/git" +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + BRANCH = "master" REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" SRCREV = "9d2657550eccebccce08cacfcdd369367b9f6be4" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" +SRC_URI = " \ + ${REPO};${BRANCHARG} \ + file://99-vcu-enc-dec.rules \ + " inherit module @@ -26,3 +31,10 @@ COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynqmp = "zynqmp" KERNEL_MODULE_AUTOLOAD += "dmaproxy" + +do_install:append() { + install -d ${D}${sysconfdir}/udev/rules.d + install -m 0644 ${WORKDIR}/99-vcu-enc-dec.rules ${D}${sysconfdir}/udev/rules.d/ +} + +FILES:${PN} = "${sysconfdir}/udev/rules.d/*" -- cgit v1.2.3-54-g00ecf From 726683a8edbce97f6317bd3766bb5d3134ccd589 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 7 Mar 2022 13:17:11 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index acfc1e7c..4709d218 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "5de5e3b5501ac5aa2a7bc5670c97b5dff2c7366f" +SRCREV = "b7fe0b19a25c1473958a363f92b56b8d20d78c0e" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index c51013bc..663dace5 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "12f54fa56ef24ee7b1d6e73299931d95dbd7f125" +SRCREV = "02e43308abeb603e33f5f4c60f3a69548133f834" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index b6aef22a..7e97486b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "71427a49117cac96dbfe9101bdc06005121c8c52" +SRCREV = "ef4ac9cad9406e869e7c20191f3a3b0bb9663d81" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From b2ba884842b45c1f6bf9d0b99eb0c795dcfd6a21 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 7 Mar 2022 16:27:45 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2adb620f..21f0ac7c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "b2cbd53471063c6653e35fe5a14ac72b0c7d6606" +ESW_REV[2022.2] = "b385865e2c6e642579520464428a0f0ae0fc312a" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 034c7de08dc5211f575f7b0486528b408e348765 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 1 Mar 2022 16:52:33 -0800 Subject: lopper.bbappend: Backport latest lopper from meta-virtualization (master) The bbappend essentially replaces the existing lopper.bb from meta-virt (honister). When meta-virt is updated, most of this bbappend will no longer be necessary. Also update the SRCREV and PV to indicate we're now based on version 1.0.2. Also update xilinx-lops path to match. Signed-off-by: Mark Hatle --- .../recipes-kernel/lopper/lopper.bbappend | 72 ++++++++++------------ .../recipes-kernel/lopper/xilinx-lops.bb | 10 +-- 2 files changed, 37 insertions(+), 45 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 034dce2d..ccbc19e2 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -1,53 +1,43 @@ -DEPENDS = " \ - dtc \ +SUMMARY = "Device Tree Lopper" +DESCRIPTION = "Tool for manipulation of system device tree files" +LICENSE = "BSD-3-Clause" +SECTION = "bootloader" + +FILESEXTRAPATHS:append := ":${THISDIR}/lopper" + +SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" +SRCREV = "f70eb86385f49545070a84ad756902b3cd607e21" +S = "${WORKDIR}/git" + +PV="v1.0.2+git${SRCPV}" + +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=8e5f5f691f01c9fdfa7a7f2d535be619" + +RDEPENDS:${PN} = " \ + python3-core \ python3-dtc \ - python3-flask \ - python3-flask-restful \ - python3-six \ - python3-pandas \ - python3-ruamel-yaml \ - python3-anytree \ - python3-pyyaml \ python3-humanfriendly \ -" - -RDEPENDS:${PN} += " \ - python3-flask \ - python3-flask-restful \ - python3-six \ - python3-pandas \ python3-ruamel-yaml \ python3-anytree \ + python3-six \ python3-pyyaml \ -" + " -SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master" -SRCREV = "17350a773a73c426a826e32e4e093effc718ecf5" - -do_install() { - install -d "${D}/${bindir}" - install -d "${D}/${datadir}/${BPN}" +inherit setuptools3 - install -m 0644 "${S}/README.md" "${D}/${datadir}/${BPN}" - install -m 0644 "${S}/README-architecture.md" "${D}/${datadir}/${BPN}" - install -m 0644 "${S}/README.pydoc" "${D}/${datadir}/${BPN}" - install -m 0644 "${S}/LICENSE.md" "${D}/${datadir}/${BPN}" +INHIBIT_PACKAGE_STRIP = "1" - install -d "${D}/${datadir}/${BPN}/assists" - cp -r "${S}/lopper/assists/"* "${D}/${datadir}/${BPN}/assists/" - - install -d "${D}/${datadir}/${BPN}/lops" - install -m 0644 "${S}/lopper/lops/"* "${D}/${datadir}/${BPN}/lops/" - - install -d "${D}/${datadir}/${BPN}/device-trees" - install -m 0644 "${S}/device-trees/"* "${D}/${datadir}/${BPN}/device-trees/" +do_install() { + distutils3_do_install - install -m 0644 "${S}/lopper/"lopper.ini "${D}/${datadir}/${BPN}/" + # we have to remove the vendor'd libfdt, since an attempt to strip it + # will be made, and it will fail in a cross environment. + rm -rf ${D}/${PYTHON_SITEPACKAGES_DIR}/${BPN}/vendor +} - install -m 0755 "${S}/"lopper*.py "${D}/${datadir}/${BPN}/" - sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' ${D}/${datadir}/${BPN}/lopper.py - sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' ${D}/${datadir}/${BPN}/lopper_sanity.py +BBCLASSEXTEND = "native nativesdk" - datadir_relpath=${@os.path.relpath(d.getVar('datadir'), d.getVar('bindir'))} - ln -s "${datadir_relpath}/${BPN}/lopper.py" "${D}/${bindir}/" +python() { + d.delVarFlag('do_configure', 'noexec') + d.delVarFlag('do_compile', 'noexec') } diff --git a/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb index 77456376..38ec473b 100644 --- a/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb +++ b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb @@ -14,14 +14,16 @@ LIC_FILES_CHKSUM = "file://lop-microblaze-yocto.dts;endline=8;md5=a0e89d39fa397e S = "${WORKDIR}" +inherit python3-dir + do_configure[noexec] = '1' do_compile[noexec] = '1' do_install() { - mkdir -p ${D}/${datadir}/lopper/lops - cp ${S}/lop-microblaze-yocto.dts ${D}/${datadir}/lopper/lops/. - cp ${S}/lop-xilinx-id-cpus.dts ${D}/${datadir}/lopper/lops/. + mkdir -p ${D}/${PYTHON_SITEPACKAGES_DIR}/lopper/lops + cp ${S}/lop-microblaze-yocto.dts ${D}/${PYTHON_SITEPACKAGES_DIR}/lopper/lops/. + cp ${S}/lop-xilinx-id-cpus.dts ${D}/${PYTHON_SITEPACKAGES_DIR}/lopper/lops/. } -FILES:${PN} += "${datadir}/lopper/lops" +FILES:${PN} += "${PYTHON_SITEPACKAGES_DIR}/lopper/lops" BBCLASSEXTEND = "native nativesdk" -- cgit v1.2.3-54-g00ecf From 5d28e5640859bc6f275b804e1344c6dd17e5a492 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 4 Mar 2022 16:30:06 -0800 Subject: meta-xilinx-standalone-experimental: Change from lopper.py to lopper Upgrade of lopper changed the executable name to lopper. Switch all of the users. Signed-off-by: Mark Hatle --- .../classes/esw.bbclass | 2 +- .../classes/esw_examples.bbclass | 4 +- .../empty-application/empty-application_git.bb | 2 +- .../freertos-hello-world_git.bb | 2 +- .../freertos-lwip-echo-server_git.bb | 4 +- .../freertos-lwip-tcp-perf-client_git.bb | 4 +- .../freertos-lwip-tcp-perf-server_git.bb | 4 +- .../freertos-lwip-udp-perf-client_git.bb | 4 +- .../freertos-lwip-udp-perf-server_git.bb | 4 +- .../hello-world/hello-world_git.bb | 2 +- .../lwip-echo-server/lwip-echo-server_git.bb | 4 +- .../lwip-tcp-perf-client_git.bb | 4 +- .../lwip-tcp-perf-server_git.bb | 4 +- .../lwip-udp-perf-client_git.bb | 4 +- .../lwip-udp-perf-server_git.bb | 4 +- .../memory-tests/memory-tests_git.bb | 2 +- .../peripheral-tests/peripheral-tests_git.bb | 4 +- .../recipes-core/meta/files/dt-processor.sh | 94 +++++++++++----------- .../recipes-drivers/clockps-example_git.bb | 2 +- .../recipes-drivers/common_git.bb | 4 +- .../recipes-drivers/ospipsv_git.bb | 2 +- .../recipes-drivers/uartlite_git.bb | 2 +- .../recipes-drivers/uartns550_git.bb | 2 +- .../recipes-drivers/uartps_git.bb | 2 +- .../recipes-drivers/uartpsv_git.bb | 2 +- .../recipes-drivers/v-frmbuf-rd_git.bb | 2 +- .../recipes-drivers/v-frmbuf-wr_git.bb | 2 +- .../recipes-libraries/freertos10-xilinx_git.bb | 2 +- .../recipes-libraries/libxil_git.bb | 2 +- .../recipes-libraries/lwip_git.bb | 2 +- .../recipes-libraries/xilffs-example_git.bb | 2 +- .../recipes-libraries/xilfpga-example_git.bb | 2 +- .../recipes-libraries/xilmailbox-example_git.bb | 4 +- .../recipes-libraries/xilnvm-example_git.bb | 2 +- .../recipes-libraries/xilpuf-example_git.bb | 2 +- .../recipes-libraries/xilsecure-example_git.bb | 2 +- .../recipes-libraries/xilstandalone_git.bb | 2 +- .../recipes-libraries/xiltimer_git.bb | 2 +- 38 files changed, 98 insertions(+), 98 deletions(-) diff --git a/meta-xilinx-standalone-experimental/classes/esw.bbclass b/meta-xilinx-standalone-experimental/classes/esw.bbclass index c650d5bf..efecb1f9 100644 --- a/meta-xilinx-standalone-experimental/classes/esw.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw.bbclass @@ -125,7 +125,7 @@ python do_generate_driver_data() { bb.error("Couldn't find source dir %s" % d.getVar('OECMAKE_SOURCEPATH')) os.chdir(d.getVar('B')) - command = ["lopper.py"] + ["-f"] + [system_dt[0]] + ["--"] + ["baremetalconfig_xlnx.py"] + [machine] + [src_dir[0]] + command = ["lopper"] + ["-f"] + [system_dt[0]] + ["--"] + ["baremetalconfig_xlnx.py"] + [machine] + [src_dir[0]] subprocess.run(command, check = True) src_file = str("x") + driver_name.replace('-', '_') + str("_g.c") if os.path.exists(src_file): diff --git a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass index 3ae01ac1..64e0810c 100644 --- a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass @@ -4,7 +4,7 @@ DEPENDS += "python3-dtc-native python3-pyyaml-native xilstandalone libxil xiltim do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ EXTRA_OECMAKE = "-DCUSTOM_LINKER_FILE=${@d.getVar('ESW_CUSTOM_LINKER_FILE')}" do_generate_eglist () { cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} drvcmake_metadata + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} drvcmake_metadata install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask generate_eglist before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb index 653ae51a..99771f38 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb @@ -8,7 +8,7 @@ inherit python3native do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0644 ${CUSTOM_SRCFILE}/* ${S}/${ESW_COMPONENT_SRC}/ diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb index 9bf220fe..e4a300d2 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil xilstandalone freertos10-xilinx xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb index ae6d8342..25610987 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb index 2380eaef..cec949f9 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb index 6a156c2d..a144ecfd 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb index bd532abf..3c3a27b0 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb index 83577806..8e532c3c 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb index 8d14acf2..9b66c129 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb @@ -8,7 +8,7 @@ inherit python3native do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb index 1aef0d73..d86e62a3 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb index 5db0c218..dd6501cf 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb index 211d9e55..1f7ae00c 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb index 42aa07fe..1b3105da 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb index b78499fe..be3d3d4b 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb @@ -6,7 +6,7 @@ DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -14,7 +14,7 @@ do_configure:prepend() { do_generate_app_data() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } addtask do_generate_app_data before do_configure after do_prepare_recipe_sysroot diff --git a/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb index 1bca8dc5..3e025962 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb @@ -8,7 +8,7 @@ inherit python3native do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} memtest + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} memtest install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb index 6275ee07..61b60ad4 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb @@ -8,7 +8,7 @@ inherit python3native do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -28,7 +28,7 @@ python do_generate_app_data() { bb.error("Couldn't find source dir %s" % d.getVar('OECMAKE_SOURCEPATH')) driver_name = d.getVar('REQUIRED_DISTRO_FEATURES') - command = ["lopper.py"] + ["-f"] + [system_dt[0]] + ["--"] + ["baremetal_gentestapp_xlnx"] + [machine] + [srcdir[0]] + command = ["lopper"] + ["-f"] + [system_dt[0]] + ["--"] + ["baremetal_gentestapp_xlnx"] + [machine] + [srcdir[0]] subprocess.run(command, check = True) with open("file_list.txt", 'r') as fd: for line in fd: diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index a8da5b4a..d0b719cb 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -107,21 +107,21 @@ cortex_a53_linux() { if [ "${overlay_dtb}" = "true" ]; then if [ "${external_fpga}" = "true" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" -- xlnx_overlay_dt ${machine} full \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} "${system_dtb}" -- xlnx_overlay_dt ${machine} partial \ - || error "lopper.py failed" + || error "lopper failed" fi dtc -q -O dtb -o pl.dtbo -b 0 -@ pl.dtsi || error "dtc failed" elif [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" \ -i "${lops_dir}/lop-domain-linux-a53.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ -i "${lops_dir}/lop-domain-linux-a53.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" fi rm -f pl.dtsi lop-a53-imux.dts.dtb lop-domain-linux-a53.dts.dtb ) @@ -174,10 +174,10 @@ cortex_a53_baremetal() { if [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-a53-imux.dts.dtb ) @@ -186,10 +186,10 @@ cortex_a53_baremetal() { if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -227,10 +227,10 @@ cortex_a53_freertos() { if [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-a53-imux.dts.dtb ) @@ -238,10 +238,10 @@ cortex_a53_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -282,21 +282,21 @@ cortex_a72_linux() { # a flag "external_fpga" which says apply overlay without loading the bit file. if [ "${external_fpga}" = "true" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" -- xlnx_overlay_dt \ - ${machine} full external_fpga || error "lopper.py failed" + ${machine} full external_fpga || error "lopper failed" else # If there is no external_fpga flag, then the default is full LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} "${system_dtb}" -- xlnx_overlay_dt \ - ${machine} full || error "lopper.py failed" + ${machine} full || error "lopper failed" fi dtc -q -O dtb -o pl.dtbo -b 0 -@ pl.dtsi || error "dtc failed" elif [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" \ -i "${lops_dir}/lop-domain-a72.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ - -i "${lops_dir}/lop-domain-a72.dts" "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + -i "${lops_dir}/lop-domain-a72.dts" "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f pl.dtsi lop-a72-imux.dts.dtb lop-domain-a72.dts.dtb ) @@ -335,10 +335,10 @@ cortex_a72_baremetal() { if [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-a72-imux.dts.dtb ) @@ -346,10 +346,10 @@ cortex_a72_baremetal() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -385,12 +385,12 @@ cortex_a72_freertos() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" lopper -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-a72-imux.dts.dtb ) @@ -398,10 +398,10 @@ cortex_a72_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -454,10 +454,10 @@ cortex_r5_baremetal() { if [ -n "$domain_file" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-r5-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-r5-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-r5-imux.dts.dtb ) @@ -465,10 +465,10 @@ cortex_r5_baremetal() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -506,10 +506,10 @@ cortex_r5_freertos() { if [ -n "$domain_file" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-r5-imux.dts" "${system_dtb}" "${dtb_file}" \ - || error "lopper.py failed" + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-r5-imux.dts" \ - "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f lop-r5-imux.dts.dtb ) @@ -517,10 +517,10 @@ cortex_r5_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -550,7 +550,7 @@ process_microblaze() { ( cd dtb || error "Unable to cd to dtb dir" ${lopper} -f --enhanced -i "${lops_dir}/lop-microblaze-yocto.dts" "${system_dtb}" \ - || error "lopper.py failed" + || error "lopper failed" rm -f lop-microblaze-yocto.dts.dtb ) >microblaze.conf @@ -575,16 +575,16 @@ pmu-microblaze() { # Build device tree ( cd dtb || error "Unable to cd to dtb dir" - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper failed" ) # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx microblaze-pmu "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx microblaze-pmu "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-pmu "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -627,16 +627,16 @@ pmc-microblaze() { # Build device tree ( cd dtb || error "Unable to cd to dtb dir" - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper failed" ) # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx microblaze-plm "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx microblaze-plm "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-plm "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -679,16 +679,16 @@ psm-microblaze() { # Build device tree ( cd dtb || error "Unable to cd to dtb dir" - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper.py failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f "${system_dtb}" "${dtb_file}" || error "lopper failed" ) # Build baremetal multiconfig if [ -n "${domain_file}" ]; then ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ - -- baremetaldrvlist_xlnx microblaze-psm "${embeddedsw}" || error "lopper.py failed" + -- baremetaldrvlist_xlnx microblaze-psm "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-psm "${embeddedsw}" \ - || error "lopper.py failed" + || error "lopper failed" fi mv libxil.conf "${libxil}" @@ -854,14 +854,14 @@ gen_local_conf() { parse_args "$@" -lopper=$(command -v lopper.py) +lopper=$(command -v lopper) lopper_dir=$(dirname "${lopper}") -lops_dir=$(dirname "${lopper_dir}")/share/lopper/lops +lops_dir=$(ls -d $(dirname "${lopper_dir}")/lib/python*/site-packages/lopper/lops | head -n 1) embeddedsw=$(dirname "${lopper_dir}")/share/embeddedsw system_conf="" multiconf="" -[ -z "${lopper}" ] && error "Unable to find lopper.py, please source the prestep environment" +[ -z "${lopper}" ] && error "Unable to find lopper, please source the prestep environment" # Generate CPU list cd "${config_dir}" || exit @@ -869,7 +869,7 @@ mkdir -p dtb multiconfig/includes ( cd dtb || error "Unable to cd to dtb dir" ${lopper} -f --enhanced -i "${lops_dir}/lop-xilinx-id-cpus.dts" "${system_dtb}" \ - /dev/null >"../cpu-list.tmp" || error "lopper.py failed" + /dev/null >"../cpu-list.tmp" || error "lopper failed" rm -f "lop-xilinx-id-cpus.dts.dtb" ) diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb index 8da16452..0bc67b11 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb @@ -10,7 +10,7 @@ inherit python3native do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/common_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/common_git.bb index 685e5585..d01a8cac 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/common_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/common_git.bb @@ -17,7 +17,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/common/src/" ESW_COMPONENT_NAME = "libcommon.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/XilinxProcessorIPLib/drivers/intc/src/ - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/XilinxProcessorIPLib/drivers/scugic/src/ + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/XilinxProcessorIPLib/drivers/intc/src/ + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/XilinxProcessorIPLib/drivers/scugic/src/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/ospipsv_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/ospipsv_git.bb index cc71a89d..19cfe8ed 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/ospipsv_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/ospipsv_git.bb @@ -13,7 +13,7 @@ addtask do_generate_driver_data before do_configure after do_prepare_recipe_sysr do_prepare_recipe_sysroot[rdeptask] = "do_unpack" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetal_xparameters_xlnx.py ${ESW_MACHINE} ${S} + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetal_xparameters_xlnx.py ${ESW_MACHINE} ${S} install -m 0755 xparameters.h ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/uartlite_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/uartlite_git.bb index 5d4e5a91..270ffb43 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/uartlite_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/uartlite_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/uartlite/src/" ESW_COMPONENT_NAME = "libuartlite.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC} install -m 0755 xuartlite_g.c ${S}/${ESW_COMPONENT_SRC} } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/uartns550_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/uartns550_git.bb index a1c9b670..8e64457e 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/uartns550_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/uartns550_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/uartns550/src/" ESW_COMPONENT_NAME = "libuartns550.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC} install -m 0755 xuartns550_g.c ${S}/${ESW_COMPONENT_SRC} } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/uartps_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/uartps_git.bb index 339450dd..c2247736 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/uartps_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/uartps_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/uartps/src/" ESW_COMPONENT_NAME = "libuartps.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xuartps_g.c ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/uartpsv_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/uartpsv_git.bb index 1b285fd8..266f1db9 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/uartpsv_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/uartpsv_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/uartpsv/src/" ESW_COMPONENT_NAME = "libuartpsv.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} stdin install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xuartpsv_g.c ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-rd_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-rd_git.bb index ee100489..da248701 100755 --- a/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-rd_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-rd_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/v_frmbuf_rd/src/" ESW_COMPONENT_NAME = "libv_frmbuf_rd.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xv_frmbufrd_g.c ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-wr_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-wr_git.bb index 7c4d1230..f2ec3b27 100755 --- a/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-wr_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/v-frmbuf-wr_git.bb @@ -10,7 +10,7 @@ ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/v_frmbuf_wr/src/" ESW_COMPONENT_NAME = "libv_frmbuf_wr.a" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetalconfig_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xv_frmbufwr_g.c ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb index 4ad2a9e6..46c349bc 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb @@ -8,6 +8,6 @@ DEPENDS += "libxil xilstandalone xiltimer" do_configure:prepend() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb index 48482de4..4adfe46e 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb @@ -12,7 +12,7 @@ REQUIRED_DISTRO_FEATURES = "${DISTRO_FEATURES}" PACKAGECONFIG ?= "${DISTRO_FEATURES} ${MACHINE_FEATURES}" do_configure:prepend() { - LOPPER_DTC_FLAGS="-b 0 -@" lopper.py ${DTS_FILE} -- baremetal_xparameters_xlnx.py ${ESW_MACHINE} ${S} + LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetal_xparameters_xlnx.py ${ESW_MACHINE} ${S} install -m 0755 xparameters.h ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb index 554e2636..09bf4192 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb @@ -16,7 +16,7 @@ EXTRA_OECMAKE:append:xilinx-freertos += "-Dlwip_api_mode=SOCKET_API" do_configure:prepend() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xtopology_g.c ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb index 6df33ea0..d5c90bba 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilffs xiltimer" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb index b3523ab7..e1af36e0 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilfpga" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb index baadc4e7..0fb74a63 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilmailbox" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } @@ -16,7 +16,7 @@ EXTRA_OECMAKE = "-DCUSTOM_LINKER_FILE=${@d.getVar('ESW_CUSTOM_LINKER_FILE')}" do_generate_eglist () { cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb index 4528fe98..7a931ed4 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilnvm" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb index ce56933c..64f49d71 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilpuf" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb index d8253e59..3c424215 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb @@ -6,7 +6,7 @@ DEPENDS += "xilsecure" do_configure:prepend() { cd ${S} - lopper.py ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb index 495fe6a8..447c3cc3 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb @@ -8,7 +8,7 @@ DEPENDS += "libgloss" do_configure:prepend() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- baremetal_bspconfig_xlnx ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} + lopper ${DTS_FILE} -- baremetal_bspconfig_xlnx ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 MemConfig.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.c ${S}/${ESW_COMPONENT_SRC}/common/ } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb index 3f93db74..0e25bbb7 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb @@ -8,6 +8,6 @@ DEPENDS += "libxil" do_configure:prepend() { # This script should also not rely on relative paths and such cd ${S} - lopper.py ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} + lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ } -- cgit v1.2.3-54-g00ecf From a57c38d7535e3d7907916eb8e420903d39e1631d Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 7 Mar 2022 11:56:24 -0800 Subject: dt-processor.sh: Add -l argument to write local.conf to a file The -l argument will write the local.conf fragment to a file of the user's choice. This can help automation that uses the dt-processor.sh. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 76 +++++++++++++--------- 1 file changed, 46 insertions(+), 30 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index d0b719cb..4dc9a3e7 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -39,6 +39,7 @@ $0 [-o ] Generate overlay dts [-e ] Apply a partial overlay [-m ] zynqmp or versal + [-l ] write local.conf changes to this file EOF exit @@ -47,7 +48,7 @@ EOF parse_args() { [ $# -eq 0 ] && usage - while getopts ":c:s:d:o:e:m:h" opt; do + while getopts ":c:s:d:o:e:m:l:h" opt; do case ${opt} in c) config_dir=$OPTARG ;; s) system_dtb=$OPTARG ;; @@ -55,6 +56,7 @@ parse_args() { d) domain_file=$OPTARG ;; e) external_fpga=$OPTARG ;; m) machine=$OPTARG ;; + l) localconf=$OPTARG ;; h) usage ;; :) error "Missing argument for -$OPTARG" ;; \?) error "Invalid option -$OPTARG" @@ -75,7 +77,7 @@ detect_machine() { pmc-microblaze | psm-microblaze) machine="versal" ;; esac - done > $1 + echo "BASE_TMPDIR = \"\${TOPDIR}\"" >> $1 + [ -n "${system_conf}" ] && echo "require ${system_conf}" >> $1 + echo "SYSTEM_DTFILE = \"${system_dtb}\"" >> $1 + echo "BBMULTICONFIG += \"${multiconf}\"" >> $1 if [ -n "${fsbl_mcdepends}" ]; then - echo "FSBL_DEPENDS = \"\"" - echo "FSBL_MCDEPENDS = \"${fsbl_mcdepends}\"" - echo "FSBL_DEPLOY_DIR = \"${fsbl_deploy_dir}\"" + echo "FSBL_DEPENDS = \"\"" >> $1 + echo "FSBL_MCDEPENDS = \"${fsbl_mcdepends}\"" >> $1 + echo "FSBL_DEPLOY_DIR = \"${fsbl_deploy_dir}\"" >> $1 fi if [ -n "${r5fsbl_mcdepends}" ]; then - echo "R5FSBL_DEPENDS = \"\"" - echo "R5FSBL_MCDEPENDS = \"${r5fsbl_mcdepends}\"" - echo "R5FSBL_DEPLOY_DIR = \"${r5fsbl_deploy_dir}\"" + echo "R5FSBL_DEPENDS = \"\"" >> $1 + echo "R5FSBL_MCDEPENDS = \"${r5fsbl_mcdepends}\"" >> $1 + echo "R5FSBL_DEPLOY_DIR = \"${r5fsbl_deploy_dir}\"" >> $1 fi if [ -n "${pmu_mcdepends}" ]; then - echo "PMU_DEPENDS = \"\"" - echo "PMU_MCDEPENDS = \"${pmu_mcdepends}\"" - echo "PMU_FIRMWARE_DEPLOY_DIR = \"${pmu_firmware_deploy_dir}\"" + echo "PMU_DEPENDS = \"\"" >> $1 + echo "PMU_MCDEPENDS = \"${pmu_mcdepends}\"" >> $1 + echo "PMU_FIRMWARE_DEPLOY_DIR = \"${pmu_firmware_deploy_dir}\"" >> $1 fi if [ -n "${plm_mcdepends}" ]; then - echo "PLM_DEPENDS = \"\"" - echo "PLM_MCDEPENDS = \"${plm_mcdepends}\"" - echo "PLM_DEPLOY_DIR = \"${plm_deploy_dir}\"" + echo "PLM_DEPENDS = \"\"" >> $1 + echo "PLM_MCDEPENDS = \"${plm_mcdepends}\"" >> $1 + echo "PLM_DEPLOY_DIR = \"${plm_deploy_dir}\"" >> $1 fi if [ -n "${psm_mcdepends}" ]; then - echo "PSM_DEPENDS = \"\"" - echo "PSM_MCDEPENDS = \"${psm_mcdepends}\"" - echo "PSM_FIRMWARE_DEPLOY_DIR = \"${psm_firmware_deploy_dir}\"" + echo "PSM_DEPENDS = \"\"" >> $1 + echo "PSM_MCDEPENDS = \"${psm_mcdepends}\"" >> $1 + echo "PSM_FIRMWARE_DEPLOY_DIR = \"${psm_firmware_deploy_dir}\"" >> $1 fi - [ "${machine}" = "versal" ] && echo "PDI_PATH = \"__PATH TO PDI FILE HERE__\"" + [ "${machine}" = "versal" ] && echo "PDI_PATH = \"__PATH TO PDI FILE HERE__\"" >> $1 echo } @@ -863,13 +862,16 @@ multiconf="" [ -z "${lopper}" ] && error "Unable to find lopper, please source the prestep environment" +cpulist=$(mktemp) + +priordir=$(pwd) # Generate CPU list cd "${config_dir}" || exit mkdir -p dtb multiconfig/includes ( cd dtb || error "Unable to cd to dtb dir" ${lopper} -f --enhanced -i "${lops_dir}/lop-xilinx-id-cpus.dts" "${system_dtb}" \ - /dev/null >"../cpu-list.tmp" || error "lopper failed" + /dev/null > ${cpulist} || error "lopper failed" rm -f "lop-xilinx-id-cpus.dts.dtb" ) @@ -877,7 +879,21 @@ detect_machine parse_cpus -gen_local_conf +cd ${priordir} +if [ -z "${localconf}" ]; then + echo + echo "To enable this, add the following to your local.conf:" + echo + tmpfile=$(mktemp) + gen_local_conf ${tmpfile} + cat $tmpfile + rm $tmpfile +else + echo + echo "Configuration for local.conf written to ${localconf}" + echo + gen_local_conf ${localconf} +fi # Cleanup our temp file -rm cpu-list.tmp +rm ${cpulist} -- cgit v1.2.3-54-g00ecf From ab41efb987fc0b016b10f27b9dd77420e7e3a000 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 7 Mar 2022 11:57:38 -0800 Subject: xilffs: Allow per recipe configuration The recipe can have: use_mkfs, read_only, and word_access specified as a per recipe configuration. Only read_only is enabled by default. Signed-off-by: Mark Hatle --- .../recipes-libraries/xilffs_git.bb | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb index 1ca8648b..0649d3d8 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb @@ -5,8 +5,9 @@ REQUIRED_DISTRO_FEATURES = "sdps" ESW_COMPONENT_SRC = "/lib/sw_services/xilffs/src/" ESW_COMPONENT_NAME = "libxilffs.a" -EXTRA_OECMAKE += "-DXILFFS_use_mkfs=OFF" -EXTRA_OECMAKE += "-DXILFFS_read_only=ON" -EXTRA_OECMAKE += "-DXILFFS_word_access=OFF" +PACKAGECONFIG ??= "read_only" +PACKAGECONFIG[use_mkfs] ="-DXILFFS_use_mkfs=ON,-DXILFFS_use_mkfs=OFF,," +PACKAGECONFIG[read_only] ="-DXILFFS_read_only=ON,-DXILFFS_read_only=OFF,," +PACKAGECONFIG[word_access]="-DXILFFS_word_access=ON,-DXILFFS_word_access=OFF,," DEPENDS += "xilstandalone libxil" -- cgit v1.2.3-54-g00ecf From f03941e1d98828e17d2bd9d6de56f61baa712f52 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 7 Mar 2022 18:05:43 -0800 Subject: device-tree: Allow the CONFIG_DTFILE to be a dts Instead of processing the CONFIG_DTFILE, process the converted (generated) DTB files. This resolves an issue where a user passes in a DTS, the system generated a DTB and attempts to install both the DTS and DTB triggering an unexpected file problem during package generation. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb index ddae03f5..13632bf8 100644 --- a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb +++ b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb @@ -39,13 +39,13 @@ DTB_FILE_NAME = "${@os.path.basename(d.getVar('CONFIG_DTFILE')).replace('.dts', DTB_BASE_NAME ?= "${MACHINE}-system${IMAGE_VERSION_SUFFIX}" do_install:prepend() { - for DTB_FILE in ${CONFIG_DTFILE}; do + for DTB_FILE in ${DTB_FILE_NAME}; do install -Dm 0644 ${DTB_FILE} ${D}/boot/devicetree/$(basename ${DTB_FILE}) done } devicetree_do_deploy:append() { - for DTB_FILE in ${CONFIG_DTFILE}; do + for DTB_FILE in ${DTB_FILE_NAME}; do install -Dm 0644 ${DTB_FILE} ${DEPLOYDIR}/devicetree/$(basename ${DTB_FILE}) done -- cgit v1.2.3-54-g00ecf From b0234dac80cd2016759650127e8bb4af1439f192 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 9 Mar 2022 13:16:52 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 663dace5..4c450ea2 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "02e43308abeb603e33f5f4c60f3a69548133f834" +SRCREV = "ffd6641c285c07b02382c8a3c2ca29a4c2406565" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index f3ed45a0..0c606100 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "e87376ce9ef6a386844e7c5d1f52f41348f18986" +SRCREV ?= "0499324af1178057c3730b0989c8fb5c5bbc4cf8" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index f8778ebd..51a0a677 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "7da7251ad605d4bc7e0fae5cb2bd927d1b7d6dea" +SRCREV = "52a9b22faeb149a6b17646b1f912f06ea6c269ca" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -- cgit v1.2.3-54-g00ecf From 9ee4ed5ea3925782bfee7a41f4be3075d2435307 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 9 Mar 2022 21:46:27 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 21f0ac7c..0aa4b6d0 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "b385865e2c6e642579520464428a0f0ae0fc312a" +ESW_REV[2022.2] = "706f63a40e6204ae2401f175c1561572bfe8c952" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From d4d55048764eab9eb3ae24b8ce7bcc5575d53fa7 Mon Sep 17 00:00:00 2001 From: rbramand Date: Tue, 8 Mar 2022 17:33:58 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index b9466b63..28df4cb4 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -2,8 +2,8 @@ REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -BRANCH= "master" -SRCREV= "bb871e556f9b8f6a57cbbac7d6b14c60b96422a2" +BRANCH= "2022.1" +SRCREV= "e98799314cbb15e3b174ab0f8b7ba66587d0412e" PV = "202210.2.13.0" -- cgit v1.2.3-54-g00ecf From ef543b3a8ee238e1e6ab2ec69019748e6fbb709d Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Mar 2022 13:22:03 -0800 Subject: dt-processor.sh: Remove SYSTEM_DTFILE Linux specific setting SYSTEM_DTFILE points to the original system-top.dts. CONFIG_DTFILE will point to the configuration specific device tree (dtb). Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 4 ---- 1 file changed, 4 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 4dc9a3e7..d7c37173 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -131,8 +131,6 @@ cortex_a53_linux() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" MACHINE = "${machine}-generic" -# Override the SYSTEM_DTFILE for Linux builds -SYSTEM_DTFILE:linux = "\${CONFIG_DTFILE}" # We don't want the kernel to build us a device-tree KERNEL_DEVICETREE:${machine}-generic = "" # We need u-boot to use the one we passed in @@ -306,8 +304,6 @@ cortex_a72_linux() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" MACHINE = "${machine}-generic" -# Override the SYSTEM_DTFILE for Linux builds -SYSTEM_DTFILE:linux = "\${CONFIG_DTFILE}" # We don't want the kernel to build us a device-tree KERNEL_DEVICETREE:${machine}-generic = "" # We need u-boot to use the one we passed in -- cgit v1.2.3-54-g00ecf From 4d2eceaeb6d0d659b8f1f84d16723dcd3dcd1b14 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Mar 2022 13:20:24 -0800 Subject: fsbl-firmware: Move to explicit psu_init settings The location for psu_init is now explicitly set. If the psu_init files are not available, a warning will be presented to the user. Signed-off-by: Mark Hatle --- .../embeddedsw/fsbl-firmware_git.bbappend | 32 +++++++++---------- .../recipes-core/meta/files/dt-processor.sh | 37 ++++++++++++++++++++-- 2 files changed, 51 insertions(+), 18 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend index 32174711..056ad990 100644 --- a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend +++ b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend @@ -15,23 +15,23 @@ ESW_COMPONENT_SRC:zynqmp = "/lib/sw_apps/zynqmp_fsbl/src" DEPENDS += "xilstandalone xiltimer xilffs xilsecure xilpm" -do_copy_psu_init[depends] += "device-tree:do_deploy" -python do_copy_psu_init() { - import glob, subprocess, os - - system_dt = d.getVar('SYSTEM_DTFILE') - src_dir = glob.glob(d.getVar('OECMAKE_SOURCEPATH')) - psu_init_src = os.path.dirname(system_dt) - src_file = psu_init_src + str("/psu_init.c") - hdr_file = psu_init_src + str("/psu_init.h") - if os.path.exists(src_file): - command = ["install"] + ["-m"] + ["0755"] + [src_file] + [src_dir[0]] - subprocess.run(command, check = True) - command = ["install"] + ["-m"] + ["0755"] + [hdr_file] + [src_dir[0]] - subprocess.run(command, check = True) +python() { + psu_init_path = d.getVar('PSU_INIT_PATH') + if not psu_init_path: + psu_init_path = os.path.dirname(d.getVar('SYSTEM_DTFILE')) + + psu_init_c = os.path.join(psu_init_path, 'psu_init.c') + psu_init_h = os.path.join(psu_init_path, 'psu_init.h') + + if os.path.exists(psu_init_c): + d.appendVar('SRC_URI', ' file://%s' % psu_init_c) + else: + bb.warn("Unable to find %s, using default version" % psu_init_c) + if os.path.exists(psu_init_h): + d.appendVar('SRC_URI', ' file://%s' % psu_init_h) + else: + bb.warn("Unable to find %s, using default version" % psu_init_h) } -addtask do_copy_psu_init before do_configure after do_prepare_recipe_sysroot -do_prepare_recipe_sysroot[rdeptask] = "do_unpack" do_install() { : diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index d7c37173..e44f1e83 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -39,6 +39,7 @@ $0 [-o ] Generate overlay dts [-e ] Apply a partial overlay [-m ] zynqmp or versal + [-p ] Path to psu_init files, defaults to system_dtb path [-l ] write local.conf changes to this file EOF @@ -56,6 +57,7 @@ parse_args() { d) domain_file=$OPTARG ;; e) external_fpga=$OPTARG ;; m) machine=$OPTARG ;; + p) psu_init_path=$OPTARG ;; l) localconf=$OPTARG ;; h) usage ;; :) error "Missing argument for -$OPTARG" ;; @@ -65,6 +67,9 @@ parse_args() { [ -f "${config_dir}/local.conf" ] || error "Invalid config dir: ${config_dir}" [ -f "${system_dtb}" ] || error "Unable to find: ${system_dtb}" + if [ -z "$psu_init_path" ]; then + psu_init_path=$(dirname ${system_dtb}) + fi } detect_machine() { @@ -195,7 +200,21 @@ cortex_a53_baremetal() { mv libxil.conf "${libxil}" mv distro.conf "${distro}" - cat <"${conf_file}" + if [ "$1" = "fsbl" ]; then + if [ ! -e "${psu_init_path}/psu_init.c" ]; then + warn "Warning: Unable to find psu_init.c in ${psu_init_path}" + fi + if [ ! -e "${psu_init_path}/psu_init.h" ]; then + warn "Warning: Unable to find psu_init.h in ${psu_init_path}" + fi + + cat <"${conf_file}" +PSU_INIT_PATH = "${psu_init_path}" +EOF + else + cat /dev/null >"${conf_file}" + fi + cat <>"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" ESW_MACHINE = "cortexa53-${machine}" DEFAULTTUNE = "cortexa53" @@ -472,7 +491,21 @@ cortex_r5_baremetal() { mv libxil.conf "${libxil}" mv distro.conf "${distro}" - cat <"${conf_file}" + if [ "$1" = "fsbl" ]; then + if [ ! -e "${psu_init_path}/psu_init.c" ]; then + warn "Warning: Unable to find psu_init.c in ${psu_init_path}" + fi + if [ ! -e "${psu_init_path}/psu_init.h" ]; then + warn "Warning: Unable to find psu_init.h in ${psu_init_path}" + fi + + cat <"${conf_file}" +PSU_INIT_PATH = "${psu_init_path}" +EOF + else + cat /dev/null >"${conf_file}" + fi + cat <>"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" ESW_MACHINE = "cortexr5-${machine}" DEFAULTTUNE = "cortexr5" -- cgit v1.2.3-54-g00ecf From 5bd416526195607a20ddbb5e38d85417a5790f29 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Mar 2022 16:29:19 -0800 Subject: dt-processor: Avoid warning messages for baremetal Baremetal doesn't use tpm, virtualization or security layers. Avoid the checks, as these layers are often used by the Linux configuration. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index e44f1e83..4aba672d 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -225,6 +225,10 @@ DISTRO = "${yocto_distro}" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -277,6 +281,10 @@ DISTRO = "xilinx-freertos" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -383,6 +391,10 @@ DISTRO = "xilinx-standalone-nolto" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -435,6 +447,10 @@ DISTRO = "xilinx-freertos" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -516,6 +532,10 @@ DISTRO = "$yocto_distro" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -568,6 +588,10 @@ DISTRO = "xilinx-freertos" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -637,6 +661,10 @@ DISTRO = "xilinx-standalone" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -689,6 +717,10 @@ DISTRO = "xilinx-standalone" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } @@ -741,6 +773,10 @@ DISTRO = "xilinx-standalone" LIBXIL_CONFIG = "conf/${libxil}" require conf/${distro} + +SKIP_META_VIRT_SANITY_CHECK = "1" +SKIP_META_SECURITY_SANITY_CHECK = "1" +SKIP_META_TPM_SANITY_CHECK = "1" EOF } -- cgit v1.2.3-54-g00ecf From f9d632a99fffc46b3c8bc55f3e38b82d63905804 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Mar 2022 16:46:00 -0800 Subject: Revert "device-tree: Allow the CONFIG_DTFILE to be a dts" This reverts commit f03941e1d98828e17d2bd9d6de56f61baa712f52. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb index 13632bf8..ddae03f5 100644 --- a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb +++ b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb @@ -39,13 +39,13 @@ DTB_FILE_NAME = "${@os.path.basename(d.getVar('CONFIG_DTFILE')).replace('.dts', DTB_BASE_NAME ?= "${MACHINE}-system${IMAGE_VERSION_SUFFIX}" do_install:prepend() { - for DTB_FILE in ${DTB_FILE_NAME}; do + for DTB_FILE in ${CONFIG_DTFILE}; do install -Dm 0644 ${DTB_FILE} ${D}/boot/devicetree/$(basename ${DTB_FILE}) done } devicetree_do_deploy:append() { - for DTB_FILE in ${DTB_FILE_NAME}; do + for DTB_FILE in ${CONFIG_DTFILE}; do install -Dm 0644 ${DTB_FILE} ${DEPLOYDIR}/devicetree/$(basename ${DTB_FILE}) done -- cgit v1.2.3-54-g00ecf From 1d7d956ce3fb7b5aba76c9798e669ea64f61e223 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 8 Mar 2022 17:32:20 -0800 Subject: device-tree: Allow the CONFIG_DTFILE to be a dts and cleanup Cleanup the conditionals, as only one file is allowed to be specified. Also use the converted version so if a dts is passed in, the dtb will be installed after it is generated. Signed-off-by: Mark Hatle --- .../recipes-bsp/device-tree/device-tree.bb | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb index ddae03f5..c5bd75c6 100644 --- a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb +++ b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb @@ -11,10 +11,6 @@ LIC_FILES_CHKSUM = " \ inherit devicetree image-artifact-names -#this way of going through SRC_URI is better but if dts is including other dtsis, need to add all of them to SRC_URI.. -#SRC_URI += "file://${CONFIG_DTFILE}" -#DT_FILES_PATH = "${@d.getVar('WORKDIR')+'/'+os.path.dirname(d.getVar('CONFIG_DTFILE'))}" - # Fall back to SYSTEM_DTFILE if specified... # CONFIG_DTFILE is intended to hold a specific configuration's (multiconfig) # device tree, while SYSTEM_DTFILE is used for the full heterogenous @@ -39,17 +35,20 @@ DTB_FILE_NAME = "${@os.path.basename(d.getVar('CONFIG_DTFILE')).replace('.dts', DTB_BASE_NAME ?= "${MACHINE}-system${IMAGE_VERSION_SUFFIX}" do_install:prepend() { - for DTB_FILE in ${CONFIG_DTFILE}; do - install -Dm 0644 ${DTB_FILE} ${D}/boot/devicetree/$(basename ${DTB_FILE}) - done + if [ -n "${DTB_FILE_NAME}" ]; then + # If it's already a dtb, we have to copy from the original location + if [ -e "${DT_FILES_PATH}/${DTB_FILE_NAME}" ]; then + install -Dm 0644 ${DT_FILES_PATH}/${DTB_FILE_NAME} ${D}/boot/devicetree/${DTB_FILE_NAME} + fi + fi } devicetree_do_deploy:append() { - for DTB_FILE in ${CONFIG_DTFILE}; do - install -Dm 0644 ${DTB_FILE} ${DEPLOYDIR}/devicetree/$(basename ${DTB_FILE}) - done - if [ -n "${DTB_FILE_NAME}" ]; then + # If it's already a dtb, we have to copy from the original location + if [ -e "${DT_FILES_PATH}/${DTB_FILE_NAME}" ]; then + install -Dm 0644 ${DT_FILES_PATH}/${DTB_FILE_NAME} ${DEPLOYDIR}/devicetree/${DTB_FILE_NAME} + fi if [ -e "${DEPLOYDIR}/devicetree/${DTB_FILE_NAME}" ]; then # We need the output to be system.dtb for WIC setup to match XSCT flow ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/${DTB_BASE_NAME}.dtb -- cgit v1.2.3-54-g00ecf From bc23fe5c5b810a7821f0de76d71b6093a05fa509 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 9 Mar 2022 09:58:18 -0800 Subject: gdb: Disable on-target GDB for microblaze Failure: ../../gdb-10.2/bfd/cpu-microblaze.c:75:1: warning: missing initializer for field 'max_reloc_offset_into_insn' of 'bfd_arch_info_type' {aka 'const struct bfd_arch_info'} [-Wmissing-field-initializers] | 75 | }, | | ^ | In file included from ../../gdb-10.2/bfd/cpu-microblaze.c:23: | ./bfd.h:1998:14: note: 'max_reloc_offset_into_insn' declared here | 1998 | signed int max_reloc_offset_into_insn; | | ^~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Mark Hatle --- meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend b/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend index 33fbe158..23866471 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend +++ b/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend @@ -1,4 +1,11 @@ MICROBLAZEPATCHES = "" MICROBLAZEPATCHES:microblaze = "gdb-microblaze.inc" +# We don't have ptrace support for on-target microblaze GDB currently. Need +# to use tcf-agent or other external debug interface. +MB_DOES_NOT_WORK = "" +MB_DOES_NOT_WORK:microblaze = "GDB is not currently supported on Microblaze." + +PNBLACKLIST[gdb] = "${MB_DOES_NOT_WORK}" + require ${MICROBLAZEPATCHES} -- cgit v1.2.3-54-g00ecf From 2d67acae484e2b2100db6cb35b0e6566722f6ade Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 9 Mar 2022 09:58:18 -0800 Subject: ltp: Disable ltp gdb dependency only on Microblaze On-target gdb does not work on microblaze, disable the dependency. This may affect certain ltp test cases. Signed-off-by: Mark Hatle --- meta-microblaze/recipes-extended/ltp/ltp_%.bbappend | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 meta-microblaze/recipes-extended/ltp/ltp_%.bbappend diff --git a/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend b/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend new file mode 100644 index 00000000..85bcc731 --- /dev/null +++ b/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend @@ -0,0 +1,2 @@ +# gdb on-target is not supported on Microblaze +RDEPENDS:${PN}:remove:microblaze = "gdb" -- cgit v1.2.3-54-g00ecf From 1116c944d91e82a94fefc7bd05d1506a1e10e47d Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Thu, 10 Mar 2022 01:39:34 +0100 Subject: device-tree: Remove ultra96 mipi device tree files The ultra96 harwdare design is updated to not include mipi anymore. Remove the corresponding SRC_URI and do_configure appends. Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- .../recipes-bsp/device-tree/device-tree.bbappend | 8 -------- 1 file changed, 8 deletions(-) diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index f236e4b8..f3c932db 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -1,4 +1,3 @@ -SRC_URI:append:ultra96 = "${@bb.utils.contains('MACHINE_FEATURES', 'mipi', ' file://mipi-support-ultra96.dtsi file://pl.dtsi', '', d)}" YAML_MAIN_MEMORY_CONFIG:ultra96 ?= "psu_ddr_0" YAML_CONSOLE_DEVICE_CONFIG:ultra96 ?= "psu_uart_1" YAML_DT_BOARD_FLAGS:ultra96 ?= "{BOARD avnet-ultra96-rev1}" @@ -39,10 +38,3 @@ YAML_DT_BOARD_FLAGS:zcu670 ?= "{BOARD zcu670-revb}" YAML_DT_BOARD_FLAGS:vpk120 ?= "{BOARD versal-vpk120-reva}" YAML_DT_BOARD_FLAGS:vpk-sc ?= "{BOARD zynqmp-vpk120-reva}" -do_configure:append:ultra96() { - if [ -e ${WORKDIR}/mipi-support-ultra96.dtsi ]; then - cp ${WORKDIR}/mipi-support-ultra96.dtsi ${DT_FILES_PATH}/mipi-support-ultra96.dtsi - cp ${WORKDIR}/pl.dtsi ${DT_FILES_PATH}/pl.dtsi - echo '/include/ "mipi-support-ultra96.dtsi"' >> ${DT_FILES_PATH}/${BASE_DTS}.dts - fi -} -- cgit v1.2.3-54-g00ecf From b02fce6cccdcf61665a3b13143f03dba7e685220 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 12 Mar 2022 13:16:41 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 4c450ea2..37f36915 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "ffd6641c285c07b02382c8a3c2ca29a4c2406565" +SRCREV = "0ae9ba138b625072d80c837560760b075bbdfd4e" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 7e97486b..bae36b8d 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "ef4ac9cad9406e869e7c20191f3a3b0bb9663d81" +SRCREV = "f35044ea63711d00090f38116a67ffe51ddcea8c" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 0c6017795ba1499cb6b6aaab67a78f10a71dbdd3 Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Fri, 11 Mar 2022 19:27:19 +0530 Subject: Updated SRCREV for 2022.1 Signed-off-by: Siva Addepalli Backported 2022.1 change to 2022.2 Signed-off-by: Mark Hatle --- .../vcu/files/0001-fix-timestamps-issues.patch | 99 ++++++++++++++++++++++ .../recipes-multimedia/vcu/libomxil-xlnx.bb | 3 + 2 files changed, 102 insertions(+) create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch diff --git a/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch b/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch new file mode 100644 index 00000000..c5521cca --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch @@ -0,0 +1,99 @@ +From b3308c608be7ed9250b9c6732f6e0a02b1a2e985 Mon Sep 17 00:00:00 2001 +From: Arthur Vinchon +Date: Wed, 2 Mar 2022 02:29:48 +0530 +Subject: [PATCH] fix: timestamps issues + +Acked-by:Varunkumar Allagadapa +--- + base/omx_component/omx_component_dec.cpp | 32 ++++++++++++++---------- + base/omx_component/omx_component_dec.h | 2 +- + 2 files changed, 20 insertions(+), 14 deletions(-) + +diff --git a/base/omx_component/omx_component_dec.cpp b/base/omx_component/omx_component_dec.cpp +index 137bf2f..b40c770 100644 +--- a/base/omx_component/omx_component_dec.cpp ++++ b/base/omx_component/omx_component_dec.cpp +@@ -58,7 +58,8 @@ static DecModule& ToDecModule(ModuleInterface& module) + + DecComponent::DecComponent(OMX_HANDLETYPE component, shared_ptr media, std::unique_ptr&& module, OMX_STRING name, OMX_STRING role, std::unique_ptr&& expertise) : + Component{component, media, std::move(module), std::move(expertise), name, role}, +- shouldPropagateData{true}, oldTimeStamp{-1} ++ oldTimeStamp{-1}, ++ dataHasBeenPropagated{false} + { + } + +@@ -77,8 +78,9 @@ void DecComponent::FlushComponent() + FlushFillEmptyBuffers(true, true); + std::unique_lock lock(mutex); + transmit.clear(); ++ oldTimeStamp = -1; ++ dataHasBeenPropagated = false; + lock.unlock(); +- shouldPropagateData = true; + } + + void DecComponent::AssociateCallBack(BufferHandleInterface* empty_, BufferHandleInterface* fill_) +@@ -104,8 +106,8 @@ void DecComponent::AssociateCallBack(BufferHandleInterface* empty_, BufferHandle + { + callbacks.EventHandler(component, app, OMX_EventBufferFlag, output.index, emptyHeader.nFlags, nullptr); + transmit.clear(); +- shouldPropagateData = true; + oldTimeStamp = -1; ++ dataHasBeenPropagated = false; + } + + if(IsCompMarked(emptyHeader.hMarkTargetComponent, component)) +@@ -351,22 +353,26 @@ void DecComponent::TreatEmptyBufferCommand(Task* task) + + if(!isInputParsed || isEarlyCallbackUsed) + { +- bool isEndOfFrameFlagRaised = (header->nFlags & OMX_BUFFERFLAG_ENDOFFRAME); ++ /* we suppose that a timestamp changes is a frame changes [concealment] */ ++ bool const transmitTimeStamp = (oldTimeStamp != header->nTimeStamp); + +- if(isEndOfFrameFlagRaised && !isEarlyCallbackUsed) ++ if(transmitTimeStamp) ++ { + transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); ++ oldTimeStamp = header->nTimeStamp; ++ dataHasBeenPropagated = true; ++ } + else + { +- /* Concealment case(header->nFlags EndOfFrame is missing): propagate data if timestamps differ */ +- shouldPropagateData |= (oldTimeStamp != header->nTimeStamp); +- +- if(shouldPropagateData) ++ bool isEndOfFrameFlagRaised = (header->nFlags & OMX_BUFFERFLAG_ENDOFFRAME); ++ if(isEndOfFrameFlagRaised) + { +- transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); +- oldTimeStamp = header->nTimeStamp; ++ if(!dataHasBeenPropagated) ++ { ++ transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); ++ } ++ dataHasBeenPropagated = false; + } +- +- shouldPropagateData = isEndOfFrameFlagRaised; + } + } + +diff --git a/base/omx_component/omx_component_dec.h b/base/omx_component/omx_component_dec.h +index 6214856..07d062e 100644 +--- a/base/omx_component/omx_component_dec.h ++++ b/base/omx_component/omx_component_dec.h +@@ -76,7 +76,7 @@ private: + void TreatEmptyBufferCommand(Task* task) override; + std::list transmit; + std::mutex mutex; +- bool shouldPropagateData; + OMX_TICKS oldTimeStamp; ++ bool dataHasBeenPropagated; + }; + +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb index f86fc3ed..2a0e49b4 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb @@ -13,6 +13,9 @@ SRCREV = "a9d452e772da6bc43f524230c79e6dc0f2442fd7" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" +# Sync to 2022.1 version +SRC_URI += "file://0001-fix-timestamps-issues.patch" + S = "${WORKDIR}/git" COMPATIBLE_MACHINE = "^$" -- cgit v1.2.3-54-g00ecf From 8fd76305620284debfc0a4506d8e3386991c0870 Mon Sep 17 00:00:00 2001 From: rbramand Date: Mon, 14 Mar 2022 16:41:12 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 28df4cb4..056c5940 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "2022.1" -SRCREV= "e98799314cbb15e3b174ab0f8b7ba66587d0412e" +SRCREV= "445d6db8407b8375b9b870befa84db2f234a25e8" PV = "202210.2.13.0" diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index 7cb9b185..6ba6beab 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -18,19 +18,23 @@ inherit cmake BBCLASSEXTEND = "native nativesdk" # util-linux is for libuuid-dev. -DEPENDS = "libdrm opencl-headers ocl-icd opencl-clhpp boost util-linux git-replacement-native protobuf-native protobuf elfutils libffi" +DEPENDS = "libdrm opencl-headers ocl-icd opencl-clhpp boost util-linux git-replacement-native protobuf-native protobuf elfutils libffi rapidjson" RDEPENDS:${PN} = "bash ocl-icd boost-system boost-filesystem zocl" EXTRA_OECMAKE += " \ -DCMAKE_BUILD_TYPE=Release \ -DCMAKE_EXPORT_COMPILE_COMANDS=ON \ " - PACKAGE_ARCH:versal-ai-core = "${SOC_VARIANT_ARCH}" EXTRA_OECMAKE:append:versal-ai-core += "-DXRT_AIE_BUILD=true" TARGET_CXXFLAGS:append:versal-ai-core += "-DXRT_ENABLE_AIE" DEPENDS:append:versal-ai-core += " libmetal libxaiengine aiefal" RDEPENDS:${PN}:append:versal-ai-core += " libxaiengine aiefal" +EXTRA_OECMAKE:append:versal += "-DXRT_LIBDFX=true" +EXTRA_OECMAKE:append:zynqmp += "-DXRT_LIBDFX=true" +DEPENDS:append:versal += "libdfx" +DEPENDS:append:zynqmp += "libdfx" + FILES_SOLIBSDEV = "" FILES:${PN} += "\ -- cgit v1.2.3-54-g00ecf From bee4893778edbb935867cfae50825544a53d0cb9 Mon Sep 17 00:00:00 2001 From: John Toomey Date: Mon, 14 Mar 2022 16:30:20 +0000 Subject: Enable ProvenCore in ATF with MACHINE_FEATURES The ProvenCore secure OS required changes have been merged into the ATF repo but require extra settings to be passed in order to enable it. When "provencore" is found in MACHINE_FEATURES the required settings are passed using EXTRA_OEMAKE. Signed-off-by: John Toomey Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 4011ddfe..5b2a6498 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -68,6 +68,9 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" +ATF_PROVENCORE = "SPD=pncd ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x10000000 PRELOADED_BL33_BASE=0x80000000" +EXTRA_OEMAKE:append = "${@bb.utils.contains('COMBINED_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" + do_configure() { oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} } -- cgit v1.2.3-54-g00ecf From db42f007e2cc89d98c55b5ca8a51ed22ea4c6090 Mon Sep 17 00:00:00 2001 From: Vikram Sreenivasa Batchali Date: Tue, 15 Mar 2022 03:06:20 +0530 Subject: pmu-firmware_%.bbappend: Move k26 configuration to meta-som Signed-off-by: Vikram Sreenivasa Batchali Remove the k26 configuration. New configuration in meta-som. Signed-off-by: Mark Hatle --- .../meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 1 - 1 file changed, 1 deletion(-) diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend index 56cede1a..e925d608 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend @@ -1,4 +1,3 @@ ULTRA96_VERSION ?= "1" YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" -YAML_COMPILER_FLAGS:append:k26 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 -DENABLE_EM -DENABLE_MOD_OVERTEMP -DOVERTEMP_DEGC=90.0 -DENABLE_DYNAMIC_MIO_CONFIG -DENABLE_IOCTL" -- cgit v1.2.3-54-g00ecf From 8f07556504b8b27f2381d2787c6f27762386bc46 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 17 Mar 2022 12:17:06 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index bae36b8d..ec014354 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "f35044ea63711d00090f38116a67ffe51ddcea8c" +SRCREV = "ae78bf6ba89f388361c223b89aed350b5ceee971" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 533fb1625481f46d214474507192e965062d7aba Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 16 Mar 2022 14:41:37 -0700 Subject: u-boot-xlnx: oe-core now provides an xxd-native if required Remove host-tool requirement, switch to using Yocto Project provided xxd-native, provided by vim-native. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/layer.conf | 2 -- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf index bb2c5de7..e8b5ebd4 100644 --- a/meta-xilinx-core/conf/layer.conf +++ b/meta-xilinx-core/conf/layer.conf @@ -43,5 +43,3 @@ SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS += " \ " XILINX_RELEASE_VERSION = "v2022.2" - -HOSTTOOLS += "xxd" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index c41a4bad..d9113cc7 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -1,6 +1,6 @@ require recipes-bsp/u-boot/u-boot.inc -DEPENDS += "bc-native dtc-native bison-native" +DEPENDS += "bc-native dtc-native bison-native xxd-native" XILINX_RELEASE_VERSION ?= "" UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" -- cgit v1.2.3-54-g00ecf From 0d663f82b6c8858e667449c99a54c219ebe7caad Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 18 Mar 2022 07:35:34 -0700 Subject: iproute2: Provide 5.15.0 version, taken from Yocto Project master Yocto Project master, commit: 93c449d6b2d1436b529c084cffca6b9a477f4b3b commit 93c449d6b2d1436b529c084cffca6b9a477f4b3b (HEAD) Author: wangmy Date: Tue Nov 9 23:02:42 2021 +0800 iproute2: upgrade 5.14.0 -> 5.15.0 (From OE-Core rev: 609fd71c5d132b77072f1eb0cc4fe94370371eff) Signed-off-by: Wang Mingyu Signed-off-by: Richard Purdie Signed-off-by: Mark Hatle --- .../recipes-connectivity/iproute2/iproute2.inc | 91 ++++++++++++++++++++++ .../0001-libc-compat.h-add-musl-workaround.patch | 39 ++++++++++ .../iproute2/iproute2_5.15.0.bb | 11 +++ 3 files changed, 141 insertions(+) create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2.inc create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-libc-compat.h-add-musl-workaround.patch create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2.inc b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2.inc new file mode 100644 index 00000000..3f070d67 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2.inc @@ -0,0 +1,91 @@ +SUMMARY = "TCP / IP networking and traffic control utilities" +DESCRIPTION = "Iproute2 is a collection of utilities for controlling \ +TCP / IP networking and traffic control in Linux. Of the utilities ip \ +and tc are the most important. ip controls IPv4 and IPv6 \ +configuration and tc stands for traffic control." +HOMEPAGE = "http://www.linuxfoundation.org/collaborate/workgroups/networking/iproute2" +SECTION = "base" +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://COPYING;md5=eb723b61539feef013de476e68b5c50a \ + file://ip/ip.c;beginline=3;endline=8;md5=689d691d0410a4b64d3899f8d6e31817" + +DEPENDS = "flex-native bison-native iptables libcap" + +inherit update-alternatives bash-completion pkgconfig + +CLEANBROKEN = "1" + +PACKAGECONFIG ??= "tipc elf devlink" +PACKAGECONFIG[tipc] = ",,libmnl," +PACKAGECONFIG[elf] = ",,elfutils," +PACKAGECONFIG[devlink] = ",,libmnl," +PACKAGECONFIG[rdma] = ",,libmnl," + +IPROUTE2_MAKE_SUBDIRS = "lib tc ip bridge misc genl ${@bb.utils.filter('PACKAGECONFIG', 'devlink tipc rdma', d)}" + +EXTRA_OEMAKE = "\ + CC='${CC}' \ + KERNEL_INCLUDE=${STAGING_INCDIR} \ + DOCDIR=${docdir}/iproute2 \ + SUBDIRS='${IPROUTE2_MAKE_SUBDIRS}' \ + SBINDIR='${base_sbindir}' \ + LIBDIR='${libdir}' \ +" + +do_configure:append () { + sh configure ${STAGING_INCDIR} + # Explicitly disable ATM support + sed -i -e '/TC_CONFIG_ATM/d' config.mk +} + +do_install () { + oe_runmake DESTDIR=${D} install + mv ${D}${base_sbindir}/ip ${D}${base_sbindir}/ip.iproute2 + install -d ${D}${datadir} + mv ${D}/share/* ${D}${datadir}/ || true + rm ${D}/share -rf || true +} + +# The .so files in iproute2-tc are modules, not traditional libraries +INSANE_SKIP:${PN}-tc = "dev-so" + +IPROUTE2_PACKAGES =+ "\ + ${PN}-devlink \ + ${PN}-genl \ + ${PN}-ifstat \ + ${PN}-ip \ + ${PN}-lnstat \ + ${PN}-nstat \ + ${PN}-rtacct \ + ${PN}-ss \ + ${PN}-tc \ + ${PN}-tipc \ + ${PN}-rdma \ +" + +PACKAGE_BEFORE_PN = "${IPROUTE2_PACKAGES}" +RDEPENDS:${PN} += "${PN}-ip" + +FILES:${PN}-tc = "${base_sbindir}/tc* \ + ${libdir}/tc/*.so" +FILES:${PN}-lnstat = "${base_sbindir}/lnstat \ + ${base_sbindir}/ctstat \ + ${base_sbindir}/rtstat" +FILES:${PN}-ifstat = "${base_sbindir}/ifstat" +FILES:${PN}-ip = "${base_sbindir}/ip.${PN} ${sysconfdir}/iproute2" +FILES:${PN}-genl = "${base_sbindir}/genl" +FILES:${PN}-rtacct = "${base_sbindir}/rtacct" +FILES:${PN}-nstat = "${base_sbindir}/nstat" +FILES:${PN}-ss = "${base_sbindir}/ss" +FILES:${PN}-tipc = "${base_sbindir}/tipc" +FILES:${PN}-devlink = "${base_sbindir}/devlink" +FILES:${PN}-rdma = "${base_sbindir}/rdma" + +ALTERNATIVE:${PN}-ip = "ip" +ALTERNATIVE_TARGET[ip] = "${base_sbindir}/ip.${BPN}" +ALTERNATIVE_LINK_NAME[ip] = "${base_sbindir}/ip" +ALTERNATIVE_PRIORITY = "100" + +ALTERNATIVE:${PN}-tc = "tc" +ALTERNATIVE_LINK_NAME[tc] = "${base_sbindir}/tc" +ALTERNATIVE_PRIORITY_${PN}-tc = "100" diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-libc-compat.h-add-musl-workaround.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-libc-compat.h-add-musl-workaround.patch new file mode 100644 index 00000000..74e3de1c --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-libc-compat.h-add-musl-workaround.patch @@ -0,0 +1,39 @@ +From c25f8d1f7a6203dfeb10b39f80ffd314bb84a58d Mon Sep 17 00:00:00 2001 +From: Baruch Siach +Date: Thu, 22 Dec 2016 15:26:30 +0200 +Subject: [PATCH] libc-compat.h: add musl workaround + +The libc-compat.h kernel header uses glibc specific macros (__GLIBC__ and +__USE_MISC) to solve conflicts with libc provided headers. This patch makes +libc-compat.h work for musl libc as well. + +Upstream-Status: Pending + +Taken From: +https://git.buildroot.net/buildroot/tree/package/iproute2/0001-Add-the-musl-workaround-to-the-libc-compat.h-copy.patch + +Signed-off-by: Baruch Siach +Signed-off-by: Maxin B. John + +--- + include/uapi/linux/libc-compat.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/include/uapi/linux/libc-compat.h b/include/uapi/linux/libc-compat.h +index a159991..22198fa 100644 +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -50,10 +50,12 @@ + #define _LIBC_COMPAT_H + + /* We have included glibc headers... */ +-#if defined(__GLIBC__) ++#if 1 ++#define __USE_MISC + + /* Coordinate with glibc net/if.h header. */ + #if defined(_NET_IF_H) && defined(__USE_MISC) ++#define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 0 + + /* GLIBC headers included first so don't define anything + * that would already be defined. */ diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb new file mode 100644 index 00000000..99a74339 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb @@ -0,0 +1,11 @@ +require iproute2.inc + +SRC_URI = "${KERNELORG_MIRROR}/linux/utils/net/${BPN}/${BP}.tar.xz \ + file://0001-libc-compat.h-add-musl-workaround.patch \ + " + +SRC_URI[sha256sum] = "38e3e4a5f9a7f5575c015027a10df097c149111eeb739993128e5b2b35b291ff" + +# CFLAGS are computed in Makefile and reference CCOPTS +# +EXTRA_OEMAKE:append = " CCOPTS='${CFLAGS}'" -- cgit v1.2.3-54-g00ecf From 1363cfc1a1819a3d6afaac5d9a395b75599c6148 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 18 Mar 2022 08:27:45 -0700 Subject: iproute2: Add backport of iplink CAN changes Signed-off-by: Mark Hatle --- ...fix-configuration-ranges-in-print_usage-a.patch | 138 +++++++ ...nk_can-code-refactoring-of-print_ctrlmode.patch | 113 ++++++ ...use-PRINT_ANY-to-factorize-code-and-fix-s.patch | 447 +++++++++++++++++++++ ...an-print-brp-and-dbrp-bittiming-variables.patch | 53 +++ .../iproute2/iproute2_5.15.0.bb | 4 + 5 files changed, 755 insertions(+) create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch create mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch new file mode 100644 index 00000000..28542305 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch @@ -0,0 +1,138 @@ +From 8316df6e6db4de2f20b7fa976a6d4f9992dda7b1 Mon Sep 17 00:00:00 2001 +From: Vincent Mailhol +Date: Thu, 4 Nov 2021 01:44:24 +0900 +Subject: [PATCH 1/5] iplink_can: fix configuration ranges in print_usage() and + add unit + +The configuration ranges in print_usage() are taken from "Table 8 - +Time segments' minimum configuration ranges" in section 11.3.1.2 +"Configuration of the bit time parameters" of ISO 11898-1. + +The standard clearly specifies that "implementations may allow time +segments that exceed the minimum required configuration ranges +specified in Table 8". + +Because no maximum ranges are given in the standard, all given ranges +{ a..b } are simply replaced with { NUMBER }. + +The actual ranges are specific to each device and can be confirmed +doing: + +$ ip --details link show can0 +1: can0: mtu 16 qdisc noop state DOWN mode DEFAULT group default qlen 10 + link/can promiscuity 0 minmtu 0 maxmtu 0 + can state STOPPED restart-ms 0 + ES582.1/ES584.1: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp-inc 1 + ES582.1/ES584.1: dtseg1 2..32 dtseg2 1..16 dsjw 1..8 dbrp 1..32 dbrp-inc 1 + clock 80000000 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 + +Finally, the unit (bps, tq, ns or ms) are given. The rationale to add +the units is that the TDC parameters (that will be introduced in the +upcoming patches) are measured in a different unit than the other +bittiming parameters: clock period (a.k.a. minimum time quantum) +instead of time quantum. Adding the units disambiguates things. + +For reference, before the change: +$ ip link set can0 type can help +Usage: ip link set DEVICE type can + [ bitrate BITRATE [ sample-point SAMPLE-POINT] ] | + [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1 + phase-seg2 PHASE-SEG2 [ sjw SJW ] ] + + [ dbitrate BITRATE [ dsample-point SAMPLE-POINT] ] | + [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1 + dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ] + + [ loopback { on | off } ] + [ listen-only { on | off } ] + [ triple-sampling { on | off } ] + [ one-shot { on | off } ] + [ berr-reporting { on | off } ] + [ fd { on | off } ] + [ fd-non-iso { on | off } ] + [ presume-ack { on | off } ] + + [ restart-ms TIME-MS ] + [ restart ] + + [ termination { 0..65535 } ] + + Where: BITRATE := { 1..1000000 } + SAMPLE-POINT := { 0.000..0.999 } + TQ := { NUMBER } + PROP-SEG := { 1..8 } + PHASE-SEG1 := { 1..8 } + PHASE-SEG2 := { 1..8 } + SJW := { 1..4 } + RESTART-MS := { 0 | NUMBER } + +...and after it: +$ ip link set can0 type can help +Usage: ip link set DEVICE type can + [ bitrate BITRATE [ sample-point SAMPLE-POINT] ] | + [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1 + phase-seg2 PHASE-SEG2 [ sjw SJW ] ] + + [ dbitrate BITRATE [ dsample-point SAMPLE-POINT] ] | + [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1 + dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ] + + [ loopback { on | off } ] + [ listen-only { on | off } ] + [ triple-sampling { on | off } ] + [ one-shot { on | off } ] + [ berr-reporting { on | off } ] + [ fd { on | off } ] + [ fd-non-iso { on | off } ] + [ presume-ack { on | off } ] + [ cc-len8-dlc { on | off } ] + + [ restart-ms TIME-MS ] + [ restart ] + + [ termination { 0..65535 } ] + + Where: BITRATE := { NUMBER in bps } + SAMPLE-POINT := { 0.000..0.999 } + TQ := { NUMBER in ns } + PROP-SEG := { NUMBER in tq } + PHASE-SEG1 := { NUMBER in tq } + PHASE-SEG2 := { NUMBER in tq } + SJW := { NUMBER in tq } + RESTART-MS := { 0 | NUMBER in ms } + +Signed-off-by: Vincent Mailhol +Signed-off-by: David Ahern +--- + ip/iplink_can.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/ip/iplink_can.c b/ip/iplink_can.c +index 6a26f3ff..0b2ff8a3 100644 +--- a/ip/iplink_can.c ++++ b/ip/iplink_can.c +@@ -44,14 +44,14 @@ static void print_usage(FILE *f) + "\n" + "\t[ termination { 0..65535 } ]\n" + "\n" +- "\tWhere: BITRATE := { 1..1000000 }\n" ++ "\tWhere: BITRATE := { NUMBER in bps }\n" + "\t SAMPLE-POINT := { 0.000..0.999 }\n" +- "\t TQ := { NUMBER }\n" +- "\t PROP-SEG := { 1..8 }\n" +- "\t PHASE-SEG1 := { 1..8 }\n" +- "\t PHASE-SEG2 := { 1..8 }\n" +- "\t SJW := { 1..4 }\n" +- "\t RESTART-MS := { 0 | NUMBER }\n" ++ "\t TQ := { NUMBER in ns }\n" ++ "\t PROP-SEG := { NUMBER in tq }\n" ++ "\t PHASE-SEG1 := { NUMBER in tq }\n" ++ "\t PHASE-SEG2 := { NUMBER in tq }\n" ++ "\t SJW := { NUMBER in tq }\n" ++ "\t RESTART-MS := { 0 | NUMBER in ms }\n" + ); + } + +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch new file mode 100644 index 00000000..88f38a81 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch @@ -0,0 +1,113 @@ +From fd5e958c494cd43611a5977028aee7e93740c01d Mon Sep 17 00:00:00 2001 +From: Vincent Mailhol +Date: Thu, 4 Nov 2021 01:44:25 +0900 +Subject: [PATCH 2/5] iplink_can: code refactoring of print_ctrlmode() + +This patch only does cleanup and do not introduce any functional +changes. + +We do some code refactoring of print_ctrlmode() in prevision of the +upcoming patch: + + - remove the first argument of print_ctrlmode(). It is a pointer to + FILE and is never used. + + - add a new function argument: enum output_type t in order to + specify the output type (i.e. PRINT_{FP,JSON,ANY}). + + - add a new function argument: const char *key in order to specify + the name of the json array (e.g. "ctrlmode"). + + - replace the _PF() macro with the print_flag() function to increase + readability. + + - directly return if none of the flags are set (previously, this + check was done before calling the function). + +Signed-off-by: Vincent Mailhol +Signed-off-by: David Ahern +--- + ip/iplink_can.c | 52 ++++++++++++++++++++++++++++--------------------- + 1 file changed, 30 insertions(+), 22 deletions(-) + +diff --git a/ip/iplink_can.c b/ip/iplink_can.c +index 0b2ff8a3..c910365d 100644 +--- a/ip/iplink_can.c ++++ b/ip/iplink_can.c +@@ -88,34 +88,43 @@ static void set_ctrlmode(char *name, char *arg, + cm->mask |= flags; + } + +-static void print_ctrlmode(FILE *f, __u32 cm) ++static void print_flag(enum output_type t, __u32 *flags, __u32 flag, ++ const char* name) + { +- open_json_array(PRINT_ANY, is_json_context() ? "ctrlmode" : "<"); +-#define _PF(cmflag, cmname) \ +- if (cm & cmflag) { \ +- cm &= ~cmflag; \ +- print_string(PRINT_ANY, NULL, cm ? "%s," : "%s", cmname); \ ++ if (*flags & flag) { ++ *flags &= ~flag; ++ print_string(t, NULL, *flags ? "%s," : "%s", name); + } +- _PF(CAN_CTRLMODE_LOOPBACK, "LOOPBACK"); +- _PF(CAN_CTRLMODE_LISTENONLY, "LISTEN-ONLY"); +- _PF(CAN_CTRLMODE_3_SAMPLES, "TRIPLE-SAMPLING"); +- _PF(CAN_CTRLMODE_ONE_SHOT, "ONE-SHOT"); +- _PF(CAN_CTRLMODE_BERR_REPORTING, "BERR-REPORTING"); +- _PF(CAN_CTRLMODE_FD, "FD"); +- _PF(CAN_CTRLMODE_FD_NON_ISO, "FD-NON-ISO"); +- _PF(CAN_CTRLMODE_PRESUME_ACK, "PRESUME-ACK"); +- _PF(CAN_CTRLMODE_CC_LEN8_DLC, "CC-LEN8-DLC"); +-#undef _PF +- if (cm) +- print_hex(PRINT_ANY, NULL, "%x", cm); +- close_json_array(PRINT_ANY, "> "); ++} ++ ++static void print_ctrlmode(enum output_type t, __u32 flags, const char* key) ++{ ++ if (!flags) ++ return; ++ ++ open_json_array(t, is_json_context() ? key : "<"); ++ ++ print_flag(t, &flags, CAN_CTRLMODE_LOOPBACK, "LOOPBACK"); ++ print_flag(t, &flags, CAN_CTRLMODE_LISTENONLY, "LISTEN-ONLY"); ++ print_flag(t, &flags, CAN_CTRLMODE_3_SAMPLES, "TRIPLE-SAMPLING"); ++ print_flag(t, &flags, CAN_CTRLMODE_ONE_SHOT, "ONE-SHOT"); ++ print_flag(t, &flags, CAN_CTRLMODE_BERR_REPORTING, "BERR-REPORTING"); ++ print_flag(t, &flags, CAN_CTRLMODE_FD, "FD"); ++ print_flag(t, &flags, CAN_CTRLMODE_FD_NON_ISO, "FD-NON-ISO"); ++ print_flag(t, &flags, CAN_CTRLMODE_PRESUME_ACK, "PRESUME-ACK"); ++ print_flag(t, &flags, CAN_CTRLMODE_CC_LEN8_DLC, "CC-LEN8-DLC"); ++ ++ if (flags) ++ print_hex(t, NULL, "%x", flags); ++ ++ close_json_array(t, "> "); + } + + static int can_parse_opt(struct link_util *lu, int argc, char **argv, + struct nlmsghdr *n) + { + struct can_bittiming bt = {}, dbt = {}; +- struct can_ctrlmode cm = {0, 0}; ++ struct can_ctrlmode cm = { 0 }; + + while (argc > 0) { + if (matches(*argv, "bitrate") == 0) { +@@ -282,8 +291,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + if (tb[IFLA_CAN_CTRLMODE]) { + struct can_ctrlmode *cm = RTA_DATA(tb[IFLA_CAN_CTRLMODE]); + +- if (cm->flags) +- print_ctrlmode(f, cm->flags); ++ print_ctrlmode(PRINT_ANY, cm->flags, "ctrlmode"); + } + + if (tb[IFLA_CAN_STATE]) { +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch new file mode 100644 index 00000000..9e8a3ea4 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch @@ -0,0 +1,447 @@ +From 67f3c7a5cc0d12a09c265031f5d1f9e51d7781d7 Mon Sep 17 00:00:00 2001 +From: Vincent Mailhol +Date: Thu, 4 Nov 2021 01:44:26 +0900 +Subject: [PATCH 3/5] iplink_can: use PRINT_ANY to factorize code and fix + signedness + +Current implementation heavily relies on some "if (is_json_context())" +switches to decide the context and then does some print_*(PRINT_JSON, +...) when in json context and some fprintf(...) else. + +Furthermore, current implementation uses either print_int() or the +conversion specifier %d to print unsigned integers. + +This patch factorizes each pairs of print_*(PRINT_JSON, ...) and +fprintf() into a single print_*(PRINT_ANY, ...) call. While doing this +replacement, it uses proper unsigned function print_uint() as well as +the conversion specifier %u when the parameter is an unsigned integer. + +Signed-off-by: Vincent Mailhol +Signed-off-by: David Ahern +--- + ip/iplink_can.c | 331 +++++++++++++++++++----------------------------- + 1 file changed, 130 insertions(+), 201 deletions(-) + +diff --git a/ip/iplink_can.c b/ip/iplink_can.c +index c910365d..c0165237 100644 +--- a/ip/iplink_can.c ++++ b/ip/iplink_can.c +@@ -275,11 +275,19 @@ static const char *can_state_names[CAN_STATE_MAX] = { + [CAN_STATE_SLEEPING] = "SLEEPING" + }; + +-static void can_print_json_timing_min_max(const char *attr, int min, int max) ++static void can_print_nl_indent(void) + { +- open_json_object(attr); +- print_int(PRINT_JSON, "min", NULL, min); +- print_int(PRINT_JSON, "max", NULL, max); ++ print_nl(); ++ print_string(PRINT_FP, NULL, "%s", "\t "); ++} ++ ++static void can_print_timing_min_max(const char *json_attr, const char *fp_attr, ++ int min, int max) ++{ ++ print_null(PRINT_FP, NULL, fp_attr, NULL); ++ open_json_object(json_attr); ++ print_uint(PRINT_ANY, "min", " %d", min); ++ print_uint(PRINT_ANY, "max", "..%d", max); + close_json_object(); + } + +@@ -305,56 +313,38 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + struct can_berr_counter *bc = + RTA_DATA(tb[IFLA_CAN_BERR_COUNTER]); + +- if (is_json_context()) { +- open_json_object("berr_counter"); +- print_int(PRINT_JSON, "tx", NULL, bc->txerr); +- print_int(PRINT_JSON, "rx", NULL, bc->rxerr); +- close_json_object(); +- } else { +- fprintf(f, "(berr-counter tx %d rx %d) ", +- bc->txerr, bc->rxerr); +- } ++ open_json_object("berr_counter"); ++ print_uint(PRINT_ANY, "tx", "(berr-counter tx %u", bc->txerr); ++ print_uint(PRINT_ANY, "rx", " rx %u) ", bc->rxerr); ++ close_json_object(); + } + + if (tb[IFLA_CAN_RESTART_MS]) { + __u32 *restart_ms = RTA_DATA(tb[IFLA_CAN_RESTART_MS]); + +- print_int(PRINT_ANY, +- "restart_ms", +- "restart-ms %d ", +- *restart_ms); ++ print_uint(PRINT_ANY, "restart_ms", "restart-ms %u ", ++ *restart_ms); + } + + /* bittiming is irrelevant if fixed bitrate is defined */ + if (tb[IFLA_CAN_BITTIMING] && !tb[IFLA_CAN_BITRATE_CONST]) { + struct can_bittiming *bt = RTA_DATA(tb[IFLA_CAN_BITTIMING]); +- +- if (is_json_context()) { +- json_writer_t *jw; +- +- open_json_object("bittiming"); +- print_int(PRINT_ANY, "bitrate", NULL, bt->bitrate); +- jw = get_json_writer(); +- jsonw_name(jw, "sample_point"); +- jsonw_printf(jw, "%.3f", +- (float) bt->sample_point / 1000); +- print_int(PRINT_ANY, "tq", NULL, bt->tq); +- print_int(PRINT_ANY, "prop_seg", NULL, bt->prop_seg); +- print_int(PRINT_ANY, "phase_seg1", +- NULL, bt->phase_seg1); +- print_int(PRINT_ANY, "phase_seg2", +- NULL, bt->phase_seg2); +- print_int(PRINT_ANY, "sjw", NULL, bt->sjw); +- close_json_object(); +- } else { +- fprintf(f, "\n bitrate %d sample-point %.3f ", +- bt->bitrate, (float) bt->sample_point / 1000.); +- fprintf(f, +- "\n tq %d prop-seg %d phase-seg1 %d phase-seg2 %d sjw %d", +- bt->tq, bt->prop_seg, +- bt->phase_seg1, bt->phase_seg2, +- bt->sjw); +- } ++ char sp[6]; ++ ++ open_json_object("bittiming"); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "bitrate", " bitrate %u", bt->bitrate); ++ snprintf(sp, sizeof(sp), "%.3f", bt->sample_point / 1000.); ++ print_string(PRINT_ANY, "sample_point", " sample-point %s", sp); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "tq", " tq %u", bt->tq); ++ print_uint(PRINT_ANY, "prop_seg", " prop-seg %u", bt->prop_seg); ++ print_uint(PRINT_ANY, "phase_seg1", " phase-seg1 %u", ++ bt->phase_seg1); ++ print_uint(PRINT_ANY, "phase_seg2", " phase-seg2 %u", ++ bt->phase_seg2); ++ print_uint(PRINT_ANY, "sjw", " sjw %u", bt->sjw); ++ close_json_object(); + } + + /* bittiming const is irrelevant if fixed bitrate is defined */ +@@ -362,28 +352,18 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + struct can_bittiming_const *btc = + RTA_DATA(tb[IFLA_CAN_BITTIMING_CONST]); + +- if (is_json_context()) { +- open_json_object("bittiming_const"); +- print_string(PRINT_JSON, "name", NULL, btc->name); +- can_print_json_timing_min_max("tseg1", +- btc->tseg1_min, +- btc->tseg1_max); +- can_print_json_timing_min_max("tseg2", +- btc->tseg2_min, +- btc->tseg2_max); +- can_print_json_timing_min_max("sjw", 1, btc->sjw_max); +- can_print_json_timing_min_max("brp", +- btc->brp_min, +- btc->brp_max); +- print_int(PRINT_JSON, "brp_inc", NULL, btc->brp_inc); +- close_json_object(); +- } else { +- fprintf(f, "\n %s: tseg1 %d..%d tseg2 %d..%d " +- "sjw 1..%d brp %d..%d brp-inc %d", +- btc->name, btc->tseg1_min, btc->tseg1_max, +- btc->tseg2_min, btc->tseg2_max, btc->sjw_max, +- btc->brp_min, btc->brp_max, btc->brp_inc); +- } ++ open_json_object("bittiming_const"); ++ can_print_nl_indent(); ++ print_string(PRINT_ANY, "name", " %s:", btc->name); ++ can_print_timing_min_max("tseg1", " tseg1", ++ btc->tseg1_min, btc->tseg1_max); ++ can_print_timing_min_max("tseg2", " tseg2", ++ btc->tseg2_min, btc->tseg2_max); ++ can_print_timing_min_max("sjw", " sjw", 1, btc->sjw_max); ++ can_print_timing_min_max("brp", " brp", ++ btc->brp_min, btc->brp_max); ++ print_uint(PRINT_ANY, "brp_inc", " brp_inc %u", btc->brp_inc); ++ close_json_object(); + } + + if (tb[IFLA_CAN_BITRATE_CONST]) { +@@ -399,64 +379,47 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + bitrate = bt->bitrate; + } + +- if (is_json_context()) { +- print_uint(PRINT_JSON, +- "bittiming_bitrate", +- NULL, bitrate); +- open_json_array(PRINT_JSON, "bitrate_const"); +- for (i = 0; i < bitrate_cnt; ++i) +- print_uint(PRINT_JSON, NULL, NULL, +- bitrate_const[i]); +- close_json_array(PRINT_JSON, NULL); +- } else { +- fprintf(f, "\n bitrate %u", bitrate); +- fprintf(f, "\n ["); +- +- for (i = 0; i < bitrate_cnt - 1; ++i) { +- /* This will keep lines below 80 signs */ +- if (!(i % 6) && i) +- fprintf(f, "\n "); +- +- fprintf(f, "%8u, ", bitrate_const[i]); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "bittiming_bitrate", " bitrate %u", ++ bitrate); ++ can_print_nl_indent(); ++ open_json_array(PRINT_ANY, is_json_context() ? ++ "bitrate_const" : " ["); ++ for (i = 0; i < bitrate_cnt; ++i) { ++ /* This will keep lines below 80 signs */ ++ if (!(i % 6) && i) { ++ can_print_nl_indent(); ++ print_string(PRINT_FP, NULL, "%s", " "); + } +- +- if (!(i % 6) && i) +- fprintf(f, "\n "); +- fprintf(f, "%8u ]", bitrate_const[i]); ++ print_uint(PRINT_ANY, NULL, ++ i < bitrate_cnt - 1 ? "%8u, " : "%8u", ++ bitrate_const[i]); + } ++ close_json_array(PRINT_JSON, " ]"); + } + + /* data bittiming is irrelevant if fixed bitrate is defined */ + if (tb[IFLA_CAN_DATA_BITTIMING] && !tb[IFLA_CAN_DATA_BITRATE_CONST]) { + struct can_bittiming *dbt = + RTA_DATA(tb[IFLA_CAN_DATA_BITTIMING]); +- +- if (is_json_context()) { +- json_writer_t *jw; +- +- open_json_object("data_bittiming"); +- print_int(PRINT_JSON, "bitrate", NULL, dbt->bitrate); +- jw = get_json_writer(); +- jsonw_name(jw, "sample_point"); +- jsonw_printf(jw, "%.3f", +- (float) dbt->sample_point / 1000.); +- print_int(PRINT_JSON, "tq", NULL, dbt->tq); +- print_int(PRINT_JSON, "prop_seg", NULL, dbt->prop_seg); +- print_int(PRINT_JSON, "phase_seg1", +- NULL, dbt->phase_seg1); +- print_int(PRINT_JSON, "phase_seg2", +- NULL, dbt->phase_seg2); +- print_int(PRINT_JSON, "sjw", NULL, dbt->sjw); +- close_json_object(); +- } else { +- fprintf(f, "\n dbitrate %d dsample-point %.3f ", +- dbt->bitrate, +- (float) dbt->sample_point / 1000.); +- fprintf(f, "\n dtq %d dprop-seg %d dphase-seg1 %d " +- "dphase-seg2 %d dsjw %d", +- dbt->tq, dbt->prop_seg, dbt->phase_seg1, +- dbt->phase_seg2, dbt->sjw); +- } ++ char dsp[6]; ++ ++ open_json_object("data_bittiming"); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "bitrate", " dbitrate %u", dbt->bitrate); ++ snprintf(dsp, sizeof(dsp), "%.3f", dbt->sample_point / 1000.); ++ print_string(PRINT_ANY, "sample_point", " dsample-point %s", ++ dsp); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "tq", " dtq %u", dbt->tq); ++ print_uint(PRINT_ANY, "prop_seg", " dprop-seg %u", ++ dbt->prop_seg); ++ print_uint(PRINT_ANY, "phase_seg1", " dphase-seg1 %u", ++ dbt->phase_seg1); ++ print_uint(PRINT_ANY, "phase_seg2", " dphase-seg2 %u", ++ dbt->phase_seg2); ++ print_uint(PRINT_ANY, "sjw", " dsjw %u", dbt->sjw); ++ close_json_object(); + } + + /* data bittiming const is irrelevant if fixed bitrate is defined */ +@@ -465,29 +428,18 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + struct can_bittiming_const *dbtc = + RTA_DATA(tb[IFLA_CAN_DATA_BITTIMING_CONST]); + +- if (is_json_context()) { +- open_json_object("data_bittiming_const"); +- print_string(PRINT_JSON, "name", NULL, dbtc->name); +- can_print_json_timing_min_max("tseg1", +- dbtc->tseg1_min, +- dbtc->tseg1_max); +- can_print_json_timing_min_max("tseg2", +- dbtc->tseg2_min, +- dbtc->tseg2_max); +- can_print_json_timing_min_max("sjw", 1, dbtc->sjw_max); +- can_print_json_timing_min_max("brp", +- dbtc->brp_min, +- dbtc->brp_max); +- +- print_int(PRINT_JSON, "brp_inc", NULL, dbtc->brp_inc); +- close_json_object(); +- } else { +- fprintf(f, "\n %s: dtseg1 %d..%d dtseg2 %d..%d " +- "dsjw 1..%d dbrp %d..%d dbrp-inc %d", +- dbtc->name, dbtc->tseg1_min, dbtc->tseg1_max, +- dbtc->tseg2_min, dbtc->tseg2_max, dbtc->sjw_max, +- dbtc->brp_min, dbtc->brp_max, dbtc->brp_inc); +- } ++ open_json_object("data_bittiming_const"); ++ can_print_nl_indent(); ++ print_string(PRINT_ANY, "name", " %s:", dbtc->name); ++ can_print_timing_min_max("tseg1", " dtseg1", ++ dbtc->tseg1_min, dbtc->tseg1_max); ++ can_print_timing_min_max("tseg2", " dtseg2", ++ dbtc->tseg2_min, dbtc->tseg2_max); ++ can_print_timing_min_max("sjw", " dsjw", 1, dbtc->sjw_max); ++ can_print_timing_min_max("brp", " dbrp", ++ dbtc->brp_min, dbtc->brp_max); ++ print_uint(PRINT_ANY, "brp_inc", " dbrp_inc %u", dbtc->brp_inc); ++ close_json_object(); + } + + if (tb[IFLA_CAN_DATA_BITRATE_CONST]) { +@@ -505,30 +457,23 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + dbitrate = dbt->bitrate; + } + +- if (is_json_context()) { +- print_uint(PRINT_JSON, "data_bittiming_bitrate", +- NULL, dbitrate); +- open_json_array(PRINT_JSON, "data_bitrate_const"); +- for (i = 0; i < dbitrate_cnt; ++i) +- print_uint(PRINT_JSON, NULL, NULL, +- dbitrate_const[i]); +- close_json_array(PRINT_JSON, NULL); +- } else { +- fprintf(f, "\n dbitrate %u", dbitrate); +- fprintf(f, "\n ["); +- +- for (i = 0; i < dbitrate_cnt - 1; ++i) { +- /* This will keep lines below 80 signs */ +- if (!(i % 6) && i) +- fprintf(f, "\n "); +- +- fprintf(f, "%8u, ", dbitrate_const[i]); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "data_bittiming_bitrate", " dbitrate %u", ++ dbitrate); ++ can_print_nl_indent(); ++ open_json_array(PRINT_ANY, is_json_context() ? ++ "data_bitrate_const" : " ["); ++ for (i = 0; i < dbitrate_cnt; ++i) { ++ /* This will keep lines below 80 signs */ ++ if (!(i % 6) && i) { ++ can_print_nl_indent(); ++ print_string(PRINT_FP, NULL, "%s", " "); + } +- +- if (!(i % 6) && i) +- fprintf(f, "\n "); +- fprintf(f, "%8u ]", dbitrate_const[i]); ++ print_uint(PRINT_ANY, NULL, ++ i < dbitrate_cnt - 1 ? "%8u, " : "%8u", ++ dbitrate_const[i]); + } ++ close_json_array(PRINT_JSON, " ]"); + } + + if (tb[IFLA_CAN_TERMINATION_CONST] && tb[IFLA_CAN_TERMINATION]) { +@@ -538,29 +483,21 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + sizeof(*trm_const); + int i; + +- if (is_json_context()) { +- print_hu(PRINT_JSON, "termination", NULL, *trm); +- open_json_array(PRINT_JSON, "termination_const"); +- for (i = 0; i < trm_cnt; ++i) +- print_hu(PRINT_JSON, NULL, NULL, trm_const[i]); +- close_json_array(PRINT_JSON, NULL); +- } else { +- fprintf(f, "\n termination %hu [ ", *trm); +- +- for (i = 0; i < trm_cnt - 1; ++i) +- fprintf(f, "%hu, ", trm_const[i]); +- +- fprintf(f, "%hu ]", trm_const[i]); +- } ++ can_print_nl_indent(); ++ print_hu(PRINT_ANY, "termination", " termination %hu [ ", *trm); ++ open_json_array(PRINT_JSON, "termination_const"); ++ for (i = 0; i < trm_cnt; ++i) ++ print_hu(PRINT_ANY, NULL, ++ i < trm_cnt - 1 ? "%hu, " : "%hu", ++ trm_const[i]); ++ close_json_array(PRINT_JSON, " ]"); + } + + if (tb[IFLA_CAN_CLOCK]) { + struct can_clock *clock = RTA_DATA(tb[IFLA_CAN_CLOCK]); + +- print_int(PRINT_ANY, +- "clock", +- "\n clock %d ", +- clock->freq); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "clock", " clock %u ", clock->freq); + } + + } +@@ -573,31 +510,23 @@ static void can_print_xstats(struct link_util *lu, + if (xstats && RTA_PAYLOAD(xstats) == sizeof(*stats)) { + stats = RTA_DATA(xstats); + +- if (is_json_context()) { +- print_int(PRINT_JSON, "restarts", +- NULL, stats->restarts); +- print_int(PRINT_JSON, "bus_error", +- NULL, stats->bus_error); +- print_int(PRINT_JSON, "arbitration_lost", +- NULL, stats->arbitration_lost); +- print_int(PRINT_JSON, "error_warning", +- NULL, stats->error_warning); +- print_int(PRINT_JSON, "error_passive", +- NULL, stats->error_passive); +- print_int(PRINT_JSON, "bus_off", NULL, stats->bus_off); +- } else { +- fprintf(f, "\n re-started bus-errors arbit-lost " +- "error-warn error-pass bus-off"); +- fprintf(f, "\n %-10d %-10d %-10d %-10d %-10d %-10d", +- stats->restarts, stats->bus_error, +- stats->arbitration_lost, stats->error_warning, +- stats->error_passive, stats->bus_off); +- } ++ can_print_nl_indent(); ++ print_string(PRINT_FP, NULL, "%s", ++ " re-started bus-errors arbit-lost error-warn error-pass bus-off"); ++ can_print_nl_indent(); ++ print_uint(PRINT_ANY, "restarts", " %-10u", stats->restarts); ++ print_uint(PRINT_ANY, "bus_error", " %-10u", stats->bus_error); ++ print_uint(PRINT_ANY, "arbitration_lost", " %-10u", ++ stats->arbitration_lost); ++ print_uint(PRINT_ANY, "error_warning", " %-10u", ++ stats->error_warning); ++ print_uint(PRINT_ANY, "error_passive", " %-10u", ++ stats->error_passive); ++ print_uint(PRINT_ANY, "bus_off", " %-10u", stats->bus_off); + } + } + +-static void can_print_help(struct link_util *lu, int argc, char **argv, +- FILE *f) ++static void can_print_help(struct link_util *lu, int argc, char **argv, FILE *f) + { + print_usage(f); + } +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch new file mode 100644 index 00000000..92bcd8d2 --- /dev/null +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch @@ -0,0 +1,53 @@ +From 0f7bb8d842b158169e0950b9a6ac642877e044bd Mon Sep 17 00:00:00 2001 +From: Vincent Mailhol +Date: Thu, 4 Nov 2021 01:44:27 +0900 +Subject: [PATCH 4/5] iplink_can: print brp and dbrp bittiming variables + +Report the value of the bit-rate prescaler (brp) for both the nominal +and the data bittiming. + +Currently, only the constant brp values (brp_{min,max,inc}) are being +reported. Also, brp is the only member of struct can_bittiming not +being reported. + +Noticeably, brp could be calculated by hand from the other bittiming +parameters with below formula: + + brp = clock * tq / 1000000000 + +with clock in hertz and tq in nano second (thus the need of a 1 +billion factor to convert it back to second). + +But because above formula is not so trivial to remember and is +subjected to rounding errors, it makes sense to directly output +{d,}bpr. + +Signed-off-by: Vincent Mailhol +Signed-off-by: David Ahern +--- + ip/iplink_can.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/ip/iplink_can.c b/ip/iplink_can.c +index c0165237..cf6b06b8 100644 +--- a/ip/iplink_can.c ++++ b/ip/iplink_can.c +@@ -344,6 +344,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + print_uint(PRINT_ANY, "phase_seg2", " phase-seg2 %u", + bt->phase_seg2); + print_uint(PRINT_ANY, "sjw", " sjw %u", bt->sjw); ++ print_uint(PRINT_ANY, "brp", " brp %u", bt->brp); + close_json_object(); + } + +@@ -419,6 +420,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) + print_uint(PRINT_ANY, "phase_seg2", " dphase-seg2 %u", + dbt->phase_seg2); + print_uint(PRINT_ANY, "sjw", " dsjw %u", dbt->sjw); ++ print_uint(PRINT_ANY, "brp", " dbrp %u", dbt->brp); + close_json_object(); + } + +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb index 99a74339..929d4ac9 100644 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb @@ -2,6 +2,10 @@ require iproute2.inc SRC_URI = "${KERNELORG_MIRROR}/linux/utils/net/${BPN}/${BP}.tar.xz \ file://0001-libc-compat.h-add-musl-workaround.patch \ + file://0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch \ + file://0002-iplink_can-code-refactoring-of-print_ctrlmode.patch \ + file://0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch \ + file://0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch \ " SRC_URI[sha256sum] = "38e3e4a5f9a7f5575c015027a10df097c149111eeb739993128e5b2b35b291ff" -- cgit v1.2.3-54-g00ecf From 1f15cdf82fadc588211d8a422faad23031a60117 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 19 Mar 2022 12:16:51 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 0aa4b6d0..eaf9ef8e 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "706f63a40e6204ae2401f175c1561572bfe8c952" +ESW_REV[2022.2] = "dd9288620d556ff4c77be8e0c2237997ede429a2" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 65230983f4183fddbe4a45cb85da656eb5054c55 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Fri, 18 Mar 2022 23:06:23 +0530 Subject: libdfx: update libdfx bb file to enable shared library support This patch updates libdfx bb file to enable shared library support Signed-off-by: Nava kishore Manne Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb index 7880b7f5..322e0dab 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb @@ -8,7 +8,7 @@ BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -SRCREV = "80f87f807d2506733f1095607be117073efdd94f" +SRCREV = "fb8fe48d6ce4a3bb99a6c3d9f17921cecdfe95fc" COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynqmp = "zynqmp" @@ -18,17 +18,17 @@ S = "${WORKDIR}/git" inherit cmake -RDEPENDS:${PN} = "${PN}-staticdev" -PACKAGES =+ "${PN}-examples" - do_install () { install -d ${D}${libdir} install -d ${D}${includedir} install -d ${D}${bindir} + oe_libinstall -so -C ${B}/src/ libdfx ${D}${libdir} install -m 0644 ${B}/src/libdfx.a ${D}${libdir} install -m 0644 ${B}/include/libdfx.h ${D}${includedir} install -m 0755 ${B}/apps/dfx_app ${D}${bindir} } -ALLOW_EMPTY:${PN} = "1" -ALLOW_EMPTY:${PN}-examples = "1" +SOLIBSDEV = ".so" +FILES:${PN} += "${libdir}/libdfx.so ${bindir}/*" +FILES:${PN}-staticdev = "${libdir}/libdfx.a" +FILES:${PN}-dev = "${includedir}" -- cgit v1.2.3-54-g00ecf From 5d93254e5061aa5810df531da57b7ee221fd5db9 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 22 Mar 2022 16:28:58 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index eaf9ef8e..5a173c2c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "dd9288620d556ff4c77be8e0c2237997ede429a2" +ESW_REV[2022.2] = "4961570f7c8d8171dc3d675ed1f487f255c26d2d" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From cfe7bd0915270a876c5664100e09ad0ff8f885e9 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 21 Mar 2022 20:38:45 -0700 Subject: Revert "iproute2: Add backport of iplink CAN changes" This reverts commit 1363cfc1a1819a3d6afaac5d9a395b75599c6148. Commit was determined to be unnecessary. Signed-off-by: Mark Hatle --- ...fix-configuration-ranges-in-print_usage-a.patch | 138 ------- ...nk_can-code-refactoring-of-print_ctrlmode.patch | 113 ------ ...use-PRINT_ANY-to-factorize-code-and-fix-s.patch | 447 --------------------- ...an-print-brp-and-dbrp-bittiming-variables.patch | 53 --- .../iproute2/iproute2_5.15.0.bb | 4 - 5 files changed, 755 deletions(-) delete mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch delete mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch delete mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch delete mode 100644 meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch deleted file mode 100644 index 28542305..00000000 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 8316df6e6db4de2f20b7fa976a6d4f9992dda7b1 Mon Sep 17 00:00:00 2001 -From: Vincent Mailhol -Date: Thu, 4 Nov 2021 01:44:24 +0900 -Subject: [PATCH 1/5] iplink_can: fix configuration ranges in print_usage() and - add unit - -The configuration ranges in print_usage() are taken from "Table 8 - -Time segments' minimum configuration ranges" in section 11.3.1.2 -"Configuration of the bit time parameters" of ISO 11898-1. - -The standard clearly specifies that "implementations may allow time -segments that exceed the minimum required configuration ranges -specified in Table 8". - -Because no maximum ranges are given in the standard, all given ranges -{ a..b } are simply replaced with { NUMBER }. - -The actual ranges are specific to each device and can be confirmed -doing: - -$ ip --details link show can0 -1: can0: mtu 16 qdisc noop state DOWN mode DEFAULT group default qlen 10 - link/can promiscuity 0 minmtu 0 maxmtu 0 - can state STOPPED restart-ms 0 - ES582.1/ES584.1: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp-inc 1 - ES582.1/ES584.1: dtseg1 2..32 dtseg2 1..16 dsjw 1..8 dbrp 1..32 dbrp-inc 1 - clock 80000000 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 - -Finally, the unit (bps, tq, ns or ms) are given. The rationale to add -the units is that the TDC parameters (that will be introduced in the -upcoming patches) are measured in a different unit than the other -bittiming parameters: clock period (a.k.a. minimum time quantum) -instead of time quantum. Adding the units disambiguates things. - -For reference, before the change: -$ ip link set can0 type can help -Usage: ip link set DEVICE type can - [ bitrate BITRATE [ sample-point SAMPLE-POINT] ] | - [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1 - phase-seg2 PHASE-SEG2 [ sjw SJW ] ] - - [ dbitrate BITRATE [ dsample-point SAMPLE-POINT] ] | - [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1 - dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ] - - [ loopback { on | off } ] - [ listen-only { on | off } ] - [ triple-sampling { on | off } ] - [ one-shot { on | off } ] - [ berr-reporting { on | off } ] - [ fd { on | off } ] - [ fd-non-iso { on | off } ] - [ presume-ack { on | off } ] - - [ restart-ms TIME-MS ] - [ restart ] - - [ termination { 0..65535 } ] - - Where: BITRATE := { 1..1000000 } - SAMPLE-POINT := { 0.000..0.999 } - TQ := { NUMBER } - PROP-SEG := { 1..8 } - PHASE-SEG1 := { 1..8 } - PHASE-SEG2 := { 1..8 } - SJW := { 1..4 } - RESTART-MS := { 0 | NUMBER } - -...and after it: -$ ip link set can0 type can help -Usage: ip link set DEVICE type can - [ bitrate BITRATE [ sample-point SAMPLE-POINT] ] | - [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1 - phase-seg2 PHASE-SEG2 [ sjw SJW ] ] - - [ dbitrate BITRATE [ dsample-point SAMPLE-POINT] ] | - [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1 - dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ] - - [ loopback { on | off } ] - [ listen-only { on | off } ] - [ triple-sampling { on | off } ] - [ one-shot { on | off } ] - [ berr-reporting { on | off } ] - [ fd { on | off } ] - [ fd-non-iso { on | off } ] - [ presume-ack { on | off } ] - [ cc-len8-dlc { on | off } ] - - [ restart-ms TIME-MS ] - [ restart ] - - [ termination { 0..65535 } ] - - Where: BITRATE := { NUMBER in bps } - SAMPLE-POINT := { 0.000..0.999 } - TQ := { NUMBER in ns } - PROP-SEG := { NUMBER in tq } - PHASE-SEG1 := { NUMBER in tq } - PHASE-SEG2 := { NUMBER in tq } - SJW := { NUMBER in tq } - RESTART-MS := { 0 | NUMBER in ms } - -Signed-off-by: Vincent Mailhol -Signed-off-by: David Ahern ---- - ip/iplink_can.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/ip/iplink_can.c b/ip/iplink_can.c -index 6a26f3ff..0b2ff8a3 100644 ---- a/ip/iplink_can.c -+++ b/ip/iplink_can.c -@@ -44,14 +44,14 @@ static void print_usage(FILE *f) - "\n" - "\t[ termination { 0..65535 } ]\n" - "\n" -- "\tWhere: BITRATE := { 1..1000000 }\n" -+ "\tWhere: BITRATE := { NUMBER in bps }\n" - "\t SAMPLE-POINT := { 0.000..0.999 }\n" -- "\t TQ := { NUMBER }\n" -- "\t PROP-SEG := { 1..8 }\n" -- "\t PHASE-SEG1 := { 1..8 }\n" -- "\t PHASE-SEG2 := { 1..8 }\n" -- "\t SJW := { 1..4 }\n" -- "\t RESTART-MS := { 0 | NUMBER }\n" -+ "\t TQ := { NUMBER in ns }\n" -+ "\t PROP-SEG := { NUMBER in tq }\n" -+ "\t PHASE-SEG1 := { NUMBER in tq }\n" -+ "\t PHASE-SEG2 := { NUMBER in tq }\n" -+ "\t SJW := { NUMBER in tq }\n" -+ "\t RESTART-MS := { 0 | NUMBER in ms }\n" - ); - } - --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch deleted file mode 100644 index 88f38a81..00000000 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0002-iplink_can-code-refactoring-of-print_ctrlmode.patch +++ /dev/null @@ -1,113 +0,0 @@ -From fd5e958c494cd43611a5977028aee7e93740c01d Mon Sep 17 00:00:00 2001 -From: Vincent Mailhol -Date: Thu, 4 Nov 2021 01:44:25 +0900 -Subject: [PATCH 2/5] iplink_can: code refactoring of print_ctrlmode() - -This patch only does cleanup and do not introduce any functional -changes. - -We do some code refactoring of print_ctrlmode() in prevision of the -upcoming patch: - - - remove the first argument of print_ctrlmode(). It is a pointer to - FILE and is never used. - - - add a new function argument: enum output_type t in order to - specify the output type (i.e. PRINT_{FP,JSON,ANY}). - - - add a new function argument: const char *key in order to specify - the name of the json array (e.g. "ctrlmode"). - - - replace the _PF() macro with the print_flag() function to increase - readability. - - - directly return if none of the flags are set (previously, this - check was done before calling the function). - -Signed-off-by: Vincent Mailhol -Signed-off-by: David Ahern ---- - ip/iplink_can.c | 52 ++++++++++++++++++++++++++++--------------------- - 1 file changed, 30 insertions(+), 22 deletions(-) - -diff --git a/ip/iplink_can.c b/ip/iplink_can.c -index 0b2ff8a3..c910365d 100644 ---- a/ip/iplink_can.c -+++ b/ip/iplink_can.c -@@ -88,34 +88,43 @@ static void set_ctrlmode(char *name, char *arg, - cm->mask |= flags; - } - --static void print_ctrlmode(FILE *f, __u32 cm) -+static void print_flag(enum output_type t, __u32 *flags, __u32 flag, -+ const char* name) - { -- open_json_array(PRINT_ANY, is_json_context() ? "ctrlmode" : "<"); --#define _PF(cmflag, cmname) \ -- if (cm & cmflag) { \ -- cm &= ~cmflag; \ -- print_string(PRINT_ANY, NULL, cm ? "%s," : "%s", cmname); \ -+ if (*flags & flag) { -+ *flags &= ~flag; -+ print_string(t, NULL, *flags ? "%s," : "%s", name); - } -- _PF(CAN_CTRLMODE_LOOPBACK, "LOOPBACK"); -- _PF(CAN_CTRLMODE_LISTENONLY, "LISTEN-ONLY"); -- _PF(CAN_CTRLMODE_3_SAMPLES, "TRIPLE-SAMPLING"); -- _PF(CAN_CTRLMODE_ONE_SHOT, "ONE-SHOT"); -- _PF(CAN_CTRLMODE_BERR_REPORTING, "BERR-REPORTING"); -- _PF(CAN_CTRLMODE_FD, "FD"); -- _PF(CAN_CTRLMODE_FD_NON_ISO, "FD-NON-ISO"); -- _PF(CAN_CTRLMODE_PRESUME_ACK, "PRESUME-ACK"); -- _PF(CAN_CTRLMODE_CC_LEN8_DLC, "CC-LEN8-DLC"); --#undef _PF -- if (cm) -- print_hex(PRINT_ANY, NULL, "%x", cm); -- close_json_array(PRINT_ANY, "> "); -+} -+ -+static void print_ctrlmode(enum output_type t, __u32 flags, const char* key) -+{ -+ if (!flags) -+ return; -+ -+ open_json_array(t, is_json_context() ? key : "<"); -+ -+ print_flag(t, &flags, CAN_CTRLMODE_LOOPBACK, "LOOPBACK"); -+ print_flag(t, &flags, CAN_CTRLMODE_LISTENONLY, "LISTEN-ONLY"); -+ print_flag(t, &flags, CAN_CTRLMODE_3_SAMPLES, "TRIPLE-SAMPLING"); -+ print_flag(t, &flags, CAN_CTRLMODE_ONE_SHOT, "ONE-SHOT"); -+ print_flag(t, &flags, CAN_CTRLMODE_BERR_REPORTING, "BERR-REPORTING"); -+ print_flag(t, &flags, CAN_CTRLMODE_FD, "FD"); -+ print_flag(t, &flags, CAN_CTRLMODE_FD_NON_ISO, "FD-NON-ISO"); -+ print_flag(t, &flags, CAN_CTRLMODE_PRESUME_ACK, "PRESUME-ACK"); -+ print_flag(t, &flags, CAN_CTRLMODE_CC_LEN8_DLC, "CC-LEN8-DLC"); -+ -+ if (flags) -+ print_hex(t, NULL, "%x", flags); -+ -+ close_json_array(t, "> "); - } - - static int can_parse_opt(struct link_util *lu, int argc, char **argv, - struct nlmsghdr *n) - { - struct can_bittiming bt = {}, dbt = {}; -- struct can_ctrlmode cm = {0, 0}; -+ struct can_ctrlmode cm = { 0 }; - - while (argc > 0) { - if (matches(*argv, "bitrate") == 0) { -@@ -282,8 +291,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - if (tb[IFLA_CAN_CTRLMODE]) { - struct can_ctrlmode *cm = RTA_DATA(tb[IFLA_CAN_CTRLMODE]); - -- if (cm->flags) -- print_ctrlmode(f, cm->flags); -+ print_ctrlmode(PRINT_ANY, cm->flags, "ctrlmode"); - } - - if (tb[IFLA_CAN_STATE]) { --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch deleted file mode 100644 index 9e8a3ea4..00000000 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch +++ /dev/null @@ -1,447 +0,0 @@ -From 67f3c7a5cc0d12a09c265031f5d1f9e51d7781d7 Mon Sep 17 00:00:00 2001 -From: Vincent Mailhol -Date: Thu, 4 Nov 2021 01:44:26 +0900 -Subject: [PATCH 3/5] iplink_can: use PRINT_ANY to factorize code and fix - signedness - -Current implementation heavily relies on some "if (is_json_context())" -switches to decide the context and then does some print_*(PRINT_JSON, -...) when in json context and some fprintf(...) else. - -Furthermore, current implementation uses either print_int() or the -conversion specifier %d to print unsigned integers. - -This patch factorizes each pairs of print_*(PRINT_JSON, ...) and -fprintf() into a single print_*(PRINT_ANY, ...) call. While doing this -replacement, it uses proper unsigned function print_uint() as well as -the conversion specifier %u when the parameter is an unsigned integer. - -Signed-off-by: Vincent Mailhol -Signed-off-by: David Ahern ---- - ip/iplink_can.c | 331 +++++++++++++++++++----------------------------- - 1 file changed, 130 insertions(+), 201 deletions(-) - -diff --git a/ip/iplink_can.c b/ip/iplink_can.c -index c910365d..c0165237 100644 ---- a/ip/iplink_can.c -+++ b/ip/iplink_can.c -@@ -275,11 +275,19 @@ static const char *can_state_names[CAN_STATE_MAX] = { - [CAN_STATE_SLEEPING] = "SLEEPING" - }; - --static void can_print_json_timing_min_max(const char *attr, int min, int max) -+static void can_print_nl_indent(void) - { -- open_json_object(attr); -- print_int(PRINT_JSON, "min", NULL, min); -- print_int(PRINT_JSON, "max", NULL, max); -+ print_nl(); -+ print_string(PRINT_FP, NULL, "%s", "\t "); -+} -+ -+static void can_print_timing_min_max(const char *json_attr, const char *fp_attr, -+ int min, int max) -+{ -+ print_null(PRINT_FP, NULL, fp_attr, NULL); -+ open_json_object(json_attr); -+ print_uint(PRINT_ANY, "min", " %d", min); -+ print_uint(PRINT_ANY, "max", "..%d", max); - close_json_object(); - } - -@@ -305,56 +313,38 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - struct can_berr_counter *bc = - RTA_DATA(tb[IFLA_CAN_BERR_COUNTER]); - -- if (is_json_context()) { -- open_json_object("berr_counter"); -- print_int(PRINT_JSON, "tx", NULL, bc->txerr); -- print_int(PRINT_JSON, "rx", NULL, bc->rxerr); -- close_json_object(); -- } else { -- fprintf(f, "(berr-counter tx %d rx %d) ", -- bc->txerr, bc->rxerr); -- } -+ open_json_object("berr_counter"); -+ print_uint(PRINT_ANY, "tx", "(berr-counter tx %u", bc->txerr); -+ print_uint(PRINT_ANY, "rx", " rx %u) ", bc->rxerr); -+ close_json_object(); - } - - if (tb[IFLA_CAN_RESTART_MS]) { - __u32 *restart_ms = RTA_DATA(tb[IFLA_CAN_RESTART_MS]); - -- print_int(PRINT_ANY, -- "restart_ms", -- "restart-ms %d ", -- *restart_ms); -+ print_uint(PRINT_ANY, "restart_ms", "restart-ms %u ", -+ *restart_ms); - } - - /* bittiming is irrelevant if fixed bitrate is defined */ - if (tb[IFLA_CAN_BITTIMING] && !tb[IFLA_CAN_BITRATE_CONST]) { - struct can_bittiming *bt = RTA_DATA(tb[IFLA_CAN_BITTIMING]); -- -- if (is_json_context()) { -- json_writer_t *jw; -- -- open_json_object("bittiming"); -- print_int(PRINT_ANY, "bitrate", NULL, bt->bitrate); -- jw = get_json_writer(); -- jsonw_name(jw, "sample_point"); -- jsonw_printf(jw, "%.3f", -- (float) bt->sample_point / 1000); -- print_int(PRINT_ANY, "tq", NULL, bt->tq); -- print_int(PRINT_ANY, "prop_seg", NULL, bt->prop_seg); -- print_int(PRINT_ANY, "phase_seg1", -- NULL, bt->phase_seg1); -- print_int(PRINT_ANY, "phase_seg2", -- NULL, bt->phase_seg2); -- print_int(PRINT_ANY, "sjw", NULL, bt->sjw); -- close_json_object(); -- } else { -- fprintf(f, "\n bitrate %d sample-point %.3f ", -- bt->bitrate, (float) bt->sample_point / 1000.); -- fprintf(f, -- "\n tq %d prop-seg %d phase-seg1 %d phase-seg2 %d sjw %d", -- bt->tq, bt->prop_seg, -- bt->phase_seg1, bt->phase_seg2, -- bt->sjw); -- } -+ char sp[6]; -+ -+ open_json_object("bittiming"); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "bitrate", " bitrate %u", bt->bitrate); -+ snprintf(sp, sizeof(sp), "%.3f", bt->sample_point / 1000.); -+ print_string(PRINT_ANY, "sample_point", " sample-point %s", sp); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "tq", " tq %u", bt->tq); -+ print_uint(PRINT_ANY, "prop_seg", " prop-seg %u", bt->prop_seg); -+ print_uint(PRINT_ANY, "phase_seg1", " phase-seg1 %u", -+ bt->phase_seg1); -+ print_uint(PRINT_ANY, "phase_seg2", " phase-seg2 %u", -+ bt->phase_seg2); -+ print_uint(PRINT_ANY, "sjw", " sjw %u", bt->sjw); -+ close_json_object(); - } - - /* bittiming const is irrelevant if fixed bitrate is defined */ -@@ -362,28 +352,18 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - struct can_bittiming_const *btc = - RTA_DATA(tb[IFLA_CAN_BITTIMING_CONST]); - -- if (is_json_context()) { -- open_json_object("bittiming_const"); -- print_string(PRINT_JSON, "name", NULL, btc->name); -- can_print_json_timing_min_max("tseg1", -- btc->tseg1_min, -- btc->tseg1_max); -- can_print_json_timing_min_max("tseg2", -- btc->tseg2_min, -- btc->tseg2_max); -- can_print_json_timing_min_max("sjw", 1, btc->sjw_max); -- can_print_json_timing_min_max("brp", -- btc->brp_min, -- btc->brp_max); -- print_int(PRINT_JSON, "brp_inc", NULL, btc->brp_inc); -- close_json_object(); -- } else { -- fprintf(f, "\n %s: tseg1 %d..%d tseg2 %d..%d " -- "sjw 1..%d brp %d..%d brp-inc %d", -- btc->name, btc->tseg1_min, btc->tseg1_max, -- btc->tseg2_min, btc->tseg2_max, btc->sjw_max, -- btc->brp_min, btc->brp_max, btc->brp_inc); -- } -+ open_json_object("bittiming_const"); -+ can_print_nl_indent(); -+ print_string(PRINT_ANY, "name", " %s:", btc->name); -+ can_print_timing_min_max("tseg1", " tseg1", -+ btc->tseg1_min, btc->tseg1_max); -+ can_print_timing_min_max("tseg2", " tseg2", -+ btc->tseg2_min, btc->tseg2_max); -+ can_print_timing_min_max("sjw", " sjw", 1, btc->sjw_max); -+ can_print_timing_min_max("brp", " brp", -+ btc->brp_min, btc->brp_max); -+ print_uint(PRINT_ANY, "brp_inc", " brp_inc %u", btc->brp_inc); -+ close_json_object(); - } - - if (tb[IFLA_CAN_BITRATE_CONST]) { -@@ -399,64 +379,47 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - bitrate = bt->bitrate; - } - -- if (is_json_context()) { -- print_uint(PRINT_JSON, -- "bittiming_bitrate", -- NULL, bitrate); -- open_json_array(PRINT_JSON, "bitrate_const"); -- for (i = 0; i < bitrate_cnt; ++i) -- print_uint(PRINT_JSON, NULL, NULL, -- bitrate_const[i]); -- close_json_array(PRINT_JSON, NULL); -- } else { -- fprintf(f, "\n bitrate %u", bitrate); -- fprintf(f, "\n ["); -- -- for (i = 0; i < bitrate_cnt - 1; ++i) { -- /* This will keep lines below 80 signs */ -- if (!(i % 6) && i) -- fprintf(f, "\n "); -- -- fprintf(f, "%8u, ", bitrate_const[i]); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "bittiming_bitrate", " bitrate %u", -+ bitrate); -+ can_print_nl_indent(); -+ open_json_array(PRINT_ANY, is_json_context() ? -+ "bitrate_const" : " ["); -+ for (i = 0; i < bitrate_cnt; ++i) { -+ /* This will keep lines below 80 signs */ -+ if (!(i % 6) && i) { -+ can_print_nl_indent(); -+ print_string(PRINT_FP, NULL, "%s", " "); - } -- -- if (!(i % 6) && i) -- fprintf(f, "\n "); -- fprintf(f, "%8u ]", bitrate_const[i]); -+ print_uint(PRINT_ANY, NULL, -+ i < bitrate_cnt - 1 ? "%8u, " : "%8u", -+ bitrate_const[i]); - } -+ close_json_array(PRINT_JSON, " ]"); - } - - /* data bittiming is irrelevant if fixed bitrate is defined */ - if (tb[IFLA_CAN_DATA_BITTIMING] && !tb[IFLA_CAN_DATA_BITRATE_CONST]) { - struct can_bittiming *dbt = - RTA_DATA(tb[IFLA_CAN_DATA_BITTIMING]); -- -- if (is_json_context()) { -- json_writer_t *jw; -- -- open_json_object("data_bittiming"); -- print_int(PRINT_JSON, "bitrate", NULL, dbt->bitrate); -- jw = get_json_writer(); -- jsonw_name(jw, "sample_point"); -- jsonw_printf(jw, "%.3f", -- (float) dbt->sample_point / 1000.); -- print_int(PRINT_JSON, "tq", NULL, dbt->tq); -- print_int(PRINT_JSON, "prop_seg", NULL, dbt->prop_seg); -- print_int(PRINT_JSON, "phase_seg1", -- NULL, dbt->phase_seg1); -- print_int(PRINT_JSON, "phase_seg2", -- NULL, dbt->phase_seg2); -- print_int(PRINT_JSON, "sjw", NULL, dbt->sjw); -- close_json_object(); -- } else { -- fprintf(f, "\n dbitrate %d dsample-point %.3f ", -- dbt->bitrate, -- (float) dbt->sample_point / 1000.); -- fprintf(f, "\n dtq %d dprop-seg %d dphase-seg1 %d " -- "dphase-seg2 %d dsjw %d", -- dbt->tq, dbt->prop_seg, dbt->phase_seg1, -- dbt->phase_seg2, dbt->sjw); -- } -+ char dsp[6]; -+ -+ open_json_object("data_bittiming"); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "bitrate", " dbitrate %u", dbt->bitrate); -+ snprintf(dsp, sizeof(dsp), "%.3f", dbt->sample_point / 1000.); -+ print_string(PRINT_ANY, "sample_point", " dsample-point %s", -+ dsp); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "tq", " dtq %u", dbt->tq); -+ print_uint(PRINT_ANY, "prop_seg", " dprop-seg %u", -+ dbt->prop_seg); -+ print_uint(PRINT_ANY, "phase_seg1", " dphase-seg1 %u", -+ dbt->phase_seg1); -+ print_uint(PRINT_ANY, "phase_seg2", " dphase-seg2 %u", -+ dbt->phase_seg2); -+ print_uint(PRINT_ANY, "sjw", " dsjw %u", dbt->sjw); -+ close_json_object(); - } - - /* data bittiming const is irrelevant if fixed bitrate is defined */ -@@ -465,29 +428,18 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - struct can_bittiming_const *dbtc = - RTA_DATA(tb[IFLA_CAN_DATA_BITTIMING_CONST]); - -- if (is_json_context()) { -- open_json_object("data_bittiming_const"); -- print_string(PRINT_JSON, "name", NULL, dbtc->name); -- can_print_json_timing_min_max("tseg1", -- dbtc->tseg1_min, -- dbtc->tseg1_max); -- can_print_json_timing_min_max("tseg2", -- dbtc->tseg2_min, -- dbtc->tseg2_max); -- can_print_json_timing_min_max("sjw", 1, dbtc->sjw_max); -- can_print_json_timing_min_max("brp", -- dbtc->brp_min, -- dbtc->brp_max); -- -- print_int(PRINT_JSON, "brp_inc", NULL, dbtc->brp_inc); -- close_json_object(); -- } else { -- fprintf(f, "\n %s: dtseg1 %d..%d dtseg2 %d..%d " -- "dsjw 1..%d dbrp %d..%d dbrp-inc %d", -- dbtc->name, dbtc->tseg1_min, dbtc->tseg1_max, -- dbtc->tseg2_min, dbtc->tseg2_max, dbtc->sjw_max, -- dbtc->brp_min, dbtc->brp_max, dbtc->brp_inc); -- } -+ open_json_object("data_bittiming_const"); -+ can_print_nl_indent(); -+ print_string(PRINT_ANY, "name", " %s:", dbtc->name); -+ can_print_timing_min_max("tseg1", " dtseg1", -+ dbtc->tseg1_min, dbtc->tseg1_max); -+ can_print_timing_min_max("tseg2", " dtseg2", -+ dbtc->tseg2_min, dbtc->tseg2_max); -+ can_print_timing_min_max("sjw", " dsjw", 1, dbtc->sjw_max); -+ can_print_timing_min_max("brp", " dbrp", -+ dbtc->brp_min, dbtc->brp_max); -+ print_uint(PRINT_ANY, "brp_inc", " dbrp_inc %u", dbtc->brp_inc); -+ close_json_object(); - } - - if (tb[IFLA_CAN_DATA_BITRATE_CONST]) { -@@ -505,30 +457,23 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - dbitrate = dbt->bitrate; - } - -- if (is_json_context()) { -- print_uint(PRINT_JSON, "data_bittiming_bitrate", -- NULL, dbitrate); -- open_json_array(PRINT_JSON, "data_bitrate_const"); -- for (i = 0; i < dbitrate_cnt; ++i) -- print_uint(PRINT_JSON, NULL, NULL, -- dbitrate_const[i]); -- close_json_array(PRINT_JSON, NULL); -- } else { -- fprintf(f, "\n dbitrate %u", dbitrate); -- fprintf(f, "\n ["); -- -- for (i = 0; i < dbitrate_cnt - 1; ++i) { -- /* This will keep lines below 80 signs */ -- if (!(i % 6) && i) -- fprintf(f, "\n "); -- -- fprintf(f, "%8u, ", dbitrate_const[i]); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "data_bittiming_bitrate", " dbitrate %u", -+ dbitrate); -+ can_print_nl_indent(); -+ open_json_array(PRINT_ANY, is_json_context() ? -+ "data_bitrate_const" : " ["); -+ for (i = 0; i < dbitrate_cnt; ++i) { -+ /* This will keep lines below 80 signs */ -+ if (!(i % 6) && i) { -+ can_print_nl_indent(); -+ print_string(PRINT_FP, NULL, "%s", " "); - } -- -- if (!(i % 6) && i) -- fprintf(f, "\n "); -- fprintf(f, "%8u ]", dbitrate_const[i]); -+ print_uint(PRINT_ANY, NULL, -+ i < dbitrate_cnt - 1 ? "%8u, " : "%8u", -+ dbitrate_const[i]); - } -+ close_json_array(PRINT_JSON, " ]"); - } - - if (tb[IFLA_CAN_TERMINATION_CONST] && tb[IFLA_CAN_TERMINATION]) { -@@ -538,29 +483,21 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - sizeof(*trm_const); - int i; - -- if (is_json_context()) { -- print_hu(PRINT_JSON, "termination", NULL, *trm); -- open_json_array(PRINT_JSON, "termination_const"); -- for (i = 0; i < trm_cnt; ++i) -- print_hu(PRINT_JSON, NULL, NULL, trm_const[i]); -- close_json_array(PRINT_JSON, NULL); -- } else { -- fprintf(f, "\n termination %hu [ ", *trm); -- -- for (i = 0; i < trm_cnt - 1; ++i) -- fprintf(f, "%hu, ", trm_const[i]); -- -- fprintf(f, "%hu ]", trm_const[i]); -- } -+ can_print_nl_indent(); -+ print_hu(PRINT_ANY, "termination", " termination %hu [ ", *trm); -+ open_json_array(PRINT_JSON, "termination_const"); -+ for (i = 0; i < trm_cnt; ++i) -+ print_hu(PRINT_ANY, NULL, -+ i < trm_cnt - 1 ? "%hu, " : "%hu", -+ trm_const[i]); -+ close_json_array(PRINT_JSON, " ]"); - } - - if (tb[IFLA_CAN_CLOCK]) { - struct can_clock *clock = RTA_DATA(tb[IFLA_CAN_CLOCK]); - -- print_int(PRINT_ANY, -- "clock", -- "\n clock %d ", -- clock->freq); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "clock", " clock %u ", clock->freq); - } - - } -@@ -573,31 +510,23 @@ static void can_print_xstats(struct link_util *lu, - if (xstats && RTA_PAYLOAD(xstats) == sizeof(*stats)) { - stats = RTA_DATA(xstats); - -- if (is_json_context()) { -- print_int(PRINT_JSON, "restarts", -- NULL, stats->restarts); -- print_int(PRINT_JSON, "bus_error", -- NULL, stats->bus_error); -- print_int(PRINT_JSON, "arbitration_lost", -- NULL, stats->arbitration_lost); -- print_int(PRINT_JSON, "error_warning", -- NULL, stats->error_warning); -- print_int(PRINT_JSON, "error_passive", -- NULL, stats->error_passive); -- print_int(PRINT_JSON, "bus_off", NULL, stats->bus_off); -- } else { -- fprintf(f, "\n re-started bus-errors arbit-lost " -- "error-warn error-pass bus-off"); -- fprintf(f, "\n %-10d %-10d %-10d %-10d %-10d %-10d", -- stats->restarts, stats->bus_error, -- stats->arbitration_lost, stats->error_warning, -- stats->error_passive, stats->bus_off); -- } -+ can_print_nl_indent(); -+ print_string(PRINT_FP, NULL, "%s", -+ " re-started bus-errors arbit-lost error-warn error-pass bus-off"); -+ can_print_nl_indent(); -+ print_uint(PRINT_ANY, "restarts", " %-10u", stats->restarts); -+ print_uint(PRINT_ANY, "bus_error", " %-10u", stats->bus_error); -+ print_uint(PRINT_ANY, "arbitration_lost", " %-10u", -+ stats->arbitration_lost); -+ print_uint(PRINT_ANY, "error_warning", " %-10u", -+ stats->error_warning); -+ print_uint(PRINT_ANY, "error_passive", " %-10u", -+ stats->error_passive); -+ print_uint(PRINT_ANY, "bus_off", " %-10u", stats->bus_off); - } - } - --static void can_print_help(struct link_util *lu, int argc, char **argv, -- FILE *f) -+static void can_print_help(struct link_util *lu, int argc, char **argv, FILE *f) - { - print_usage(f); - } --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch deleted file mode 100644 index 92bcd8d2..00000000 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2/0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0f7bb8d842b158169e0950b9a6ac642877e044bd Mon Sep 17 00:00:00 2001 -From: Vincent Mailhol -Date: Thu, 4 Nov 2021 01:44:27 +0900 -Subject: [PATCH 4/5] iplink_can: print brp and dbrp bittiming variables - -Report the value of the bit-rate prescaler (brp) for both the nominal -and the data bittiming. - -Currently, only the constant brp values (brp_{min,max,inc}) are being -reported. Also, brp is the only member of struct can_bittiming not -being reported. - -Noticeably, brp could be calculated by hand from the other bittiming -parameters with below formula: - - brp = clock * tq / 1000000000 - -with clock in hertz and tq in nano second (thus the need of a 1 -billion factor to convert it back to second). - -But because above formula is not so trivial to remember and is -subjected to rounding errors, it makes sense to directly output -{d,}bpr. - -Signed-off-by: Vincent Mailhol -Signed-off-by: David Ahern ---- - ip/iplink_can.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/ip/iplink_can.c b/ip/iplink_can.c -index c0165237..cf6b06b8 100644 ---- a/ip/iplink_can.c -+++ b/ip/iplink_can.c -@@ -344,6 +344,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - print_uint(PRINT_ANY, "phase_seg2", " phase-seg2 %u", - bt->phase_seg2); - print_uint(PRINT_ANY, "sjw", " sjw %u", bt->sjw); -+ print_uint(PRINT_ANY, "brp", " brp %u", bt->brp); - close_json_object(); - } - -@@ -419,6 +420,7 @@ static void can_print_opt(struct link_util *lu, FILE *f, struct rtattr *tb[]) - print_uint(PRINT_ANY, "phase_seg2", " dphase-seg2 %u", - dbt->phase_seg2); - print_uint(PRINT_ANY, "sjw", " dsjw %u", dbt->sjw); -+ print_uint(PRINT_ANY, "brp", " dbrp %u", dbt->brp); - close_json_object(); - } - --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb index 929d4ac9..99a74339 100644 --- a/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb +++ b/meta-xilinx-core/recipes-connectivity/iproute2/iproute2_5.15.0.bb @@ -2,10 +2,6 @@ require iproute2.inc SRC_URI = "${KERNELORG_MIRROR}/linux/utils/net/${BPN}/${BP}.tar.xz \ file://0001-libc-compat.h-add-musl-workaround.patch \ - file://0001-iplink_can-fix-configuration-ranges-in-print_usage-a.patch \ - file://0002-iplink_can-code-refactoring-of-print_ctrlmode.patch \ - file://0003-iplink_can-use-PRINT_ANY-to-factorize-code-and-fix-s.patch \ - file://0004-iplink_can-print-brp-and-dbrp-bittiming-variables.patch \ " SRC_URI[sha256sum] = "38e3e4a5f9a7f5575c015027a10df097c149111eeb739993128e5b2b35b291ff" -- cgit v1.2.3-54-g00ecf From 8a0cab1ab6444c33e7283732d7f4679dcbb52f49 Mon Sep 17 00:00:00 2001 From: Rohit Visavalia Date: Tue, 22 Mar 2022 04:52:13 -0700 Subject: zynqmp: xorg: Update xorg configuration file to use busid Instead of relying in Xorg's default flow(dri/card0) use DP PS busid for Display device. User can update busid based on display device used. Signed-off-by: Rohit Visavalia Signed-off-by: Mark Hatle --- .../recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf index 9ef39462..0e2988de 100644 --- a/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf +++ b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf @@ -13,6 +13,7 @@ EndSection Section "Device" Identifier "ZynqMP" Driver "armsoc" + Option "BusId" "fd4a0000.display" Option "DRI2" "true" Option "DRI2_PAGE_FLIP" "false" Option "DRI2_WAIT_VSYNC" "true" -- cgit v1.2.3-54-g00ecf From f14cbf990d66977cb9383a6da6da6a7cfe5c68f4 Mon Sep 17 00:00:00 2001 From: Rohit Visavalia Date: Tue, 22 Mar 2022 04:52:14 -0700 Subject: xserver-nodm-init: limit the number of restart for service With current option "Restart=always", xserver-nodm service will keep on restart if it fails. By limiting the restart count(5) unnecessary restart can be avoided. Signed-off-by: Rohit Visavalia Signed-off-by: Mark Hatle --- .../x11-common/xserver-nodm-init/xserver-nodm.service.in | 13 +++++++++++++ .../x11-common/xserver-nodm-init_%.bbappend | 1 + 2 files changed, 14 insertions(+) create mode 100644 meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init/xserver-nodm.service.in create mode 100755 meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend diff --git a/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init/xserver-nodm.service.in b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init/xserver-nodm.service.in new file mode 100644 index 00000000..5a4a6a05 --- /dev/null +++ b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init/xserver-nodm.service.in @@ -0,0 +1,13 @@ +[Unit] +Description=Xserver startup without a display manager +StartLimitBurst=5 +StartLimitIntervalSec=100 + +[Service] +EnvironmentFile=/etc/default/xserver-nodm +User=@USER@ +ExecStart=/etc/xserver-nodm/Xserver +Restart=always + +[Install] +Alias=display-manager.service diff --git a/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend new file mode 100755 index 00000000..eadb7e4a --- /dev/null +++ b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend @@ -0,0 +1 @@ +FILESEXTRAPATHS:append := "${THISDIR}/${PN}:" -- cgit v1.2.3-54-g00ecf From d186a309c686058fae43ad19f0026cfed518607e Mon Sep 17 00:00:00 2001 From: Venkateshwar Rao Gannavarapu Date: Thu, 24 Mar 2022 13:42:56 +0530 Subject: kernel-module-hdmi: Update SRCVER Updated SRCVER for 2022.1 Signed-off-by: Venkateshwar Rao Gannavarapu Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb index b3489bb7..82415e19 100644 --- a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb +++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb @@ -11,7 +11,7 @@ S = "${WORKDIR}/git" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https" -SRCREV = "bd448ffdbf59c1643160c0edd1b3a676fd0e23ed" +SRCREV = "25b6fe7a26a975be15c002b48cfd4c291486491e" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 474912916231260bcb1079da5c1cc4da7efd971a Mon Sep 17 00:00:00 2001 From: rbramand Date: Mon, 28 Mar 2022 12:10:53 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 056c5940..9d8b1d57 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "2022.1" -SRCREV= "445d6db8407b8375b9b870befa84db2f234a25e8" +SRCREV= "63ebdf0148634b7fa2880e48276da4ef0dc7ecdf" PV = "202210.2.13.0" -- cgit v1.2.3-54-g00ecf From b1ead83a2de3d31b068b05df12e40e6cbe444d40 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 31 Mar 2022 13:17:15 +0530 Subject: Update SRCREV and LICENSE checksum for ESW Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 5a173c2c..3bb177c4 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "4961570f7c8d8171dc3d675ed1f487f255c26d2d" +ESW_REV[2022.2] = "b7a49e141432141ec1f5e3a2256ba95c837cea4f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" @@ -36,8 +36,8 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1-next] = '87cee16dbcd2c2f7ceef30163838056e' -LIC_FILES_CHKSUM[master-next] = '87cee16dbcd2c2f7ceef30163838056e' -LIC_FILES_CHKSUM[master] = '87cee16dbcd2c2f7ceef30163838056e' +LIC_FILES_CHKSUM[master-next] = 'f3d40ec01cd45728f200f85c1e7a2ded' +LIC_FILES_CHKSUM[master] = 'f3d40ec01cd45728f200f85c1e7a2ded' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" -- cgit v1.2.3-54-g00ecf From efb7be44b3377e7fe5683bae749df590658f8a79 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 31 Mar 2022 16:24:27 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 4709d218..f02bb879 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "b7fe0b19a25c1473958a363f92b56b8d20d78c0e" +SRCREV = "67ca59c67f542322554d78820bf9ddaa736d6a84" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 37f36915..055d2a24 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "0ae9ba138b625072d80c837560760b075bbdfd4e" +SRCREV = "b4a6e1a57216931db461ae723818bf57ad1c1835" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index ec014354..7275593a 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "ae78bf6ba89f388361c223b89aed350b5ceee971" +SRCREV = "345aa64fe04d1de0995cb41afc671b7ef499dffd" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From dc5b59fca132689629214763127ca6240c48ab0e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 31 Mar 2022 22:58:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3bb177c4..4d7a08be 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "b7a49e141432141ec1f5e3a2256ba95c837cea4f" +ESW_REV[2022.2] = "092ce866dff2a7242b166805e4af25355052b71d" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 5cae9775ec4a1744a6bd43d8d0ad828e6ca256e0 Mon Sep 17 00:00:00 2001 From: John Toomey Date: Wed, 30 Mar 2022 11:37:51 +0100 Subject: Fix ATF provencore enable not working arm-trusted-firmware checks if "provencore" is in COMBINED_FEATURES but this is not correct as COMBINED_FEATURES contains the intersection of MACHINE_FEATURES and DISTRO_FEATURES rather than the union and the required settings do not get applied. This change checks for "provencore" in MACHINE_FEATURES. Signed-off-by: John Toomey Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 5b2a6498..5591fa63 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -69,7 +69,7 @@ EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" ATF_PROVENCORE = "SPD=pncd ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x10000000 PRELOADED_BL33_BASE=0x80000000" -EXTRA_OEMAKE:append = "${@bb.utils.contains('COMBINED_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" +EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" do_configure() { oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} -- cgit v1.2.3-54-g00ecf From e716f0cc60c7dcfcd5e989370488c000a4420d5e Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Thu, 31 Mar 2022 15:48:29 +0530 Subject: recipes-kernel: linux: add auto load support for usb2244 driver This patch adds usb2244 (USB-SD) autoload module support for the kr260 board. Signed-off-by: Piyush Mehta Signed-off-by: Mark Hatle --- meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bbappend | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bbappend b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bbappend index 285621b1..6fd1a3c3 100644 --- a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bbappend +++ b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx-dev.bbappend @@ -1,4 +1,5 @@ KERNEL_MODULE_AUTOLOAD:k26 += "usb5744" +KERNEL_MODULE_AUTOLOAD:k26 += "usb2244" # MicroBlaze BSP fragments KERNEL_FEATURES:append:kc705-microblazeel = " bsp/xilinx/kc705-microblazeel-features/kc705-microblazeel-features.scc" -- cgit v1.2.3-54-g00ecf From e5afe2debd1994b66433490108f5d1f3ea2441b1 Mon Sep 17 00:00:00 2001 From: rbramand Date: Thu, 31 Mar 2022 16:38:29 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 9d8b1d57..14d3ea25 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -2,8 +2,8 @@ REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -BRANCH= "2022.1" -SRCREV= "63ebdf0148634b7fa2880e48276da4ef0dc7ecdf" +BRANCH= "master" +SRCREV= "ac5840899cb350aa0db7575547b49e0fdc24cb97" PV = "202210.2.13.0" -- cgit v1.2.3-54-g00ecf From 34e25a7ef6be15bd6d8120b7c0a292a3bbe71480 Mon Sep 17 00:00:00 2001 From: RamyaSree Date: Thu, 31 Mar 2022 15:52:50 +0530 Subject: Update to bootgen SRCREV to point to latest commit. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb index 8f89200d..85880158 100644 --- a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb @@ -11,7 +11,7 @@ RDEPENDS:${PN} += "openssl" REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" BRANCH ?= "master" -SRCREV = "2b8859218defc9983b6d312c8be48d0c08070ca1" +SRCREV = "4eac958eb6c831ffa5768a0e2cd4be23c5efe2e0" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 3084f56453891b9570c5c2be479b2f2afab6bfbc Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Fri, 1 Apr 2022 07:36:49 +0530 Subject: Updated SRCREV for 2022.1 Signed-off-by: Siva Addepalli Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 5bba168c..719b99c2 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "4e6eef210db4dc0399a70688f17413850012f3a1" +SRCREV = "ca342c901c1116ffdc1c58513ea35997b2ace53f" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From 5141ee7a92d6de0f159607e65158726bd8417d9c Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 2 Apr 2022 12:17:05 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 7275593a..3014a1bf 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "345aa64fe04d1de0995cb41afc671b7ef499dffd" +SRCREV = "57d751774476772c1bc02fbdeb7c75a3f917695d" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 54e4ceab902ed0f4493133b5c11dbff90aebc335 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 1 Apr 2022 11:40:07 +0530 Subject: meta-xilinx-standalone-experimental: recipes-bsp: embeddedsw: plm-firmware: Update dependencies as per latest source code With the updated source code plm is depending on xilnvm library update the dependency for the same. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-bsp/embeddedsw/plm-firmware_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/plm-firmware_git.bbappend b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/plm-firmware_git.bbappend index 558e5fd9..8a72a184 100644 --- a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/plm-firmware_git.bbappend +++ b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/plm-firmware_git.bbappend @@ -18,4 +18,4 @@ do_install() { : } -DEPENDS += "xilstandalone xiltimer xilffs xilpdi xilplmi xilloader xilpm xilsecure xilsem" +DEPENDS += "xilstandalone xiltimer xilffs xilpdi xilplmi xilloader xilpm xilsecure xilsem xilnvm" -- cgit v1.2.3-54-g00ecf From 58ac45a28df88461eeff5c07570d3f64aa3d84d8 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 1 Apr 2022 11:40:08 +0530 Subject: meta-xilinx-standalone-experimental: recipes-libraries: xilnvm: Update dependencies as per latest source code With the updated source code xilnvm is depending on xilplmi library update the dependency for the same. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-libraries/xilnvm_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm_git.bb index cd73f69f..9114aa72 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm_git.bb @@ -3,4 +3,4 @@ inherit esw ESW_COMPONENT_SRC = "/lib/sw_services/xilnvm/src/" ESW_COMPONENT_NAME = "libxilnvm.a" -DEPENDS += "libxil xiltimer" +DEPENDS += "libxil xiltimer xilplmi" -- cgit v1.2.3-54-g00ecf From 3237767e23367fcac0aed9c689431593793ecadb Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 1 Apr 2022 11:40:09 +0530 Subject: meta-xilinx-standalone-experimental: recipes-libraries: xilpuf: Update dependencies as per latest source code With the updated source code xilpuf is depending on xilplmi library update the dependency for the same. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb index d6d3550c..4f9332c7 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb @@ -3,4 +3,4 @@ inherit esw ESW_COMPONENT_SRC = "/lib/sw_services/xilpuf/src/" ESW_COMPONENT_NAME = "libxilpuf.a" -DEPENDS += "libxil xiltimer" +DEPENDS += "libxil xiltimer xilplmi" -- cgit v1.2.3-54-g00ecf From 5eda1310b02be7176d8306ed041ebe65a6194300 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 1 Apr 2022 11:40:10 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update branch This commit updates the branch to xilinx-v2022.1-sdt-experimental branch. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index ee7492ea..ba47883c 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -4,10 +4,9 @@ # Make it clear decoupling is 'experimental' in the version ESW_VER = "experimental" -REPO = "git://github.com/Xilinx/embeddedsw-experimental-dt-support.git;protocol=https" +REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" -ESW_BRANCH[experimental] = "xilinx-v2021.1-sdt-experimental" -ESW_REV[experimental] = "329bf8fa54110034c8436d0b3b4aa40e8a56b02d" +ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" +ESW_REV[experimental] = "a2d3e16376898780a75719688f2254349ae98962" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' -LIC_FILES_CHKSUM[xilinx-v2021.1-sdt-experimental] = '7c92de7a21a6613265035c28f4a92f48' - +LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = '1d552a9ac3973bf5fcff6fb9cb2034ea' -- cgit v1.2.3-54-g00ecf From eb060e678f792000872dbf9b32fa9b5686f3a127 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 1 Apr 2022 10:16:52 -0700 Subject: meta-xilinx-standalone-experimental: recipes-bsp: embeddedsw: fsbl-firmware: properly copy the psu_init* files The files are copied into ${WORKDIR} and need to be made available to be used by the sources. Signed-off-by: Mark Hatle --- .../recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend index 056ad990..439f47f4 100644 --- a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend +++ b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend @@ -33,6 +33,16 @@ python() { bb.warn("Unable to find %s, using default version" % psu_init_h) } +do_compile:prepend() { + if [ -e ${WORKDIR}/psu_init.c ]; then + install -m 0644 ${WORKDIR}/psu_init.c ${S}/${ESW_COMPONENT_SRC} + fi + + if [ -e ${WORKDIR}/psu_init.h ]; then + install -m 0644 ${WORKDIR}/psu_init.h ${S}/${ESW_COMPONENT_SRC} + fi +} + do_install() { : } -- cgit v1.2.3-54-g00ecf From 53811409279533ee8c463355f5196d9a1ae92a3b Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 5 Apr 2022 16:06:32 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 055d2a24..752218df 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "b4a6e1a57216931db461ae723818bf57ad1c1835" +SRCREV = "f1a3ac43e52d9e2a26f164c9b6e9d8ae9fd32a41" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 4d7a08be..1614b61b 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" -ESW_REV[2022.2] = "092ce866dff2a7242b166805e4af25355052b71d" +ESW_REV[2022.2] = "0918623a1f607eef78fa77309d235beac8f7f95b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 04a26976d96eba550a0dfd28b912b64eb1ef66cd Mon Sep 17 00:00:00 2001 From: rbramand Date: Mon, 4 Apr 2022 12:16:28 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 14d3ea25..c964d747 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "ac5840899cb350aa0db7575547b49e0fdc24cb97" +SRCREV= "08f182574a2e7b3e545a81cb399b2aeff0ea913b" PV = "202210.2.13.0" -- cgit v1.2.3-54-g00ecf From 3fe9375d75c1e5266cef1feb27c57d6a5b83ca1f Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 4 Apr 2022 11:11:01 -0700 Subject: linux-firmware-ti-bt: dbg package requires dev package which requires base Add an empty base package w/ an RDEPENDS on the specifically named firmware package. This allows the automatic installation of -dev or -dbg packages to work properly. Signed-off-by: Mark Hatle --- .../recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb b/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb index 1ad8ae2e..6bb39051 100644 --- a/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb +++ b/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb @@ -53,6 +53,10 @@ do_install() { # 11.8.32 = WL180x, WL183x, WL185x PG2.1 or PG2.2, 8.32 ROM Version PACKAGES =+ "${PN}-wl180x ${PN}-license" +# Ensure if someone installs the main one, they get the specific named package +ALLOW_EMPTY:${PN} = "1" +RDEPENDS:${PN} += "${PN}-wl180x" + FILES:${PN}-license = "${nonarch_base_libdir}/firmware/License.ti-bt" FILES:${PN}-wl180x = "${nonarch_base_libdir}/firmware/TIInit_11.8.32.bts \ -- cgit v1.2.3-54-g00ecf From c7199a981baa46911b1ec8e71e980ec2239c2971 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 6 Apr 2022 12:17:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 3014a1bf..175ceff1 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "57d751774476772c1bc02fbdeb7c75a3f917695d" +SRCREV = "b69197c3f3202af1a06397760e890444f726d900" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 04d0674c3ad8173293da0e7bdda712a2b4ffbee1 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 5 Apr 2022 14:05:30 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update SRCREV for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index ba47883c..d88d379e 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "a2d3e16376898780a75719688f2254349ae98962" +ESW_REV[experimental] = "cf261e654ec41c0b91362c83d2d58bc38a942708" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = '1d552a9ac3973bf5fcff6fb9cb2034ea' -- cgit v1.2.3-54-g00ecf From 666a2dccb046e3d424bfc278f25cdec42351efe0 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 5 Apr 2022 12:18:07 -0700 Subject: xserver-nodm-init: Fix FILESEXTRAPATHS : placement Signed-off-by: Mark Hatle --- .../recipes-graphics/x11-common/xserver-nodm-init_%.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend index eadb7e4a..0a789a20 100755 --- a/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend +++ b/meta-xilinx-core/recipes-graphics/x11-common/xserver-nodm-init_%.bbappend @@ -1 +1 @@ -FILESEXTRAPATHS:append := "${THISDIR}/${PN}:" +FILESEXTRAPATHS:append := ":${THISDIR}/${PN}" -- cgit v1.2.3-54-g00ecf From 49912c9a380bd1b472abe925e83b785b16e76dfb Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 5 Apr 2022 09:13:28 -0700 Subject: meta-xilinx-standalone-experimental: fsbl-firmware: Fix issue with fetch into wrong directory The file:// items were being placed in the same path structure in WORKDIR as they were in the original path passed into the recipe. Instead we want the files to always just show up in the WORKDIR. Move to using a simple file://psu_init.[ch] entry, but use FILESEXTRAPATHS to handle the access to the correct path. Upside is that everything works as expected, downside, if the path to the psu_init files also contain other items refered to by SRC_URI, it could pick up that version instead. With the current implementation, this is unlikely to be a problem. The code also moves the warning about using the default psu_init files to the do_compile. Unfortunately doing it in the anonymous python causes the warning to be generated for all multiconfigs, even ones that will never build the fsbl files. There is no simply way to disable this warning in those cases. Signed-off-by: Mark Hatle --- .../embeddedsw/fsbl-firmware_git.bbappend | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend index 439f47f4..330f0ead 100644 --- a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend +++ b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend @@ -8,6 +8,7 @@ inherit esw # Not compatible with Zynq COMPATIBLE_MACHINE:zynq = "none" +COMPATIBLE_MACHINE:microblaze = "none" ESW_COMPONENT_SRC = "/lib/sw_apps/undefined/src" ESW_COMPONENT_SRC:zynq = "/lib/sw_apps/zynq_fsbl/src" @@ -23,23 +24,30 @@ python() { psu_init_c = os.path.join(psu_init_path, 'psu_init.c') psu_init_h = os.path.join(psu_init_path, 'psu_init.h') + add_path = False if os.path.exists(psu_init_c): - d.appendVar('SRC_URI', ' file://%s' % psu_init_c) - else: - bb.warn("Unable to find %s, using default version" % psu_init_c) + d.appendVar('SRC_URI', ' file://psu_init.c') + add_path = True + if os.path.exists(psu_init_h): - d.appendVar('SRC_URI', ' file://%s' % psu_init_h) - else: - bb.warn("Unable to find %s, using default version" % psu_init_h) + d.appendVar('SRC_URI', ' file://psu_init.h') + add_path = True + + if add_path: + d.prependVar('FILESEXTRAPATHS', '%s:' % psu_init_path) } do_compile:prepend() { if [ -e ${WORKDIR}/psu_init.c ]; then install -m 0644 ${WORKDIR}/psu_init.c ${S}/${ESW_COMPONENT_SRC} + else + bbwarn "Using the default psu_init.c, this may not work correctly." fi if [ -e ${WORKDIR}/psu_init.h ]; then install -m 0644 ${WORKDIR}/psu_init.h ${S}/${ESW_COMPONENT_SRC} + else + bbwarn "Using the default psu_init.h, this may not work correctly." fi } -- cgit v1.2.3-54-g00ecf From 6945929681a1466a5310e7cce1c30e0aa9d6b7d3 Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Tue, 5 Apr 2022 21:34:19 -0700 Subject: dfx-mgr: new SRCREV, remove libdfxgraph Remove libdfxgraph package since the new SRCREV is due to removal of the opendfx-graph code. Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 719b99c2..525fbd46 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "ca342c901c1116ffdc1c58513ea35997b2ace53f" +SRCREV = "6c34598afeced2a6a4e6c500dd8c036be3890d4c" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" @@ -50,9 +50,6 @@ do_install(){ oe_soinstall ${B}/src/libdfx-mgr.so.${SOVERSION} ${D}${libdir} - install -m 0644 ${S}/opendfx-graph/include/graph_api.h ${D}${includedir} - oe_soinstall ${B}/opendfx-graph/libdfxgraph.so.${SOVERSION} ${D}${libdir} - install -m 0755 ${S}/src/daemon.conf ${D}${sysconfdir}/dfx-mgrd/ if ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'true', 'false', d)}; then @@ -65,9 +62,8 @@ do_install(){ install -m 0644 ${WORKDIR}/dfx-mgr.service ${D}${systemd_system_unitdir} } -PACKAGES =+ "libdfx-mgr libdfxgraph" +PACKAGES =+ "libdfx-mgr" FILES:${PN} += "${base_libdir}/firmware/xilinx" FILES:${PN} += "${@bb.utils.contains('DISTRO_FEATURES','sysvinit','${sysconfdir}/init.d/dfx-mgr.sh', '', d)} ${systemd_system_unitdir}" FILES:libdfx-mgr = "${libdir}/libdfx-mgr.so.${SOVERSION} ${libdir}/libdfx-mgr.so.${SOMAJOR}" -FILES:libdfxgraph = "${libdir}/libdfxgraph.so.${SOVERSION} ${libdir}/libdfxgraph.so.${SOMAJOR}" -- cgit v1.2.3-54-g00ecf From 1df9b28d5284e2ee333c705ce0b41686a87decba Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Wed, 6 Apr 2022 10:42:29 -0700 Subject: dt-processor: Update to use latest lopper Latest lopper separates the pruning of nodes into separate lop files. Ensure that: 1. Latest lopper is used 2. These pruning operations are included in the A53 and A72 Linux lopper runs. Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- .../recipes-core/meta/files/dt-processor.sh | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index ccbc19e2..78fbe92d 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "f70eb86385f49545070a84ad756902b3cd607e21" +SRCREV = "0d56f35e739c62aba2a47523590241e6bfe1db65" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 4aba672d..c0c9df18 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -123,11 +123,15 @@ cortex_a53_linux() { elif [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" \ - -i "${lops_dir}/lop-domain-linux-a53.dts" "${system_dtb}" "${dtb_file}" \ + -i "${lops_dir}/lop-domain-linux-a53.dts" \ + -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ + "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ - -i "${lops_dir}/lop-domain-linux-a53.dts" "${system_dtb}" "${dtb_file}" \ + -i "${lops_dir}/lop-domain-linux-a53.dts" \ + -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ + "${system_dtb}" "${dtb_file}" \ || error "lopper failed" fi rm -f pl.dtsi lop-a53-imux.dts.dtb lop-domain-linux-a53.dts.dtb -- cgit v1.2.3-54-g00ecf From e7ebfe05ca75c1a15665ca6f4cb2580a34931373 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 6 Apr 2022 18:37:19 -0700 Subject: Revert "Updated SRCREV for 2022.1" This reverts commit 0c6017795ba1499cb6b6aaab67a78f10a71dbdd3. Prep for 2022.2 update Signed-off-by: Mark Hatle --- .../vcu/files/0001-fix-timestamps-issues.patch | 99 ---------------------- .../recipes-multimedia/vcu/libomxil-xlnx.bb | 3 - 2 files changed, 102 deletions(-) delete mode 100644 meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch diff --git a/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch b/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch deleted file mode 100644 index c5521cca..00000000 --- a/meta-xilinx-core/recipes-multimedia/vcu/files/0001-fix-timestamps-issues.patch +++ /dev/null @@ -1,99 +0,0 @@ -From b3308c608be7ed9250b9c6732f6e0a02b1a2e985 Mon Sep 17 00:00:00 2001 -From: Arthur Vinchon -Date: Wed, 2 Mar 2022 02:29:48 +0530 -Subject: [PATCH] fix: timestamps issues - -Acked-by:Varunkumar Allagadapa ---- - base/omx_component/omx_component_dec.cpp | 32 ++++++++++++++---------- - base/omx_component/omx_component_dec.h | 2 +- - 2 files changed, 20 insertions(+), 14 deletions(-) - -diff --git a/base/omx_component/omx_component_dec.cpp b/base/omx_component/omx_component_dec.cpp -index 137bf2f..b40c770 100644 ---- a/base/omx_component/omx_component_dec.cpp -+++ b/base/omx_component/omx_component_dec.cpp -@@ -58,7 +58,8 @@ static DecModule& ToDecModule(ModuleInterface& module) - - DecComponent::DecComponent(OMX_HANDLETYPE component, shared_ptr media, std::unique_ptr&& module, OMX_STRING name, OMX_STRING role, std::unique_ptr&& expertise) : - Component{component, media, std::move(module), std::move(expertise), name, role}, -- shouldPropagateData{true}, oldTimeStamp{-1} -+ oldTimeStamp{-1}, -+ dataHasBeenPropagated{false} - { - } - -@@ -77,8 +78,9 @@ void DecComponent::FlushComponent() - FlushFillEmptyBuffers(true, true); - std::unique_lock lock(mutex); - transmit.clear(); -+ oldTimeStamp = -1; -+ dataHasBeenPropagated = false; - lock.unlock(); -- shouldPropagateData = true; - } - - void DecComponent::AssociateCallBack(BufferHandleInterface* empty_, BufferHandleInterface* fill_) -@@ -104,8 +106,8 @@ void DecComponent::AssociateCallBack(BufferHandleInterface* empty_, BufferHandle - { - callbacks.EventHandler(component, app, OMX_EventBufferFlag, output.index, emptyHeader.nFlags, nullptr); - transmit.clear(); -- shouldPropagateData = true; - oldTimeStamp = -1; -+ dataHasBeenPropagated = false; - } - - if(IsCompMarked(emptyHeader.hMarkTargetComponent, component)) -@@ -351,22 +353,26 @@ void DecComponent::TreatEmptyBufferCommand(Task* task) - - if(!isInputParsed || isEarlyCallbackUsed) - { -- bool isEndOfFrameFlagRaised = (header->nFlags & OMX_BUFFERFLAG_ENDOFFRAME); -+ /* we suppose that a timestamp changes is a frame changes [concealment] */ -+ bool const transmitTimeStamp = (oldTimeStamp != header->nTimeStamp); - -- if(isEndOfFrameFlagRaised && !isEarlyCallbackUsed) -+ if(transmitTimeStamp) -+ { - transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); -+ oldTimeStamp = header->nTimeStamp; -+ dataHasBeenPropagated = true; -+ } - else - { -- /* Concealment case(header->nFlags EndOfFrame is missing): propagate data if timestamps differ */ -- shouldPropagateData |= (oldTimeStamp != header->nTimeStamp); -- -- if(shouldPropagateData) -+ bool isEndOfFrameFlagRaised = (header->nFlags & OMX_BUFFERFLAG_ENDOFFRAME); -+ if(isEndOfFrameFlagRaised) - { -- transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); -- oldTimeStamp = header->nTimeStamp; -+ if(!dataHasBeenPropagated) -+ { -+ transmit.push_back(PropagatedData { header->hMarkTargetComponent, header->pMarkData, header->nTickCount, header->nTimeStamp, header->nFlags }); -+ } -+ dataHasBeenPropagated = false; - } -- -- shouldPropagateData = isEndOfFrameFlagRaised; - } - } - -diff --git a/base/omx_component/omx_component_dec.h b/base/omx_component/omx_component_dec.h -index 6214856..07d062e 100644 ---- a/base/omx_component/omx_component_dec.h -+++ b/base/omx_component/omx_component_dec.h -@@ -76,7 +76,7 @@ private: - void TreatEmptyBufferCommand(Task* task) override; - std::list transmit; - std::mutex mutex; -- bool shouldPropagateData; - OMX_TICKS oldTimeStamp; -+ bool dataHasBeenPropagated; - }; - --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb index 2a0e49b4..f86fc3ed 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb @@ -13,9 +13,6 @@ SRCREV = "a9d452e772da6bc43f524230c79e6dc0f2442fd7" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -# Sync to 2022.1 version -SRC_URI += "file://0001-fix-timestamps-issues.patch" - S = "${WORKDIR}/git" COMPATIBLE_MACHINE = "^$" -- cgit v1.2.3-54-g00ecf From 055ac14a542c7090a45ecb040284d9cc6bf37fd6 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 11 Apr 2022 07:59:22 -0700 Subject: meta-xilinx-standalone: move to release embeddedsw branch Signed-off-by: Mark Hatle (cherry picked from commit 6e7407565e10a9d70ec37365996031bb4fe14269) Signed-off-by: Mark Hatle --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 1614b61b..092738e7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -9,7 +9,7 @@ ESW_BRANCH[2020.1] = "release-2020.1" ESW_BRANCH[2020.2] = "master-rel-2020.2" ESW_BRANCH[2021.1] = "xlnx_rel_v2021.1" ESW_BRANCH[2021.2] = "xlnx_rel_v2021.2" -ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1-next" +ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1" ESW_BRANCH[2022.2] = "master-next" ESW_BRANCH[git] = "master-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" @@ -20,7 +20,7 @@ ESW_REV[2020.1] = "338150ab3628a1ea6b06e964b16e712b131882dd" ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" -ESW_REV[2022.1] = "c82bb6f04c77580746c7475d85e43c37d5fe5fa4" +ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" ESW_REV[2022.2] = "0918623a1f607eef78fa77309d235beac8f7f95b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" @@ -35,7 +35,7 @@ LIC_FILES_CHKSUM[release-2020.1] = '8b565227e1264d677db8f841c2948cba' LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' -LIC_FILES_CHKSUM[xlnx_rel_v2022.1-next] = '87cee16dbcd2c2f7ceef30163838056e' +LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM[master-next] = 'f3d40ec01cd45728f200f85c1e7a2ded' LIC_FILES_CHKSUM[master] = 'f3d40ec01cd45728f200f85c1e7a2ded' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" -- cgit v1.2.3-54-g00ecf From 9403fc26b709c6babf868b8b6e2fab927220563d Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Mon, 11 Apr 2022 11:15:16 -0700 Subject: dfx-mgr: new SRCREV, remove xrt Remove xrt due to changes in the new SRCREV Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 525fbd46..78147881 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "6c34598afeced2a6a4e6c500dd8c036be3890d4c" +SRCREV = "b82419d93ec3cff6fe8095b5298a28bffb75b184" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" @@ -22,7 +22,7 @@ S = "${WORKDIR}/git" inherit cmake update-rc.d systemd -DEPENDS += " libwebsockets inotify-tools libdfx xrt zocl libdrm" +DEPENDS += " libwebsockets inotify-tools libdfx zocl libdrm" EXTRA_OECMAKE += " \ -DCMAKE_SYSROOT:PATH=${RECIPE_SYSROOT} \ " -- cgit v1.2.3-54-g00ecf From 7aeb23ee3072153f20c9a09d71f47505a2bc8a41 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 11 Apr 2022 16:38:40 +0530 Subject: meta-xilinx-standalone-experimental: Deploy images to sub folder having component/recipe name This commit updates the deploy task to deploy images to a sub folder having component name. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/classes/esw_examples.bbclass | 4 ++-- .../recipes-drivers/clockps-example_git.bb | 4 ++-- .../recipes-libraries/xilffs-example_git.bb | 4 ++-- .../recipes-libraries/xilfpga-example_git.bb | 4 ++-- .../recipes-libraries/xilmailbox-example_git.bb | 4 ++-- .../recipes-libraries/xilnvm-example_git.bb | 4 ++-- .../recipes-libraries/xilpuf-example_git.bb | 4 ++-- .../recipes-libraries/xilsecure-example_git.bb | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) diff --git a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass index 64e0810c..0ebc38a0 100644 --- a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass @@ -26,8 +26,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb index 0bc67b11..97871326 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb @@ -31,8 +31,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb index d5c90bba..7f3618c8 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb @@ -20,8 +20,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb index e1af36e0..5137c591 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb @@ -20,8 +20,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb index 0fb74a63..a525e1bc 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb @@ -29,8 +29,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb index 7a931ed4..ef8b6e64 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb @@ -20,8 +20,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb index 64f49d71..d43b4da9 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb @@ -20,8 +20,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb index 3c424215..4c2be337 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb @@ -20,8 +20,8 @@ do_install() { } do_deploy() { - install -d ${DEPLOYDIR}/${MACHINE}-${BPN}/ - install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${MACHINE}-${BPN}/ + install -d ${DEPLOYDIR}/${BPN}/ + install -Dm 0644 ${WORKDIR}/package/${base_libdir}/firmware/*.elf ${DEPLOYDIR}/${BPN}/ } addtask deploy before do_build after do_package -- cgit v1.2.3-54-g00ecf From 1ddaf20eb0935d76d95011084c90fda02e614508 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 11 Apr 2022 16:38:50 +0530 Subject: meta-xilinx-standalone-experimental: recipes-core: meta: dt-processor.sh: Add support for generating petalinux conf file This commit adds an optional -P argument for generating the petalinux conf file, Generated file will be consumed by the petalinux tool. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index c0c9df18..441dc7d2 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -41,6 +41,7 @@ $0 [-m ] zynqmp or versal [-p ] Path to psu_init files, defaults to system_dtb path [-l ] write local.conf changes to this file + [-P ] Path to petalinux schema file EOF exit @@ -49,7 +50,7 @@ EOF parse_args() { [ $# -eq 0 ] && usage - while getopts ":c:s:d:o:e:m:l:h" opt; do + while getopts ":c:s:d:o:e:m:l:h:P:" opt; do case ${opt} in c) config_dir=$OPTARG ;; s) system_dtb=$OPTARG ;; @@ -59,6 +60,7 @@ parse_args() { m) machine=$OPTARG ;; p) psu_init_path=$OPTARG ;; l) localconf=$OPTARG ;; + P) petalinux_schema=$OPTARG ;; h) usage ;; :) error "Missing argument for -$OPTARG" ;; \?) error "Invalid option -$OPTARG" @@ -920,6 +922,13 @@ gen_local_conf() { echo } +gen_petalinux_conf() { + cd "${config_dir}" || exit + ( + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} "${system_dtb}" -- petalinuxconfig_xlnx ${petalinux_schema} \ + || error "lopper failed" + ) +} parse_args "$@" lopper=$(command -v lopper) @@ -964,5 +973,12 @@ else gen_local_conf ${localconf} fi +if [ -n "${petalinux_schema}" ]; then + echo + echo "Generating petalinux config file:" + echo + gen_petalinux_conf +fi + # Cleanup our temp file rm ${cpulist} -- cgit v1.2.3-54-g00ecf From 5f90862766341cc7c0267d3156f7c57f763a8421 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 13 Apr 2022 11:19:34 +0530 Subject: Updated MD5SUM and SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 092738e7..14ed6996 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "0918623a1f607eef78fa77309d235beac8f7f95b" +ESW_REV[2022.2] = "a418d4d2b9681bfa850fac60cd70490e3d5fac9b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" @@ -36,8 +36,8 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' -LIC_FILES_CHKSUM[master-next] = 'f3d40ec01cd45728f200f85c1e7a2ded' -LIC_FILES_CHKSUM[master] = 'f3d40ec01cd45728f200f85c1e7a2ded' +LIC_FILES_CHKSUM[master-next] = 'e62cb7a722c4430999e0a55a7234035d' +LIC_FILES_CHKSUM[master] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" -- cgit v1.2.3-54-g00ecf From 07e4b930badbf3d033da532f9c6c3fb2e7649e75 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 13 Apr 2022 13:35:26 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 175ceff1..90a35ded 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "b69197c3f3202af1a06397760e890444f726d900" +SRCREV = "0b70857ca66da7d471f5c17d1af67a2af273a960" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 9213a5183559ad69f3f9fbe56312b9241b292682 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 13 Apr 2022 13:36:32 -0700 Subject: zocl: This is not compatible with microblaze architecture Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb index 40578aa2..ea0728f3 100644 --- a/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb +++ b/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb @@ -1,6 +1,7 @@ SUMMARY = "Xilinx Runtime(XRT) driver module" DESCRIPTION = "Xilinx Runtime driver module provides memory management and compute unit schedule" +COMPATIBLE_MACHINE:microblaze = "none" require recipes-xrt/xrt/xrt.inc -- cgit v1.2.3-54-g00ecf From acc5dc830f3216e6140bbad44164589ccea84b1a Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 12 Apr 2022 12:28:31 +0530 Subject: lopper: updated srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 78fbe92d..df034543 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "0d56f35e739c62aba2a47523590241e6bfe1db65" +SRCREV = "cc3de250f5bbd9e41e2b2cc09fb19f18d79f3ae3" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 171c4114b2f9f039698e2538f2898a2913fc742d Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Tue, 12 Apr 2022 08:27:49 -0700 Subject: dt-processor: Use pruning lop file for Versal A72 Linux loper runs Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 441dc7d2..2dc48b75 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -325,11 +325,15 @@ cortex_a72_linux() { elif [ -n "${domain_file}" ]; then LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" \ - -i "${lops_dir}/lop-domain-a72.dts" "${system_dtb}" "${dtb_file}" \ + -i "${lops_dir}/lop-domain-a72.dts" \ + -i "${lops_dir}/lop-domain-a72-prune.dts" \ + "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ - -i "${lops_dir}/lop-domain-a72.dts" "${system_dtb}" "${dtb_file}" || error "lopper failed" + -i "${lops_dir}/lop-domain-a72.dts" \ + -i "${lops_dir}/lop-domain-a72-prune.dts" \ + "${system_dtb}" "${dtb_file}" || error "lopper failed" fi rm -f pl.dtsi lop-a72-imux.dts.dtb lop-domain-a72.dts.dtb ) -- cgit v1.2.3-54-g00ecf From f21519defd344740743d612131991d740c0836a9 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 15 Apr 2022 12:16:53 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 51a0a677..7a7980f9 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "52a9b22faeb149a6b17646b1f912f06ea6c269ca" +SRCREV = "4db892198d7466a0502353c6e3191aa14c10876d" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -- cgit v1.2.3-54-g00ecf From ecbac7d8fb48ef8e26303d287e2bd001db785f17 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 20 Apr 2022 06:33:49 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 14ed6996..3b643277 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a418d4d2b9681bfa850fac60cd70490e3d5fac9b" +ESW_REV[2022.2] = "ce070046630c34ae58b353eb4d0d2da96517bb58" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From c0d0ad1e9b7fb91d392aee30b3fa4718725f6413 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 21 Apr 2022 17:02:49 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 7a7980f9..121e4add 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "4db892198d7466a0502353c6e3191aa14c10876d" +SRCREV = "75b6a9b4f3877946cca003c285df2585768e6f3b" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3b643277..7843b7e7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "ce070046630c34ae58b353eb4d0d2da96517bb58" +ESW_REV[2022.2] = "85c86ddc42f28381eaafe6aedeada6141e67bad2" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From e5b1b99eb133c6b7fa4aafe8b177aff383e9d608 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 18 Apr 2022 11:52:58 +0530 Subject: lopper: updated srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index df034543..c5232218 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "cc3de250f5bbd9e41e2b2cc09fb19f18d79f3ae3" +SRCREV = "5c3074bc460fa13c679bf41159e23a854fdf9b89" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 033b7ef7a605c4288f92715f13ae186eaf0dae15 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 26 Apr 2022 12:17:24 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 121e4add..9d5bb210 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "75b6a9b4f3877946cca003c285df2585768e6f3b" +SRCREV = "9105d22e6deaac62426152052631e69e1c024f00" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -- cgit v1.2.3-54-g00ecf From f1453f63d971db61f5852116d71a4714be4dff30 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 26 Apr 2022 20:46:27 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 7843b7e7..95a3aaf3 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "85c86ddc42f28381eaafe6aedeada6141e67bad2" +ESW_REV[2022.2] = "b7b67b9d992ef4ad51d6d28c03483bde15232565" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 06f7be2f7f9498261ca72301e99bee7155361e06 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 27 Apr 2022 14:40:32 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 90a35ded..39e1778b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15" KBRANCH="master" -SRCREV = "0b70857ca66da7d471f5c17d1af67a2af273a960" +SRCREV = "e087c38733a5df77e474c8e1706785974c5bfbab" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 95a3aaf3..b72b2f75 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "b7b67b9d992ef4ad51d6d28c03483bde15232565" +ESW_REV[2022.2] = "66302640418b8cac1a689965226f23cde22f6e4e" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 4815eec01ff1d9d7cc4e159dc8e61dd5c501f9fe Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 28 Apr 2022 14:09:58 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 752218df..6aaf3c00 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "f1a3ac43e52d9e2a26f164c9b6e9d8ae9fd32a41" +SRCREV = "771e1b36ea91069cf48ca7bf763373b3444e7b31" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index b72b2f75..69529994 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "66302640418b8cac1a689965226f23cde22f6e4e" +ESW_REV[2022.2] = "927719d4a006c9766972aa94e02666e5e7badb07" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 90c9443255bb78058f5e27b5639fd3ed24987670 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 17 Feb 2022 08:48:58 -0800 Subject: linux-xlnx: Move default branch to latest LTS New default branch is xlnx_rebase_5.15_LTS. Update the SRCREV to the latest, based on 5.15.19. Signed-off-by: Mark Hatle (cherry picked from commit d511d31679d2c3c997aba3d736180f4026a7b907) Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 39e1778b..60301f18 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ -LINUX_VERSION = "5.15" -KBRANCH="master" -SRCREV = "e087c38733a5df77e474c8e1706785974c5bfbab" +LINUX_VERSION = "5.15.19" +KBRANCH="xlnx_rebase_v5.15_LTS" +SRCREV = "b0c1be301e78c320df8c4d93b18393bfd7fd4e9d" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 9097f6a96da97bad6a688d0bee40f03423b21d7b Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Tue, 26 Apr 2022 20:22:20 -0700 Subject: lopper: updated srcrev for 2022.2 Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index c5232218..d032f45e 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "5c3074bc460fa13c679bf41159e23a854fdf9b89" +SRCREV = "01ae24278dd819d296015c58eb669d6e5ae41a17" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From e75c70e4db78afa8f5c5ec1790359ede5e8bf00e Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Wed, 27 Apr 2022 16:50:18 +0530 Subject: fpga-manager-script: adding this recipe to meta-xilinx This fpgautil recipe was part of meta-xilinx-tools. This is required in decoupling flow as well till dfx mgr gets stabled and meta-xilinx-tools layer will no be there in decoupling flow. So moving this recipe to meta-xilinx. Signed-off-by: Varalaxmi Bingi Signed-off-by: Mark Hatle --- .../fpga-manager-script/files/fpgautil.c | 464 +++++++++++++++++++++ .../fpga-manager-script/fpga-manager-script_1.0.bb | 23 + 2 files changed, 487 insertions(+) create mode 100644 meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c create mode 100644 meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c new file mode 100644 index 00000000..0b77569d --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c @@ -0,0 +1,464 @@ +/****************************************************************************** + * + * Copyright (C) 2019-2020 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do + * so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * @file: fpgautil.c + * Simple command line tool to load fpga via overlay or through sysfs interface + * and read fpga configuration using Xilinx Zynq/ZynqMP fpga manager + * Author: Appana Durga Kedareswara Rao + * Author: Nava kishore Manne + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define OVERLAY 1 +#define FPGA_SYSFS 2 +#define READBACK 3 +#define ENCRYPTION_USERKEY_EN (0x20U) + +int fpga_getplatform() +{ + char fpstr[100]; + FILE *fptr; + char *zynqmpstr = "Xilinx ZynqMP FPGA Manager"; + + if ((fptr = fopen("/sys/class/fpga_manager/fpga0/name", "r")) == NULL) + { + printf("Error! opening file"); + // Program exits if file pointer returns NULL. + exit(1); + } + + // reads text until newline + fscanf(fptr,"%[^\n]", fpstr); + fclose(fptr); + + if (!strcmp(zynqmpstr, fpstr)) + return 1; + else + return 0; + +} + +void print_usage(char *prg) +{ + int iszynqmp = fpga_getplatform(); + + fprintf(stderr, "\n%s: FPGA Utility for Loading/reading PL Configuration\n\n", prg); + fprintf(stderr, "Usage: %s -b -o \n\r", prg); + fprintf(stderr, "\n"); + fprintf(stderr, "Options: -b (Bin file path)\n"); + fprintf(stderr, " -o (DTBO file path)\n"); + fprintf(stderr, " -f Optional: \n"); + fprintf(stderr, " f := \n"); + fprintf(stderr, " -n FPGA Regions represent FPGA's\n"); + fprintf(stderr, " and partial reconfiguration\n"); + fprintf(stderr, " regions of FPGA's in the\n"); + fprintf(stderr, " Device Tree\n"); + if (iszynqmp) + { + fprintf(stderr, " Default: \n"); + fprintf(stderr, " -s Optional: \n"); + fprintf(stderr, " s := \n"); + fprintf(stderr, " -k Optional: \n"); + fprintf(stderr, " -r Optional: \n"); + fprintf(stderr, " Default: By default Read back contents will be stored in readback.bin file\n"); + fprintf(stderr, " -t Optional: \n"); + fprintf(stderr, " 0 - Configuration Register readback\n"); + fprintf(stderr, " 1 - Configuration Data Frames readback\n"); + fprintf(stderr, " Default: 0 (Configuration register readback)\n"); + fprintf(stderr, " -R Optional: Remove overlay from a live tree\n"); + } + + fprintf(stderr, " \n"); + fprintf(stderr, "Examples:\n"); + fprintf(stderr, "(Load Full bitstream using Overlay)\n"); + fprintf(stderr, "%s -b top.bit.bin -o can.dtbo -f Full -n Full \n", prg); + fprintf(stderr, "(Load Partial bitstream using Overlay)\n"); + fprintf(stderr, "%s -b rm0.bit.bin -o rm0.dtbo -f Partial -n PR0\n", prg); + fprintf(stderr, "(Load Full bitstream using sysfs interface)\n"); + fprintf(stderr, "%s -b top.bit.bin -f Full\n", prg); + fprintf(stderr, "(Load Partial bitstream using sysfs interface)\n"); + fprintf(stderr, "%s -b rm0.bit.bin -f Partial\n", prg); + if (iszynqmp) + { + fprintf(stderr, "(Load Authenticated bitstream through the sysfs interface)\n"); + fprintf(stderr, "%s -b top.bit.bin -f Full -s AuthDDR \n", prg); + fprintf(stderr, "(Load Parital Encrypted Userkey bitstream using Overlay)\n"); + fprintf(stderr, "%s -b top.bit.bin -o pl.dtbo -f Partial -s EnUsrKey -k <32byte key value>\n", prg); + fprintf(stderr, "(Read PL Configuration Registers)\n"); + fprintf(stderr, "%s -b top.bit.bin -r\n", prg); + } + fprintf(stderr, " \n"); +} + +int gettime(struct timeval t0, struct timeval t1) +{ + return ((t1.tv_sec - t0.tv_sec) * 1000.0f + (t1.tv_usec -t0.tv_usec) / 1000.0f); +} + +int fpga_state() +{ + FILE *fptr; + char buf[10]; + char *state_operating = "operating"; + char *state_unknown = "unknown"; + + system("cat /sys/class/fpga_manager/fpga0/state >> state.txt"); + fptr = fopen("state.txt", "r"); + if (fptr) { + fgets(buf, 10, fptr); + fclose(fptr); + system("rm state.txt"); + if ((strncmp(buf, state_operating, 9) == 0) || (strncmp(buf, state_unknown, 7) == 0)) + return 0; + else + return 1; + } + + return 1; +} + +static int fpga_overlay_check(char *cmd, char *state) +{ + char buf[512]; + FILE *fptr; + int len; + + system(cmd); + len = strlen(state) + 1; + fptr = fopen("state.txt", "r"); + if (fptr) { + fgets(buf, len, fptr); + fclose(fptr); + system("rm state.txt"); + if (!strcmp(buf, state)) + return 0; + else + return 1; + } + + return 1; +} + +struct fpgaflag { + char *flag; + unsigned int value; +}; + +static struct fpgaflag flagdump[] = { + {.flag = "Full", .value = 0x0}, + {.flag = "Partial", .value = 0x1}, + {.flag = "AuthDDR", .value = 0x40}, + {.flag = "AuthOCM", .value = 0x80}, + {.flag = "EnUsrKey", .value = 0x20}, + {.flag = "EnDevKey", .value = 0x4}, + {.flag = "AuthEnUsrKeyDDR", .value = 0x60}, + {.flag = "AuthEnUsrKeyOCM", .value = 0xA0}, + {.flag = "AuthEnDevKeyDDR", .value = 0x44}, + {.flag = "AuthEnDevKeyOCM", .value = 0x84}, + {} +}; + +static int cmd_flags(int argc, const char *name) +{ + int valid_flag = 0; + int flag = 0; + struct fpgaflag *p = flagdump; + + while (p->flag) { + if (!strcmp(name, p->flag)) { + flag = p->value; + break; + } + p++; + } + + return flag; +} + +static int isvalid_flags(int argc, const char *name, bool is_secure) +{ + int valid_flag = 0; + int count = 0; + struct fpgaflag *p; + + if (!is_secure) + p = flagdump; + else + p = &flagdump[2]; + + while (p->flag) { + if (!strcmp(name, p->flag)) + return 0; + else if ((!is_secure) && (++count == 2)) + return 1; + p++; + } + + return 1; +} + +int main(int argc, char **argv) +{ + int ret; + int iszynqmp = fpga_getplatform(); + char *binfile = NULL, *overlay = NULL, *AesKey = NULL, *flag = NULL, *partial_overlay = NULL; + char *region = NULL, *Module[100] = {0}; + int opt, flags = 0, flow = 0,rm_overlay = 0, readback_type = 0, sflags = 0; + char command[2048], folder[512], *token, *tmp, *tmp1, *tmp2 , *tmp3; + const char *filename = "readback", *name; + struct stat sb; + double time; + struct timeval t1, t0; + + if (argc == 1) { + print_usage(basename(argv[0])); + return 1; + } + + while ((opt = getopt(argc, argv, "o:b:n:f:s:p:k:rt::Rh?:")) != -1) { + switch (opt) { + case 'o': + overlay = optarg; + flow = OVERLAY; + break; + case 'b': + binfile = optarg; + if (!(flow == OVERLAY)) + flow = FPGA_SYSFS; + break; + case 'n': + region = optarg; + break; + case 'f': + if (flow == OVERLAY) { + name = argv[6]; + flags = cmd_flags(argc, name); + } else if (flow == FPGA_SYSFS) { + name = argv[4]; + flags = cmd_flags(argc, name); + } + + ret = isvalid_flags(argc, name, false); + if (ret) { + printf("Error: Invalid arugments :%s\n", strerror(1)); + print_usage(basename(argv[0])); + return -EINVAL; + } + + flags += sflags; + break; + case 's': + if (flow == OVERLAY) { + name = argv[8]; + sflags = cmd_flags(argc, name); + } else if (flow == FPGA_SYSFS) { + name = argv[6]; + sflags = cmd_flags(argc, name); + } + + ret = isvalid_flags(argc, name, true); + if (ret) { + printf("Error: Invalid arugments :%s\n", strerror(1)); + print_usage(basename(argv[0])); + return -EINVAL; + } + + flags += sflags; + break; + case 'p': + partial_overlay = optarg; + break; + case 'k': + AesKey = optarg; + break; + case 't': + if (optarg == NULL && argv[4] != NULL) + readback_type = atoi(argv[4]); + break; + case 'r': + if (optarg == NULL && argv[2] != NULL) + filename = argv[2]; + flow = READBACK; + break; + case 'R': + rm_overlay = 1; + break; + case '?': + case 'h': + default: + print_usage(basename(argv[0])); + return 1; + break; + } + } + + if(region != NULL) + snprintf(folder, sizeof(folder), "/configfs/device-tree/overlays/%s", region); + else if (!(flags & 1)) + snprintf(folder, sizeof(folder), "/configfs/device-tree/overlays/full"); + else if (overlay != NULL) { + printf("Error: Provide valid Overlay region info\n\r"); + return 1; + } + system("mkdir -p /lib/firmware"); + if (rm_overlay) { + if (((stat(folder, &sb) == 0) && S_ISDIR(sb.st_mode))) { + snprintf(command, sizeof(command), "rmdir %s", folder); + system(command); + } + return 0; + } + + if (flow == OVERLAY) { + if (((stat(folder, &sb) == 0) && S_ISDIR(sb.st_mode))) { + printf("Error: Overlay already exists in the live tree\n\r"); + return 1; + } + + if (((stat("/configfs/device-tree/", &sb) == 0) && S_ISDIR(sb.st_mode))) { + } else { + system("mkdir /configfs"); + system("mount -t configfs configfs /configfs"); + } + + if (binfile != NULL) { + snprintf(command, sizeof(command), "cp %s /lib/firmware", binfile); + system(command); + } + + snprintf(command, sizeof(command), "cp %s /lib/firmware", overlay); + system(command); + tmp = strdup(overlay); + while((token = strsep(&tmp, "/"))) { + tmp1 = token; + } + + if (binfile != NULL) { + snprintf(command, sizeof(command), "echo %x > /sys/class/fpga_manager/fpga0/flags", flags); + system(command); + if (ENCRYPTION_USERKEY_EN & flags) { + snprintf(command, sizeof(command), "echo %s > /sys/class/fpga_manager/fpga0/key", AesKey); + system(command); + } + } + + snprintf(command, sizeof(command), "mkdir %s", folder); + system(command); + snprintf(command, sizeof(command), "echo -n %s > %s/path", tmp1, folder); + gettimeofday(&t0, NULL); + system(command); + gettimeofday(&t1, NULL); + time = gettime(t0, t1); + + snprintf(command, sizeof(command), "cat %s/path >> state.txt", folder); + ret = fpga_overlay_check(command, tmp1); + if (ret) { + printf("Failed to apply Overlay\n\r"); + } + + /* Delete Bin file and DTBO file*/ + snprintf(command, sizeof(command), "rm /lib/firmware/%s", tmp1); + system(command); + if (binfile != NULL) { + tmp = strdup(binfile); + while((token = strsep(&tmp, "/"))) { + tmp1 = token; + } + snprintf(command, sizeof(command), "rm /lib/firmware/%s", tmp1); + system(command); + } + + /* FPGA state check */ + if (binfile != NULL) { + if (!fpga_state()) { + printf("Time taken to load BIN is %f Milli Seconds\n\r", time); + printf("BIN FILE loaded through FPGA manager successfully\n\r"); + } else { + printf("BIN FILE loading through FPGA manager failed\n\r"); + } + } + } else if (flow == FPGA_SYSFS) { + if (argc < 3) { + printf("%s: For more information run %s -h\n", strerror(22), basename(argv[0])); + return 1; + } + snprintf(command, sizeof(command), "cp %s /lib/firmware", binfile); + system(command); + snprintf(command, sizeof(command), "echo %x > /sys/class/fpga_manager/fpga0/flags", flags); + system(command); + if (ENCRYPTION_USERKEY_EN & flags) { + snprintf(command, sizeof(command), "echo %s > /sys/class/fpga_manager/fpga0/key", AesKey); + system(command); + } + tmp = strdup(binfile); + while((token = strsep(&tmp, "/"))) { + tmp1 = token; + } + snprintf(command, sizeof(command), "echo %s > /sys/class/fpga_manager/fpga0/firmware", tmp1); + gettimeofday(&t0, NULL); + system(command); + gettimeofday(&t1, NULL); + time = gettime(t0, t1); + + /* Delete Bin file and DTBO file*/ + snprintf(command, sizeof(command), "rm /lib/firmware/%s", tmp1); + system(command); + + /* FPGA state check */ + if (!fpga_state()) { + printf("Time taken to load BIN is %f Milli Seconds\n\r", time); + printf("BIN FILE loaded through FPGA manager successfully\n\r"); + } else { + printf("BIN FILE loading through FPGA manager failed\n\r"); + } + } else if (flow == READBACK) { + if (readback_type > 1) { + printf("Invalid arugments :%s\n", strerror(1)); + printf("For more information run %s -h\n", basename(argv[0])); + return -EINVAL; + } + snprintf(command, sizeof(command), "echo %x > /sys/module/zynqmp_fpga/parameters/readback_type", readback_type); + system(command); + snprintf(command, sizeof(command), "cat /sys/kernel/debug/fpga/fpga0/image >> %s.bin", filename); + system(command); + printf("Readback contents are stored in the file %s.bin\n\r", filename); + } + + return 0; +} diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb new file mode 100644 index 00000000..416edf17 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb @@ -0,0 +1,23 @@ +SUMMARY = "Install user script to support fpga-manager" +DESCRIPTION = "Install user script that loads and unloads overlays using kernel fpga-manager" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://${WORKDIR}/fpgautil.c;beginline=1;endline=24;md5=8010e59a286b1e3a73a9fdd93bd18778" + +SRC_URI = "\ + file://fpgautil.c \ + " +S = "${WORKDIR}" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +do_compile() { + ${CC} ${LDFLAGS} fpgautil.c -o fpgautil +} + +do_install() { + install -Dm 0755 ${S}/fpgautil ${D}${bindir}/fpgautil +} + +FILES:${PN} = "\ + ${bindir}/fpgautil \ + " -- cgit v1.2.3-54-g00ecf From 10c209172ae6ff91293ac1aeee706e9eb5c52e48 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Wed, 27 Apr 2022 17:33:55 +0530 Subject: dt-processor.sh: adding pdi_path argument (-i) Expecting the pdi also in the system device tree path. This patch will add teh PDI_PATH variable in versal case. if pdi not present in sdt path it will throw warning. if more then one pdi is present, throw a warning. Signed-off-by: Varalaxmi Bingi Also fix -p and -h usage. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 2dc48b75..36a81cc7 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -40,6 +40,7 @@ $0 [-e ] Apply a partial overlay [-m ] zynqmp or versal [-p ] Path to psu_init files, defaults to system_dtb path + [-i ] Path to the pdi file [-l ] write local.conf changes to this file [-P ] Path to petalinux schema file @@ -50,7 +51,7 @@ EOF parse_args() { [ $# -eq 0 ] && usage - while getopts ":c:s:d:o:e:m:l:h:P:" opt; do + while getopts ":c:s:d:o:e:m:l:hP:p:i:" opt; do case ${opt} in c) config_dir=$OPTARG ;; s) system_dtb=$OPTARG ;; @@ -59,11 +60,12 @@ parse_args() { e) external_fpga=$OPTARG ;; m) machine=$OPTARG ;; p) psu_init_path=$OPTARG ;; + i) pdi_path=$OPTARG ;; l) localconf=$OPTARG ;; P) petalinux_schema=$OPTARG ;; h) usage ;; :) error "Missing argument for -$OPTARG" ;; - \?) error "Invalid option -$OPTARG" + \?) error "Invalid option -$OPTARG" ;; esac done @@ -72,6 +74,9 @@ parse_args() { if [ -z "$psu_init_path" ]; then psu_init_path=$(dirname ${system_dtb}) fi + if [ -z "$pdi_path" ]; then + pdi_path=$(dirname ${system_dtb}) + fi } detect_machine() { @@ -297,6 +302,15 @@ EOF cortex_a72_linux() { info "cortex-a72 for Linux [ $1 ]" + # Find the first file ending in .pdi + full_pdi_path=$(ls ${pdi_path}/*.pdi 2>/dev/null | head -n 1) + if [ -z "${full_pdi_path}" ]; then + warn "Warning: Unable to find a pdi file in ${pdi_path}" + full_pdi_path="__PATH TO PDI FILE HERE__" + elif [ "${full_pdi_path}" != "$(ls ${pdi_path}/*.pdi 2>/dev/null)" ]; then + warn "Warning: multiple PDI files found, using first found $(basename ${full_pdi_path})." + fi + if [ "$1" = "None" ]; then dtb_file="cortexa72-${machine}-linux.dtb" system_conf=conf/cortexa72-${machine}-linux.conf @@ -922,7 +936,7 @@ gen_local_conf() { echo "PSM_MCDEPENDS = \"${psm_mcdepends}\"" >> $1 echo "PSM_FIRMWARE_DEPLOY_DIR = \"${psm_firmware_deploy_dir}\"" >> $1 fi - [ "${machine}" = "versal" ] && echo "PDI_PATH = \"__PATH TO PDI FILE HERE__\"" >> $1 + [ "${machine}" = "versal" ] && echo "PDI_PATH = \"${full_pdi_path}\"" >> $1 echo } -- cgit v1.2.3-54-g00ecf From cf110f452c45c9b486825cf9e8026afdb564727a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 29 Apr 2022 18:54:20 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 0c606100..a2360532 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "0499324af1178057c3730b0989c8fb5c5bbc4cf8" +SRCREV ?= "9b6baf6ddc986d635f63c3499d80e658f3b5f410" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 9d5bb210..8210c470 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "9105d22e6deaac62426152052631e69e1c024f00" +SRCREV = "2e67d56098aea93908e815f2fd612264446b8222" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 60301f18..95f273ca 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.19" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "b0c1be301e78c320df8c4d93b18393bfd7fd4e9d" +SRCREV = "f48fd056666c4c274cf30928f71eaa6c3f302a6b" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 69529994..d14406f7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "927719d4a006c9766972aa94e02666e5e7badb07" +ESW_REV[2022.2] = "a2dc7522febc5f24b4c441baf09b289327733234" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From dde09265939487b4814a0f944961bac9393e74e3 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 2 May 2022 15:11:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 8210c470..ef309c15 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "2e67d56098aea93908e815f2fd612264446b8222" +SRCREV = "1e6427f56d78ddcaf8dc00beaedc6d9ded9e265d" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 95f273ca..10565a9f 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.19" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "f48fd056666c4c274cf30928f71eaa6c3f302a6b" +SRCREV = "3029941a1c223de78d0d728286a1ea915f2ffaa3" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d14406f7..3654a8cc 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a2dc7522febc5f24b4c441baf09b289327733234" +ESW_REV[2022.2] = "571dfcd7e9b82cebeac79eac5157660f6c1372bf" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 00058c1442a59632e89ec7aace110bb09747387c Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 28 Apr 2022 20:50:49 -0600 Subject: recipes-kernel: Add udev rules files for linux-xlnx in-tree drivers This recipe is to add generic udev rules files for linux-xlnx in-tree drivers. - Create a new aie group. - Add udev rules for aie devices and change permissions and ownership group to "aie" so that any new user added to aie groups can access aie devices(/dev/aie0) from linux userspace. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../linux-xlnx-udev-rules/linux-xlnx-udev-rules.bb | 37 ++++++++++++++++++++++ .../linux-xlnx-udev-rules/99-aie-device.rules | 2 ++ 2 files changed, 39 insertions(+) create mode 100644 meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules.bb create mode 100644 meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules/99-aie-device.rules diff --git a/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules.bb b/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules.bb new file mode 100644 index 00000000..f5b0ff95 --- /dev/null +++ b/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules.bb @@ -0,0 +1,37 @@ +SUMMARY = "Udev rules files for Linux drivers" +DESCRIPTION = "Generic udev rules recipe for Xilinx Linux in tree drivers" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +SRC_URI = "\ + file://99-aie-device.rules \ +" + +S = "${WORKDIR}" + +inherit useradd + +COMPATIBLE_MACHINE ?= "^$" +COMPATIBLE_MACHINE:zynq = ".*" +COMPATIBLE_MACHINE:zynqmp = ".*" +COMPATIBLE_MACHINE:microblaze = ".*" +COMPATIBLE_MACHINE:versal = ".*" + +do_configure[noexec] = '1' +do_compile[noexec] = '1' + +do_install () { + install -d ${D}${sysconfdir}/udev/rules.d + for rule in $(find ${WORKDIR} -maxdepth 1 -type f -name "*.rules"); do + if ${@bb.utils.contains_any('SOC_VARIANT', ['ai-core', 'ai-edge'], 'true', 'false' ,d)}; then + install -m 0644 ${WORKDIR}/99-aie-device.rules ${D}${sysconfdir}/udev/rules.d/ + fi + install -m 0644 $rule ${D}${sysconfdir}/udev/rules.d/ + done +} + +USERADD_PACKAGES = "${PN}" +GROUPADD_PARAM:${PN} += "${@bb.utils.contains_any('SOC_VARIANT', ['ai-core', 'ai-edge'], '-r aie;', '', d)}" + +FILES:${PN} += "${sysconfdir}/udev/rules.d/*" + diff --git a/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules/99-aie-device.rules b/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules/99-aie-device.rules new file mode 100644 index 00000000..fffcf6e6 --- /dev/null +++ b/meta-xilinx-core/recipes-kernel/linux-xlnx-udev-rules/linux-xlnx-udev-rules/99-aie-device.rules @@ -0,0 +1,2 @@ +# Device rules for AIE drivers. +ACTION=="add", SUBSYSTEM=="aie", KERNEL=="aie[0-9]*", MODE="0660", GROUP="aie" -- cgit v1.2.3-54-g00ecf From 69add411db616dd0f3be54a6faa1749674bc6e47 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 29 Apr 2022 12:38:54 +0530 Subject: meta-xilinx-standalone-experimental: recipes-bsp: embeddedsw: fsbl-firmware: Copy psu_init file before do_configure task With recent changes in fsbl application, fsbl CMakeList is expecting psu_init.h file to be avaible before do_configure stage, This commit updates the recipe for the same. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend index 330f0ead..43dcc106 100644 --- a/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend +++ b/meta-xilinx-standalone-experimental/recipes-bsp/embeddedsw/fsbl-firmware_git.bbappend @@ -37,7 +37,7 @@ python() { d.prependVar('FILESEXTRAPATHS', '%s:' % psu_init_path) } -do_compile:prepend() { +do_configure:prepend() { if [ -e ${WORKDIR}/psu_init.c ]; then install -m 0644 ${WORKDIR}/psu_init.c ${S}/${ESW_COMPONENT_SRC} else -- cgit v1.2.3-54-g00ecf From be295f47f2cfab397861416f50e96eda612ce77b Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 29 Apr 2022 12:39:06 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index d88d379e..402c34a0 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "cf261e654ec41c0b91362c83d2d58bc38a942708" +ESW_REV[experimental] = "011e260bdc69a93d2120c5007984ba36c49c7ee5" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = '1d552a9ac3973bf5fcff6fb9cb2034ea' -- cgit v1.2.3-54-g00ecf From 98ea8ecc4cea58161b0994c7519195996c41caba Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 2 May 2022 19:28:54 +0530 Subject: lopper: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index d032f45e..8d15542f 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "01ae24278dd819d296015c58eb669d6e5ae41a17" +SRCREV = "cd25873ec00a414f1e93f2eb3cebf0fe0b41d1e9" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From ea12b72b50072cf43ce0aa142100d2a3166f21e7 Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Fri, 29 Apr 2022 14:49:20 +0530 Subject: u-boot-xlnx_%.bbappend: reorganizing u-boot recipe code This patch will move the u-boot code from meta-xilinx-tools to meta-xilinx. Not all flows use the meta-xilinx-tools layer. Signed-off-by: Varalaxmi Bingi Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-xlnx.inc | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index d9113cc7..d152c15c 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -18,3 +18,43 @@ B = "${WORKDIR}/build" FILESEXTRAPATHS:prepend := "${THISDIR}/u-boot:" SYSROOT_DIRS += "/boot" + +BASE_DTS ?= "${@os.path.basename(d.getVar('CONFIG_DTFILE') or "system-top")}" +DTB_PATH ?= "/boot/devicetree/" +DTB_NAME ?= "" + +EXTRA_OEMAKE += "${@'EXT_DTB=${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME}' if (d.getVar('DTB_NAME') != '') else '' }" + +python __anonymous () { + #check if there are any dtb providers + providerdtb = d.getVar("PREFERRED_PROVIDER_virtual/dtb") + if providerdtb: + d.appendVarFlag('do_configure', 'depends', ' virtual/dtb:do_populate_sysroot') + if d.getVar("DTB_NAME") is not None: + d.setVar('DTB_NAME', d.getVar('BASE_DTS')+ '.dtb') + + if d.getVar('UBOOT_IMAGE_BLOB') == "1": + d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') +} + +UBOOTELF_NODTB_IMAGE ?= "u-boot-nodtb.elf" +UBOOTELF_NODTB_BINARY ?= "u-boot" +do_deploy:prepend() { + cd ${B} + + if [ -f "${UBOOTELF_NODTB_BINARY}" ]; then + install ${UBOOTELF_NODTB_BINARY} ${DEPLOYDIR}/${UBOOTELF_NODTB_IMAGE} + fi + + #following lines are from uboot-sign.bbclass, vars are defined there + if [ -e "${UBOOT_DTB_BINARY}" ]; then + install ${UBOOT_DTB_BINARY} ${DEPLOYDIR}/${UBOOT_DTB_IMAGE} + ln -sf ${UBOOT_DTB_IMAGE} ${DEPLOYDIR}/${UBOOT_DTB_BINARY} + ln -sf ${UBOOT_DTB_IMAGE} ${DEPLOYDIR}/${UBOOT_DTB_SYMLINK} + fi + if [ -f "${UBOOT_NODTB_BINARY}" ]; then + install ${UBOOT_NODTB_BINARY} ${DEPLOYDIR}/${UBOOT_NODTB_IMAGE} + ln -sf ${UBOOT_NODTB_IMAGE} ${DEPLOYDIR}/${UBOOT_NODTB_SYMLINK} + ln -sf ${UBOOT_NODTB_IMAGE} ${DEPLOYDIR}/${UBOOT_NODTB_BINARY} + fi +} -- cgit v1.2.3-54-g00ecf From f8d5a51bbb029dfe5a9f8217f4c93fdec0607616 Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Tue, 3 May 2022 05:27:37 +0530 Subject: meta-xilinx-bsp:device-tree: provencore memory reservation Provencore Linux driver and testapp is enabled through MACHINE_FEATURES. When provencore is enabled, reserve memory required for provencore through device tree. This patch adds pnc.dtsi to system-top.dts file when provencore is enabled. pnc.dtsi contains the memory address and memory size that needs to be reserved. Signed-off-by: Akshay Belsare Signed-off-by: Mark Hatle --- .../recipes-bsp/device-tree/device-tree.bbappend | 6 ++++++ meta-xilinx-bsp/recipes-bsp/device-tree/files/pnc.dtsi | 13 +++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/pnc.dtsi diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend index df31778c..94020f25 100644 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend @@ -20,4 +20,10 @@ SRC_URI:append:kc705-microblazeel = " \ file://pl.dtsi \ file://system-conf.dtsi \ " +SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' file://pnc.dtsi', '', d)}" +do_configure:append() { + if [ ${@bb.utils.contains('MACHINE_FEATURES', 'provencore', 'true', '', d)} ]; then + echo '#include "pnc.dtsi"' >> ${DT_FILES_PATH}/system-top.dts + fi +} diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/pnc.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/pnc.dtsi new file mode 100644 index 00000000..760b76be --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/device-tree/files/pnc.dtsi @@ -0,0 +1,13 @@ +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pnc-reserved-memory@70000000{ + compatible = "pnc,secure-memory"; + reg = <0x0 0x70000000 0x0 0x0FF00000>; + no-map; + }; + }; +}; -- cgit v1.2.3-54-g00ecf From 48a70b151434c00f2518eb079833b8f8d8ff6ec3 Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Tue, 3 May 2022 05:27:38 +0530 Subject: meta-xilinx-bsp:uboot-device-tree: provencore memory reservation Provencore Linux driver and testapp is enabled through MACHINE_FEATURES. When provencore is enabled, reserve memory required for provencore through uboot device tree. This patch adds pnc.dtsi to system-top.dts file when provencore is enabled. pnc.dtsi contains the memory address and memory size that needs to be reserved. Signed-off-by: Akshay Belsare Signed-off-by: Mark Hatle --- .../recipes-bsp/uboot-device-tree/files/pnc.dtsi | 13 +++++++++++++ .../uboot-device-tree/uboot-device-tree.bbappend | 9 +++++++++ 2 files changed, 22 insertions(+) create mode 100644 meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi create mode 100644 meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend diff --git a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi new file mode 100644 index 00000000..760b76be --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi @@ -0,0 +1,13 @@ +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pnc-reserved-memory@70000000{ + compatible = "pnc,secure-memory"; + reg = <0x0 0x70000000 0x0 0x0FF00000>; + no-map; + }; + }; +}; diff --git a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend new file mode 100644 index 00000000..f01276b2 --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' file://pnc.dtsi', '', d)}" + +do_configure:append() { + if [ ${@bb.utils.contains('MACHINE_FEATURES', 'provencore', 'true', '', d)} ]; then + echo '#include "pnc.dtsi"' >> ${DT_FILES_PATH}/system-top.dts + fi +} -- cgit v1.2.3-54-g00ecf From 7eb72cd3a4ff9a741e276c4c3fc98040a3157925 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 4 May 2022 18:31:32 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 402c34a0..8852d4ab 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "011e260bdc69a93d2120c5007984ba36c49c7ee5" +ESW_REV[experimental] = "0c2abe78368b83e7ef122668ee7ad44a02184b25" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' -LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = '1d552a9ac3973bf5fcff6fb9cb2034ea' +LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 1cc380dc462634c9fadadd7984e2f51d5d91a525 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 4 May 2022 18:31:33 +0530 Subject: meta-xilinx-standalone-experimental: recipes-drivers: sysmonpsv: Update depends as per latest driver source Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-drivers/sysmonpsv_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/sysmonpsv_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/sysmonpsv_git.bb index 92c634a4..06b82811 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/sysmonpsv_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/sysmonpsv_git.bb @@ -4,7 +4,7 @@ REQUIRED_DISTRO_FEATURES = "sysmonpsv" inherit esw python3native -DEPENDS += "xilstandalone " +DEPENDS += "xilstandalone ${@'scugic' if d.getVar('ESW_MACHINE') != 'microblaze-plm' and d.getVar('ESW_MACHINE') != 'microblaze-psm' else ''}" ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/sysmonpsv/src/" ESW_COMPONENT_NAME = "libsysmonpsv.a" -- cgit v1.2.3-54-g00ecf From 3ad41276689ff826feebbe60623549188ae38cb9 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 6 May 2022 12:17:32 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 6aaf3c00..30c3bcd6 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "771e1b36ea91069cf48ca7bf763373b3444e7b31" +SRCREV = "a40ff93a4d77f90815d15be2bfbce525f66eb9ac" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 10565a9f..c317373d 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.19" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "3029941a1c223de78d0d728286a1ea915f2ffaa3" +SRCREV = "3076249fc30bf463f8390f89009de928ad3e95ff" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3654a8cc..38a0f8af 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "571dfcd7e9b82cebeac79eac5157660f6c1372bf" +ESW_REV[2022.2] = "67e974bea9c9d7de6988cdd43fae5d941dcca075" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From e12ce1728ffe51a420ab034b172c606258d3d8a8 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 7 May 2022 12:17:26 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index a2360532..b4f14f94 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "9b6baf6ddc986d635f63c3499d80e658f3b5f410" +SRCREV ?= "08ec8ac394f36932c9c349430a8ffe5ae08b7803" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index ef309c15..8433fc04 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "1e6427f56d78ddcaf8dc00beaedc6d9ded9e265d" +SRCREV = "8f4f82ff21242926b6acc597a06d27d55d6779de" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -- cgit v1.2.3-54-g00ecf From e5552fa6b9879d43673decc49628375da12f13cb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 9 May 2022 14:47:57 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c317373d..3f22e4da 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.19" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "3076249fc30bf463f8390f89009de928ad3e95ff" +SRCREV = "63ddb06d5da5f9804b96213b697283dee17f42dd" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 38a0f8af..8e80e5dc 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "67e974bea9c9d7de6988cdd43fae5d941dcca075" +ESW_REV[2022.2] = "87a3baed1f6ccdf31a9c182691c964b2de09e615" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From d65e337809b34d4aac26b698a99620128a8ab094 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 10 May 2022 13:19:46 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 8e80e5dc..57df688a 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "87a3baed1f6ccdf31a9c182691c964b2de09e615" +ESW_REV[2022.2] = "524b5ea09359cb000d332873d609654704be4a8c" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From c933f83a698d0cac9ce0c9a712b6cbbac227893f Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 5 May 2022 18:50:43 -0600 Subject: meta-xilinx: Clean up vendor specific machine configuration files 1. Add new metal-xilinx-vendor layer which supports vendor specific machine configuration files, device-tree, kernel, platform-init etc. 2. Moved below vendor machine conf files, dt and related configs from meta-xilinx-bsp and meta-xilinx-contrib to meta-xilinx-vendor layer. - microzed-zynq7.conf - minized-zynq7.conf - picozed-zynq7.conf - zedboard-zynq7.conf - zybo-zynq7.conf - zybo-linux-bd-zynq7.conf - ultra96-zynqmp.conf 3. Obsolete qemu-zynq7, s3adsp1800-qemu-microblazeeb, v350-versal and vc-p-a2197-00-versal from meta-xilinx-bsp layer. Users should use zynq-generic.conf for zynq7000 qemu boot should be functionally equivalent to qemu-zynq7. 4. Add new MAINTAINERS.md file and move maintainers, Mailing list and Patches content from meta-xilinx-* README.md to MAINTAINERS.md file. 5. Updated README.md file for supported board machines files in meta-xilinx-bsp, meta-xilinx-contrib and meta-xilinx-vendor layers. 6. Disabled old drm kernel patches for zybo-linux-bd-zynq mahcine in meta-xilinx-contrib layer as these patches doesn't apply on 5.x kernel, if we don't hear from patch submitter we will remove these patches from meta-xilinx-contrib layer. 7. Removed drm kernel cache metadate for zybo-linux-bd-zynq7 machine as these configs are already available in xilinx_zynq_defconfig. 8. Fixed build issue for u-boot by changing PREFERRED_PROVIDER_virtual/bootloader from u-boot to u-boot-xlnx. 9. Add meta-xilinx-vendor to bblayers.conf.sample Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- MAINTAINERS.md | 34 + meta-microblaze/README.md | 25 +- meta-xilinx-bsp/README.md | 102 +- .../conf/machine/include/board/ultra96.inc | 12 - meta-xilinx-bsp/conf/machine/microzed-zynq7.conf | 26 - .../conf/machine/ml605-qemu-microblazeel.conf | 20 - meta-xilinx-bsp/conf/machine/picozed-zynq7.conf | 28 - meta-xilinx-bsp/conf/machine/qemu-zynq7.conf | 9 - .../conf/machine/s3adsp1800-qemu-microblazeeb.conf | 21 - meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf | 23 - meta-xilinx-bsp/conf/machine/v350-versal.conf | 19 - .../conf/machine/vc-p-a2197-00-versal.conf | 10 - meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf | 24 - .../conf/machine/zybo-linux-bd-zynq7.conf | 27 - meta-xilinx-bsp/conf/machine/zybo-zynq7.conf | 29 - .../recipes-bsp/device-tree/device-tree.bbappend | 5 - .../recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 3 - .../recipes-bsp/device-tree/device-tree.bbappend | 10 - .../device-tree/files/picozed-zynq7.dts | 98 - .../device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi | 63 - .../device-tree/files/zybo-linux-bd-zynq7/pl.dtsi | 215 - .../zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts | 184 - .../platform-init/platform-init.bbappend | 4 - .../platform-init/picozed-zynq7/ps7_init_gpl.c | 13191 ------------------- .../platform-init/picozed-zynq7/ps7_init_gpl.h | 130 - meta-xilinx-contrib/README.md | 42 +- .../conf/machine/minized-zynq7.conf | 27 - .../conf/machine/ml605-qemu-microblazeel.conf | 20 + .../linux/linux-xlnx_2022.2.bbappend | 13 +- meta-xilinx-core/README.md | 30 +- meta-xilinx-core/conf/bblayers.conf.sample | 1 + meta-xilinx-pynq/README.md | 27 +- meta-xilinx-standalone-experimental/README.md | 37 +- meta-xilinx-standalone/README.md | 39 +- meta-xilinx-vendor/COPYING.MIT | 17 + meta-xilinx-vendor/README.md | 37 + meta-xilinx-vendor/conf/layer.conf | 13 + .../conf/machine/include/board/ultra96.inc | 12 + .../conf/machine/microzed-zynq7.conf | 23 + meta-xilinx-vendor/conf/machine/minized-zynq7.conf | 24 + meta-xilinx-vendor/conf/machine/picozed-zynq7.conf | 25 + .../conf/machine/ultra96-zynqmp.conf | 23 + .../conf/machine/zedboard-zynq7.conf | 24 + .../conf/machine/zybo-linux-bd-zynq7.conf | 24 + meta-xilinx-vendor/conf/machine/zybo-zynq7.conf | 27 + .../recipes-bsp/device-tree/device-tree.bbappend | 7 + .../recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 3 + .../recipes-bsp/device-tree/device-tree.bbappend | 13 + .../device-tree/files/picozed-zynq7.dts | 98 + .../device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi | 63 + .../device-tree/files/zybo-linux-bd-zynq7/pl.dtsi | 215 + .../zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts | 184 + .../platform-init/platform-init.bbappend | 4 + .../platform-init/picozed-zynq7/ps7_init_gpl.c | 13191 +++++++++++++++++++ .../platform-init/picozed-zynq7/ps7_init_gpl.h | 130 + 55 files changed, 14318 insertions(+), 14387 deletions(-) create mode 100644 MAINTAINERS.md delete mode 100644 meta-xilinx-bsp/conf/machine/include/board/ultra96.inc delete mode 100644 meta-xilinx-bsp/conf/machine/microzed-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf delete mode 100644 meta-xilinx-bsp/conf/machine/picozed-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/qemu-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf delete mode 100644 meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf delete mode 100644 meta-xilinx-bsp/conf/machine/v350-versal.conf delete mode 100644 meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zybo-zynq7.conf delete mode 100644 meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h delete mode 100644 meta-xilinx-contrib/conf/machine/minized-zynq7.conf create mode 100644 meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf create mode 100644 meta-xilinx-vendor/COPYING.MIT create mode 100644 meta-xilinx-vendor/README.md create mode 100644 meta-xilinx-vendor/conf/layer.conf create mode 100644 meta-xilinx-vendor/conf/machine/include/board/ultra96.inc create mode 100644 meta-xilinx-vendor/conf/machine/microzed-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/minized-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/picozed-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf create mode 100644 meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/zybo-zynq7.conf create mode 100644 meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend create mode 100644 meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h diff --git a/MAINTAINERS.md b/MAINTAINERS.md new file mode 100644 index 00000000..d14b73e5 --- /dev/null +++ b/MAINTAINERS.md @@ -0,0 +1,34 @@ +# Maintainers, Mailing list, Patches + +Please send any patches, pull requests, comments or questions for this layer to +the [meta-xilinx mailing list](https://lists.yoctoproject.org/g/meta-xilinx): + + meta-xilinx@lists.yoctoproject.org + +When sending patches, please make sure the email subject line includes +"[meta-xilinx][PATCH]" and cc'ing the maintainers. + +For more details follow the OE community patch submission guidelines, as described in: + +https://www.openembedded.org/wiki/Commit_Patch_Message_Guidelines +https://www.openembedded.org/wiki/How_to_submit_a_patch_to_OpenEmbedded + +`git send-email --subject-prefix 'meta-xilinx][PATCH' --to meta-xilinx@yoctoproject.org` + +**Maintainers:** + + Mark Hatle + Sandeep Gundlupet Raju + John Toomey + +> **Note:** + +* meta-xilinx-contrib layer: + * We don't have any maintainers when user submit a patch to this layer + email meta-xilinx@yoctoproject.org and cc'ing below reviewers. + +**Reviewers:** + + Mark Hatle + Sandeep Gundlupet Raju + John Toomey diff --git a/meta-microblaze/README.md b/meta-microblaze/README.md index 9e7ea2c6..acf6c253 100644 --- a/meta-microblaze/README.md +++ b/meta-microblaze/README.md @@ -1,24 +1,8 @@ -meta-microblaze -=============== +# meta-microblaze This layer provides support specific to the MicroBlaze architecture - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -26,3 +10,8 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) + + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-bsp/README.md b/meta-xilinx-bsp/README.md index e4142861..f41f6d4a 100644 --- a/meta-xilinx-bsp/README.md +++ b/meta-xilinx-bsp/README.md @@ -1,56 +1,38 @@ -meta-xilinx -=========== +# meta-xilinx -This layer provides support for MicroBlaze, Zynq and ZynqMP. +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures Xilinx evaluation boards. -Additional documentation: +## Additional documentation: -* [Building](README.building.md) -* [Booting](README.booting.md) +* [Building](../README.building.md) +* [Booting](../README.booting.md) -Supported Boards/Machines -========================= +## Supported Boards/Machines -Boards/Machines supported by this layer: +**Boards/Machines supported by this layer:** -* MicroBlaze: - * [Xilinx ML605 (QEMU)](conf/machine/ml605-qemu-microblazeel.conf) - `ml605-qemu-microblazeel` (QEMU support) - * [Xilinx S3A DSP 1800 (QEMU)](conf/machine/s3adsp1800-qemu-microblazeeb.conf) - `s3adsp1800-qemu-microblazeeb` (QEMU support) - * [Xilinx KC705](conf/machine/kc705-microblazeel.conf) - `kc705-microblazeel` -* Zynq: - * [Zynq (QEMU)](conf/machine/qemu-zynq7.conf) - `qemu-zynq7` (QEMU Support) - * [Xilinx ZC702](conf/machine/zc702-zynq7.conf) - `zc702-zynq7` (with QEMU support) - * [Xilinx ZC706](conf/machine/zc706-zynq7.conf) - `zc706-zynq7` (with QEMU support) - * [Avnet MicroZed](conf/machine/microzed-zynq7.conf) - `microzed-zynq7` - * [Avnet PicoZed](conf/machine/picozed-zynq7.conf) - `picozed-zynq7` - * [Avnet/Digilent ZedBoard](conf/machine/zedboard-zynq7.conf) - `zedboard-zynq7` - * [Digilent Zybo](conf/machine/zybo-zynq7.conf) - `zybo-zynq7` - * [Digilent Zybo Linux BD](conf/machine/zybo-linux-bd-zynq7.conf) - `zybo-linux-bd-zynq7` -* ZynqMP: - * [Xilinx ZCU102](conf/machine/zcu102-zynqmp.conf) - `zcu102-zynqmp` (QEMU support) - * [Xilinx ZCU106](conf/machine/zcu106-zynqmp.conf) - `zcu106-zynqmp` - * [Xilinx ZCU104](conf/machine/zcu104-zynqmp.conf) - `zcu104-zynqmp` +| Platform | Xilinx Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx KC705](https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html)|[kc705-microblazeel](conf/machine/kc705-microblazeel.conf)|`kc705-full`| +|Zynq-7000|Zynq (QEMU)|[qemu-zynq7](conf/machine/qemu-zynq7.conf)|NA| +||[Xilinx ZC702](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html)|[zc702-zynq7](conf/machine/zc702-zynq7.conf)|`zc702`| +||[Xilinx ZC706](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html)|[zc706-zynq7](conf/machine/zc706-zynq7.conf)|`zc706`| +|ZynqMP|[Xilinx ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html)|[zcu102-zynqmp](conf/machine/zcu102-zynqmp.conf)|`zcu102-rev1.0`| +||[Xilinx ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html)|[zcu104-zynqmp](conf/machine/zcu104-zynqmp.conf)|`zcu104-revc`| +||[Xilinx ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html)|[zcu106-zynqmp](conf/machine/zcu106-zynqmp.conf)|`zcu106-reva`| +||[Xilinx ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html)|[zcu111-zynqmp](conf/machine/zcu111-zynqmp.conf)|`zcu111-reva`| +||[Xilinx ZCU1275](https://www.xilinx.com/products/boards-and-kits/zcu1275.html)|[zcu1275-zynqmp](conf/machine/zcu1275-zynqmp.conf)|`zcu1275-revb`| +||[Xilinx ZCU1285](https://www.xilinx.com/products/boards-and-kits/zcu1285.html)|[zcu1285-zynqmp](conf/machine/zcu1285-zynqmp.conf)|`zcu1285-reva`| +||[Xilinx ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html)|[zcu208-zynqmp](conf/machine/zcu208-zynqmp.conf)|`zcu208-reva`| +||[Xilinx ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html)|[zcu216-zynqmp](conf/machine/zcu216-zynqmp.conf)|`zcu216-reva`| +|Versal|[Xilinx VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html)|[vck190-versal](conf/machine/vck190-versal.conf)|`versal-vck190-reva-x-ebm-01-reva`| +||[Xilinx VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html)|[vmk180-versal](conf/machine/vmk180-versal.conf)|`versal-vmk180-reva-x-ebm-01-reva`| +||[Xilinx VCK5000](https://www.xilinx.com/products/boards-and-kits/vck5000.html)|[vck5000-versal](conf/machine/vck5000-versal.conf)|`versal-vck5000-reva-x-ebm-01-reva`| -Additional information on Xilinx architectures can be found at: - http://www.xilinx.com/support/index.htm +> **Note:** Additional information on Xilinx architectures can be found at: + https://www.xilinx.com/products/silicon-devices.html -For Zybo Linux BD reference design, please see meta-xilinx-contrib layer - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -58,31 +40,9 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) -Recipe Licenses -=============== - -Due to licensing restrictions some recipes in this layer rely on closed source -or restricted content provided by Xilinx. In order to use these recipes you must -accept or agree to the licensing terms (e.g. EULA, Export Compliance, NDA, -Redistribution, etc). This layer **does not enforce** any legal requirement, it -is the **responsibility of the user** the ensure that they are in compliance -with any licenses or legal requirements for content used. - -In order to use recipes that rely on restricted content the `xilinx` license -flag must be white-listed in the build configuration (e.g. `local.conf`). This -can be done on a per package basis: - - LICENSE_FLAGS_WHITELIST += "xilinx_pmu-rom" - -or generally: - - LICENSE_FLAGS_WHITELIST += "xilinx" - -Generally speaking Xilinx content that is provided as a restricted download -cannot be obtained without a Xilinx account, in order to use this content you -must first download it with your Xilinx account and place the downloaded content -in the `downloads/` directory of your build or on a `PREMIRROR`. Attempting to -fetch the content using bitbake will fail, indicating the URL from which to -acquire the content. + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc b/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc deleted file mode 100644 index bfb57e00..00000000 --- a/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc +++ /dev/null @@ -1,12 +0,0 @@ -# Ultra96 items that need to be configured from zynqmp-generic -KERNEL_DEVICETREE:ultra96 = "xilinx/zynqmp-zcu100-revC.dtb" - -# Affects meta-xilinx-tools xsctyaml.bbclass related items -YAML_SERIAL_CONSOLE_STDIN:ultra96 ?= "psu_uart_1" -YAML_SERIAL_CONSOLE_STDOUT:ultra96 ?= "psu_uart_1" - -YAML_COMPILER_FLAGS:append:ultra96 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " - -# Enable bluetooth and wifi module -MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append:ultra96 = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" - diff --git a/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf b/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf deleted file mode 100644 index c0e8e6dd..00000000 --- a/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf +++ /dev/null @@ -1,26 +0,0 @@ -#@TYPE: Machine -#@NAME: microzed-zynq7 -#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/) - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" - -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -KERNEL_DEVICETREE = "zynq-microzed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf deleted file mode 100644 index 157a75c2..00000000 --- a/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf +++ /dev/null @@ -1,20 +0,0 @@ -#@TYPE: Machine -#@NAME: ml605-qemu-microblazeel -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model) - -TUNE_FEATURES:tune-microblaze ?= "microblaze v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard" - -require conf/machine/microblaze-generic.conf - -USE_VT = "" - -# Use the networking setup from qemuarm -MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" -FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-ml605" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf b/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf deleted file mode 100644 index d4f63f95..00000000 --- a/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf +++ /dev/null @@ -1,28 +0,0 @@ -#@TYPE: Machine -#@NAME: picozed-zynq7 -#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/) -# -# Note: This machine configuration is intended as a generic config for -# the picozed SOM. It also covers the multiple SKUs for the picoZed -# including 7010, 7020, 7015 and 7030. - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" - -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf b/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf deleted file mode 100644 index f28e3d4a..00000000 --- a/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf +++ /dev/null @@ -1,9 +0,0 @@ -#@TYPE: Machine -#@NAME: qemu-zynq7 -#@DESCRIPTION: Zynq QEMU machine support ('xilinx-zynq-a9' model) - -require conf/machine/zynq-generic.conf - -# Use the networking setup from qemuarm -MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" -FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" diff --git a/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf b/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf deleted file mode 100644 index 12621357..00000000 --- a/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf +++ /dev/null @@ -1,21 +0,0 @@ -#@TYPE: Machine -#@NAME: s3adsp1800-qemu-microblazeeb -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-s3adsp1800' model) - -TUNE_FEATURES:tune-microblaze ?= "microblaze v8.00 bigendian barrel-shift pattern-compare multiply-low" - -require conf/machine/microblaze-generic.conf - -MACHINE_FEATURES = "" - -USE_VT = "" -SERIAL_CONSOLES ?= "115200;ttyUL0" - -KERNEL_IMAGETYPE ?= "linux.bin.ub" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-s3adsp1800" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf b/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf deleted file mode 100644 index ff74ac3d..00000000 --- a/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf +++ /dev/null @@ -1,23 +0,0 @@ -#@TYPE: Machine -#@NAME: ultra96-zynqmp -#@DESCRIPTION: Machine support for Ultra96 Evaluation Board. -# - -SOC_VARIANT = 'eg' - -require conf/machine/zynqmp-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":ultra96" - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu100-revC.dtb" - -# Affects meta-xilinx-tools xsctyaml.bbclass related items -YAML_SERIAL_CONSOLE_STDIN ?= "psu_uart_1" -YAML_SERIAL_CONSOLE_STDOUT ?= "psu_uart_1" - -YAML_COMPILER_FLAGS:append = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " - -# Enable bluetooth and wifi module -MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" - diff --git a/meta-xilinx-bsp/conf/machine/v350-versal.conf b/meta-xilinx-bsp/conf/machine/v350-versal.conf deleted file mode 100644 index d865dc5a..00000000 --- a/meta-xilinx-bsp/conf/machine/v350-versal.conf +++ /dev/null @@ -1,19 +0,0 @@ -#@TYPE: Machine -#@NAME: v350-versal -##@DESCRIPTION: Machine support for v350 versal. - -SOC_VARIANT = "ai-core" - -require conf/machine/versal-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":v350" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ -" diff --git a/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf b/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf deleted file mode 100644 index c20166e3..00000000 --- a/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf +++ /dev/null @@ -1,10 +0,0 @@ -#@TYPE: Machine -#@NAME: vc-p-a2197-versal -##@DESCRIPTION: Machine support for vc-p-a2197 versal . - -SOC_VARIANT = "ai-core" - -require conf/machine/versal-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":vc-p-a2197-00" diff --git a/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf b/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf deleted file mode 100644 index 4da6bb4e..00000000 --- a/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf +++ /dev/null @@ -1,24 +0,0 @@ -#@TYPE: Machine -#@NAME: zedboard-zynq7 -#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/) -# -# For details on the Evaluation board: -# http://www.zedboard.org/content/overview -# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard: -# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard -# - -require conf/machine/zynq-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":zedboard" - -SPL_BINARY ?= "spl/boot.bin" - -KERNEL_DEVICETREE = "zynq-zed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - boot.scr \ - " diff --git a/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf deleted file mode 100644 index df26ea0d..00000000 --- a/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf +++ /dev/null @@ -1,27 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-linux-bd-zynq7 -#@DESCRIPTION: Machine support for zybo-linux-bd project. -# -# generated base on ZYBO linux-bd project -# - -require conf/machine/zynq-generic.conf - -PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot" - -MACHINE_FEATURES += "keyboard screen alsa sdio" - -SPL_BINARY ?= "spl/boot.bin" -FORCE_PLATFORM_INIT = "1" -UBOOT_ELF = "u-boot" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - bitstream \ - uEnv.txt \ - " - -KERNEL_FEATURES += " \ - bsp/xilinx/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc \ - features/xilinx/v4l2/v4l2.scc \ - " diff --git a/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf b/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf deleted file mode 100644 index aa1eafe4..00000000 --- a/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf +++ /dev/null @@ -1,29 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-zynq7 -#@DESCRIPTION: Machine support for ZYBO. -# -# For details on the ZYBO board: -# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO -# - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -KERNEL_DEVICETREE = "zynq-zybo.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index f3c932db..2640c2c2 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -1,7 +1,3 @@ -YAML_MAIN_MEMORY_CONFIG:ultra96 ?= "psu_ddr_0" -YAML_CONSOLE_DEVICE_CONFIG:ultra96 ?= "psu_uart_1" -YAML_DT_BOARD_FLAGS:ultra96 ?= "{BOARD avnet-ultra96-rev1}" - YAML_MAIN_MEMORY_CONFIG:kc705 ?= "mig_7series_0" YAML_CONSOLE_DEVICE_CONFIG:kc705 ?= "axi_uartlite_0" YAML_DT_BOARD_FLAGS:kc705 ?= "{BOARD kc705-full}" @@ -10,7 +6,6 @@ YAML_DT_BOARD_FLAGS:zcu102 ?= "{BOARD zcu102-rev1.0}" YAML_DT_BOARD_FLAGS:zcu106 ?= "{BOARD zcu106-reva}" YAML_DT_BOARD_FLAGS:zc702 ?= "{BOARD zc702}" YAML_DT_BOARD_FLAGS:zc706 ?= "{BOARD zc706}" -YAML_DT_BOARD_FLAGS:zedboard ?= "{BOARD zedboard}" YAML_DT_BOARD_FLAGS:zc1254 ?= "{BOARD zc1254-reva}" YAML_DT_BOARD_FLAGS:zcu104 ?= "{BOARD zcu104-revc}" YAML_DT_BOARD_FLAGS:zcu111 ?= "{BOARD zcu111-reva}" diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend deleted file mode 100644 index e925d608..00000000 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -ULTRA96_VERSION ?= "1" -YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" - diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend index 94020f25..83f8c57b 100644 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend @@ -1,19 +1,9 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" # device tree sources for the various machines -COMPATIBLE_MACHINE:picozed-zynq7 = ".*" -SRC_URI:append:picozed-zynq7 = " file://picozed-zynq7.dts" - COMPATIBLE_MACHINE:qemu-zynq7 = ".*" SRC_URI:append:qemu-zynq7 = " file://qemu-zynq7.dts" -COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = ".*" -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://zybo-linux-bd-zynq7.dts \ - file://pcw.dtsi \ - file://pl.dtsi \ - " - COMPATIBLE_MACHINE:kc705-microblazeel = ".*" SRC_URI:append:kc705-microblazeel = " \ file://kc705-microblazeel.dts \ diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts deleted file mode 100644 index 6f9b653a..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" - -/ { - model = "Avnet picoZed"; - compatible = "avnet,picozed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ - }; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - compatible = "marvell,88e1512", "marvell,88e1510"; - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&sdhci1 { - status = "okay"; - /* SD1 is onnected to a non-removable eMMC flash device */ - non-removable; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; - -&qspi { - status = "okay"; - primary_flash: ps7-qspi@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - /* Example 16M partition table using U-Boot + U-Boot SPL */ - partition@0x0 { - label = "boot"; - reg = <0x0 0xe0000>; - }; - partition@0xe0000 { - label = "ubootenv"; - reg = <0xe0000 0x20000>; - }; - partition@0x100000 { - label = "uboot"; - reg = <0x100000 0x100000>; - }; - partition@0x200000 { - label = "kernel"; - reg = <0x200000 0x4f0000>; - }; - partition@0x6f0000 { - label = "devicetree"; - reg = <0x6f0000 0x10000>; - }; - partition@0x700000 { - label = "rootfs"; - reg = <0x700000 0x400000>; - }; - partition@0xb00000 { - label = "spare"; - reg = <0xb00000 0x500000>; - }; - }; -}; - diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi deleted file mode 100644 index 0f678d39..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - cpus { - cpu@0 { - operating-points = <650000 1000000 325000 1000000>; - }; - }; -}; -&gem0 { - phy-mode = "rgmii-id"; - status = "okay"; - xlnx,ptp-enet-clock = <0x6750918>; -}; -&gpio0 { - emio-gpio-width = <64>; - gpio-mask-high = <0x0>; - gpio-mask-low = <0x5600>; -}; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; -&intc { - num_cpus = <2>; - num_interrupts = <96>; -}; -&qspi { - is-dual = <0>; - num-cs = <1>; - status = "okay"; -}; -&sdhci0 { - status = "okay"; - xlnx,has-cd = <0x1>; - xlnx,has-power = <0x0>; - xlnx,has-wp = <0x1>; -}; -&uart1 { - current-speed = <115200>; - device_type = "serial"; - port-number = <0>; - status = "okay"; -}; -&usb0 { - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; - usb-reset = <&gpio0 46 0>; -}; -&clkc { - fclk-enable = <0x3>; - ps-clk-frequency = <50000000>; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi deleted file mode 100644 index 32bc7688..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - amba_pl: amba_pl { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges ; - axi_dynclk_0: axi_dynclk@43c10000 { - compatible = "xlnx,axi-dynclk-1.0"; - reg = <0x43c10000 0x10000>; - xlnx,s00-axi-addr-width = <0x5>; - xlnx,s00-axi-data-width = <0x20>; - }; - axi_gpio_btn: gpio@41210000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41210000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_hdmi: gpio@41230000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - interrupt-parent = <&intc>; - interrupts = <0 29 4>; - reg = <0x41230000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_led: gpio@41200000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41200000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_sw: gpio@41220000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41220000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_i2s_adi_0: axi_i2s_adi@43c20000 { - compatible = "xlnx,axi-i2s-adi-1.0"; - reg = <0x43c20000 0x10000>; - xlnx,bclk-pol = <0x0>; - xlnx,dma-type = <0x1>; - xlnx,has-rx = <0x1>; - xlnx,has-tx = <0x1>; - xlnx,lrclk-pol = <0x0>; - xlnx,num-ch = <0x1>; - xlnx,s-axi-min-size = <0x000001FF>; - xlnx,slot-width = <0x18>; - }; - axi_vdma_0: dma@43000000 { - #dma-cells = <1>; - compatible = "xlnx,axi-vdma-1.00.a"; - clocks = <&clkc 15>; - clock-names = "s_axi_lite_aclk"; - interrupt-parent = <&intc>; - interrupts = <0 30 4>; - reg = <0x43000000 0x10000>; - xlnx,flush-fsync = <0x1>; - xlnx,num-fstores = <0x1>; - dma-channel@43000000 { - compatible = "xlnx,axi-vdma-mm2s-channel"; - interrupts = <0 30 4>; - xlnx,datawidth = <0x20>; - xlnx,device-id = <0x0>; - }; - }; - v_tc_0: v_tc@43c00000 { - compatible = "xlnx,v-tc-6.1"; - interrupt-parent = <&intc>; - interrupts = <0 31 4>; - reg = <0x43c00000 0x10000>; - xlnx,det-achroma-en = <0x0>; - xlnx,det-avideo-en = <0x1>; - xlnx,det-fieldid-en = <0x0>; - xlnx,det-hblank-en = <0x1>; - xlnx,det-hsync-en = <0x1>; - xlnx,det-vblank-en = <0x1>; - xlnx,det-vsync-en = <0x1>; - xlnx,detect-en = <0x0>; - xlnx,fsync-hstart0 = <0x0>; - xlnx,fsync-hstart1 = <0x0>; - xlnx,fsync-hstart10 = <0x0>; - xlnx,fsync-hstart11 = <0x0>; - xlnx,fsync-hstart12 = <0x0>; - xlnx,fsync-hstart13 = <0x0>; - xlnx,fsync-hstart14 = <0x0>; - xlnx,fsync-hstart15 = <0x0>; - xlnx,fsync-hstart2 = <0x0>; - xlnx,fsync-hstart3 = <0x0>; - xlnx,fsync-hstart4 = <0x0>; - xlnx,fsync-hstart5 = <0x0>; - xlnx,fsync-hstart6 = <0x0>; - xlnx,fsync-hstart7 = <0x0>; - xlnx,fsync-hstart8 = <0x0>; - xlnx,fsync-hstart9 = <0x0>; - xlnx,fsync-vstart0 = <0x0>; - xlnx,fsync-vstart1 = <0x0>; - xlnx,fsync-vstart10 = <0x0>; - xlnx,fsync-vstart11 = <0x0>; - xlnx,fsync-vstart12 = <0x0>; - xlnx,fsync-vstart13 = <0x0>; - xlnx,fsync-vstart14 = <0x0>; - xlnx,fsync-vstart15 = <0x0>; - xlnx,fsync-vstart2 = <0x0>; - xlnx,fsync-vstart3 = <0x0>; - xlnx,fsync-vstart4 = <0x0>; - xlnx,fsync-vstart5 = <0x0>; - xlnx,fsync-vstart6 = <0x0>; - xlnx,fsync-vstart7 = <0x0>; - xlnx,fsync-vstart8 = <0x0>; - xlnx,fsync-vstart9 = <0x0>; - xlnx,gen-achroma-en = <0x0>; - xlnx,gen-achroma-polarity = <0x1>; - xlnx,gen-auto-switch = <0x0>; - xlnx,gen-avideo-en = <0x1>; - xlnx,gen-avideo-polarity = <0x1>; - xlnx,gen-cparity = <0x0>; - xlnx,gen-f0-vblank-hend = <0x500>; - xlnx,gen-f0-vblank-hstart = <0x500>; - xlnx,gen-f0-vframe-size = <0x2ee>; - xlnx,gen-f0-vsync-hend = <0x500>; - xlnx,gen-f0-vsync-hstart = <0x500>; - xlnx,gen-f0-vsync-vend = <0x2d9>; - xlnx,gen-f0-vsync-vstart = <0x2d4>; - xlnx,gen-f1-vblank-hend = <0x500>; - xlnx,gen-f1-vblank-hstart = <0x500>; - xlnx,gen-f1-vframe-size = <0x2ee>; - xlnx,gen-f1-vsync-hend = <0x500>; - xlnx,gen-f1-vsync-hstart = <0x500>; - xlnx,gen-f1-vsync-vend = <0x2d9>; - xlnx,gen-f1-vsync-vstart = <0x2d4>; - xlnx,gen-fieldid-en = <0x0>; - xlnx,gen-fieldid-polarity = <0x1>; - xlnx,gen-hactive-size = <0x500>; - xlnx,gen-hblank-en = <0x1>; - xlnx,gen-hblank-polarity = <0x1>; - xlnx,gen-hframe-size = <0x672>; - xlnx,gen-hsync-en = <0x1>; - xlnx,gen-hsync-end = <0x596>; - xlnx,gen-hsync-polarity = <0x1>; - xlnx,gen-hsync-start = <0x56e>; - xlnx,gen-interlaced = <0x0>; - xlnx,gen-vactive-size = <0x2d0>; - xlnx,gen-vblank-en = <0x1>; - xlnx,gen-vblank-polarity = <0x1>; - xlnx,gen-video-format = <0x2>; - xlnx,gen-vsync-en = <0x1>; - xlnx,gen-vsync-polarity = <0x1>; - xlnx,generate-en = <0x1>; - xlnx,has-axi4-lite = <0x1>; - xlnx,has-intc-if = <0x0>; - xlnx,interlace-en = <0x0>; - xlnx,max-lines = <0x1000>; - xlnx,max-pixels = <0x1000>; - xlnx,num-fsyncs = <0x1>; - xlnx,sync-en = <0x0>; - }; - }; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts deleted file mode 100644 index 19654392..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; -/include/ "skeleton.dtsi" -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" -/include/ "pcw.dtsi" -/include/ "pl.dtsi" - -/ { - model = "Digilent-Zybo-Linux-BD-v2015.4"; - aliases { - serial0 = &uart1; - ethernet0 = &gem0; - spi0 = &qspi; - }; - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - btn4 { - label = "btn4"; - gpios = <&gpio0 50 0>; - linux,code = <108>; /* down */ - gpio-key,wakeup; - autorepeat; - }; - btn5 { - label = "btn5"; - gpios = <&gpio0 51 0>; - linux,code = <103>; /* up */ - gpio-key,wakeup; - autorepeat; - }; - }; - - usb_phy0: usb_phy@0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&amba { - u-boot,dm-pre-reloc; -}; - -&amba_pl { - encoder_0: digilent_encoder { - compatible = "digilent,drm-encoder"; - dglnt,edid-i2c = <&i2c1>; - }; - - xilinx_drm { - compatible = "xlnx,drm"; - xlnx,vtc = <&v_tc_0>; - xlnx,connector-type = "HDMIA"; - xlnx,encoder-slave = <&encoder_0>; - clocks = <&axi_dynclk_0>; - planes { - xlnx,pixel-format = "xrgb8888"; - plane0 { - dmas = <&axi_vdma_0 0>; - dma-names = "dma0"; - }; - }; - }; - - i2s_clk: i2s_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12288000>; - clock-output-names = "i2s_clk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "ZYBO-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MICIN", "Microphone Jack", - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - dailink0_master: simple-audio-card,cpu { - clocks = <&i2s_clk>; - sound-dai = <&axi_i2s_adi_0>; - }; - simple-audio-card,codec { - clocks = <&i2s_clk>; - sound-dai = <&ssm2603>; - }; - }; -}; - -&axi_dynclk_0 { - compatible = "digilent,axi-dynclk"; - #clock-cells = <0>; - clocks = <&clkc 15>; -}; - -&axi_i2s_adi_0 { - #sound-dai-cells = <0>; - compatible = "adi,axi-i2s-1.00.a"; - clocks = <&clkc 15>, <&i2s_clk>; - clock-names = "axi", "ref"; - dmas = <&dmac_s 0 &dmac_s 1>; - dma-names = "tx", "rx"; -}; - -&gem0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - local-mac-address = []; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&i2c0 { - eeprom@50 { - /* Microchip 24AA02E48 */ - compatible = "microchip,24c02"; - reg = <0x50>; - }; - - ssm2603: ssm2603@1a{ - #sound-dai-cells = <0>; - compatible = "adi,ssm2603"; - reg = <0x1a>; - }; -}; - -&qspi { - #address-cells = <1>; - #size-cells = <0>; - flash0: flash@0 { - compatible = "micron,m25p80", "s25fl128s"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - partition@0x00000000 { - label = "boot"; - reg = <0x00000000 0x00300000>; - }; - partition@0x00300000 { - label = "bootenv"; - reg = <0x00300000 0x00020000>; - }; - partition@0x00320000 { - label = "kernel"; - reg = <0x00320000 0x00a80000>; - }; - partition@0x00da0000 { - label = "spare"; - reg = <0x00da0000 0x00000000>; - }; - }; -}; - -&usb0 { - usb-phy = <&usb_phy0>; -}; - -&v_tc_0 { - compatible = "xlnx,v-tc-5.01.a"; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend deleted file mode 100644 index fbe42821..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend +++ /dev/null @@ -1,4 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/platform-init:" - -COMPATIBLE_MACHINE:picozed-zynq7 = "picozed-zynq7" - diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c deleted file mode 100644 index 5587ab25..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c +++ /dev/null @@ -1,13191 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} - - - - diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h deleted file mode 100644 index df5205e8..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h +++ /dev/null @@ -1,130 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 100000000 -#define FPGA2_FREQ 33333336 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif - - diff --git a/meta-xilinx-contrib/README.md b/meta-xilinx-contrib/README.md index 952392af..1b11d347 100644 --- a/meta-xilinx-contrib/README.md +++ b/meta-xilinx-contrib/README.md @@ -1,35 +1,21 @@ -meta-xilinx-contrib -=================== +# meta-xilinx-contrib This layer is a contribution layer to support for MicroBlaze, Zynq and ZynqMP architectures. -This layer depends on meta-xilinx-bsp layer. +Any patches from open source contributors for vendor board can be added here. -Supported Boards/Machines -========================= +## Supported Boards/Machines -* Zynq: - * Digilent Zybo Linux BD Reference design - * [Avnet MiniZed](conf/machine/minized-zynq7.conf) - `minized-zynq7` +**Boards/Machines supported by this layer:** -Maintainers, Mailing list, Patches -================================== -Please send any patches, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): +| Platform | Vendor Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx ML605 (QEMU)](https://www.digikey.com/en/products/detail/amd-xilinx/EK-V6-ML605-G/2175174)|[ml605-qemu-microblazeel](conf/machine/ml605-qemu-microblazeel.conf)|NA| +|Zynq-7000|NA|NA|NA| +|ZynqMP|NA|NA|NA| +|Versal|NA|NA|NA| - meta-xilinx@lists.yoctoproject.org with '[meta-xilinx-contrib]' in the subject. - - -Subscribe to mailing list at -https://lists.yoctoproject.org/listinfo/meta-xilinx - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -37,7 +23,9 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.openembedded.org/meta-xilinx - + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core, meta-xilinx-vendor + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-contrib/conf/machine/minized-zynq7.conf b/meta-xilinx-contrib/conf/machine/minized-zynq7.conf deleted file mode 100644 index a7c549cc..00000000 --- a/meta-xilinx-contrib/conf/machine/minized-zynq7.conf +++ /dev/null @@ -1,27 +0,0 @@ -#@TYPE: Machine -#@NAME: minized-zynq7 -#@DESCRIPTION: Machine support for MiniZed. (http://www.minized.org/) - -require conf/machine/include/tune-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "ext2 vfat usbhost wifi bluetooth" - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -UBOOT_MACHINE ?= "zynq_minized_config" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/bootloader \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "linux-firmware-bcm43430" - -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - " diff --git a/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf new file mode 100644 index 00000000..157a75c2 --- /dev/null +++ b/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf @@ -0,0 +1,20 @@ +#@TYPE: Machine +#@NAME: ml605-qemu-microblazeel +#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model) + +TUNE_FEATURES:tune-microblaze ?= "microblaze v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard" + +require conf/machine/microblaze-generic.conf + +USE_VT = "" + +# Use the networking setup from qemuarm +MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" +FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" + +# This machine is a targeting a QEMU model, runqemu setup: +QB_MEM = "-m 256" +QB_MACHINE = "-machine petalogix-ml605" +QB_OPT_APPEND = "-nographic -serial mon:stdio" +QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend index 2ce919ac..8ba7a490 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend @@ -1,9 +1,12 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ - file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ - file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ - " +# Note: These patches are very old and doesn't apply on top of 5.x +# kernel. For more details refer README.md file. + +#SRC_URI:append:zybo-linux-bd-zynq7 = " \ +# file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ +# file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ +# file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ +# " SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-core/README.md b/meta-xilinx-core/README.md index 8997760c..d450c4b3 100644 --- a/meta-xilinx-core/README.md +++ b/meta-xilinx-core/README.md @@ -1,24 +1,8 @@ -meta-xilinx-core -================ +# meta-xilinx-core -This layer provides support for MicroBlaze, Zynq and ZynqMP. +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures. - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -26,9 +10,10 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) + -Configuring Machines -==================== +## Configuring Machines All machines that use meta-xilinx-tools should be derived from one of the following: microblaze-generic, zynq-generic, zynqmp-generic, or @@ -58,8 +43,7 @@ require you to specify the path to a PDI file using PDI_PATH. The XSCT version will extract the PDI automatically. -Recipe Licenses -=============== +## Recipe Licenses Due to licensing restrictions some recipes in this layer rely on closed source or restricted content provided by Xilinx. In order to use these recipes you must diff --git a/meta-xilinx-core/conf/bblayers.conf.sample b/meta-xilinx-core/conf/bblayers.conf.sample index 890ef3b6..a98e8936 100644 --- a/meta-xilinx-core/conf/bblayers.conf.sample +++ b/meta-xilinx-core/conf/bblayers.conf.sample @@ -23,6 +23,7 @@ BBLAYERS ?= " \ ##OEROOT##/../meta-xilinx/meta-xilinx-pynq \ ##OEROOT##/../meta-xilinx/meta-xilinx-standalone \ ##OEROOT##/../meta-xilinx/meta-xilinx-contrib \ + ##OEROOT##/../meta-xilinx/meta-xilinx-vendor \ ##OEROOT##/../meta-xilinx-tools \ ##OEROOT##/../meta-petalinux \ ##OEROOT##/../meta-virtualization \ diff --git a/meta-xilinx-pynq/README.md b/meta-xilinx-pynq/README.md index a40ff96b..7f8163f2 100644 --- a/meta-xilinx-pynq/README.md +++ b/meta-xilinx-pynq/README.md @@ -1,26 +1,19 @@ # meta-xilinx-pynq -================================ - -Introduction -------------------------- +## Introduction This layer collects recipes required to build and run PYNQ based examples using jupyter-notebooks on yocto -Maintainers, Patches/Submissions, Community -=========================================== -Please open pull requests for any changes. - -Maintainers: - - Sai Hari Chandana Kalluri (chandana.kalluri@xilinx.com) - Peter Ogden (ogden@xilinx.com) +## Dependencies -Layer dependencies -===================== +This layer depends on: -URI: git://git.openembedded.org/bitbake + URI: git://git.openembedded.org/bitbake -URI: git://git.openembedded.org/openembedded-core + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) -URI: git://git.openembedded.org/meta-openembedded + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-standalone-experimental/README.md b/meta-xilinx-standalone-experimental/README.md index e49b01f2..99675b0a 100644 --- a/meta-xilinx-standalone-experimental/README.md +++ b/meta-xilinx-standalone-experimental/README.md @@ -1,5 +1,5 @@ -meta-xilinx-standalone-experimental -=================================== +# meta-xilinx-standalone-experimental + This layer contains experimental items that may eventually be added to the meta-xilinx-standalone layer. The components in this layer may or may not be buildable as they may require unreleased code. @@ -9,9 +9,9 @@ this should be considered to be a preview release only. For instance, some components may not be buildable, expect APIs to change on various parts and pieces. -Build Instructions ------------------- -Note: to use this layer you must REMOVE meta-xilinx-tools from your +## Build Instructions + +**Note:** to use this layer you must REMOVE meta-xilinx-tools from your project. meta-xilinx-tools is not compatible with this experimental approach. You may also have to remove other layers that depend on meta-xilinx-tools, such as meta-som. @@ -32,27 +32,18 @@ To install the setup SDK: Then follow the instructions in the 'prestep/README-setup' file. -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this -layer to the [meta-xilinx mailing list] -(https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: - URI: git://git.yoctoproject.org/poky + URI: git://git.openembedded.org/bitbake + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-standalone + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core, meta-xilinx-bsp, meta-xilinx-standalone + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-bsp diff --git a/meta-xilinx-standalone/README.md b/meta-xilinx-standalone/README.md index a3514230..ea9fdbc4 100644 --- a/meta-xilinx-standalone/README.md +++ b/meta-xilinx-standalone/README.md @@ -1,5 +1,4 @@ -meta-xilinx-standalone -====================== +# meta-xilinx-standalone This layer is meant to augment Yocto/OE functionality to provide a Baremetal/Standalone Toolchain as well as a generic version of various @@ -8,15 +7,14 @@ firmware that is required to boot a ZynqMP or Versal system. For optimized versions of the firmware and additional components you must use the meta-xilinx-tools layer. -Building --------- +## Building + The software in this layer may be used in either a standard single configuration build, or a multiconfig build. A multiconfig build, along with the MACHINES defined in meta-xilinx-bsps will automate the generation of certain firmwares. -Toolchains ----------- +## Toolchains To build standalone toolchains similar to those embedded with the Xilinx xsct tooling: @@ -29,8 +27,7 @@ Use one of the custom machines: MACHINE= DISTRO=xilinx-standalone bitbake meta-toolchain -Standalone Firmware -------------------- +## Standalone Firmware The standalone firmware is a genericly configured firmware, it can be build either in a single standalong configuration, or via an automated @@ -89,25 +86,17 @@ MACHINE=zynqmp-generic bitbake fsbl pmufw MACHINE=versal-generic bitbake plmfw psmfw -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this -layer to the [meta-xilinx mailing list] -(https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org +## Dependencies -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle +This layer depends on: -Dependencies -============ + URI: git://git.openembedded.org/bitbake -This layer depends on: + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/poky + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core, meta-xilinx-bsp + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-bsp diff --git a/meta-xilinx-vendor/COPYING.MIT b/meta-xilinx-vendor/COPYING.MIT new file mode 100644 index 00000000..fb950dc6 --- /dev/null +++ b/meta-xilinx-vendor/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/meta-xilinx-vendor/README.md b/meta-xilinx-vendor/README.md new file mode 100644 index 00000000..51ff84e1 --- /dev/null +++ b/meta-xilinx-vendor/README.md @@ -0,0 +1,37 @@ +# meta-xilinx-vendor + +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures vendor boards. + +## Supported Boards/Machines + +**Boards/Machines supported by this layer:** + + +| Platform | Vendor Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx S3A DSP 1800](https://shop.trenz-electronic.de/en/TE0320-00-EV02I-FPGA-Module-with-Spartan-3A-DSP-1800K-EV02I-1-Gbit-DDR-RAM)|[s3adsp1800-qemu-microblazeeb](conf/machine/s3adsp1800-qemu-microblazeeb.conf)|NA| +|Zynq-7000|[Avent Microzed](https://www.xilinx.com/products/boards-and-kits/1-5lakcu.html)|[microzed-zynq7](conf/machine/microzed-zynq7.conf)|`zynq-microzed.dtb`| +||[Avnet Picozed](https://www.xilinx.com/products/boards-and-kits/1-58nuel.html)|[picozed-zynq7](conf/machine/picozed-zynq7.conf)|NA| +||[Avnet Minized](https://www.xilinx.com/products/boards-and-kits/1-odbhjd.html)|[minized-zynq7](conf/machine/minized-zynq7.conf)|NA| +||[Avnet/Digilent ZedBoard](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html)|[zedboard-zynq7](conf/machine/zedboard-zynq7.conf)|NA| +||[Digilent Zybo](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-zynq7](conf/machine/zybo-zynq7.conf)|`zynq-zybo.dtb`| +||[Digilent Zybo Linux BD](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-linux-bd-zynq7](conf/machine/zybo-linux-bd-zynq7.conf)|NA| +|ZynqMP|[Avent Ultra96](https://www.xilinx.com/products/boards-and-kits/1-vad4rl.html)|[ultra96-zynqmp](conf/machine/ultra96-zynqmp.conf)|`avnet-ultra96-rev1`| +|Versal|NA|NA|NA| + +> **Note:** +`For Zybo Linux BD reference design, please see meta-xilinx-contrib layer` + +## Dependencies + +This layer depends on: + + URI: git://git.openembedded.org/bitbake + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) + + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-vendor/conf/layer.conf b/meta-xilinx-vendor/conf/layer.conf new file mode 100644 index 00000000..b3e81efc --- /dev/null +++ b/meta-xilinx-vendor/conf/layer.conf @@ -0,0 +1,13 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have a packages directory, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "xilinx-vendor" +BBFILE_PATTERN_xilinx-vendor = "^${LAYERDIR}/" +BBFILE_PRIORITY_xilinx-vendor = "5" + +LAYERDEPENDS_xilinx-vendor = "xilinx" +LAYERSERIES_COMPAT_xilinx-vendor = "honister" diff --git a/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc b/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc new file mode 100644 index 00000000..bfb57e00 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc @@ -0,0 +1,12 @@ +# Ultra96 items that need to be configured from zynqmp-generic +KERNEL_DEVICETREE:ultra96 = "xilinx/zynqmp-zcu100-revC.dtb" + +# Affects meta-xilinx-tools xsctyaml.bbclass related items +YAML_SERIAL_CONSOLE_STDIN:ultra96 ?= "psu_uart_1" +YAML_SERIAL_CONSOLE_STDOUT:ultra96 ?= "psu_uart_1" + +YAML_COMPILER_FLAGS:append:ultra96 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " + +# Enable bluetooth and wifi module +MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append:ultra96 = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" + diff --git a/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf b/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf new file mode 100644 index 00000000..ce8058e4 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf @@ -0,0 +1,23 @@ +#@TYPE: Machine +#@NAME: microzed-zynq7 +#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/) + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +KERNEL_DEVICETREE = "zynq-microzed.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/conf/machine/minized-zynq7.conf b/meta-xilinx-vendor/conf/machine/minized-zynq7.conf new file mode 100644 index 00000000..af9d982d --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/minized-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: minized-zynq7 +#@DESCRIPTION: Machine support for MiniZed. (http://www.minized.org/) + +require conf/machine/zynq-generic.conf + +MACHINE_FEATURES = "ext2 vfat usbhost wifi bluetooth" + +UBOOT_MACHINE ?= "zynq_minized_config" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/bootloader \ + " + +SERIAL_CONSOLES ?= "115200;ttyPS0" + +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" + +MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "linux-firmware-bcm43430" + +IMAGE_BOOT_FILES += " \ + uEnv.txt \ + " diff --git a/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf b/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf new file mode 100644 index 00000000..31f5e220 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf @@ -0,0 +1,25 @@ +#@TYPE: Machine +#@NAME: picozed-zynq7 +#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/) +# +# Note: This machine configuration is intended as a generic config for +# the picozed SOM. It also covers the multiple SKUs for the picoZed +# including 7010, 7020, 7015 and 7030. + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf b/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf new file mode 100644 index 00000000..ff74ac3d --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf @@ -0,0 +1,23 @@ +#@TYPE: Machine +#@NAME: ultra96-zynqmp +#@DESCRIPTION: Machine support for Ultra96 Evaluation Board. +# + +SOC_VARIANT = 'eg' + +require conf/machine/zynqmp-generic.conf + +# Add board compatibility override +MACHINEOVERRIDES .= ":ultra96" + +KERNEL_DEVICETREE = "xilinx/zynqmp-zcu100-revC.dtb" + +# Affects meta-xilinx-tools xsctyaml.bbclass related items +YAML_SERIAL_CONSOLE_STDIN ?= "psu_uart_1" +YAML_SERIAL_CONSOLE_STDOUT ?= "psu_uart_1" + +YAML_COMPILER_FLAGS:append = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " + +# Enable bluetooth and wifi module +MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" + diff --git a/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf b/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf new file mode 100644 index 00000000..4da6bb4e --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: zedboard-zynq7 +#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/) +# +# For details on the Evaluation board: +# http://www.zedboard.org/content/overview +# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard: +# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard +# + +require conf/machine/zynq-generic.conf + +# Add board compatibility override +MACHINEOVERRIDES .= ":zedboard" + +SPL_BINARY ?= "spl/boot.bin" + +KERNEL_DEVICETREE = "zynq-zed.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + boot.scr \ + " diff --git a/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf new file mode 100644 index 00000000..98718ae3 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: zybo-linux-bd-zynq7 +#@DESCRIPTION: Machine support for zybo-linux-bd project. +# +# generated base on ZYBO linux-bd project +# + +require conf/machine/zynq-generic.conf + +MACHINE_FEATURES += "keyboard screen alsa sdio" + +SPL_BINARY ?= "spl/boot.bin" +FORCE_PLATFORM_INIT = "1" +UBOOT_ELF = "u-boot" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + bitstream \ + uEnv.txt \ + " + +KERNEL_FEATURES += " \ + features/xilinx/v4l2/v4l2.scc \ + " diff --git a/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf b/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf new file mode 100644 index 00000000..74d117c0 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf @@ -0,0 +1,27 @@ +#@TYPE: Machine +#@NAME: zybo-zynq7 +#@DESCRIPTION: Machine support for ZYBO. +# +# For details on the ZYBO board: +# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO +# + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +KERNEL_DEVICETREE = "zynq-zybo.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..963940f5 --- /dev/null +++ b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,7 @@ +# Ultra96 device tree configuration +YAML_MAIN_MEMORY_CONFIG:ultra96 ?= "psu_ddr_0" +YAML_CONSOLE_DEVICE_CONFIG:ultra96 ?= "psu_uart_1" +YAML_DT_BOARD_FLAGS:ultra96 ?= "{BOARD avnet-ultra96-rev1}" + +# ZedBoard device tree configuration +YAML_DT_BOARD_FLAGS:zedboard ?= "{BOARD zedboard}" diff --git a/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend new file mode 100644 index 00000000..e925d608 --- /dev/null +++ b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend @@ -0,0 +1,3 @@ +ULTRA96_VERSION ?= "1" +YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..341e69dc --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,13 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +# device tree sources for the various machines +COMPATIBLE_MACHINE:picozed-zynq7 = ".*" +SRC_URI:append:picozed-zynq7 = " file://picozed-zynq7.dts" + +COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = ".*" +SRC_URI:append:zybo-linux-bd-zynq7 = " \ + file://zybo-linux-bd-zynq7.dts \ + file://pcw.dtsi \ + file://pl.dtsi \ + " + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts new file mode 100644 index 00000000..6f9b653a --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts @@ -0,0 +1,98 @@ +/dts-v1/; +/include/ "zynq-7000.dtsi" +/include/ "zynq-7000-qspi-dummy.dtsi" + +/ { + model = "Avnet picoZed"; + compatible = "avnet,picozed", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + compatible = "marvell,88e1512", "marvell,88e1510"; + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +&sdhci1 { + status = "okay"; + /* SD1 is onnected to a non-removable eMMC flash device */ + non-removable; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&qspi { + status = "okay"; + primary_flash: ps7-qspi@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + /* Example 16M partition table using U-Boot + U-Boot SPL */ + partition@0x0 { + label = "boot"; + reg = <0x0 0xe0000>; + }; + partition@0xe0000 { + label = "ubootenv"; + reg = <0xe0000 0x20000>; + }; + partition@0x100000 { + label = "uboot"; + reg = <0x100000 0x100000>; + }; + partition@0x200000 { + label = "kernel"; + reg = <0x200000 0x4f0000>; + }; + partition@0x6f0000 { + label = "devicetree"; + reg = <0x6f0000 0x10000>; + }; + partition@0x700000 { + label = "rootfs"; + reg = <0x700000 0x400000>; + }; + partition@0xb00000 { + label = "spare"; + reg = <0xb00000 0x500000>; + }; + }; +}; + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi new file mode 100644 index 00000000..0f678d39 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi @@ -0,0 +1,63 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Fri Mar 4 15:40:49 2016 +*/ + + +/ { + cpus { + cpu@0 { + operating-points = <650000 1000000 325000 1000000>; + }; + }; +}; +&gem0 { + phy-mode = "rgmii-id"; + status = "okay"; + xlnx,ptp-enet-clock = <0x6750918>; +}; +&gpio0 { + emio-gpio-width = <64>; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; +}; +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; +&intc { + num_cpus = <2>; + num_interrupts = <96>; +}; +&qspi { + is-dual = <0>; + num-cs = <1>; + status = "okay"; +}; +&sdhci0 { + status = "okay"; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; +}; +&uart1 { + current-speed = <115200>; + device_type = "serial"; + port-number = <0>; + status = "okay"; +}; +&usb0 { + dr_mode = "host"; + phy_type = "ulpi"; + status = "okay"; + usb-reset = <&gpio0 46 0>; +}; +&clkc { + fclk-enable = <0x3>; + ps-clk-frequency = <50000000>; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi new file mode 100644 index 00000000..32bc7688 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi @@ -0,0 +1,215 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Fri Mar 4 15:40:49 2016 +*/ + + +/ { + amba_pl: amba_pl { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges ; + axi_dynclk_0: axi_dynclk@43c10000 { + compatible = "xlnx,axi-dynclk-1.0"; + reg = <0x43c10000 0x10000>; + xlnx,s00-axi-addr-width = <0x5>; + xlnx,s00-axi-data-width = <0x20>; + }; + axi_gpio_btn: gpio@41210000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41210000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_hdmi: gpio@41230000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + interrupt-parent = <&intc>; + interrupts = <0 29 4>; + reg = <0x41230000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x1>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_led: gpio@41200000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41200000 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x1>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_sw: gpio@41220000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41220000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_i2s_adi_0: axi_i2s_adi@43c20000 { + compatible = "xlnx,axi-i2s-adi-1.0"; + reg = <0x43c20000 0x10000>; + xlnx,bclk-pol = <0x0>; + xlnx,dma-type = <0x1>; + xlnx,has-rx = <0x1>; + xlnx,has-tx = <0x1>; + xlnx,lrclk-pol = <0x0>; + xlnx,num-ch = <0x1>; + xlnx,s-axi-min-size = <0x000001FF>; + xlnx,slot-width = <0x18>; + }; + axi_vdma_0: dma@43000000 { + #dma-cells = <1>; + compatible = "xlnx,axi-vdma-1.00.a"; + clocks = <&clkc 15>; + clock-names = "s_axi_lite_aclk"; + interrupt-parent = <&intc>; + interrupts = <0 30 4>; + reg = <0x43000000 0x10000>; + xlnx,flush-fsync = <0x1>; + xlnx,num-fstores = <0x1>; + dma-channel@43000000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupts = <0 30 4>; + xlnx,datawidth = <0x20>; + xlnx,device-id = <0x0>; + }; + }; + v_tc_0: v_tc@43c00000 { + compatible = "xlnx,v-tc-6.1"; + interrupt-parent = <&intc>; + interrupts = <0 31 4>; + reg = <0x43c00000 0x10000>; + xlnx,det-achroma-en = <0x0>; + xlnx,det-avideo-en = <0x1>; + xlnx,det-fieldid-en = <0x0>; + xlnx,det-hblank-en = <0x1>; + xlnx,det-hsync-en = <0x1>; + xlnx,det-vblank-en = <0x1>; + xlnx,det-vsync-en = <0x1>; + xlnx,detect-en = <0x0>; + xlnx,fsync-hstart0 = <0x0>; + xlnx,fsync-hstart1 = <0x0>; + xlnx,fsync-hstart10 = <0x0>; + xlnx,fsync-hstart11 = <0x0>; + xlnx,fsync-hstart12 = <0x0>; + xlnx,fsync-hstart13 = <0x0>; + xlnx,fsync-hstart14 = <0x0>; + xlnx,fsync-hstart15 = <0x0>; + xlnx,fsync-hstart2 = <0x0>; + xlnx,fsync-hstart3 = <0x0>; + xlnx,fsync-hstart4 = <0x0>; + xlnx,fsync-hstart5 = <0x0>; + xlnx,fsync-hstart6 = <0x0>; + xlnx,fsync-hstart7 = <0x0>; + xlnx,fsync-hstart8 = <0x0>; + xlnx,fsync-hstart9 = <0x0>; + xlnx,fsync-vstart0 = <0x0>; + xlnx,fsync-vstart1 = <0x0>; + xlnx,fsync-vstart10 = <0x0>; + xlnx,fsync-vstart11 = <0x0>; + xlnx,fsync-vstart12 = <0x0>; + xlnx,fsync-vstart13 = <0x0>; + xlnx,fsync-vstart14 = <0x0>; + xlnx,fsync-vstart15 = <0x0>; + xlnx,fsync-vstart2 = <0x0>; + xlnx,fsync-vstart3 = <0x0>; + xlnx,fsync-vstart4 = <0x0>; + xlnx,fsync-vstart5 = <0x0>; + xlnx,fsync-vstart6 = <0x0>; + xlnx,fsync-vstart7 = <0x0>; + xlnx,fsync-vstart8 = <0x0>; + xlnx,fsync-vstart9 = <0x0>; + xlnx,gen-achroma-en = <0x0>; + xlnx,gen-achroma-polarity = <0x1>; + xlnx,gen-auto-switch = <0x0>; + xlnx,gen-avideo-en = <0x1>; + xlnx,gen-avideo-polarity = <0x1>; + xlnx,gen-cparity = <0x0>; + xlnx,gen-f0-vblank-hend = <0x500>; + xlnx,gen-f0-vblank-hstart = <0x500>; + xlnx,gen-f0-vframe-size = <0x2ee>; + xlnx,gen-f0-vsync-hend = <0x500>; + xlnx,gen-f0-vsync-hstart = <0x500>; + xlnx,gen-f0-vsync-vend = <0x2d9>; + xlnx,gen-f0-vsync-vstart = <0x2d4>; + xlnx,gen-f1-vblank-hend = <0x500>; + xlnx,gen-f1-vblank-hstart = <0x500>; + xlnx,gen-f1-vframe-size = <0x2ee>; + xlnx,gen-f1-vsync-hend = <0x500>; + xlnx,gen-f1-vsync-hstart = <0x500>; + xlnx,gen-f1-vsync-vend = <0x2d9>; + xlnx,gen-f1-vsync-vstart = <0x2d4>; + xlnx,gen-fieldid-en = <0x0>; + xlnx,gen-fieldid-polarity = <0x1>; + xlnx,gen-hactive-size = <0x500>; + xlnx,gen-hblank-en = <0x1>; + xlnx,gen-hblank-polarity = <0x1>; + xlnx,gen-hframe-size = <0x672>; + xlnx,gen-hsync-en = <0x1>; + xlnx,gen-hsync-end = <0x596>; + xlnx,gen-hsync-polarity = <0x1>; + xlnx,gen-hsync-start = <0x56e>; + xlnx,gen-interlaced = <0x0>; + xlnx,gen-vactive-size = <0x2d0>; + xlnx,gen-vblank-en = <0x1>; + xlnx,gen-vblank-polarity = <0x1>; + xlnx,gen-video-format = <0x2>; + xlnx,gen-vsync-en = <0x1>; + xlnx,gen-vsync-polarity = <0x1>; + xlnx,generate-en = <0x1>; + xlnx,has-axi4-lite = <0x1>; + xlnx,has-intc-if = <0x0>; + xlnx,interlace-en = <0x0>; + xlnx,max-lines = <0x1000>; + xlnx,max-pixels = <0x1000>; + xlnx,num-fsyncs = <0x1>; + xlnx,sync-en = <0x0>; + }; + }; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts new file mode 100644 index 00000000..19654392 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts @@ -0,0 +1,184 @@ +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "zynq-7000.dtsi" +/include/ "zynq-7000-qspi-dummy.dtsi" +/include/ "pcw.dtsi" +/include/ "pl.dtsi" + +/ { + model = "Digilent-Zybo-Linux-BD-v2015.4"; + aliases { + serial0 = &uart1; + ethernet0 = &gem0; + spi0 = &qspi; + }; + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + btn4 { + label = "btn4"; + gpios = <&gpio0 50 0>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + btn5 { + label = "btn5"; + gpios = <&gpio0 51 0>; + linux,code = <103>; /* up */ + gpio-key,wakeup; + autorepeat; + }; + }; + + usb_phy0: usb_phy@0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 46 1>; + }; +}; + +&amba { + u-boot,dm-pre-reloc; +}; + +&amba_pl { + encoder_0: digilent_encoder { + compatible = "digilent,drm-encoder"; + dglnt,edid-i2c = <&i2c1>; + }; + + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,vtc = <&v_tc_0>; + xlnx,connector-type = "HDMIA"; + xlnx,encoder-slave = <&encoder_0>; + clocks = <&axi_dynclk_0>; + planes { + xlnx,pixel-format = "xrgb8888"; + plane0 { + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + }; + }; + }; + + i2s_clk: i2s_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + clock-output-names = "i2s_clk"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "ZYBO-Sound-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MICIN", "Microphone Jack", + "Headphone Jack", "LHPOUT", + "Headphone Jack", "RHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + dailink0_master: simple-audio-card,cpu { + clocks = <&i2s_clk>; + sound-dai = <&axi_i2s_adi_0>; + }; + simple-audio-card,codec { + clocks = <&i2s_clk>; + sound-dai = <&ssm2603>; + }; + }; +}; + +&axi_dynclk_0 { + compatible = "digilent,axi-dynclk"; + #clock-cells = <0>; + clocks = <&clkc 15>; +}; + +&axi_i2s_adi_0 { + #sound-dai-cells = <0>; + compatible = "adi,axi-i2s-1.00.a"; + clocks = <&clkc 15>, <&i2s_clk>; + clock-names = "axi", "ref"; + dmas = <&dmac_s 0 &dmac_s 1>; + dma-names = "tx", "rx"; +}; + +&gem0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + local-mac-address = []; + phy0: phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +&i2c0 { + eeprom@50 { + /* Microchip 24AA02E48 */ + compatible = "microchip,24c02"; + reg = <0x50>; + }; + + ssm2603: ssm2603@1a{ + #sound-dai-cells = <0>; + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&qspi { + #address-cells = <1>; + #size-cells = <0>; + flash0: flash@0 { + compatible = "micron,m25p80", "s25fl128s"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + partition@0x00000000 { + label = "boot"; + reg = <0x00000000 0x00300000>; + }; + partition@0x00300000 { + label = "bootenv"; + reg = <0x00300000 0x00020000>; + }; + partition@0x00320000 { + label = "kernel"; + reg = <0x00320000 0x00a80000>; + }; + partition@0x00da0000 { + label = "spare"; + reg = <0x00da0000 0x00000000>; + }; + }; +}; + +&usb0 { + usb-phy = <&usb_phy0>; +}; + +&v_tc_0 { + compatible = "xlnx,v-tc-5.01.a"; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend new file mode 100644 index 00000000..fbe42821 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend @@ -0,0 +1,4 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/platform-init:" + +COMPATIBLE_MACHINE:picozed-zynq7 = "picozed-zynq7" + diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c new file mode 100644 index 00000000..5587ab25 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c @@ -0,0 +1,13191 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h new file mode 100644 index 00000000..df5205e8 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h @@ -0,0 +1,130 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 33333336 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + + -- cgit v1.2.3-54-g00ecf From 0c19d07c7f0bc767c160c8fcce15b30601cd6d8d Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Mon, 9 May 2022 18:50:15 +0530 Subject: u-boot-xlnx.inc: stripping .dtb from BASE_DTS variable This patch will remove the .dtb from BASE_DTS as the .dtb will be added later in the python function. Signed-off-by: Varalaxmi Bingi Allow CONFIG_DTFILE to be blank. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index d152c15c..f0ea2ca3 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -19,7 +19,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/u-boot:" SYSROOT_DIRS += "/boot" -BASE_DTS ?= "${@os.path.basename(d.getVar('CONFIG_DTFILE') or "system-top")}" +BASE_DTS ?= "${@os.path.basename(d.getVar('CONFIG_DTFILE') or '').rstrip('.dtb') or 'system-top'}" DTB_PATH ?= "/boot/devicetree/" DTB_NAME ?= "" -- cgit v1.2.3-54-g00ecf From 2848271f22a77abd2086fa4438886f885a75e1ef Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Tue, 10 May 2022 18:33:08 +0530 Subject: libdfx: Update bb file to align with libdfx CMake changes. This patch updates bb file to align with libdfx latest CMake changes. Signed-off-by: Nava kishore Manne Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb index 322e0dab..97ab5954 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb @@ -8,7 +8,7 @@ BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -SRCREV = "fb8fe48d6ce4a3bb99a6c3d9f17921cecdfe95fc" +SRCREV = "f3c30294b96544081a64b054d4bc3db4ab8202b7" COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynqmp = "zynqmp" @@ -28,7 +28,3 @@ do_install () { install -m 0755 ${B}/apps/dfx_app ${D}${bindir} } -SOLIBSDEV = ".so" -FILES:${PN} += "${libdir}/libdfx.so ${bindir}/*" -FILES:${PN}-staticdev = "${libdir}/libdfx.a" -FILES:${PN}-dev = "${includedir}" -- cgit v1.2.3-54-g00ecf From ece00a76504abe8c90ed32ab5d6dbdcc2ceaf2d0 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 10 May 2022 09:44:30 -0600 Subject: meta-xilinx: Move booting README from bsp layer Move README.booting.md file from meta-xilinx-bsp layer to meta-xilinx. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- README.booting.md | 266 ++++++++++++++++++++++++++++++++++++++ meta-xilinx-bsp/README.booting.md | 266 -------------------------------------- 2 files changed, 266 insertions(+), 266 deletions(-) create mode 100644 README.booting.md delete mode 100644 meta-xilinx-bsp/README.booting.md diff --git a/README.booting.md b/README.booting.md new file mode 100644 index 00000000..dc48f6b2 --- /dev/null +++ b/README.booting.md @@ -0,0 +1,266 @@ +Booting meta-xilinx boards +========================== + +Contents +-------- + +* [Loading via JTAG](#loading-via-jtag) + * [XSDB](#xsdb) + * [Load Bitstream](#load-bitstream) + * [Load U-Boot (MicroBlaze)](#load-u-boot-microblaze) + * [Load U-Boot (Zynq)](#load-u-boot-zynq) + * [U-Boot Console](#u-boot-console) + * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree) + * [Booting via U-Boot](#booting-via-u-boot) +* [Loading via SD](#loading-via-sd) + * [Preparing SD/MMC](#preparing-sdmmc) + * [Installing U-Boot](#installing-u-boot) + * [Installing Kernel and Device Tree](#installing-kernel-and-device-tree) + * [Installing Root Filesystem](#installing-root-filesystem) + * [U-Boot Configuration File](#u-boot-configuration-file) + * [Booting](#booting) +* [Loading via TFTP](#loading-via-tftp) + * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree-1) + * [Booting via U-Boot](#booting-via-u-boot-1) + + +Loading via JTAG +---------------- +This boot flow requires the use of the Xilinx tools, specifically XSDB and the +associated JTAG device drivers. This also requires access to the JTAG interface +on the board, a number of Xilinx and third-party boards come with on-board JTAG +modules. + +### XSDB +Start `xsdb` and connect. Ensure that the target chip is visible. + + $ xsdb + xsdb% connect + xsdb% targets + +### Load Bitstream +**(Note: This step is only required for platforms which have a bitstream e.g. +MicroBlaze.)** + +Download the bitstream for the system using XSDB with the `fpga -f` command. If +a bitstream is available from meta-xilinx is will be located in the +`deploy/images//` directory. + + xsdb% fpga -f download.bit + +### Load U-Boot (MicroBlaze) +Download `u-boot.elf` to the target CPU via the use of XSDB. + + xsdb% targets -set -filter {name =~ "MicroBlaze*"} + xsdb% rst + xsdb% dow u-boot.elf + xsdb% con + +### Load U-Boot (Zynq) +Ensure the board is configured to boot from JTAG. The Zynq platform requires the +loading of SPL first, this can be done by loading the `u-boot-spl.bin` and +executing it at location `0x0`. `u-boot-spl.bin` is not output to the deploy +directory by default, it can be obtained from the work directory for U-Boot +(`git/spl/u-boot-spl.bin`) or can be extracted from `boot.bin` using +`dd if=boot.bin of=u-boot-spl.bin bs=1 skip=2240`. + + xsdb% targets -set -filter {name =~ "ARM*#0"} + xsdb% dow -data u-boot-spl.bin 0x0 + xsdb% rwr pc 0x0 + xsdb% con + +On the UART console the following should appear, indicating SPL was loaded. + + U-Boot SPL 2016.01 + Trying to boot from unknown boot device + SPL: Unsupported Boot Device! + SPL: failed to boot from all boot devices + ### ERROR ### Please RESET the board ### + +Once SPL has loaded U-Boot can now be loaded into memory and executed. Download +`u-boot.elf` to the target. + + xsdb% stop + xsdb% dow u-boot.elf + xsdb% con + +### U-Boot Console +U-Boot will load and the console will be available on the UART interface. + + ... + Hit any key to stop autoboot: 0 + U-Boot> + +### Kernel, Root Filesystem and Device Tree +Whilst it is possible to load the images via JTAG this connection is slow and +this process can take a long time to execute (more than 10 minutes). If your +system has ethernet it is recommended that you use TFTP to load these images +using U-Boot. + +Once U-Boot has been loaded, pause the execution using XSDB and use the `dow` +command to load the images into the targets memory. Once the images are loaded +continue the execution and return to the U-Boot console. + +MicroBlaze (kc705-microblazeel): + + xsdb% stop + xsdb% dow -data linux.bin.ub 0x85000000 + xsdb% dow -data core-image-minimal-kc705-microblazeel.cpio.gz.u-boot 0x86000000 + xsdb% dow -data kc705-microblazeel.dtb 0x84000000 + xsdb% con + +Zynq: + + xsdb% stop + xsdb% dow -data uImage 0x2000000 + xsdb% dow -data core-image-minimal-.cpio.gz.u-boot 0x3000000 + xsdb% dow -data .dtb 0x2A00000 + xsdb% con + +### Booting via U-Boot +At the U-Boot console use the `bootm` command to execute the kernel. + +MicroBlaze (kc705-microblazeel): + + U-Boot> bootm 0x85000000 0x86000000 0x84000000 + +Zynq: + + U-Boot> bootm 0x2000000 0x3000000 0x2A00000 + + +Loading via SD +--------------------- +**(Note: This section only applies to Zynq and ZynqMP.)** + +### Preparing SD/MMC +Setup the card with the first partition formatted as FAT16. If you intend to +boot with the root filesystem located on the SD card, also create a second +partition formatted as EXT4. + +It is recommended that the first partition be at least 64MB in size, however +this value will depend on whether using a ramdisk for the root filesystem and +how large the ramdisk is. + +This section describes how to manually prepare and populate an SD card image. +There are automation tools in OpenEmbedded that can generate disk images already +formatted and prepared such that they can be written directly to a disk. Refer +to the Yocto Project Development Manual for more details: + http://www.yoctoproject.org/docs/current/dev-manual/dev-manual.html#creating-partitioned-images + +### Installing U-Boot (Zynq) +Add the following files to the first partition: + +* `boot.bin` +* `u-boot.img` + +### Installing U-Boot (ZynqMP) +Add the following files to the first partition: + +* `boot.bin` +* `u-boot.bin` + +### Installing Kernel and Device Tree (Zynq) +Add the following files to the first partition: + +* `uImage` +* `.dtb` + +### Installing Kernel and Device Tree (ZynqMP) +Add the following files to the first partition: + +* `Image` +* `.dtb` + +### Install ARM Trusted Firmware (ZynqMP) +Add the following file to the first partition: + + * `atf-uboot.ub` + +### Install U-boot environment file (ZynqMP) +Add the following file to the first partition: + + * `uEnv.txt` + +### Installing Root Filesystem +If using a ramdisk also add the `.cpio.gz.u-boot` type of root filesystem image +to the first partition. + +* `core-image-minimal-.cpio.gz.u-boot` + +If using the SD card as the root filesystem, populate the second partition with +the content of the root filesystem. To install the root filesystem extract the +corresponding tarball into the root of the second partition (the following +command assumes that the second partition is mounted at /media/root). + + tar x -C /media/root -f core-image-minimal-.tar.gz + +### U-Boot Configuration File +Also create the file `uEnv.txt` on the first partition of the SD card partition, +with the following contents. Replacing the names of files where appropriate. + + kernel_image=uImage + devicetree_image=.dtb + +If using a ramdisk root filesystem setup the `ramdisk_image` variable. + + ramdisk_image=core-image-minimal-.cpio.gz.u-boot + +If using the SD card as the root filesystem setup the kernel boot args, and +`uenvcmd` variable. + + bootargs=root=/dev/mmcblk0p2 rw rootwait + uenvcmd=fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && bootm 0x3000000 - 0x2A00000 + +### Booting +Insert the SD card and connect UART to a terminal program and power on the +board. (For boards that have configurable boot jumper/switches ensure the board +is configured for SD). + +Initially U-Boot SPL will load, which will in turn load U-Boot. U-Boot will use +the `uEnv.txt` to automatically load and execute the kernel. + + +Loading via TFTP +---------------- +**(Note: This boot flow requires ethernet on the baord and a TFTP server)** + +Boot your system into U-Boot, using one of boot methods (e.g. JTAG, SD, QSPI). + +### Kernel, Root Filesystem and Device Tree +Place the following images into the root of the TFTP server directory: + +* `core-image-minimal-.cpio.gz.u-boot` +* `uImage` (Zynq) or `linux.bin.ub` (MicroBlaze) +* `.dtb` + +### Booting via U-Boot +The serial console of the target board will display the U-Boot console. +Configure the `ipaddr` and `serverip` of the U-Boot environment. + + U-Boot> set serverip + U-Boot> set ipaddr + +Using the U-Boot console; load the Kernel, root filesystem and the DTB into +memory. And then boot Linux using the `bootm` command. (Note the load addresses +will be dependant on machine used) + +MicroBlaze (kc705-microblazeel): + + U-Boot> tftpboot 0x85000000 linux.bin.ub + U-Boot> tftpboot 0x86000000 core-image-minimal-kc705-microblazeel.cpio.gz.u-boot + U-Boot> tftpboot 0x84000000 kc705-microblazeel.dtb + U-Boot> bootm 0x85000000 0x86000000 0x84000000 + +Zynq: + + U-Boot> tftpboot 0x2000000 uImage + U-Boot> tftpboot 0x3000000 core-image-minimal-.cpio.gz.u-boot + U-Boot> tftpboot 0x2A00000 .dtb + U-Boot> bootm 0x2000000 0x3000000 0x2A00000 + +U-Boot will prepare the Kernel for boot and then it will being to execute. + + ... + Starting kernel... + diff --git a/meta-xilinx-bsp/README.booting.md b/meta-xilinx-bsp/README.booting.md deleted file mode 100644 index dc48f6b2..00000000 --- a/meta-xilinx-bsp/README.booting.md +++ /dev/null @@ -1,266 +0,0 @@ -Booting meta-xilinx boards -========================== - -Contents --------- - -* [Loading via JTAG](#loading-via-jtag) - * [XSDB](#xsdb) - * [Load Bitstream](#load-bitstream) - * [Load U-Boot (MicroBlaze)](#load-u-boot-microblaze) - * [Load U-Boot (Zynq)](#load-u-boot-zynq) - * [U-Boot Console](#u-boot-console) - * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree) - * [Booting via U-Boot](#booting-via-u-boot) -* [Loading via SD](#loading-via-sd) - * [Preparing SD/MMC](#preparing-sdmmc) - * [Installing U-Boot](#installing-u-boot) - * [Installing Kernel and Device Tree](#installing-kernel-and-device-tree) - * [Installing Root Filesystem](#installing-root-filesystem) - * [U-Boot Configuration File](#u-boot-configuration-file) - * [Booting](#booting) -* [Loading via TFTP](#loading-via-tftp) - * [Kernel, Root Filesystem and Device Tree](#kernel-root-filesystem-and-device-tree-1) - * [Booting via U-Boot](#booting-via-u-boot-1) - - -Loading via JTAG ----------------- -This boot flow requires the use of the Xilinx tools, specifically XSDB and the -associated JTAG device drivers. This also requires access to the JTAG interface -on the board, a number of Xilinx and third-party boards come with on-board JTAG -modules. - -### XSDB -Start `xsdb` and connect. Ensure that the target chip is visible. - - $ xsdb - xsdb% connect - xsdb% targets - -### Load Bitstream -**(Note: This step is only required for platforms which have a bitstream e.g. -MicroBlaze.)** - -Download the bitstream for the system using XSDB with the `fpga -f` command. If -a bitstream is available from meta-xilinx is will be located in the -`deploy/images//` directory. - - xsdb% fpga -f download.bit - -### Load U-Boot (MicroBlaze) -Download `u-boot.elf` to the target CPU via the use of XSDB. - - xsdb% targets -set -filter {name =~ "MicroBlaze*"} - xsdb% rst - xsdb% dow u-boot.elf - xsdb% con - -### Load U-Boot (Zynq) -Ensure the board is configured to boot from JTAG. The Zynq platform requires the -loading of SPL first, this can be done by loading the `u-boot-spl.bin` and -executing it at location `0x0`. `u-boot-spl.bin` is not output to the deploy -directory by default, it can be obtained from the work directory for U-Boot -(`git/spl/u-boot-spl.bin`) or can be extracted from `boot.bin` using -`dd if=boot.bin of=u-boot-spl.bin bs=1 skip=2240`. - - xsdb% targets -set -filter {name =~ "ARM*#0"} - xsdb% dow -data u-boot-spl.bin 0x0 - xsdb% rwr pc 0x0 - xsdb% con - -On the UART console the following should appear, indicating SPL was loaded. - - U-Boot SPL 2016.01 - Trying to boot from unknown boot device - SPL: Unsupported Boot Device! - SPL: failed to boot from all boot devices - ### ERROR ### Please RESET the board ### - -Once SPL has loaded U-Boot can now be loaded into memory and executed. Download -`u-boot.elf` to the target. - - xsdb% stop - xsdb% dow u-boot.elf - xsdb% con - -### U-Boot Console -U-Boot will load and the console will be available on the UART interface. - - ... - Hit any key to stop autoboot: 0 - U-Boot> - -### Kernel, Root Filesystem and Device Tree -Whilst it is possible to load the images via JTAG this connection is slow and -this process can take a long time to execute (more than 10 minutes). If your -system has ethernet it is recommended that you use TFTP to load these images -using U-Boot. - -Once U-Boot has been loaded, pause the execution using XSDB and use the `dow` -command to load the images into the targets memory. Once the images are loaded -continue the execution and return to the U-Boot console. - -MicroBlaze (kc705-microblazeel): - - xsdb% stop - xsdb% dow -data linux.bin.ub 0x85000000 - xsdb% dow -data core-image-minimal-kc705-microblazeel.cpio.gz.u-boot 0x86000000 - xsdb% dow -data kc705-microblazeel.dtb 0x84000000 - xsdb% con - -Zynq: - - xsdb% stop - xsdb% dow -data uImage 0x2000000 - xsdb% dow -data core-image-minimal-.cpio.gz.u-boot 0x3000000 - xsdb% dow -data .dtb 0x2A00000 - xsdb% con - -### Booting via U-Boot -At the U-Boot console use the `bootm` command to execute the kernel. - -MicroBlaze (kc705-microblazeel): - - U-Boot> bootm 0x85000000 0x86000000 0x84000000 - -Zynq: - - U-Boot> bootm 0x2000000 0x3000000 0x2A00000 - - -Loading via SD ---------------------- -**(Note: This section only applies to Zynq and ZynqMP.)** - -### Preparing SD/MMC -Setup the card with the first partition formatted as FAT16. If you intend to -boot with the root filesystem located on the SD card, also create a second -partition formatted as EXT4. - -It is recommended that the first partition be at least 64MB in size, however -this value will depend on whether using a ramdisk for the root filesystem and -how large the ramdisk is. - -This section describes how to manually prepare and populate an SD card image. -There are automation tools in OpenEmbedded that can generate disk images already -formatted and prepared such that they can be written directly to a disk. Refer -to the Yocto Project Development Manual for more details: - http://www.yoctoproject.org/docs/current/dev-manual/dev-manual.html#creating-partitioned-images - -### Installing U-Boot (Zynq) -Add the following files to the first partition: - -* `boot.bin` -* `u-boot.img` - -### Installing U-Boot (ZynqMP) -Add the following files to the first partition: - -* `boot.bin` -* `u-boot.bin` - -### Installing Kernel and Device Tree (Zynq) -Add the following files to the first partition: - -* `uImage` -* `.dtb` - -### Installing Kernel and Device Tree (ZynqMP) -Add the following files to the first partition: - -* `Image` -* `.dtb` - -### Install ARM Trusted Firmware (ZynqMP) -Add the following file to the first partition: - - * `atf-uboot.ub` - -### Install U-boot environment file (ZynqMP) -Add the following file to the first partition: - - * `uEnv.txt` - -### Installing Root Filesystem -If using a ramdisk also add the `.cpio.gz.u-boot` type of root filesystem image -to the first partition. - -* `core-image-minimal-.cpio.gz.u-boot` - -If using the SD card as the root filesystem, populate the second partition with -the content of the root filesystem. To install the root filesystem extract the -corresponding tarball into the root of the second partition (the following -command assumes that the second partition is mounted at /media/root). - - tar x -C /media/root -f core-image-minimal-.tar.gz - -### U-Boot Configuration File -Also create the file `uEnv.txt` on the first partition of the SD card partition, -with the following contents. Replacing the names of files where appropriate. - - kernel_image=uImage - devicetree_image=.dtb - -If using a ramdisk root filesystem setup the `ramdisk_image` variable. - - ramdisk_image=core-image-minimal-.cpio.gz.u-boot - -If using the SD card as the root filesystem setup the kernel boot args, and -`uenvcmd` variable. - - bootargs=root=/dev/mmcblk0p2 rw rootwait - uenvcmd=fatload mmc 0 0x3000000 ${kernel_image} && fatload mmc 0 0x2A00000 ${devicetree_image} && bootm 0x3000000 - 0x2A00000 - -### Booting -Insert the SD card and connect UART to a terminal program and power on the -board. (For boards that have configurable boot jumper/switches ensure the board -is configured for SD). - -Initially U-Boot SPL will load, which will in turn load U-Boot. U-Boot will use -the `uEnv.txt` to automatically load and execute the kernel. - - -Loading via TFTP ----------------- -**(Note: This boot flow requires ethernet on the baord and a TFTP server)** - -Boot your system into U-Boot, using one of boot methods (e.g. JTAG, SD, QSPI). - -### Kernel, Root Filesystem and Device Tree -Place the following images into the root of the TFTP server directory: - -* `core-image-minimal-.cpio.gz.u-boot` -* `uImage` (Zynq) or `linux.bin.ub` (MicroBlaze) -* `.dtb` - -### Booting via U-Boot -The serial console of the target board will display the U-Boot console. -Configure the `ipaddr` and `serverip` of the U-Boot environment. - - U-Boot> set serverip - U-Boot> set ipaddr - -Using the U-Boot console; load the Kernel, root filesystem and the DTB into -memory. And then boot Linux using the `bootm` command. (Note the load addresses -will be dependant on machine used) - -MicroBlaze (kc705-microblazeel): - - U-Boot> tftpboot 0x85000000 linux.bin.ub - U-Boot> tftpboot 0x86000000 core-image-minimal-kc705-microblazeel.cpio.gz.u-boot - U-Boot> tftpboot 0x84000000 kc705-microblazeel.dtb - U-Boot> bootm 0x85000000 0x86000000 0x84000000 - -Zynq: - - U-Boot> tftpboot 0x2000000 uImage - U-Boot> tftpboot 0x3000000 core-image-minimal-.cpio.gz.u-boot - U-Boot> tftpboot 0x2A00000 .dtb - U-Boot> bootm 0x2000000 0x3000000 0x2A00000 - -U-Boot will prepare the Kernel for boot and then it will being to execute. - - ... - Starting kernel... - -- cgit v1.2.3-54-g00ecf From f1040cc8ec9d7463eec7efd5b0f4a503c2dade96 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 11 May 2022 12:17:55 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 30c3bcd6..37badabb 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "a40ff93a4d77f90815d15be2bfbce525f66eb9ac" +SRCREV = "2cac76919acd30eaaefa733f33036c176e928ed6" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From b977710c7c8c816482ba7ba600ccccf99130d90c Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 12 May 2022 12:47:28 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 37badabb..6c09a5b4 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "2cac76919acd30eaaefa733f33036c176e928ed6" +SRCREV = "edabd0ef3652a60cd510f556015c57310c3b9364" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 57df688a..cc4b4b53 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "524b5ea09359cb000d332873d609654704be4a8c" +ESW_REV[2022.2] = "7e69a420489185a98e5bbfeb1f2d4783248adb4e" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From ce70cc1055c32d4ea22a6386d84cbc4bb0cdc39f Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 10 May 2022 19:00:56 -0700 Subject: qemu-xilinx: Disable dynamic git fetch during build All fetching must happen in the do_fetch operation. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 8433fc04..9e95ea54 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -35,7 +35,6 @@ PACKAGECONFIG[sdl] = "--enable-sdl,--disable-sdl,libsdl2" PACKAGECONFIG[pie] = "--enable-pie,--disable-pie,," DISABLE_STATIC:pn-${PN} = "" -EXTRA_OECONF:remove = " --with-git=/bin/false --with-git-submodules=ignore" PTEST_ENABLED = "" -- cgit v1.2.3-54-g00ecf From 1fde19c83b1f618c231019f9a9327acf6e52b4ac Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Wed, 11 May 2022 15:49:26 +0530 Subject: u-boot-zynq-uenv: Use devnum instead sdbootdev Use the devnum uboot env variable to detect and read the images from mmc. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb index 4e02cb40..861479b2 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb @@ -25,7 +25,7 @@ def uboot_boot_cmd(d): def get_sdbootdev(d): if d.getVar("SOC_FAMILY") in ["zynqmp"]: - return "${sdbootdev}" + return "${devnum}" else: return "0" @@ -69,7 +69,7 @@ def uenv_populate(d): # bootargs, default to booting with the rootfs device being partition 2 KERNEL_BOOTARGS:zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait" -KERNEL_BOOTARGS:zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${sdbootdev}p2 rw rootwait" +KERNEL_BOOTARGS:zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${devnum}p2 rw rootwait" KERNEL_LOAD_ADDRESS:zynq = "0x2080000" KERNEL_LOAD_ADDRESS:zynqmp = "0x200000" -- cgit v1.2.3-54-g00ecf From f6daf7deef2c9f5cd97a2fe68f5507594e0ad7f8 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Wed, 11 May 2022 16:21:59 +0530 Subject: u-boot-zynq-scr: Update the image offsets as per petalinux Update the image offsets/sizes as per the petalinux 2022.2 changes. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-zynq-scr.bb | 34 +++++++++++++--------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb index 766b2b81..667472a1 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb @@ -16,11 +16,11 @@ COMPATIBLE_MACHINE:microblaze = "microblaze" KERNELDT = "${@os.path.basename(d.getVar('KERNEL_DEVICETREE').split(' ')[0]) if d.getVar('KERNEL_DEVICETREE') else ''}" DEVICE_TREE_NAME ?= "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', d.getVar('KERNELDT'), d)}" -#Need to copy a rootfs.cpio.gz.u-boot as uramdisk.image.gz into boot partition -RAMDISK_IMAGE ?= "" -RAMDISK_IMAGE:zynq ?= "uramdisk.image.gz" +#Need to copy a rootfs.cpio.gz.u-boot into boot partition +RAMDISK_IMAGE ?= "rootfs.cpio.gz.u-boot" +RAMDISK_IMAGE1 ?= "ramdisk.cpio.gz.u-boot" -PXERAMDISK_IMAGE ?= "${@'ramdisk.cpio.gz.u-boot' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}" +PXERAMDISK_IMAGE ?= "${'@${RAMDISK_IMAGE1}' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}" KERNEL_BOOTCMD:zynqmp ?= "booti" KERNEL_BOOTCMD:zynq ?= "bootm" @@ -67,14 +67,14 @@ DEVICETREE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('DEVICETREE_OFFSET'))}" DEVICETREE_OFFSET:microblaze ?= "0x1e00000" DEVICETREE_OFFSET:zynqmp ?= "0x100000" -DEVICETREE_OFFSET:zynq ?= "0x2000000" +DEVICETREE_OFFSET:zynq ?= "0x100000" DEVICETREE_OFFSET:versal ?= "0x1000" KERNEL_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('KERNEL_OFFSET'))}" KERNEL_OFFSET:microblaze ?= "0x0" KERNEL_OFFSET:zynqmp ?= "0x200000" -KERNEL_OFFSET:zynq ?= "0x2080000" +KERNEL_OFFSET:zynq ?= "0x200000" KERNEL_OFFSET:versal ?= "0x200000" KERNEL_IMAGE ?= "${KERNEL_IMAGETYPE}" @@ -84,7 +84,7 @@ RAMDISK_IMAGE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('RAMDISK_OFFSET'))}" RAMDISK_OFFSET:microblaze ?= "0x2e00000" RAMDISK_OFFSET:zynq ?= "0x4000000" RAMDISK_OFFSET:zynqmp ?= "0x4000000" -RAMDISK_OFFSET:versal ?= "0x6000000" +RAMDISK_OFFSET:versal ?= "0x4000000" FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('FIT_IMAGE_OFFSET'))}" FIT_IMAGE_OFFSET ?= "0x10000000" @@ -96,17 +96,18 @@ FIT_IMAGE ?= "image.ub" QSPI_KERNEL_OFFSET:microblaze ?= "0xBC0000" QSPI_KERNEL_SIZE:microblaze ?= "0x500000" QSPI_RAMDISK_SIZE:microblaze ?= "0xA00000" +QSPI_RAMDISK_SIZE:microblaze ?= "0x4000000" ## For zynq ## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory -QSPI_KERNEL_OFFSET:zynq ?= "0x1000000" -QSPI_RAMDISK_OFFSET:zynq ?= "0x1580000" +QSPI_KERNEL_OFFSET:zynq ?= "0xA00000" +QSPI_RAMDISK_OFFSET:zynq ?= "0x1000000" NAND_KERNEL_OFFSET:zynq ?= "0x1000000" NAND_RAMDISK_OFFSET:zynq ?= "0x4600000" -QSPI_KERNEL_SIZE:zynq ?= "0x500000" -QSPI_RAMDISK_SIZE:zynq ?= "0xA00000" +QSPI_KERNEL_SIZE:zynq ?= "0x600000" +QSPI_RAMDISK_SIZE:zynq ?= "0xF80000" NAND_KERNEL_SIZE ?= "0x3200000" NAND_RAMDISK_SIZE ?= "0x3200000" @@ -144,13 +145,18 @@ QSPI_KERNEL_IMAGE:versal ?= "image.ub" NAND_KERNEL_IMAGE ?= "image.ub" -QSPI_FIT_IMAGE_OFFSET ?= "0x1080000" +QSPI_FIT_IMAGE_OFFSET ?= "0xF40000" +QSPI_FIT_IMAGE_OFFSET:zynqmpdr ?= "0x3F80000" +QSPI_FIT_IMAGE_OFFSET:zynq ?= "0xA80000" +QSPI_FIT_IMAGE_OFFSET:microblaze ?= "0xC00000" + QSPI_FIT_IMAGE_SIZE ?= "0x6400000" QSPI_FIT_IMAGE_SIZE:zynqmpdr ?= "0x3F00000" -QSPI_FIT_IMAGE_SIZE:zynq ?= "0xF00000" +QSPI_FIT_IMAGE_SIZE:zynq ?= "0x1500000" QSPI_FIT_IMAGE_SIZE:microblaze ?= "0xF00000" -NAND_FIT_IMAGE_OFFSET ?= "0x1080000" +NAND_FIT_IMAGE_OFFSET ?= "0x4180000" +NAND_FIT_IMAGE_OFFSET:zynq ?= "0x1080000" NAND_FIT_IMAGE_SIZE ?= "0x6400000" SDBOOTDEV ?= "0" -- cgit v1.2.3-54-g00ecf From 94ad99a23b802ec80418760bab82516a0639bb70 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Wed, 11 May 2022 16:28:59 +0530 Subject: u-boot-zynq-scr.bb: Use the boot.cmd.generic for boot.scr Using specific arch bootcmd script works only for SD bootmode. This patch will allow yocto flow to use the boot.cmd.generic script to generate the boot.scr which will support for jtag/sd/usb/qspi/ospi/nand which already used by petalinux. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb index 667472a1..e72a84ce 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb @@ -27,8 +27,8 @@ KERNEL_BOOTCMD:zynq ?= "bootm" KERNEL_BOOTCMD:versal ?= "booti" KERNEL_BOOTCMD:microblaze ?= "bootm" -BOOTMODE ?= "sd" -BOOTFILE_EXT ?= ".${SOC_FAMILY}" +BOOTMODE ?= "generic" +BOOTFILE_EXT ?= "" #Make this value to "1" to skip appending base address to ddr offsets. SKIP_APPEND_BASEADDR ?= "0" -- cgit v1.2.3-54-g00ecf From 837b491486bc1e73b619354a19db371bcbb46046 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 11 May 2022 16:33:10 -0700 Subject: linux-xlnx: Update SRCREV and Version to 5.15.36 Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 3f22e4da..c0aea4b2 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ -LINUX_VERSION = "5.15.19" +LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "63ddb06d5da5f9804b96213b697283dee17f42dd" +SRCREV = "9ef3be1de28ec61f4dad2b16b1097b7e2270a5a6" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 6746bd5872a28d306073ad70d75a00d6c6fcf927 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 13 May 2022 13:21:16 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 6c09a5b4..7af4e3c5 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "edabd0ef3652a60cd510f556015c57310c3b9364" +SRCREV = "3b1903c9fc1fa4b0efae8446e5a2edbcfec2b8b9" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index cc4b4b53..1943eb86 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "7e69a420489185a98e5bbfeb1f2d4783248adb4e" +ESW_REV[2022.2] = "261262fbd03f398122d6df54103de79532d82e1a" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 3bdfe70e44ffe25e04f520780c4a7a82ece3dbce Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 17 May 2022 13:01:46 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 7af4e3c5..34466e88 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "3b1903c9fc1fa4b0efae8446e5a2edbcfec2b8b9" +SRCREV = "7bff6a148353c019adbca1540ef5fff634e62394" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From a64ff0bf015adcefbe691a94ac3e8ecf1a2ba911 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Mon, 16 May 2022 21:03:24 +0530 Subject: libdfx: Remove custom do_install() task A top-level Makefile and install rules have been added in the libdfx repo. This makes the custom do_install() task obsolete. So this patch removes the do_install() from libdfx bb file. Signed-off-by: Nava kishore Manne Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb index 97ab5954..a0102fe9 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb @@ -8,7 +8,7 @@ BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -SRCREV = "f3c30294b96544081a64b054d4bc3db4ab8202b7" +SRCREV = "1a1454ed0c3a56912250182f591c051f355fbf47" COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynqmp = "zynqmp" @@ -18,13 +18,3 @@ S = "${WORKDIR}/git" inherit cmake -do_install () { - install -d ${D}${libdir} - install -d ${D}${includedir} - install -d ${D}${bindir} - oe_libinstall -so -C ${B}/src/ libdfx ${D}${libdir} - install -m 0644 ${B}/src/libdfx.a ${D}${libdir} - install -m 0644 ${B}/include/libdfx.h ${D}${includedir} - install -m 0755 ${B}/apps/dfx_app ${D}${bindir} -} - -- cgit v1.2.3-54-g00ecf From 59761067f3c5a7127a61fb50fcbad370988808b8 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 18 May 2022 12:17:50 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c0aea4b2..70b50325 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "9ef3be1de28ec61f4dad2b16b1097b7e2270a5a6" +SRCREV = "8894e1e9f60dbe6585907cf5fd49eebefbf53837" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From b89b140da4be6e8b29d168d5c54e36aed97f12d5 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 19 May 2022 12:26:11 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index b4f14f94..269974a5 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "08ec8ac394f36932c9c349430a8ffe5ae08b7803" +SRCREV ?= "247e9edbd9c491d78dd41ee3c85ea38a309c0f67" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 9e95ea54..07104a0e 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "8f4f82ff21242926b6acc597a06d27d55d6779de" +SRCREV = "63e8a6dadee6fdc4e117ee12c29ff6f4c5c77027" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 70b50325..a69ef80b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "8894e1e9f60dbe6585907cf5fd49eebefbf53837" +SRCREV = "a9ff6d0b21c8b2928d29ede9f74e1249fc953d44" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 7aa883ed005d8152b3399b25fa4b2468548433b4 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 20 May 2022 13:31:24 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 1943eb86..4294c595 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "261262fbd03f398122d6df54103de79532d82e1a" +ESW_REV[2022.2] = "01d1e75ad57a172bf1077cc38b33ebba178b16ec" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 8f183fb7cc81c3dc3481ff1757957b7d72930fcd Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 18 May 2022 11:16:49 -0700 Subject: u-boot-xlnx: Move all u-boot FIT image (blob) implementation to here The implementation appeared to have been split between meta-som and meta-xilinx-core. The core implementation should be generic and in meta-xilinx-core. Specifics for the som board (or other boards) will be captured in the board specific layers. Note: This code may be moved in the future as part of a consolidation of device tree related items. Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-xlnx-blob.inc | 113 +++++++++++++++++++++ .../recipes-bsp/u-boot/u-boot-xlnx.inc | 5 +- 2 files changed, 115 insertions(+), 3 deletions(-) create mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc new file mode 100644 index 00000000..f7c2b880 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc @@ -0,0 +1,113 @@ +# U-boot fitimage/blob generator + +UBOOT_IMAGE_BLOB ?= "" +DT_BLOB_DIR ?= "${B}/arch/arm/dts/dt-blob" +UBOOT_BLOB_NAME ?= "${MACHINE}-fit-dtb${IMAGE_VERSION_SUFFIX}.blob" + +IMPORT_CC_DTBS ?= "" +CC_DTBS_DUP ?= "" + +MKIMAGE_DTBLOB_OPTS ?= "-E -B 0x8" + +# Everything is swtiched on with UBOOT_IMAGE_BLOB = '1' +inherit ${@'image-artifact-names' if d.getVar('UBOOT_IMAGE_BLOB') == "1" else ''} + +python() { + if d.getVar('UBOOT_IMAGE_BLOB') == "1": + d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') + d.appendVarFlag('do_compile', 'cleandirs', ' ${DT_BLOB_DIR}') + d.appendVar('PROVIDES', ' u-boot-xlnx-fit-blob') + d.appendVar('DEPENDS', ' u-boot-mkimage-native') +} + + +dtblob_emit_its_section() { + case $2 in + header) + cat << EOF > $1 +/dts-v1/; + +/ { + description = "DT Blob Creation"; +EOF + ;; + imagestart) + cat << EOF >> $1 + + images { +EOF + ;; + confstart) + cat << EOF >> $1 + + configurations { +EOF + ;; + sectend) + cat << EOF >> $1 + }; +EOF + ;; + fitend) + cat << EOF >> $1 +}; +EOF + ;; + esac +} + +dtblob_emit_dtb () { + dtb_csum="md5" + cat << EOF >> $1 + fdt-$2 { + description = "$(basename $3 .dtb)"; + data = /incbin/("$3"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "$dtb_csum"; + }; + }; +EOF +} + +#1.file name +#2.config node +#3.config node description +#4.DTB count +dtblob_emit_config () { + default_dtb=1 + if [ $4 -eq $default_dtb ]; then + cat << EOF >> $1 + default = "config_$4"; +EOF + fi + cat << EOF >> $1 + config_$4 { + description = "$3"; + fdt = "fdt-$2"; + }; +EOF +} + +do_install:append() { + ( + cd ${B} + + if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then + install -d ${D}/boot + install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${D}/boot + ln -sf `basename ${UBOOT_BLOB_NAME}` ${D}/boot/fit-dtb.blob + fi + ) +} + +do_deploy:prepend() { + cd ${B} + + if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then + install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${DEPLOYDIR}/ + ln -sf `basename ${UBOOT_BLOB_NAME}` ${DEPLOYDIR}/fit-dtb.blob + fi +} diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index f0ea2ca3..909dd72a 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -32,11 +32,10 @@ python __anonymous () { d.appendVarFlag('do_configure', 'depends', ' virtual/dtb:do_populate_sysroot') if d.getVar("DTB_NAME") is not None: d.setVar('DTB_NAME', d.getVar('BASE_DTS')+ '.dtb') - - if d.getVar('UBOOT_IMAGE_BLOB') == "1": - d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') } +require u-boot-xlnx-blob.inc + UBOOTELF_NODTB_IMAGE ?= "u-boot-nodtb.elf" UBOOTELF_NODTB_BINARY ?= "u-boot" do_deploy:prepend() { -- cgit v1.2.3-54-g00ecf From 58d950c0d74f6593a5ea53479dab13884dd0c03f Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 18 May 2022 12:19:09 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 8852d4ab..db37ec78 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "0c2abe78368b83e7ef122668ee7ad44a02184b25" +ESW_REV[experimental] = "e45aab92bbcfbe57f7a06aefce2ffa3d29f3cf6d" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 71339a004aad788d54b784c4b8f58af74adc11a8 Mon Sep 17 00:00:00 2001 From: rbramand Date: Wed, 18 May 2022 15:45:02 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Update license entries to match current version. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 4 ++-- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index c964d747..a8976822 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,8 +3,8 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "08f182574a2e7b3e545a81cb399b2aeff0ea913b" -PV = "202210.2.13.0" +SRCREV= "a3befd1ac0b78555ee7150a3199795ed9b49887a" +PV = "202220.2.14.0" diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index 6ba6beab..4a697bf4 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -8,8 +8,7 @@ LIC_FILES_CHKSUM = "file://../LICENSE;md5=da5408f748bce8a9851dac18e66f4bcf \ file://runtime_src/core/edge/drm/zocl/LICENSE;md5=7d040f51aae6ac6208de74e88a3795f8 \ file://runtime_src/core/pcie/driver/linux/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ - file://runtime_src/core/pcie/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 \ - file://runtime_src/core/edge/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 " + file://runtime_src/core/tools/xbutil2/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 " S = "${WORKDIR}/git/src" -- cgit v1.2.3-54-g00ecf From 01f30a353aa0f369f35a8432d6a747b5432772b8 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 23 May 2022 14:32:36 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 4294c595..9d83ade6 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "01d1e75ad57a172bf1077cc38b33ebba178b16ec" +ESW_REV[2022.2] = "ed7850419526ae4031ea3d9eca2f3f4c3440b07f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 0f12dfc11fc95b4353afce5d14f7e40fc4f417bf Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 23 May 2022 08:13:16 -0700 Subject: Revert "u-boot-xlnx: Move all u-boot FIT image (blob) implementation to here" This reverts commit ca1bb9a66c01463565b8dfac043c9b854d67114d. Patch missed the do_blob_generate function Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-xlnx-blob.inc | 113 --------------------- .../recipes-bsp/u-boot/u-boot-xlnx.inc | 5 +- 2 files changed, 3 insertions(+), 115 deletions(-) delete mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc deleted file mode 100644 index f7c2b880..00000000 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc +++ /dev/null @@ -1,113 +0,0 @@ -# U-boot fitimage/blob generator - -UBOOT_IMAGE_BLOB ?= "" -DT_BLOB_DIR ?= "${B}/arch/arm/dts/dt-blob" -UBOOT_BLOB_NAME ?= "${MACHINE}-fit-dtb${IMAGE_VERSION_SUFFIX}.blob" - -IMPORT_CC_DTBS ?= "" -CC_DTBS_DUP ?= "" - -MKIMAGE_DTBLOB_OPTS ?= "-E -B 0x8" - -# Everything is swtiched on with UBOOT_IMAGE_BLOB = '1' -inherit ${@'image-artifact-names' if d.getVar('UBOOT_IMAGE_BLOB') == "1" else ''} - -python() { - if d.getVar('UBOOT_IMAGE_BLOB') == "1": - d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') - d.appendVarFlag('do_compile', 'cleandirs', ' ${DT_BLOB_DIR}') - d.appendVar('PROVIDES', ' u-boot-xlnx-fit-blob') - d.appendVar('DEPENDS', ' u-boot-mkimage-native') -} - - -dtblob_emit_its_section() { - case $2 in - header) - cat << EOF > $1 -/dts-v1/; - -/ { - description = "DT Blob Creation"; -EOF - ;; - imagestart) - cat << EOF >> $1 - - images { -EOF - ;; - confstart) - cat << EOF >> $1 - - configurations { -EOF - ;; - sectend) - cat << EOF >> $1 - }; -EOF - ;; - fitend) - cat << EOF >> $1 -}; -EOF - ;; - esac -} - -dtblob_emit_dtb () { - dtb_csum="md5" - cat << EOF >> $1 - fdt-$2 { - description = "$(basename $3 .dtb)"; - data = /incbin/("$3"); - type = "flat_dt"; - arch = "arm64"; - compression = "none"; - hash-1 { - algo = "$dtb_csum"; - }; - }; -EOF -} - -#1.file name -#2.config node -#3.config node description -#4.DTB count -dtblob_emit_config () { - default_dtb=1 - if [ $4 -eq $default_dtb ]; then - cat << EOF >> $1 - default = "config_$4"; -EOF - fi - cat << EOF >> $1 - config_$4 { - description = "$3"; - fdt = "fdt-$2"; - }; -EOF -} - -do_install:append() { - ( - cd ${B} - - if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then - install -d ${D}/boot - install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${D}/boot - ln -sf `basename ${UBOOT_BLOB_NAME}` ${D}/boot/fit-dtb.blob - fi - ) -} - -do_deploy:prepend() { - cd ${B} - - if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then - install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${DEPLOYDIR}/ - ln -sf `basename ${UBOOT_BLOB_NAME}` ${DEPLOYDIR}/fit-dtb.blob - fi -} diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index 909dd72a..f0ea2ca3 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -32,9 +32,10 @@ python __anonymous () { d.appendVarFlag('do_configure', 'depends', ' virtual/dtb:do_populate_sysroot') if d.getVar("DTB_NAME") is not None: d.setVar('DTB_NAME', d.getVar('BASE_DTS')+ '.dtb') -} -require u-boot-xlnx-blob.inc + if d.getVar('UBOOT_IMAGE_BLOB') == "1": + d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') +} UBOOTELF_NODTB_IMAGE ?= "u-boot-nodtb.elf" UBOOTELF_NODTB_BINARY ?= "u-boot" -- cgit v1.2.3-54-g00ecf From b3470a5676ffb13addb446d0e8842e83b9c05eb2 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 18 May 2022 11:16:49 -0700 Subject: u-boot-xlnx: Move all u-boot FIT image (blob) implementation to here The implementation appeared to have been split between meta-som and meta-xilinx-core. The core implementation should be generic and in meta-xilinx-core. Specifics for the som board (or other boards) will be captured in the board specific layers. Note: This code may be moved in the future as part of a consolidation of device tree related items. Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-xlnx-blob.inc | 156 +++++++++++++++++++++ .../recipes-bsp/u-boot/u-boot-xlnx.inc | 5 +- 2 files changed, 158 insertions(+), 3 deletions(-) create mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc new file mode 100644 index 00000000..717b8dd3 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc @@ -0,0 +1,156 @@ +# U-boot fitimage/blob generator + +UBOOT_IMAGE_BLOB ?= "" +DT_BLOB_DIR ?= "${B}/arch/arm/dts/dt-blob" +UBOOT_BLOB_NAME ?= "${MACHINE}-fit-dtb${IMAGE_VERSION_SUFFIX}.blob" + +IMPORT_CC_DTBS ?= "" +CC_DTBS_DUP ?= "" + +MKIMAGE_DTBLOB_OPTS ?= "-E -B 0x8" + +# Everything is swtiched on with UBOOT_IMAGE_BLOB = '1' +inherit ${@'image-artifact-names' if d.getVar('UBOOT_IMAGE_BLOB') == "1" else ''} + +python() { + if d.getVar('UBOOT_IMAGE_BLOB') == "1": + d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') + d.appendVarFlag('do_compile', 'cleandirs', ' ${DT_BLOB_DIR}') + d.appendVar('PROVIDES', ' u-boot-xlnx-fit-blob') + d.appendVar('DEPENDS', ' u-boot-mkimage-native') +} + +dtblob_emit_its_section() { + case $2 in + header) + cat << EOF > $1 +/dts-v1/; + +/ { + description = "DT Blob Creation"; +EOF + ;; + imagestart) + cat << EOF >> $1 + + images { +EOF + ;; + confstart) + cat << EOF >> $1 + + configurations { +EOF + ;; + sectend) + cat << EOF >> $1 + }; +EOF + ;; + fitend) + cat << EOF >> $1 +}; +EOF + ;; + esac +} + +dtblob_emit_dtb () { + dtb_csum="md5" + cat << EOF >> $1 + fdt-$2 { + description = "$(basename $3 .dtb)"; + data = /incbin/("$3"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "$dtb_csum"; + }; + }; +EOF +} + +#1.file name +#2.config node +#3.config node description +#4.DTB count +dtblob_emit_config () { + default_dtb=1 + if [ $4 -eq $default_dtb ]; then + cat << EOF >> $1 + default = "config_$4"; +EOF + fi + cat << EOF >> $1 + config_$4 { + description = "$3"; + fdt = "fdt-$2"; + }; +EOF +} + +do_blob_generate () { + oe_runmake -C ${S} O=${B} dtbs + install -d ${DT_BLOB_DIR} + for CC_DTB in ${IMPORT_CC_DTBS}; do + DTBO=$(echo $CC_DTB | cut -d: -f1) + DTB=$(echo $CC_DTB | cut -d: -f2) + bbnote "fdtoverlay -o ${DT_BLOB_DIR}/${DTB} -i ${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME} ${B}/arch/arm/dts/${DTBO}" + if [ -f ${B}/arch/arm/dts/${DTBO} ]; then + fdtoverlay -o ${DT_BLOB_DIR}/${DTB} \ + -i ${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME} ${B}/arch/arm/dts/${DTBO} + fi + done + + cd ${DT_BLOB_DIR} + its_filename="dtblob.its" + dtblob_emit_its_section "${its_filename}" "header" + dtblob_emit_its_section "${its_filename}" "imagestart" + for dtb in ${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME} $(find ${DT_BLOB_DIR} -name '*.dtb' | sort); do + dtblob_emit_dtb "${its_filename}" "$(basename $dtb .dtb)" "$dtb" + done + dtblob_emit_its_section "${its_filename}" "sectend" + dtblob_emit_its_section "${its_filename}" "confstart" + dtbcount=1 + for dtb in ${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME} $(find ${DT_BLOB_DIR} -name '*.dtb' | sort); do + dtblob_emit_config "${its_filename}" "$(basename $dtb .dtb)" "$(basename $dtb .dtb)" "$dtbcount" + dtbcount=`expr $dtbcount + 1` + done + + for CC_DTB_DUP in ${CC_DTBS_DUP}; do + DTB=$(echo $CC_DTB_DUP | cut -d: -f1) + DUP_DTB=$(echo $CC_DTB_DUP | cut -d: -f2) + if [ -f ${DT_BLOB_DIR}/${DTB}.dtb ]; then + bbnote "Node ${DT_BLOB_DIR}/${DTB} with ${DT_BLOB_DIR}/${DUP_DTB}" + dtblob_emit_config "${its_filename}" "$DTB" "$DUP_DTB" "$dtbcount" + dtbcount=`expr $dtbcount + 1` + fi + done + + dtblob_emit_its_section "${its_filename}" "sectend" + dtblob_emit_its_section "${its_filename}" "fitend" + + mkimage ${MKIMAGE_DTBLOB_OPTS} -f "${its_filename}" "${UBOOT_BLOB_NAME}" +} + +do_install:append() { + ( + cd ${B} + + if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then + install -d ${D}/boot + install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${D}/boot + ln -sf `basename ${UBOOT_BLOB_NAME}` ${D}/boot/fit-dtb.blob + fi + ) +} + +do_deploy:prepend() { + cd ${B} + + if [ -e "${DT_BLOB_DIR}/${UBOOT_BLOB_NAME}" ]; then + install -m 0644 ${DT_BLOB_DIR}/${UBOOT_BLOB_NAME} ${DEPLOYDIR}/ + ln -sf `basename ${UBOOT_BLOB_NAME}` ${DEPLOYDIR}/fit-dtb.blob + fi +} diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index f0ea2ca3..909dd72a 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -32,11 +32,10 @@ python __anonymous () { d.appendVarFlag('do_configure', 'depends', ' virtual/dtb:do_populate_sysroot') if d.getVar("DTB_NAME") is not None: d.setVar('DTB_NAME', d.getVar('BASE_DTS')+ '.dtb') - - if d.getVar('UBOOT_IMAGE_BLOB') == "1": - d.appendVarFlag('do_compile', 'postfuncs', ' do_blob_generate') } +require u-boot-xlnx-blob.inc + UBOOTELF_NODTB_IMAGE ?= "u-boot-nodtb.elf" UBOOTELF_NODTB_BINARY ?= "u-boot" do_deploy:prepend() { -- cgit v1.2.3-54-g00ecf From 50856529876064a717fa970fa2eb4835631680f8 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Mon, 23 May 2022 17:22:42 +0530 Subject: fpgautil: Update the fpgautil help This patch updates the fpgautil help to describe the usage of fpgautil -R Signed-off-by: Nava kishore Manne Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c index 0b77569d..e4fb1d2f 100644 --- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c +++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c @@ -123,6 +123,12 @@ void print_usage(char *prg) fprintf(stderr, "(Read PL Configuration Registers)\n"); fprintf(stderr, "%s -b top.bit.bin -r\n", prg); } + + fprintf(stderr, "(Remove Partial Overlay)\n"); + fprintf(stderr, "%s -R -n PR0\n", prg); + fprintf(stderr, "(Remove Full Overlay)\n"); + fprintf(stderr, "%s -R -n Full\n", prg); + fprintf(stderr, "Note: %s -R is responsible for only removing the dtbo file from the livetree. it will not remove the PL logic from the FPGA region.\n", prg); fprintf(stderr, " \n"); } -- cgit v1.2.3-54-g00ecf From d2d9506c0b04299e785816636952e3002533d1fb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 24 May 2022 13:01:08 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 9d83ade6..b3239989 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "ed7850419526ae4031ea3d9eca2f3f4c3440b07f" +ESW_REV[2022.2] = "3edcf81e126dd63171bb0505364ca165986bcbea" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 7eb7f00d11529bf244562bafaa7b1dee3b2ed769 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 25 May 2022 13:46:20 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 34466e88..eb18f860 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "7bff6a148353c019adbca1540ef5fff634e62394" +SRCREV = "58f2b35afbe321d589781b6b04f3a279d9843dbd" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index a69ef80b..3c10b3ef 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "a9ff6d0b21c8b2928d29ede9f74e1249fc953d44" +SRCREV = "d861ae47c0a847564d152d77fd0bd7f2103855a7" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From d7d6b2c32a21ad1d383a2f63e77b6009afe21ff4 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 26 May 2022 13:08:27 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index b3239989..2a540db7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "3edcf81e126dd63171bb0505364ca165986bcbea" +ESW_REV[2022.2] = "19d2c8dec9f3270d1943dbbd1072742e06f31f04" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 1e7e07c84b89e7792af96e03c9f1f7239ddf66c0 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 19 May 2022 10:18:06 +0530 Subject: lopper: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 8d15542f..31200532 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "cd25873ec00a414f1e93f2eb3cebf0fe0b41d1e9" +SRCREV = "692cbc908b35ddb952e6ef4308c9c51584f52ed3" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 9f1712e832c92ba7f598b2cfedf1d5c1cae04f61 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 19 May 2022 15:24:42 +0530 Subject: meta-xilinx-standalone-experimental: recipes-libraries: libxil: Remove MACHINE_FEATURES from packageconfig libxil recipe PACKAGECONFIG is depending on only DISTRO_FEATURES, but existing recipe is including MACHINE_FEATURES features also due to which getting warnings invalid PACKAGECONFIG. This commit fixes this issue. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb index 4adfe46e..75c54837 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/libxil_git.bb @@ -9,7 +9,7 @@ ESW_COMPONENT_NAME = "libxil.a" DEPENDS += "xilstandalone " REQUIRED_DISTRO_FEATURES = "${DISTRO_FEATURES}" -PACKAGECONFIG ?= "${DISTRO_FEATURES} ${MACHINE_FEATURES}" +PACKAGECONFIG ?= "${DISTRO_FEATURES}" do_configure:prepend() { LOPPER_DTC_FLAGS="-b 0 -@" lopper ${DTS_FILE} -- baremetal_xparameters_xlnx.py ${ESW_MACHINE} ${S} -- cgit v1.2.3-54-g00ecf From cbb8af2b3475620313fedb4fc677498b6461fb45 Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Fri, 20 May 2022 10:21:18 +0530 Subject: meta-xilinx-core:recipes-bsp:arm-trusted-firmware: Update PNCD NS IRQ The SDP_PNCD_NS_IRQ flag is meant to set the NS interrupt number that will be used between ProvenCore OS and linux ProvenCore driver ATF is the one triggering this interrupt so it must be aware of its value. This value is hardcoded in ProvenCore binary as 51 As per input from ProvenRun the flag SPD_PNCD_NS_IRQ=51 is to be added, for right NS interruption to be used in PNCD Signed-off-by: Akshay Belsare Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 5591fa63..eaf750a6 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -68,7 +68,7 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" -ATF_PROVENCORE = "SPD=pncd ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x10000000 PRELOADED_BL33_BASE=0x80000000" +ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x10000000 PRELOADED_BL33_BASE=0x80000000" EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" do_configure() { -- cgit v1.2.3-54-g00ecf From 30d666532660082d9c3fb9d96d205fbb3f88e2f0 Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Fri, 20 May 2022 10:21:19 +0530 Subject: meta-xilinx-core:recipes-bsp:arm-trusted-firmware: Update BL32 memory size PMUFW reserves memory range 0x7ff0_0000 to 0x7fff_ffff for DDR Software Self-Refresh(refer PG201, enabled by defualt). Update the ZYNQMP_BL32_MEM_SIZE to 0x0ff0_0000 and thus memory range from 0x7000_0000 to 0x7fef_ffff. Provencore uses memory range 0x7000_0000 to 0x7fdf_ffff Signed-off-by: Akshay Belsare Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index eaf750a6..28083b3d 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -68,7 +68,7 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" -ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x10000000 PRELOADED_BL33_BASE=0x80000000" +ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x0FF00000 PRELOADED_BL33_BASE=0x80000000" EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" do_configure() { -- cgit v1.2.3-54-g00ecf From 4bad7caa74667b13e79300747e156dc52cb4999d Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 20 May 2022 16:20:52 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index db37ec78..2a498149 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "e45aab92bbcfbe57f7a06aefce2ffa3d29f3cf6d" +ESW_REV[experimental] = "b4727281ed58d095cfa758eaca5f556b485c932f" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 704db482b8037ab1eaf505451e44cb5ffa274f77 Mon Sep 17 00:00:00 2001 From: Praveen Teja Kundanala Date: Wed, 25 May 2022 10:52:05 +0530 Subject: meta-xilinx-standalone-experimental:recipes-libraries:xilsecure:updated depends as per 2022.1 xilsecure library Updated depends in xilsecure_git.bb as per 2022.1 xilsecure library Signed-off-by: Praveen Teja Kundanala Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-libraries/xilsecure_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure_git.bb index 8ccbb623..b8e2aa16 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure_git.bb @@ -3,4 +3,4 @@ inherit esw ESW_COMPONENT_SRC = "/lib/sw_services/xilsecure/src/" ESW_COMPONENT_NAME = "libxilsecure.a" -DEPENDS += "libxil xiltimer ${@'xilplmi' if d.getVar('ESW_MACHINE') == 'microblaze-plm' else ''}" +DEPENDS += "libxil xiltimer ${@'xilplmi' if d.getVar('ESW_MACHINE') == 'microblaze-plm' else 'xilmailbox'}" -- cgit v1.2.3-54-g00ecf From 6d76400d66efd16d6a668f5b84f13399a4e5db62 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 30 May 2022 12:25:21 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index eb18f860..aa751ca2 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "58f2b35afbe321d589781b6b04f3a279d9843dbd" +SRCREV = "38f57528ddc5f3d317301c3d412144e7f5bf6342" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2a540db7..a0a41158 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "19d2c8dec9f3270d1943dbbd1072742e06f31f04" +ESW_REV[2022.2] = "0d5f911a8da175cbea573627945c134db14039ec" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From d49b7d31e7fa3b22206979ffa2af5ce6b7c548ca Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 31 May 2022 11:48:51 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index aa751ca2..3be4f8b5 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "38f57528ddc5f3d317301c3d412144e7f5bf6342" +SRCREV = "a6b25711343354515775151589d50fdc0d5e7b1c" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index a0a41158..09eca4e5 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "0d5f911a8da175cbea573627945c134db14039ec" +ESW_REV[2022.2] = "4bd85e382588f90e5327cf3dba9b4694332cbdc1" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 4740c6d8a0684d572a61474e0d0f3dd057c8a429 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 1 Jun 2022 11:47:46 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 07104a0e..7c9c4a2b 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "63e8a6dadee6fdc4e117ee12c29ff6f4c5c77027" +SRCREV = "d774cf8aa99ab29bee0b1da45d450c7d3b80f7a5" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 09eca4e5..3a2cc5fe 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "4bd85e382588f90e5327cf3dba9b4694332cbdc1" +ESW_REV[2022.2] = "6cb1f1f2134b93e0ee6f66ebcb07db3a00e6dd4b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 69486af829acd83ce78c4687da46afce7da250a4 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 26 May 2022 11:23:34 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 2a498149..b6a5f47e 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "b4727281ed58d095cfa758eaca5f556b485c932f" +ESW_REV[experimental] = "77fb19f5e800799e325540fd534701e921c6086e" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 8051d1ecfa665f8f4314149e7cb9926165ab8940 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 30 May 2022 12:52:22 +0530 Subject: u-boot-zynq-scr: '@' should be outside the variable Due syntax issue in defining variable the pxelinux.cfg file was not generated properly. This patch will fix that issue. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb index e72a84ce..cf1ba209 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb @@ -20,7 +20,7 @@ DEVICE_TREE_NAME ?= "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'dev RAMDISK_IMAGE ?= "rootfs.cpio.gz.u-boot" RAMDISK_IMAGE1 ?= "ramdisk.cpio.gz.u-boot" -PXERAMDISK_IMAGE ?= "${'@${RAMDISK_IMAGE1}' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}" +PXERAMDISK_IMAGE ?= "${@'${RAMDISK_IMAGE1}' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}" KERNEL_BOOTCMD:zynqmp ?= "booti" KERNEL_BOOTCMD:zynq ?= "bootm" -- cgit v1.2.3-54-g00ecf From f7268d92980681c3a408f80f872a30592c64d1ff Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 30 May 2022 19:01:09 +0530 Subject: meta-xilinx-standalone-experimental: recipes-core: meta: files: dt-processor.sh: Generate Linux domain dts file Add support for generating Linux domain dts file along with dtb, Generated dts file consumed by the petalinux tool to add support for custom dts files (ex: system-user. dtsi). Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 36a81cc7..1323e9d0 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -107,10 +107,12 @@ cortex_a53_linux() { if [ "$1" = "None" ]; then dtb_file="cortexa53-${machine}-linux.dtb" + dts_file="cortexa53-${machine}-linux.dts" system_conf=conf/cortexa53-${machine}-linux.conf conf_file=cortexa53-${machine}-linux.conf else dtb_file="cortexa53-${machine}-$1-linux.dtb" + dts_file="cortexa53-${machine}-$1-linux.dts" multiconf="${multiconf} cortexa53-${machine}-linux" conf_file=multiconfig/cortexa53-${machine}-$1-linux.conf fi @@ -134,12 +136,23 @@ cortex_a53_linux() { -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ "${system_dtb}" "${dtb_file}" \ || error "lopper failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" \ + -i "${lops_dir}/lop-domain-linux-a53.dts" \ + -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ + "${system_dtb}" "${dts_file}" \ + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ -i "${lops_dir}/lop-domain-linux-a53.dts" \ -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ "${system_dtb}" "${dtb_file}" \ || error "lopper failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a53-imux.dts" \ + -i "${lops_dir}/lop-domain-linux-a53.dts" \ + -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ + "${system_dtb}" "${dts_file}" \ + || error "lopper failed" fi rm -f pl.dtsi lop-a53-imux.dts.dtb lop-domain-linux-a53.dts.dtb ) @@ -313,10 +326,12 @@ cortex_a72_linux() { if [ "$1" = "None" ]; then dtb_file="cortexa72-${machine}-linux.dtb" + dts_file="cortexa72-${machine}-linux.dts" system_conf=conf/cortexa72-${machine}-linux.conf conf_file=cortexa72-${machine}-linux.conf else dtb_file="cortexa72-${machine}-$1-linux.dtb" + dts_file="cortexa72-${machine}-$1-linux.dts" multiconf="${multiconf} cortexa72-${machine}-linux" conf_file=multiconfig/cortexa72-${machine}-$1-linux.conf fi @@ -343,11 +358,21 @@ cortex_a72_linux() { -i "${lops_dir}/lop-domain-a72-prune.dts" \ "${system_dtb}" "${dtb_file}" \ || error "lopper failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" \ + -i "${lops_dir}/lop-domain-a72.dts" \ + -i "${lops_dir}/lop-domain-a72-prune.dts" \ + "${system_dtb}" "${dts_file}" \ + || error "lopper failed" else LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ -i "${lops_dir}/lop-domain-a72.dts" \ -i "${lops_dir}/lop-domain-a72-prune.dts" \ "${system_dtb}" "${dtb_file}" || error "lopper failed" + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -i "${lops_dir}/lop-a72-imux.dts" \ + -i "${lops_dir}/lop-domain-a72.dts" \ + -i "${lops_dir}/lop-domain-a72-prune.dts" \ + "${system_dtb}" "${dts_file}" || error "lopper failed" fi rm -f pl.dtsi lop-a72-imux.dts.dtb lop-domain-a72.dts.dtb ) -- cgit v1.2.3-54-g00ecf From 5e0db265772435b3e133b1d79953adfcdc351c56 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 3 Jun 2022 14:19:13 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index f02bb879..e6e47082 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "67ca59c67f542322554d78820bf9ddaa736d6a84" +SRCREV = "145c6169fdf6a2855e0bc9b2ee889a23be751966" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 3be4f8b5..241324b4 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "a6b25711343354515775151589d50fdc0d5e7b1c" +SRCREV = "3113b53d8cb1913ef8162cadf45f44ebf2ed9eea" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 3c10b3ef..8763736b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "d861ae47c0a847564d152d77fd0bd7f2103855a7" +SRCREV = "28cd4306cc939a3c769b245ae248b80a22aa097d" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3a2cc5fe..bb2babe7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6cb1f1f2134b93e0ee6f66ebcb07db3a00e6dd4b" +ESW_REV[2022.2] = "a0415774ae3903d7106f4f1854deebeb055edf4b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 02f983aaa6f05ba077b795c1c7d9cef99e39e80d Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 1 Jun 2022 18:34:55 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index b6a5f47e..05f2956a 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "77fb19f5e800799e325540fd534701e921c6086e" +ESW_REV[experimental] = "bbd79053de5e89088d49de181cc395cb7823e820" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 573d5423bc839826675e6f389db69b00b07d3121 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 6 Jun 2022 11:54:06 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index bb2babe7..9f2b1736 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a0415774ae3903d7106f4f1854deebeb055edf4b" +ESW_REV[2022.2] = "85e1d3cb680470d50d6e1e9bf977775be2803aa3" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 1201510a14e0e316cca79d06d511aa60b785d2c2 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 7 Jun 2022 12:56:56 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index e6e47082..908bcf48 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "145c6169fdf6a2855e0bc9b2ee889a23be751966" +SRCREV = "afccfa4bc4ebabe0163279ee0984206d055d57c8" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" -- cgit v1.2.3-54-g00ecf From 3a5ca8eda7e67dbdeb8dda1036e95745c21a47af Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 3 Jun 2022 11:14:46 +0530 Subject: lopper: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 31200532..30c8d443 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "692cbc908b35ddb952e6ef4308c9c51584f52ed3" +SRCREV = "0c6298469ebb7fa726912a559299f47e169a1450" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From ca0ae12186c4d13305d72cc636e9107a67e38ad2 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 6 Jun 2022 18:34:15 -0700 Subject: xrt: Add workaround for xrt/xrt_kernel.h issue Workaround for issue CR-1132277 Signed-off-by: Mark Hatle --- ...h-experimental-xrt_hw_context.h-requries-.patch | 31 ++++++++++++++++++++++ meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 3 +++ 2 files changed, 34 insertions(+) create mode 100644 meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch b/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch new file mode 100644 index 00000000..05b59c35 --- /dev/null +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch @@ -0,0 +1,31 @@ +From 16adf8611f9b6de41c7fa37f0222441720efe503 Mon Sep 17 00:00:00 2001 +From: Mark Hatle +Date: Mon, 6 Jun 2022 14:11:47 -0700 +Subject: [PATCH] xrt_kernel.h: experimental/xrt_hw_context.h requries C++ + +Move the include under the cplusplus check to avoid the error: + # error xrt_hwcontext is only implemented for C++ + +Signed-off-by: Mark Hatle +--- + src/runtime_src/core/include/xrt/xrt_kernel.h | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/src/runtime_src/core/include/xrt/xrt_kernel.h b/src/runtime_src/core/include/xrt/xrt_kernel.h +index bbc9a30d5..93445dc81 100644 +--- a/src/runtime_src/core/include/xrt/xrt_kernel.h ++++ b/src/runtime_src/core/include/xrt/xrt_kernel.h +@@ -11,9 +11,8 @@ + #include "xrt/xrt_device.h" + #include "xrt/xrt_uuid.h" + +-#include "experimental/xrt_hw_context.h" +- + #ifdef __cplusplus ++# include "experimental/xrt_hw_context.h" + # include "experimental/xrt_enqueue.h" + # include + # include +-- +2.17.1 + diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index 4a697bf4..fc55b3d3 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -10,6 +10,9 @@ LIC_FILES_CHKSUM = "file://../LICENSE;md5=da5408f748bce8a9851dac18e66f4bcf \ file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ file://runtime_src/core/tools/xbutil2/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 " +# Temporary fix +SRC_URI += "file://0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch;striplevel=2" + S = "${WORKDIR}/git/src" inherit cmake -- cgit v1.2.3-54-g00ecf From b0482fdaf31e6da66d152e5c0b93dcc6070c4ab1 Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Tue, 7 Jun 2022 13:58:40 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 78147881..08e56054 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "b82419d93ec3cff6fe8095b5298a28bffb75b184" +SRCREV = "dd5071d31ce772b0e411f18decda19407f8b1dc3" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb index f86fc3ed..dbe52de9 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb @@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" -SRCREV = "a9d452e772da6bc43f524230c79e6dc0f2442fd7" +SRCREV = "6752f5da88a8783f689ae762065295b89902d6d4" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb index 348f9dec..ac864bb3 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb @@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV = "9c5170fb3fa9239ed915f40f61761cc9873425ce" +SRCREV = "57ddd9c066fa622044fdef74b4605e9fbcc4ebfb" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb index 1d675cbf..28e2fb8e 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb @@ -10,7 +10,7 @@ S = "${WORKDIR}/git" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" -SRCREV = "569f980527fd58f43baf16bd0b294bf8c7cdf963" +SRCREV = "3980c778d71fa51a15e89bf70fd8fb28d5cb12e0" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 76df3276b0d75611f0e673e27f82f15f5f62e114 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Wed, 1 Jun 2022 17:04:21 +0530 Subject: xilinx-qemu: Use addto_recipe_sysroot task To populate the QEMU binaries into sysroot the populate_sysroot task isn't enough for qemu-xilinx-helper-native, we need to use addto_recipe_sysroot task. This patch will correct the mapping. u-boot-zynq-uenv failing to add DEPENDS when EXTRA_IMAGEDEPENDS has recipe:task. This patch will split the recipe name and add it to DEPENDS. Signed-off-by: Raju Kumar Pothuraju While unusual, the PR is updated, as the qemu and qemu helper need to have the same version/pr or the path logic doesn't work properly. Signed-off-by: Mark Hatle --- .../conf/machine/include/machine-xilinx-qemu.inc | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb | 16 ++++++++++++++-- .../qemu/qemu-xilinx-helper-native_1.0.bb | 2 ++ 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc index c2093ca6..15dfae13 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc @@ -5,7 +5,7 @@ IMAGE_CLASSES += "qemuboot-xilinx" # depend on qemu-helper-native, which will depend on QEMU -EXTRA_IMAGEDEPENDS += "qemu-helper-native" +EXTRA_IMAGEDEPENDS += "qemu-helper-native:do_addto_recipe_sysroot" PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native" PREFERRED_PROVIDER_qemu = "qemu-xilinx" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb index 861479b2..82936894 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb @@ -4,8 +4,6 @@ LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda INHIBIT_DEFAULT_DEPS = "1" -DEPENDS:append := "virtual/kernel ${@oe.utils.str_filter_out(d.getVar("BPN"), d.getVar("EXTRA_IMAGEDEPENDS"), d)}" - COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynq = ".*" COMPATIBLE_MACHINE:zynqmp = ".*" @@ -14,6 +12,18 @@ PACKAGE_ARCH = "${MACHINE_ARCH}" inherit deploy image-wic-utils +def remove_task_from_depends(d): + extra_imagedepends = d.getVar('EXTRA_IMAGEDEPENDS') or '' + uenv_depends = '' + for imagedepend in extra_imagedepends.split(): + if imagedepend == d.getVar("BPN"): + continue + elif ':' in imagedepend: + uenv_depends += ' %s' % imagedepend.split(':')[0] + else: + uenv_depends += ' %s' % imagedepend + return uenv_depends + def uboot_boot_cmd(d): if d.getVar("KERNEL_IMAGETYPE") in ["uImage", "fitImage"]: return "bootm" @@ -67,6 +77,8 @@ def uenv_populate(d): return env +DEPENDS:append := "virtual/kernel ${@remove_task_from_depends(d)}" + # bootargs, default to booting with the rootfs device being partition 2 KERNEL_BOOTARGS:zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait" KERNEL_BOOTARGS:zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${devnum}p2 rw rootwait" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb index eb14c0c1..2450d275 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb @@ -2,6 +2,7 @@ FILESEXTRAPATHS:prepend := "${COREBASE}/meta/recipes-devtools/qemu/qemu-helper:" # provide it, to replace the existing PROVIDES = "qemu-helper-native" +PR = "r1" LICENSE = "GPLv2" LIC_FILES_CHKSUM = "file://${WORKDIR}/tunctl.c;endline=4;md5=ff3a09996bc5fff6bc5d4e0b4c28f999" @@ -32,3 +33,4 @@ do_install() { install tunctl ${STAGING_BINDIR_NATIVE} } +addtask addto_recipe_sysroot after do_populate_sysroot before do_build -- cgit v1.2.3-54-g00ecf From 6f3724662ef833bd0ea5c8a7f86a49efc6b01b1c Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 8 Jun 2022 12:22:41 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 8763736b..c3341bc2 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "28cd4306cc939a3c769b245ae248b80a22aa097d" +SRCREV = "21e0373d8477c67f5e78448385cda0548d5fdc18" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 53c0f55eb7cf2866258a21daadd551bb20da8749 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 7 Jun 2022 10:14:46 -0600 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 05f2956a..979c302c 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "bbd79053de5e89088d49de181cc395cb7823e820" +ESW_REV[experimental] = "31ba1ddec48083383e3ef177a51109a4d22b35d3" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 7a1481d2933074b4eb5a23e867fc544dc5eea366 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 9 Jun 2022 12:47:01 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 9f2b1736..3c04a8a8 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "85e1d3cb680470d50d6e1e9bf977775be2803aa3" +ESW_REV[2022.2] = "81cd39f091342feec117755b9c45c9a82110e41e" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From df635f57c487f5574241ab1a24000c194274ad09 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 10 Jun 2022 13:09:35 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 241324b4..65a667f5 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "3113b53d8cb1913ef8162cadf45f44ebf2ed9eea" +SRCREV = "956d53a34f217429165459576f65a32897102cf6" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 269974a5..6c511575 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "247e9edbd9c491d78dd41ee3c85ea38a309c0f67" +SRCREV ?= "d21c341ec3afa12de24143ce161ee6695adf7bda" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 7c9c4a2b..c4f71749 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "d774cf8aa99ab29bee0b1da45d450c7d3b80f7a5" +SRCREV = "9b6adc7c2aee811b22a8b59bd0c33c36b65dc9d0" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3c04a8a8..5a4eedf6 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "81cd39f091342feec117755b9c45c9a82110e41e" +ESW_REV[2022.2] = "201cc444702fabc8593202b20d49ea8a4b499dd6" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 0a7c3ec8960af8e0246e332d9c08a883d570eb28 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 13 Jun 2022 12:22:50 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c3341bc2..4c3641b0 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "21e0373d8477c67f5e78448385cda0548d5fdc18" +SRCREV = "532c121dece3ee3ce664d339cc37144ffc1333aa" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 5a4eedf6..bf8c79c4 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "201cc444702fabc8593202b20d49ea8a4b499dd6" +ESW_REV[2022.2] = "6ce4e091f6ba7d35737694c17add7f9e3d3eba33" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From f86c64668a4e45b98130410467dafd9c1f7a7fb5 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 8 Jun 2022 15:18:53 -0700 Subject: Revert "esw.bbclass: Workaround for experimental esw build" This reverts commit bf6da5278138538e4a28fd2ecf843afe094cbbe2. --- meta-xilinx-standalone-experimental/classes/esw.bbclass | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/meta-xilinx-standalone-experimental/classes/esw.bbclass b/meta-xilinx-standalone-experimental/classes/esw.bbclass index efecb1f9..78cb289c 100644 --- a/meta-xilinx-standalone-experimental/classes/esw.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw.bbclass @@ -6,9 +6,7 @@ require conf/dtb-embeddedsw.inc SRCREV_FORMAT = "src_decouple" S = "${WORKDIR}/git" -#B = "${WORKDIR}/build" -B = "${S}" - +B = "${WORKDIR}/build" OECMAKE_SOURCEPATH = "${S}/${ESW_COMPONENT_SRC}" LICFILENAME = "license.txt" -- cgit v1.2.3-54-g00ecf From d44ab8d60eda1ba361715ad7dc8976dccf072e86 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 8 Jun 2022 17:41:33 -0700 Subject: uboot-device-tree: Move bbappend into meta-xilinx-tools The provencore bbappend only applied when meta-xilinx-tools is available, so move the bbappend to meta-xilinux-tools. Signed-off-by: Mark Hatle --- .../recipes-bsp/uboot-device-tree/files/pnc.dtsi | 13 ------------- .../uboot-device-tree/uboot-device-tree.bbappend | 9 --------- 2 files changed, 22 deletions(-) delete mode 100644 meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend diff --git a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi deleted file mode 100644 index 760b76be..00000000 --- a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/files/pnc.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -/ { - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pnc-reserved-memory@70000000{ - compatible = "pnc,secure-memory"; - reg = <0x0 0x70000000 0x0 0x0FF00000>; - no-map; - }; - }; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend deleted file mode 100644 index f01276b2..00000000 --- a/meta-xilinx-bsp/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/files:" - -SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' file://pnc.dtsi', '', d)}" - -do_configure:append() { - if [ ${@bb.utils.contains('MACHINE_FEATURES', 'provencore', 'true', '', d)} ]; then - echo '#include "pnc.dtsi"' >> ${DT_FILES_PATH}/system-top.dts - fi -} -- cgit v1.2.3-54-g00ecf From 7c5519b8b1dc782fd0fa50ac426094f9225de80a Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 8 Jun 2022 17:49:49 -0700 Subject: meta-xilinx-standalone-experimental: Wrap do_configure:prepend The do_configure prepend steps need to run in the 'S' directory, so wrap the operations to prevent them from changing the working directory for the rest of the do_configure operations. Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/classes/esw_examples.bbclass | 2 ++ .../recipes-applications/empty-application/empty-application_git.bb | 2 ++ .../freertos-hello-world/freertos-hello-world_git.bb | 2 ++ .../freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb | 2 ++ .../freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb | 2 ++ .../freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb | 2 ++ .../freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb | 2 ++ .../freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb | 2 ++ .../recipes-applications/hello-world/hello-world_git.bb | 2 ++ .../recipes-applications/lwip-echo-server/lwip-echo-server_git.bb | 2 ++ .../lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb | 2 ++ .../lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb | 2 ++ .../lwip-udp-perf-client/lwip-udp-perf-client_git.bb | 2 ++ .../lwip-udp-perf-server/lwip-udp-perf-server_git.bb | 2 ++ .../recipes-applications/memory-tests/memory-tests_git.bb | 2 ++ .../recipes-applications/peripheral-tests/peripheral-tests_git.bb | 2 ++ .../recipes-drivers/clockps-example_git.bb | 2 ++ .../recipes-libraries/freertos10-xilinx_git.bb | 2 ++ meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb | 2 ++ .../recipes-libraries/xilffs-example_git.bb | 2 ++ .../recipes-libraries/xilfpga-example_git.bb | 2 ++ .../recipes-libraries/xilmailbox-example_git.bb | 2 ++ .../recipes-libraries/xilnvm-example_git.bb | 2 ++ .../recipes-libraries/xilpuf-example_git.bb | 2 ++ .../recipes-libraries/xilsecure-example_git.bb | 2 ++ .../recipes-libraries/xilstandalone_git.bb | 2 ++ meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb | 2 ++ 27 files changed, 54 insertions(+) diff --git a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass index 0ebc38a0..508da535 100644 --- a/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw_examples.bbclass @@ -3,10 +3,12 @@ inherit esw deploy python3native DEPENDS += "python3-dtc-native python3-pyyaml-native xilstandalone libxil xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb index 99771f38..8ffb01cb 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/empty-application/empty-application_git.bb @@ -7,11 +7,13 @@ DEPENDS += "libxil xiltimer" inherit python3native do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0644 ${CUSTOM_SRCFILE}/* ${S}/${ESW_COMPONENT_SRC}/ + ) } CUSTOM_APP_IMAGE_NAME ??= "custom-application" diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb index e4a300d2..f97240f8 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-hello-world/freertos-hello-world_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_hello_world/src/" DEPENDS += "libxil xilstandalone freertos10-xilinx xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_install() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb index 25610987..5e58c601 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-echo-server/freertos-lwip-echo-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_lwip_echo_server/src/" DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb index cec949f9..e4a2b041 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-client/freertos-lwip-tcp-perf-client_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_lwip_tcp_perf_client/src/" DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb index a144ecfd..bf892954 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-tcp-perf-server/freertos-lwip-tcp-perf-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_lwip_tcp_perf_server/src/" DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb index 3c3a27b0..0a28d3df 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-client/freertos-lwip-udp-perf-client_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_lwip_udp_perf_client/src/" DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb index 8e532c3c..0212dab2 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/freertos-lwip-udp-perf-server/freertos-lwip-udp-perf-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/freertos_lwip_udp_perf_server/src/" DEPENDS += "libxil lwip xiltimer freertos10-xilinx" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb index 9b66c129..16d9d030 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/hello-world/hello-world_git.bb @@ -7,10 +7,12 @@ DEPENDS += "libxil xiltimer" inherit python3native do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_install() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb index d86e62a3..84909f18 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-echo-server/lwip-echo-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/lwip_echo_server/src/" DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb index dd6501cf..eea50f60 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-client/lwip-tcp-perf-client_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/lwip_tcp_perf_client/src/" DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb index 1f7ae00c..fac6ace0 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-tcp-perf-server/lwip-tcp-perf-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/lwip_tcp_perf_server/src/" DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb index 1b3105da..0c1b1f9b 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-client/lwip-udp-perf-client_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/lwip_udp_perf_client/src/" DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb index be3d3d4b..8973ee60 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/lwip-udp-perf-server/lwip-udp-perf-server_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_apps/lwip_udp_perf_server/src/" DEPENDS += "libxil lwip xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb index 3e025962..f2af00f6 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/memory-tests/memory-tests_git.bb @@ -7,10 +7,12 @@ DEPENDS += "libxil xiltimer" inherit python3native do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} memtest install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } do_install() { diff --git a/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb b/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb index 61b60ad4..21422739 100644 --- a/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-applications/peripheral-tests/peripheral-tests_git.bb @@ -7,10 +7,12 @@ DEPENDS += "libxil xiltimer" inherit python3native do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } python do_generate_app_data() { diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb index 97871326..67fb695e 100644 --- a/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-drivers/clockps-example_git.bb @@ -9,10 +9,12 @@ DEPENDS += "libxil xiltimer resetps" inherit python3native do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } CLOCKPS_EX_IMAGE_NAME ??= "${BPN}" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb index 46c349bc..22d7955e 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/freertos10-xilinx_git.bb @@ -7,7 +7,9 @@ DEPENDS += "libxil xilstandalone xiltimer" do_configure:prepend() { # This script should also not rely on relative paths and such + ( cd ${S} lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb index 09bf4192..bced1499 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/lwip_git.bb @@ -15,10 +15,12 @@ EXTRA_OECMAKE:append:xilinx-freertos += "-Dlwip_api_mode=SOCKET_API" do_configure:prepend() { # This script should also not rely on relative paths and such + ( cd ${S} lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 xtopology_g.c ${S}/${ESW_COMPONENT_SRC}/ + ) } do_install() { diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb index 7f3618c8..ff12a5df 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilffs/examples/" DEPENDS += "xilffs xiltimer" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb index 5137c591..df5c1bbe 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilfpga-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilfpga/examples/" DEPENDS += "xilfpga" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb index a525e1bc..1e457d18 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilmailbox-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilmailbox/examples/" DEPENDS += "xilmailbox" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb index ef8b6e64..a656e7ec 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilnvm-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilnvm/examples/" DEPENDS += "xilnvm" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb index d43b4da9..9f1e8baa 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilpuf/examples/" DEPENDS += "xilpuf" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb index 4c2be337..2267571f 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilsecure-example_git.bb @@ -5,10 +5,12 @@ ESW_COMPONENT_SRC = "/lib/sw_services/xilsecure/examples/" DEPENDS += "xilsecure" do_configure:prepend() { + ( cd ${S} lopper ${DTS_FILE} -- baremetallinker_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 memory.ld ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } ESW_CUSTOM_LINKER_FILE ?= "None" diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb index 447c3cc3..70a46c5e 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilstandalone_git.bb @@ -7,8 +7,10 @@ DEPENDS += "libgloss" do_configure:prepend() { # This script should also not rely on relative paths and such + ( cd ${S} lopper ${DTS_FILE} -- baremetal_bspconfig_xlnx ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} install -m 0755 MemConfig.cmake ${S}/${ESW_COMPONENT_SRC}/ install -m 0755 *.c ${S}/${ESW_COMPONENT_SRC}/common/ + ) } diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb index 0e25bbb7..dd19671d 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xiltimer_git.bb @@ -7,7 +7,9 @@ DEPENDS += "libxil" do_configure:prepend() { # This script should also not rely on relative paths and such + ( cd ${S} lopper ${DTS_FILE} -- bmcmake_metadata_xlnx.py ${ESW_MACHINE} ${S}/${ESW_COMPONENT_SRC} hwcmake_metadata ${S} install -m 0755 *.cmake ${S}/${ESW_COMPONENT_SRC}/ + ) } -- cgit v1.2.3-54-g00ecf From 77f283404dcff5e89a5ef8830a68435782e575d1 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 8 Jun 2022 17:51:59 -0700 Subject: xilffs-example: Add REQURIED_DISTRO_FEATURES to match dependency xilffs Resolve build wanring about xilffs-example not having REQUIRED_DISTRO_FEATURES when one of it's dependencies has them. Signed-off-by: Mark Hatle --- .../recipes-libraries/xilffs-example_git.bb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb index ff12a5df..bb976377 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs-example_git.bb @@ -1,5 +1,8 @@ inherit esw deploy +# Requires by dependency xilffs +REQUIRED_DISTRO_FEATURES = "sdps" + ESW_COMPONENT_SRC = "/lib/sw_services/xilffs/examples/" DEPENDS += "xilffs xiltimer" -- cgit v1.2.3-54-g00ecf From 64092e7e4bb81bfd58be705b7429bbabc2260ff2 Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Tue, 7 Jun 2022 22:52:45 -0700 Subject: dfx-mgr: SRCREV: fix listapp, add dfx-mgr.service The SRCREV is for HEADERSIZE fix and adding dfx-mgr.service from this to dfx-mgr repo to help Ubuntu packaging. Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 08e56054..b7589567 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "dd5071d31ce772b0e411f18decda19407f8b1dc3" +SRCREV = "af395f9b568cc0054456706a6452bac752b290c1" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From 1197387e16dec312ddb0a2c356ba9835d85aa15c Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Thu, 9 Jun 2022 00:31:17 +0530 Subject: meta-xilinx-core:recipes-bsp:arm-trusted-firmware: Remove multiple entry of flag The flag PRELOADED_BL33_BASE is populated from petalinux for different platforms. Removing the hardcoded entry which is causing multiple instance of the same flag to the make command Signed-off-by: Akshay Belsare Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 28083b3d..4b076444 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -68,7 +68,7 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" -ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x0FF00000 PRELOADED_BL33_BASE=0x80000000" +ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x0FF00000" EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" do_configure() { -- cgit v1.2.3-54-g00ecf From a521797b3b0e4acdecb417da29998d9f03124261 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 9 Jun 2022 08:17:51 -0600 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 979c302c..e54d1b79 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "31ba1ddec48083383e3ef177a51109a4d22b35d3" +ESW_REV[experimental] = "7dd3a7c345e9ef197fa5a7e640bb286992d07935" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From f38977b1e3b348bb1e2e72b86b412e8bf43cd491 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 15 Jun 2022 11:25:57 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 4c3641b0..621bf866 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "532c121dece3ee3ce664d339cc37144ffc1333aa" +SRCREV = "563bbe59ad2f3c55ef8a077d97019e70e0f992fd" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 8d47b69a7391e02786ab7d8fae506219a75c48fb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 16 Jun 2022 13:31:40 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 621bf866..2e889247 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "563bbe59ad2f3c55ef8a077d97019e70e0f992fd" +SRCREV = "59523b5c4aca0174f1f8cba2a07d3b3328b7c80e" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index bf8c79c4..e801d5cd 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6ce4e091f6ba7d35737694c17add7f9e3d3eba33" +ESW_REV[2022.2] = "0545b159d558d3ae170cd92198be7beb81165665" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From acb1a53c4b762b79bc847012e8d08831976991e4 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 16 Jun 2022 16:48:17 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 65a667f5..e33072e2 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "956d53a34f217429165459576f65a32897102cf6" +SRCREV = "c5ca1d14039c5d7bf1e48d5805a0532d71706b64" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From e129b600ade8dd20b879797cc430de6d591a999b Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 13 Jun 2022 14:22:44 -0600 Subject: layer.conf: Add xilinx-tools as dynamic layers Add meta-xilinx-tools as dynamic-layers. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-vendor/conf/layer.conf | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/meta-xilinx-vendor/conf/layer.conf b/meta-xilinx-vendor/conf/layer.conf index b3e81efc..3d1ff571 100644 --- a/meta-xilinx-vendor/conf/layer.conf +++ b/meta-xilinx-vendor/conf/layer.conf @@ -5,6 +5,11 @@ BBPATH .= ":${LAYERDIR}" BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ ${LAYERDIR}/recipes-*/*/*.bbappend" +BBFILES_DYNAMIC += " \ +xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bb \ +xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bbappend \ +" + BBFILE_COLLECTIONS += "xilinx-vendor" BBFILE_PATTERN_xilinx-vendor = "^${LAYERDIR}/" BBFILE_PRIORITY_xilinx-vendor = "5" -- cgit v1.2.3-54-g00ecf From bb855e43a4dad0d55b7a8f18fba51cc09fcda71f Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Wed, 15 Jun 2022 07:14:23 -0700 Subject: lopper: Update srcrev for 2022.2 Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 30c8d443..715f8e02 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "0c6298469ebb7fa726912a559299f47e169a1450" +SRCREV = "14d2aa3fb20d173b47d2aad89f9bb69106bfd39d" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From ef98251ff871c1b47c5125752715defa81e6bf1a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 17 Jun 2022 13:53:46 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index c4f71749..5d0e420c 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "9b6adc7c2aee811b22a8b59bd0c33c36b65dc9d0" +SRCREV = "4695d9d02c672e9ba10b46e6444b7d87a74a5338" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index e801d5cd..bd4a73aa 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "0545b159d558d3ae170cd92198be7beb81165665" +ESW_REV[2022.2] = "a0ad9730a221f3713fc7cb409c163172908f7d37" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From ca2bb33906bb47afd86044f1ffe49b580a745a0d Mon Sep 17 00:00:00 2001 From: Swagath Gadde Date: Thu, 9 Jun 2022 11:20:20 +0530 Subject: device-tree.bbappend:wire vpk180 and vhk158 board dts This patch will wire the vpk180 and vhk158 board dts wrt yocto MACHINEOVERRIDES. Signed-off-by: Swagath Gadde Signed-off-by: Mark Hatle --- .../meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index 2640c2c2..130dd5f9 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -32,4 +32,5 @@ YAML_DT_BOARD_FLAGS:k26 ?= "{BOARD zynqmp-sm-k26-reva}" YAML_DT_BOARD_FLAGS:zcu670 ?= "{BOARD zcu670-revb}" YAML_DT_BOARD_FLAGS:vpk120 ?= "{BOARD versal-vpk120-reva}" YAML_DT_BOARD_FLAGS:vpk-sc ?= "{BOARD zynqmp-vpk120-reva}" - +YAML_DT_BOARD_FLAGS:vpk180 ?= "{BOARD versal-vpk180-reva}" +YAML_DT_BOARD_FLAGS:vhk158 ?= "{BOARD versal-vhk158-reva}" -- cgit v1.2.3-54-g00ecf From 78d043708028e9148f35a9df9eff944173365145 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 12 May 2022 17:15:07 -0600 Subject: u-boot: Remove deprecated board defconfigs Board specific u-boot defconfigs are deprecated from u-boot source, hence remove deprecated defconfigs from u-boot recipes. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb | 9 --------- meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend | 9 --------- 2 files changed, 18 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb index 3e40bfa1..0c7685a5 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb @@ -17,12 +17,3 @@ SRCREV ?= "${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/bootloader", "u-b PV = "${UBRANCH}-xilinx-dev+git${SRCPV}" -# Newer versions of u-boot have support for these -HAS_PLATFORM_INIT ?= " \ - zynq_microzed_config \ - zynq_zed_config \ - zynq_zc702_config \ - zynq_zc706_config \ - zynq_zybo_config \ - " - diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend index b8522369..56083ce3 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend @@ -1,11 +1,2 @@ include u-boot-spl-zynq-init.inc -# u-boot 2016.11 has support for these -HAS_PLATFORM_INIT ??= " \ - zynq_microzed_config \ - zynq_zed_config \ - zynq_zc702_config \ - zynq_zc706_config \ - zynq_zybo_config \ - " - -- cgit v1.2.3-54-g00ecf From 303a4a23262ff2999e23bcc174342a73e8767de5 Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Fri, 17 Jun 2022 19:55:05 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index b7589567..65b60251 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "af395f9b568cc0054456706a6452bac752b290c1" +SRCREV = "0b15aa49b4af64449bd859a025bb3c97c0e9a64e" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From 2e2fa4ddb3cdb887a0b5b044fa95852ef3682c14 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 20 Jun 2022 13:54:13 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index e33072e2..ee08f2c2 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "c5ca1d14039c5d7bf1e48d5805a0532d71706b64" +SRCREV = "9abe5b9ec40ac6348ca4661e9bf295b309db9b6f" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 2e889247..dd2221be 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "59523b5c4aca0174f1f8cba2a07d3b3328b7c80e" +SRCREV = "623b93338922e56f9b8fe9a43961f120d7a999f8" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index bd4a73aa..06cdb463 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a0ad9730a221f3713fc7cb409c163172908f7d37" +ESW_REV[2022.2] = "91d4a3cec5f4704ddab8e18404956a01ada36e46" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 2bc257b94db2f519b98194275b853bee0a944ae9 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 21 Jun 2022 11:59:59 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index dd2221be..9b16dfdf 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "623b93338922e56f9b8fe9a43961f120d7a999f8" +SRCREV = "1e67f149fb5eb4f5eb4e0d4f69194eac6d2497d7" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 06cdb463..cb501a8d 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "91d4a3cec5f4704ddab8e18404956a01ada36e46" +ESW_REV[2022.2] = "b4cdb271dce6eded7c88da4d501233c319a7f6be" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 510f582ec8566a5772ca3925e8055706d715fe85 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 22 Jun 2022 11:57:18 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index cb501a8d..d695837a 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "b4cdb271dce6eded7c88da4d501233c319a7f6be" +ESW_REV[2022.2] = "9b25998167a3d72ff90ff8a7c43740aa86234038" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 574eba1a8e952a0b0dae4e0848dd7fcd80eee80f Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 22 Jun 2022 14:14:44 -0700 Subject: Revert "xrt: Add workaround for xrt/xrt_kernel.h issue" This reverts commit ca0ae12186c4d13305d72cc636e9107a67e38ad2. No longer necessary Signed-off-by: Mark Hatle --- ...h-experimental-xrt_hw_context.h-requries-.patch | 31 ---------------------- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 3 --- 2 files changed, 34 deletions(-) delete mode 100644 meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch b/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch deleted file mode 100644 index 05b59c35..00000000 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt/0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 16adf8611f9b6de41c7fa37f0222441720efe503 Mon Sep 17 00:00:00 2001 -From: Mark Hatle -Date: Mon, 6 Jun 2022 14:11:47 -0700 -Subject: [PATCH] xrt_kernel.h: experimental/xrt_hw_context.h requries C++ - -Move the include under the cplusplus check to avoid the error: - # error xrt_hwcontext is only implemented for C++ - -Signed-off-by: Mark Hatle ---- - src/runtime_src/core/include/xrt/xrt_kernel.h | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/src/runtime_src/core/include/xrt/xrt_kernel.h b/src/runtime_src/core/include/xrt/xrt_kernel.h -index bbc9a30d5..93445dc81 100644 ---- a/src/runtime_src/core/include/xrt/xrt_kernel.h -+++ b/src/runtime_src/core/include/xrt/xrt_kernel.h -@@ -11,9 +11,8 @@ - #include "xrt/xrt_device.h" - #include "xrt/xrt_uuid.h" - --#include "experimental/xrt_hw_context.h" -- - #ifdef __cplusplus -+# include "experimental/xrt_hw_context.h" - # include "experimental/xrt_enqueue.h" - # include - # include --- -2.17.1 - diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index fc55b3d3..4a697bf4 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -10,9 +10,6 @@ LIC_FILES_CHKSUM = "file://../LICENSE;md5=da5408f748bce8a9851dac18e66f4bcf \ file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ file://runtime_src/core/tools/xbutil2/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 " -# Temporary fix -SRC_URI += "file://0001-xrt_kernel.h-experimental-xrt_hw_context.h-requries-.patch;striplevel=2" - S = "${WORKDIR}/git/src" inherit cmake -- cgit v1.2.3-54-g00ecf From 9c9495ce0dc933b168d9407a99bdd4f192ff4e76 Mon Sep 17 00:00:00 2001 From: rbramand Date: Tue, 21 Jun 2022 21:29:06 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index a8976822..e825c88c 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "a3befd1ac0b78555ee7150a3199795ed9b49887a" +SRCREV= "004ea23733e63b9ab5f704609e6821824106a051" PV = "202220.2.14.0" -- cgit v1.2.3-54-g00ecf From ea890d09553928ec865c9c31ac8b02397fee74df Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 21 Jun 2022 21:39:03 -0600 Subject: README.md: Ultra96 is compatible with v1 board Update README stating that Ultra96 machine configuration file is compatible with v1 board and refer to meta-avnet for v2 board. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-vendor/README.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-vendor/README.md b/meta-xilinx-vendor/README.md index 51ff84e1..84cbf1be 100644 --- a/meta-xilinx-vendor/README.md +++ b/meta-xilinx-vendor/README.md @@ -16,11 +16,15 @@ This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architecture ||[Avnet/Digilent ZedBoard](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html)|[zedboard-zynq7](conf/machine/zedboard-zynq7.conf)|NA| ||[Digilent Zybo](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-zynq7](conf/machine/zybo-zynq7.conf)|`zynq-zybo.dtb`| ||[Digilent Zybo Linux BD](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-linux-bd-zynq7](conf/machine/zybo-linux-bd-zynq7.conf)|NA| -|ZynqMP|[Avent Ultra96](https://www.xilinx.com/products/boards-and-kits/1-vad4rl.html)|[ultra96-zynqmp](conf/machine/ultra96-zynqmp.conf)|`avnet-ultra96-rev1`| +|ZynqMP|[Avent Ultra96 v1](https://www.xilinx.com/products/boards-and-kits/1-vad4rl.html)|[ultra96-zynqmp](conf/machine/ultra96-zynqmp.conf)|`avnet-ultra96-rev1`| |Versal|NA|NA|NA| > **Note:** -`For Zybo Linux BD reference design, please see meta-xilinx-contrib layer` +``` +1. For Zybo Linux BD reference design refer meta-xilinx-contrib layer. +2. Ultra96 Machine configuration file is unsupported and is compatible with v1 board only. Refer to meta-avnet for v2 board. +``` + ## Dependencies -- cgit v1.2.3-54-g00ecf From 52852606e216f55366caba1c76d05a78af2c7669 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 23 Jun 2022 19:55:08 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index ee08f2c2..73b1e376 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "9abe5b9ec40ac6348ca4661e9bf295b309db9b6f" +SRCREV = "42b10139fb295afa118963a19ae9e146e403b86c" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 9b16dfdf..6c3ae93c 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "1e67f149fb5eb4f5eb4e0d4f69194eac6d2497d7" +SRCREV = "8684044b601946fceda13df7e84a2a8c68309e00" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d695837a..20fbd66c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "9b25998167a3d72ff90ff8a7c43740aa86234038" +ESW_REV[2022.2] = "6dfff2d004c14381cad48f26becaa8f97fc3e18b" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 04b77d6c3e9e98d8a38d2c07a75ade774877fcf8 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 24 Jun 2022 11:10:38 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 20fbd66c..dd07ac71 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6dfff2d004c14381cad48f26becaa8f97fc3e18b" +ESW_REV[2022.2] = "a11d2a64c887f1e6aa5d8826c481a32b30696dd7" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 517b209fc99d8c798f798b503198cb5487a02800 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 27 Jun 2022 10:58:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index dd07ac71..04468909 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a11d2a64c887f1e6aa5d8826c481a32b30696dd7" +ESW_REV[2022.2] = "5a6ad3916d0302541687acbb4aade1c28e2f7dec" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 0c83168601454a99bc8820982bb820e1b9d42810 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 24 Jun 2022 17:11:42 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index e54d1b79..581b03ac 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "7dd3a7c345e9ef197fa5a7e640bb286992d07935" +ESW_REV[experimental] = "eedfb4ee4614dae985719123266f9390abdef48c" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 30324555e14593bff4ef2c5ff00493e483cf3209 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 27 Jun 2022 10:13:08 +0530 Subject: meta-xilinx-standalone-experimental: recipes-drivers: Add recipe for compiling bram driver examples This recipe compiles the bram driver examples. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-drivers/bram-example_git.bb | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 meta-xilinx-standalone-experimental/recipes-drivers/bram-example_git.bb diff --git a/meta-xilinx-standalone-experimental/recipes-drivers/bram-example_git.bb b/meta-xilinx-standalone-experimental/recipes-drivers/bram-example_git.bb new file mode 100644 index 00000000..6e2c4918 --- /dev/null +++ b/meta-xilinx-standalone-experimental/recipes-drivers/bram-example_git.bb @@ -0,0 +1,5 @@ +inherit esw_examples features_check + +REQUIRED_DISTRO_FEATURES = "bram" + +ESW_COMPONENT_SRC = "/XilinxProcessorIPLib/drivers/bram/examples/" -- cgit v1.2.3-54-g00ecf From 516c749a000d3113b2d1ad903e89166729119135 Mon Sep 17 00:00:00 2001 From: Harsha Date: Thu, 23 Jun 2022 13:05:14 +0530 Subject: meta-xilinx-standalone-experimanetal:recipes-libraries:xilpuf:Updates DEPENDS for 2022.2 This patch updated DEPENDS to fix build issue for xilpuf-example recipe. Signed-off-by: Harsha Signed-off-by: Mark Hatle --- .../recipes-libraries/xilpuf-example_git.bb | 2 +- meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb index 9f1e8baa..ad2d5c47 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf-example_git.bb @@ -2,7 +2,7 @@ inherit esw deploy ESW_COMPONENT_SRC = "/lib/sw_services/xilpuf/examples/" -DEPENDS += "xilpuf" +DEPENDS += "xilpuf xilsecure" do_configure:prepend() { ( diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb index 4f9332c7..266503d1 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilpuf_git.bb @@ -3,4 +3,4 @@ inherit esw ESW_COMPONENT_SRC = "/lib/sw_services/xilpuf/src/" ESW_COMPONENT_NAME = "libxilpuf.a" -DEPENDS += "libxil xiltimer xilplmi" +DEPENDS += "libxil xiltimer ${@'xilplmi' if d.getVar('ESW_MACHINE') == 'microblaze-plm' else 'xilmailbox'}" -- cgit v1.2.3-54-g00ecf From 001e3cafc84447ebbcc389026207a1269cdf2fb7 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:14 +0530 Subject: image-types-xilinx-qemu: Add qemu-sd-fatimg support qemu-sd: Qemu 6.X onwards SD image should be of power of 2, this patch will read the generate qemu-sd image and find out its next power of 2 and adjust the size using qemu-img resize command. qemu-sd-fatimg: Due to circular dependencies in yocto when we enable INITRAMFS_IMAGE + wic and we need SD fat image to boot versal on qemu. For this added new image conversion type qemu-sd-fatimg, it will generate the sd fatimg containing boot.bin,boot.scr,rootfs.cpio.gz.u-boot files. Usage: IMAGE_FSTYPES += "cpio.gz.u-boot.qemu-sd-fatimg" NOTE: qemu-sd-fatimg creation is a workaround fix for circular dependencies. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- .../classes/image-types-xilinx-qemu.bbclass | 55 ++++++++++++++++++++-- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass b/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass index 63318087..9532287d 100644 --- a/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass +++ b/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass @@ -5,6 +5,55 @@ # block device to match that of valid SD card sizes (which are multiples of # 512K). -CONVERSIONTYPES:append = " qemu-sd" -CONVERSION_CMD:qemu-sd = "cp ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd; truncate -s %256M ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd" -CONVERSION_DEPENDS_qemu-sd = "coreutils-native" +CONVERSIONTYPES:append = " qemu-sd qemu-sd-fatimg" +CONVERSION_CMD:qemu-sd () { + cp ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd + # Get the wic.qemu-sd file size + file_size=`stat -c '%s' ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd` + powerof2=1 + file_size=${file_size%.*} + # Get the next power of 2 value for the image size value + while [ ${powerof2} -lt ${file_size} ]; do + powerof2=$(expr $powerof2 \* 2) + done + # Resize the image using qemu-img + qemu-img resize -f raw ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd ${powerof2} +} + +BOOT_VOLUME_ID ?= "BOOT" +BOOT_SPACE ?= "1047552" +IMAGE_ALIGNMENT ?= "1024" + +# Create SD image in case of INITRAMFS_IMAGE set due to circular dependencies. +# This creates FAT partitioned SD image containing boot.bin,boot.scr and rootfs.cpio.gz.u-boot files. +# This is a workaround fix until we fix the circular dependencies +# Usage: IMAGE_FSTYPES:append = " cpio.gz.u-boot.qemu-sd-fatimg" +CONVERSION_CMD:qemu-sd-fatimg () { + QEMU_IMG="${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd-fatimg" + BOOT_SPACE_ALIGNED=$(expr ${BOOT_SPACE} + ${IMAGE_ALIGNMENT} - 1) + BOOT_SPACE_ALIGNED=$(expr ${BOOT_SPACE_ALIGNED} - ${BOOT_SPACE_ALIGNED} % ${IMAGE_ALIGNMENT}) + QEMUIMG_SIZE=$(expr ${IMAGE_ALIGNMENT} + ${BOOT_SPACE_ALIGNED}) + dd if=/dev/zero of=${QEMU_IMG} bs=1024 count=0 seek=${QEMUIMG_SIZE} + parted -s ${QEMU_IMG} mklabel msdos + parted -s ${QEMU_IMG} unit KiB mkpart primary fat32 ${IMAGE_ALIGNMENT} $(expr ${BOOT_SPACE_ALIGNED} \+ ${IMAGE_ALIGNMENT} \- 1) + parted -s ${QEMU_IMG} set 1 boot on + parted ${QEMU_IMG} print + BOOT_BLOCKS=$(LC_ALL=C parted -s ${QEMU_IMG} unit b print | awk '/ 1 / { print substr($4, 1, length($4 -1)) / 512 /2 }') + rm -f ${WORKDIR}/${BOOT_VOLUME_ID}.img + mkfs.vfat -n "${BOOT_VOLUME_ID}" -S 512 -C ${WORKDIR}/${BOOT_VOLUME_ID}.img $BOOT_BLOCKS + if [ -e ${DEPLOY_DIR_IMAGE}/boot.bin ]; then + mcopy -i ${WORKDIR}/${BOOT_VOLUME_ID}.img -s ${DEPLOY_DIR_IMAGE}/boot.bin ::/ + fi + if [ -e ${DEPLOY_DIR_IMAGE}/boot.scr ]; then + mcopy -i ${WORKDIR}/${BOOT_VOLUME_ID}.img -s ${DEPLOY_DIR_IMAGE}/boot.scr ::/ + fi + if [ ${INITRAMFS_IMAGE} = ${IMAGE_BASENAME} ] && [ x"${INITRAMFS_IMAGE_BUNDLE}" != "x1" ]; then + mcopy -i ${WORKDIR}/${BOOT_VOLUME_ID}.img -s ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ::rootfs.cpio.gz.u-boot + fi + dd if=${WORKDIR}/${BOOT_VOLUME_ID}.img of=${QEMU_IMG} conv=notrunc seek=1 bs=$(expr ${IMAGE_ALIGNMENT} \* 1024) +} + +CONVERSION_DEPENDS_qemu-sd = "qemu-xilinx-system-native" +CONVERSION_DEPENDS_qemu-sd-fatimg = "mtools-native:do_populate_sysroot \ + dosfstools-native:do_populate_sysroot \ + parted-native:do_populate_sysroot" -- cgit v1.2.3-54-g00ecf From 8ea306be9e877f335989ddcf22358b29c985146d Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:15 +0530 Subject: qemuboot-xilinx:machine-xilinx-default: Update kernel images For zynq,microblaze qemu supports direct kernel boot by specifying kernel image name to QB_DEFAULT_KERNEL. Adjusting the kernel image based on the bundle image selection. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/classes/qemuboot-xilinx.bbclass | 4 ++++ meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc | 1 + 2 files changed, 5 insertions(+) diff --git a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass index 48dfa6e2..59d3f0ab 100644 --- a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass +++ b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass @@ -12,6 +12,10 @@ QB_MACHINE_XILINX:microblaze = "-M microblaze-fdt-plnx" # defaults QB_DEFAULT_KERNEL ?= "none" +QB_DEFAULT_KERNEL:zynq ?= "${@'zImage' if \ + d.getVar('INITRAMFS_IMAGE_BUNDLE') != '1' else 'zImage-initramfs-${MACHINE}.bin'}" +QB_DEFAULT_KERNEL:microblaze ?= "${@'simpleImage.mb' if \ + d.getVar('INITRAMFS_IMAGE_BUNDLE') != '1' else 'simpleImage.mb-initramfs-${MACHINE}.bin'}" inherit qemuboot diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc index a15e92c6..a4b0c59a 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc @@ -46,6 +46,7 @@ def get_default_image_boot_files(d): # kernel images kerneltypes = set((d.getVar("KERNEL_IMAGETYPE") or "").split()) kerneltypes |= set((d.getVar("KERNEL_IMAGETYPES") or "").split()) + kerneltypes |= set((d.getVar("KERNEL_ALT_IMAGETYPE") or "").split()) for i in kerneltypes: files.append(i) -- cgit v1.2.3-54-g00ecf From b3da2c94f77ea7ae892b6adb3c3eebfac1a028b2 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:16 +0530 Subject: machine-xilinx-qemu: Add generic functions to add qemu args This patch will add generic fuctions to add qemu args as per the configuration set and soc_family. Ex: - Adding Image, rootfs and boot.scr files for zynqmp if in case of IMAGE_INITRAMFS set. - Add boot mode as 5 for versal - Return the rootfs type per configuration - Skip adding rootfs in case of bundle image as kernel image will have it. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- .../conf/machine/include/machine-xilinx-qemu.inc | 59 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc index 15dfae13..8cf9d4ed 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc @@ -12,6 +12,63 @@ PREFERRED_PROVIDER_qemu = "qemu-xilinx" PREFERRED_PROVIDER_qemu-native = "qemu-xilinx-native" PREFERRED_PROVIDER_nativesdk-qemu = "nativesdk-qemu-xilinx" +def qemu_add_extra_args(d): + initramfs_image = d.getVar('INITRAMFS_IMAGE') or "" + bundle_image = d.getVar('INITRAMFS_IMAGE_BUNDLE') or "" + deploy_dir = d.getVar('DEPLOY_DIR_IMAGE') or "" + machine_name = d.getVar('MACHINE') or "" + soc_family = d.getVar('SOC_FAMILY') or "" + qb_extra_args = '' + # Add kernel image and boot.scr to qemu boot command when initramfs_image supplied + kernel_name = '' + bootscr_image = '%s/boot.scr' % deploy_dir + if soc_family in ('zynqmp', 'versal'): + kernel_name = 'Image' + bootscr_loadaddr = '0x20000000' + if initramfs_image: + kernel_image = '%s/%s' % (deploy_dir, kernel_name) + if bundle_image == "1": + kernel_image = '%s/%s-initramfs-%s.bin' % (deploy_dir, kernel_name, machine_name) + kernel_loadaddr = '0x200000' + if kernel_name: + qb_extra_args = ' -device loader,file=%s,addr=%s,force-raw=on' % (kernel_image, kernel_loadaddr) + qb_extra_args += ' -device loader,file=%s,addr=%s,force-raw=on' % (bootscr_image, bootscr_loadaddr) + if soc_family == 'versal': + qb_extra_args += ' -boot mode=5' + else: + if soc_family in ('zynqmp', 'versal'): + qb_extra_args = ' -boot mode=5' + return qb_extra_args + +def qemu_rootfs_params(d,param): + initramfs_image = d.getVar('INITRAMFS_IMAGE') or "" + bundle_image = d.getVar('INITRAMFS_IMAGE_BUNDLE') or "" + soc_family = d.getVar('SOC_FAMILY') or "" + tune_features = (d.getVar('TUNE_FEATURES') or []).split() + if param == 'rootfs': + return 'none' if bundle_image == "1" else '' + elif param == 'fstype': + fstype_dict = { + "microblaze": "cpio.gz", + "zynq": "cpio.gz", + "zynqmp": "cpio.gz.u-boot", + "versal": "cpio.gz.u-boot.qemu-sd-fatimg" + } + if initramfs_image: + if 'microblaze' in tune_features: + return fstype_dict['microblaze'] + else: + return fstype_dict[soc_family] + else: + return 'wic.qemu-sd' + elif param == 'rootfs-opt': + if not initramfs_image or soc_family == 'versal': + sd_index = "1" + if soc_family == 'zynq': sd_index = "0" + return ' -drive if=sd,index=%s,file=@ROOTFS@,format=raw' % (sd_index) + elif soc_family not in ('zynq') or 'microblaze' in tune_features: + return ' -device loader,file=@ROOTFS@,addr=0x04000000,force-raw=on' + def qemu_default_dtb(d): if d.getVar("IMAGE_BOOT_FILES", True): dtbs = d.getVar("IMAGE_BOOT_FILES", True).split(" ") @@ -51,5 +108,3 @@ QB_SYSTEM_NAME:aarch64 ?= "${@qemu_target_binary(d)}-multiarch" QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" QB_DEFAULT_FSTYPE ?= "cpio" QB_DTB ?= "${@qemu_default_dtb(d)}" -QB_KERNEL_CMDLINE_APPEND ?= "${@qemu_default_serial(d)}" - -- cgit v1.2.3-54-g00ecf From 4e7d85bec9839b8dfb67df4633906c58b4153097 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:17 +0530 Subject: microblaze-generic: Add runqemu support for microblaze-generic This patch will add runqemu support for microblaze-generic machines for INITRD/INITRAMFS types. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 9004282a..01499fdc 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -29,7 +29,7 @@ MACHINE_ARCH = "${@['${MB_MACHINE_ARCH}', '${DEF_MACHINE_ARCH}']['microblaze-gen MACHINE_FEATURES = "" -KERNEL_IMAGETYPE = "linux.bin.ub" +KERNEL_IMAGETYPE ?= "linux.bin.ub" KERNEL_IMAGETYPES = "" SERIAL_CONSOLES ?= "115200;ttyS0" @@ -39,6 +39,19 @@ EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-nativ UBOOT_MACHINE ?= "microblaze-generic_defconfig" UBOOT_INITIAL_ENV = "" +IMAGE_FSTYPES:append = " cpio.gz" +QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" +QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" + +QB_KERNEL_CMDLINE = "none" + +QB_OPT_APPEND = " \ + -nographic -serial mon:stdio \ + " + +QB_DTB = "system.dtb" +QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE}" #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' ${MB_MACHINE_ARCH}']['microblaze-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From bfefe0786b2781335e8af983e197c17dec000167 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:18 +0530 Subject: versal-generic: Add runqemu support for versal-generic This patch will add runqemu support for versal-generic when INITRAMFS/INITRD/EXT4 configurations. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-generic.conf | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index 3509d8c4..a1e0975a 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -29,7 +29,9 @@ HDF_MACHINE = "vck190-versal" # Default SD image build onfiguration, use qemu-sd to pad IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" +# Add wic.qemu-sd only if initramfs_image not set due to circular dependecies +IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot.qemu-sd-fatimg'}" + WKS_FILES ?= "sdimage-bootpart.wks" EXTRA_IMAGEDEPENDS += " \ @@ -58,12 +60,8 @@ QB_NETWORK_DEVICE = "" QB_KERNEL_CMDLINE_APPEND ?= "" QB_NET = "none" -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND:append:qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" - -# Use booti 80000 6000000 4000000 to launch -QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none" +QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch" QEMU_HW_DTB_PS ?="${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" @@ -74,8 +72,8 @@ QEMU_HW_DTB_PMC_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-pmc-vir QB_OPT_APPEND:append:qemuboot-xilinx = " \ -hw-dtb ${QEMU_HW_DTB_PS} \ - -display none \ - -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \ + -serial null -serial null -serial mon:stdio -serial null -display none \ + ${@qemu_add_extra_args(d)} \ " # PLM instance args @@ -84,7 +82,7 @@ QB_PLM_OPT = " \ -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw \ -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \ -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \ - -device loader,file=${DEPLOY_DIR_IMAGE}/pmc_cdo.bin,addr=0xf2000000,force-raw \ + -device loader,file=${DEPLOY_DIR_IMAGE}/CDO/pmc_cdo.bin,addr=0xf2000000,force-raw \ -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \ -device loader,addr=0xF1110624,data=0x0,data-len=4 \ -device loader,addr=0xF1110620,data=0x1,data-len=4 \ -- cgit v1.2.3-54-g00ecf From 82eef8579a9d936108827816b702cc92cf0f5d06 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:19 +0530 Subject: zynq-generic.conf: Add runqemu support for zynq-generic This patch will add runqemu support for zynq-generic machines when INITRAMFS/INITRD/EXT4 sets. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynq-generic.conf | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 59fc3976..488c4244 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -25,16 +25,27 @@ SERIAL_CONSOLES ?= "115200;ttyPS0" MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" +IMAGE_BOOT_FILES += " \ + ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ + boot.scr \ + " + HDF_MACHINE = "zc702-zynq7" +IMAGE_CLASSES += "image-types-xilinx-qemu" +# Add wic.qemu-sd only if initramfs_image not set due to circular dependecies +IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz'}" +WKS_FILES ?= "sdimage-bootpart.wks" QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic" -QB_DEFAULT_KERNEL:qemuboot-xilinx = "zImage" - +QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE} -net nic" QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "cpio.gz" +QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" +QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" + +QB_KERNEL_CMDLINE = "none" + QB_DTB = "system.dtb" -QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) QB_OPT_APPEND = " \ @@ -45,6 +56,7 @@ QB_OPT_APPEND = " \ -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \ -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \ -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \ + -machine linux=on \ " #### No additional settings should be after the Postamble -- cgit v1.2.3-54-g00ecf From 77c50a2c17a5a1069520549769d77f542aff25b4 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Mon, 27 Jun 2022 17:36:20 +0530 Subject: zynqmp-generic.conf: Add runqemu support for zynqmp-generic This patch will add runqemu support for zynqmp-generic machines when INITRAMFS/INITRD/EXT4 sets. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynqmp-generic.conf | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf index 6bc42364..27bf36b0 100644 --- a/meta-xilinx-core/conf/machine/zynqmp-generic.conf +++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf @@ -34,7 +34,8 @@ SPL_BINARY ?= "spl/boot.bin" # Default SD image build onfiguration, use qemu-sd to pad IMAGE_CLASSES += "image-types-xilinx-qemu" -IMAGE_FSTYPES += "wic.qemu-sd" +# Add wic.qemu-sd only if initramfs_image not set due to circular dependecies +IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot'}" WKS_FILES ?= "sdimage-bootpart.wks" SERIAL_CONSOLES ?= "115200;ttyPS0" @@ -71,13 +72,13 @@ QB_OPT_APPEND:append:qemuboot-xilinx = " \ ${@qemu_zynqmp_unhalt(d, True)} \ -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \ -device loader,file=${DEPLOY_DIR_IMAGE}/u-boot.elf \ - -device loader,file=${DEPLOY_DIR_IMAGE}/system.dtb,addr=0x100000 \ + -device loader,file=${DEPLOY_DIR_IMAGE}/system.dtb,addr=0x100000,force-raw=on \ + ${@qemu_add_extra_args(d)} \ " -# Attach the rootfs disk image to the second SD interface of QEMU (which is SD0) -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND:append:qemuboot-xilinx = " -boot mode=5" -QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" +QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" +QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS_OPT:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs-opt')}" QB_PMU_OPT = " \ -M microblaze-fdt \ -- cgit v1.2.3-54-g00ecf From 06a4017ce232415f44aed48f7ec7706b006f761d Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 28 Jun 2022 13:05:34 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 04468909..24ed260c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "5a6ad3916d0302541687acbb4aade1c28e2f7dec" +ESW_REV[2022.2] = "a4ea3ba6c25cad8291e5d454ca23a0dde80e44ea" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From d8c575afec4e733f567e715c7d04af07dae6c3b1 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 29 Jun 2022 11:07:09 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 73b1e376..2d7f2efc 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "42b10139fb295afa118963a19ae9e146e403b86c" +SRCREV = "d6bed589137c81081f49fdb40842d336abe9281f" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From a936ee68fa47ac97e9045642c7aaf74d196a304e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 30 Jun 2022 11:35:50 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 6c511575..fa03e3e0 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,4 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "d21c341ec3afa12de24143ce161ee6695adf7bda" +SRCREV ?= "ba78633a5aef6fe279ec90d1429480bb75365452" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 6c3ae93c..60da20f8 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "8684044b601946fceda13df7e84a2a8c68309e00" +SRCREV = "37f45b0af0578ffed13f74ffdd53cdd10ce6c9bf" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 24ed260c..2dd84985 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a4ea3ba6c25cad8291e5d454ca23a0dde80e44ea" +ESW_REV[2022.2] = "93abeacddcd6657c209c17b11d3e98889ec0c79c" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 18d63898bcf7a2c8cb717fe5e02d1c3af67cd129 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 4 Jul 2022 11:53:50 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 60da20f8..2c0491a2 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "37f45b0af0578ffed13f74ffdd53cdd10ce6c9bf" +SRCREV = "50470cc53c4c22e09797a106e8fb06606383b904" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2dd84985..61786c8d 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "93abeacddcd6657c209c17b11d3e98889ec0c79c" +ESW_REV[2022.2] = "fc03d2e5fca705e3b257b627643eef812ab7c009" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From a08c400cf66b27c636c339177d1f8b2e3bff67d4 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 5 Jul 2022 13:26:32 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 2d7f2efc..f5e88b4b 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "d6bed589137c81081f49fdb40842d336abe9281f" +SRCREV = "682674d3286122c2ff74e438d30daa455b174d0a" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 2c0491a2..0a744303 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "50470cc53c4c22e09797a106e8fb06606383b904" +SRCREV = "3cec245cdbe3b55b1ac3f0b090d9828ae553cc70" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 877821eb1a4894836b60a134a73bc83bc99617e3 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Thu, 30 Jun 2022 13:59:54 +0530 Subject: machine:*-generic.conf: Use += instead of append Using append enabling the FSTYPE when using the soc override in petalinux. Using += to add/reflect the value only in yocto or defined with ?= or = operators. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 2 +- meta-xilinx-core/conf/machine/versal-generic.conf | 2 +- meta-xilinx-core/conf/machine/zynq-generic.conf | 2 +- meta-xilinx-core/conf/machine/zynqmp-generic.conf | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 01499fdc..4bf519df 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -39,7 +39,7 @@ EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-nativ UBOOT_MACHINE ?= "microblaze-generic_defconfig" UBOOT_INITIAL_ENV = "" -IMAGE_FSTYPES:append = " cpio.gz" +IMAGE_FSTYPES += "cpio.gz" QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index a1e0975a..8d17c3af 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -30,7 +30,7 @@ HDF_MACHINE = "vck190-versal" # Default SD image build onfiguration, use qemu-sd to pad IMAGE_CLASSES += "image-types-xilinx-qemu" # Add wic.qemu-sd only if initramfs_image not set due to circular dependecies -IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot.qemu-sd-fatimg'}" +IMAGE_FSTYPES += "${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot.qemu-sd-fatimg'}" WKS_FILES ?= "sdimage-bootpart.wks" diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 488c4244..315a8b97 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -33,7 +33,7 @@ IMAGE_BOOT_FILES += " \ HDF_MACHINE = "zc702-zynq7" IMAGE_CLASSES += "image-types-xilinx-qemu" # Add wic.qemu-sd only if initramfs_image not set due to circular dependecies -IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz'}" +IMAGE_FSTYPES += "${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz'}" WKS_FILES ?= "sdimage-bootpart.wks" QB_MEM = "-m 1024" diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf index 27bf36b0..164a7c9c 100644 --- a/meta-xilinx-core/conf/machine/zynqmp-generic.conf +++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf @@ -35,7 +35,7 @@ SPL_BINARY ?= "spl/boot.bin" # Default SD image build onfiguration, use qemu-sd to pad IMAGE_CLASSES += "image-types-xilinx-qemu" # Add wic.qemu-sd only if initramfs_image not set due to circular dependecies -IMAGE_FSTYPES:append = " ${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot'}" +IMAGE_FSTYPES += "${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' else 'cpio.gz.u-boot'}" WKS_FILES ?= "sdimage-bootpart.wks" SERIAL_CONSOLES ?= "115200;ttyPS0" -- cgit v1.2.3-54-g00ecf From 2572be37f07fbe2e40ca76977535ea9c8108ce69 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 5 Jul 2022 18:30:43 +0530 Subject: meta-xilinx-standalone-experimental: recipes-libraries: xilffs: Enable word_access by default In the xilffs library default configuration word_access is enabled by default, enable the same in the recipe too. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb index 0649d3d8..8792fdbd 100644 --- a/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb +++ b/meta-xilinx-standalone-experimental/recipes-libraries/xilffs_git.bb @@ -5,7 +5,7 @@ REQUIRED_DISTRO_FEATURES = "sdps" ESW_COMPONENT_SRC = "/lib/sw_services/xilffs/src/" ESW_COMPONENT_NAME = "libxilffs.a" -PACKAGECONFIG ??= "read_only" +PACKAGECONFIG ??= "read_only word_access" PACKAGECONFIG[use_mkfs] ="-DXILFFS_use_mkfs=ON,-DXILFFS_use_mkfs=OFF,," PACKAGECONFIG[read_only] ="-DXILFFS_read_only=ON,-DXILFFS_read_only=OFF,," PACKAGECONFIG[word_access]="-DXILFFS_word_access=ON,-DXILFFS_word_access=OFF,," -- cgit v1.2.3-54-g00ecf From d7d211b2dc39c4aef83be003aa7ad3e2d8ed78d7 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 5 Jul 2022 21:04:21 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 581b03ac..808add38 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "eedfb4ee4614dae985719123266f9390abdef48c" +ESW_REV[experimental] = "d15dfc69fad875e0b19315b0ad50c615dcef5125" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From ff7e08112c4dbd435c897266228a20cce04e78ca Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 6 Jul 2022 11:06:09 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 61786c8d..ba1905ed 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "fc03d2e5fca705e3b257b627643eef812ab7c009" +ESW_REV[2022.2] = "2fe3b280b9369288d9875db75d3899f15ba1e130" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From c8cda87578cc565bc7a62c764c44026ecf8fa87d Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 7 Jul 2022 13:31:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index ba1905ed..c6cbc6a6 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "2fe3b280b9369288d9875db75d3899f15ba1e130" +ESW_REV[2022.2] = "6a230a06f7fcfc21d3e8e5c101f1bc9284e5550f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 6bf41e229c854b8525bea0d6303ab98dd0e33650 Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Wed, 6 Jul 2022 14:11:58 -0700 Subject: lopper: Update srcrev for 2022.2 Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 715f8e02..6e19bbcb 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "14d2aa3fb20d173b47d2aad89f9bb69106bfd39d" +SRCREV = "69d88490a6e2a21d80d529b56a5c8f2e1754c28d" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From f5f2c4fd789298fa523123b162705fc18cab47a9 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 7 Jul 2022 16:04:23 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 808add38..10a86a89 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "d15dfc69fad875e0b19315b0ad50c615dcef5125" +ESW_REV[experimental] = "b2e8fbfd126f06bbefb55df11772dc310005ba08" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 40a8e575737be91414bed98821d9775643b4dd90 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Thu, 7 Jul 2022 19:33:08 +0530 Subject: meta-xilinx-standalone-experimental: recipes-core: meta: files: dt-processor.sh: Remove permissive flag while processing domain yaml files Earlier in the lopper, domain yaml support is there only with the permissive flag, With the latest lopper source code passing this flag is optional, When we have this flag in the lopper command and if the output format is dts in that case it will include invalid phandle references also(As this option is designed to maintain all phandle references) in the final dts resulting compilation errors, so to avoid above mentioned issue remove the permissive flag from the domain handling. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 38 +++++++++++----------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index 1323e9d0..c1f076d8 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -130,13 +130,13 @@ cortex_a53_linux() { fi dtc -q -O dtb -o pl.dtbo -b 0 -@ pl.dtsi || error "dtc failed" elif [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" \ -i "${lops_dir}/lop-domain-linux-a53.dts" \ -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ "${system_dtb}" "${dtb_file}" \ || error "lopper failed" - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" \ -i "${lops_dir}/lop-domain-linux-a53.dts" \ -i "${lops_dir}/lop-domain-linux-a53-prune.dts" \ @@ -201,7 +201,7 @@ cortex_a53_baremetal() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -213,7 +213,7 @@ cortex_a53_baremetal() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" \ || error "lopper failed" else @@ -272,7 +272,7 @@ cortex_a53_freertos() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a53-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -284,7 +284,7 @@ cortex_a53_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa53-${machine} "${embeddedsw}" \ @@ -352,13 +352,13 @@ cortex_a72_linux() { fi dtc -q -O dtb -o pl.dtbo -b 0 -@ pl.dtsi || error "dtc failed" elif [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" \ -i "${lops_dir}/lop-domain-a72.dts" \ -i "${lops_dir}/lop-domain-a72-prune.dts" \ "${system_dtb}" "${dtb_file}" \ || error "lopper failed" - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" \ -i "${lops_dir}/lop-domain-a72.dts" \ -i "${lops_dir}/lop-domain-a72-prune.dts" \ @@ -407,7 +407,7 @@ cortex_a72_baremetal() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -419,7 +419,7 @@ cortex_a72_baremetal() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" \ @@ -463,7 +463,7 @@ cortex_a72_freertos() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "${domain_file}" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" lopper -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" lopper -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-a72-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -475,7 +475,7 @@ cortex_a72_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexa72-${machine} "${embeddedsw}" \ @@ -534,7 +534,7 @@ cortex_r5_baremetal() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "$domain_file" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-r5-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -546,7 +546,7 @@ cortex_r5_baremetal() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" \ @@ -604,7 +604,7 @@ cortex_r5_freertos() { ( cd dtb || error "Unable to cd to dtb dir" if [ -n "$domain_file" ]; then - LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --permissive --enhanced -x '*.yaml' \ + LOPPER_DTC_FLAGS="-b 0 -@" ${lopper} -f --enhanced -x '*.yaml' \ -i "${domain_file}" -i "${lops_dir}/lop-r5-imux.dts" "${system_dtb}" "${dtb_file}" \ || error "lopper failed" else @@ -616,7 +616,7 @@ cortex_r5_freertos() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx cortexr5-${machine} "${embeddedsw}" \ @@ -684,7 +684,7 @@ pmu-microblaze() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx microblaze-pmu "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-pmu "${embeddedsw}" \ @@ -740,7 +740,7 @@ pmc-microblaze() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx microblaze-plm "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-plm "${embeddedsw}" \ @@ -796,7 +796,7 @@ psm-microblaze() { # Build baremetal multiconfig if [ -n "${domain_file}" ]; then - ${lopper} -f --permissive --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ + ${lopper} -f --enhanced -x '*.yaml' -i "${domain_file}" "${system_dtb}" \ -- baremetaldrvlist_xlnx microblaze-psm "${embeddedsw}" || error "lopper failed" else ${lopper} -f "${system_dtb}" -- baremetaldrvlist_xlnx microblaze-psm "${embeddedsw}" \ -- cgit v1.2.3-54-g00ecf From 940f186b868d64cde570c790968183f0b1e02be2 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 6 Jul 2022 14:01:22 -0600 Subject: u-boot-xlnx: Add support for U-boot user specified dts Add support for U-boot user specified dts by setting below variables in local.conf file. UBOOT_USER_SPECIFIED_DTS:pn-u-boot-xlnx = "versal-vck190-revA-x-ebm-01-revA" This will fetch user specified dts from from u-boot repo path u-boot-xlnx/arch/arm/dts/versal-vck190-revA-x-ebm-01-revA.dts when user doesn't want to use EXT_DTB from device-tree recipes. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-xlnx.inc | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index 909dd72a..fe819ba6 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -20,10 +20,16 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/u-boot:" SYSROOT_DIRS += "/boot" BASE_DTS ?= "${@os.path.basename(d.getVar('CONFIG_DTFILE') or '').rstrip('.dtb') or 'system-top'}" -DTB_PATH ?= "/boot/devicetree/" +DTB_PATH ?= "boot/devicetree/" DTB_NAME ?= "" -EXTRA_OEMAKE += "${@'EXT_DTB=${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME}' if (d.getVar('DTB_NAME') != '') else '' }" +# This vairable is used for U-boot user specified dts from u-boot repo path +# u-boot-xlnx/arch/arm/dts/versal-vck190-revA-x-ebm-01-revA.dts. +# Note: .dts extension is not required for this variable settings. +# Example: UBOOT_USER_SPECIFIED_DTS = "versal-vck190-revA-x-ebm-01-revA" +UBOOT_USER_SPECIFIED_DTS ?= "" + +EXTRA_OEMAKE += "${@'EXT_DTB=${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME}' if (d.getVar('DTB_NAME') != '' and d.getVar('UBOOT_USER_SPECIFIED_DTS') == '') else 'DEVICE_TREE=${UBOOT_USER_SPECIFIED_DTS}'}" python __anonymous () { #check if there are any dtb providers @@ -34,6 +40,14 @@ python __anonymous () { d.setVar('DTB_NAME', d.getVar('BASE_DTS')+ '.dtb') } +do_configure:prepend () { + if [ -n "${UBOOT_USER_SPECIFIED_DTS}" && ! -f ${S}/arch/arm/dts/${UBOOT_USER_SPECIFIED_DTS}.dts ]; then + bbfatal "Uboot user specified dts (${UBOOT_USER_SPECIFIED_DTS}.dts) is not found in \ +the${S}/arch/arm/dts directory, you need to patch dts file to u-boot source and use this configuration. \ +For more details refer https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#configuration " + fi +} + require u-boot-xlnx-blob.inc UBOOTELF_NODTB_IMAGE ?= "u-boot-nodtb.elf" @@ -56,4 +70,11 @@ do_deploy:prepend() { ln -sf ${UBOOT_NODTB_IMAGE} ${DEPLOYDIR}/${UBOOT_NODTB_SYMLINK} ln -sf ${UBOOT_NODTB_IMAGE} ${DEPLOYDIR}/${UBOOT_NODTB_BINARY} fi + + # In ZynqMP u-boot.dtb is generated by default but not for versal, Hence manually deploy. + if [ "${SOC_FAMILY}" == "versal" ]; then + if [ -f ${B}/arch/arm/dts/${UBOOT_USER_SPECIFIED_DTS}.dtb ]; then + install -Dm 0644 ${B}/arch/arm/dts/${UBOOT_USER_SPECIFIED_DTS}.dtb ${DEPLOYDIR}/u-boot.dtb + fi + fi } -- cgit v1.2.3-54-g00ecf From 05b31961190033c82ef3e3c87e80abef71e213c0 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 7 Jul 2022 10:51:22 -0700 Subject: u-boot-xlnx-blob.inc: Move to using UBOOT_IMAGE_BLOB_DEFAULT UBOOT_IMAGE_BLOB may need a machine (override) specific default value, but we always want the user to be above to override this easily. Adding the new UBOOT_IMAGE_BLOB_DEFAULT allows us to set the default in a BSP layer, while continuing to make the UBOOT_IMAGE_BLOB setting easy for the user to adjust. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc index 717b8dd3..5f09a99f 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-blob.inc @@ -1,6 +1,7 @@ # U-boot fitimage/blob generator -UBOOT_IMAGE_BLOB ?= "" +UBOOT_IMAGE_BLOB_DEFAULT = "" +UBOOT_IMAGE_BLOB ?= "${UBOOT_IMAGE_BLOB_DEFAULT}" DT_BLOB_DIR ?= "${B}/arch/arm/dts/dt-blob" UBOOT_BLOB_NAME ?= "${MACHINE}-fit-dtb${IMAGE_VERSION_SUFFIX}.blob" -- cgit v1.2.3-54-g00ecf From 6e4dde2acafd40d6187cb1bb5e84b67a99dbf938 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 8 Jul 2022 16:21:27 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index f5e88b4b..29dac456 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "682674d3286122c2ff74e438d30daa455b174d0a" +SRCREV = "fd57de2c4516d00c424226f1e3eff28bf9b25e2d" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index c6cbc6a6..9326a646 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6a230a06f7fcfc21d3e8e5c101f1bc9284e5550f" +ESW_REV[2022.2] = "674b19c5c4e07d3f73acc53a441a4466208f4154" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From e1287392f608d3990a0770e7ce00de59f3083c5e Mon Sep 17 00:00:00 2001 From: Manikanta Sreeram Date: Fri, 8 Jul 2022 06:26:12 -0600 Subject: Updated SRCREV for 2022.2 revert u-boot commit to old commit due to kernal fail found for zynq boards Signe-off-by: Manikanta Sreeram --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 29dac456..f5e88b4b 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "fd57de2c4516d00c424226f1e3eff28bf9b25e2d" +SRCREV = "682674d3286122c2ff74e438d30daa455b174d0a" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From 1603e89a2e266c44a0574ffecb665d973bb23a05 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 11 Jul 2022 15:41:31 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 9326a646..1e41dd64 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "674b19c5c4e07d3f73acc53a441a4466208f4154" +ESW_REV[2022.2] = "495ee011d69890e1eb96cfb85d15ed2115cf8d0f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 5fb2c9147da93ec57dbfa147b4c3d01c08f3c567 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 12 Jul 2022 11:27:14 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 0a744303..dc204d7b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "3cec245cdbe3b55b1ac3f0b090d9828ae553cc70" +SRCREV = "782529d063390382abaacec5d4a7f8c138b93715" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 1e41dd64..afbeb6cd 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "495ee011d69890e1eb96cfb85d15ed2115cf8d0f" +ESW_REV[2022.2] = "eab9ebb2cdfcdd46c4078b2ecfe2e098bda1dd15" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From b3e105d6a1b74dddb74af69ecfb8c3b180ab5578 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 13 Jul 2022 17:20:56 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 908bcf48..9b4a7ce1 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "afccfa4bc4ebabe0163279ee0984206d055d57c8" +SRCREV = "c7e8c327df53e97e1ad5e52e3b8ae2ba57f6565d" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index afbeb6cd..2bd842f3 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "eab9ebb2cdfcdd46c4078b2ecfe2e098bda1dd15" +ESW_REV[2022.2] = "a99033075acccd12ecd894dce946f34d863f2bbf" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From a89575d76d999f724739fa59f4558409c6b9fe87 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 14 Jul 2022 15:31:06 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 5d0e420c..2b70bf4e 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "4695d9d02c672e9ba10b46e6444b7d87a74a5338" +SRCREV = "6408fce60f3b2dac12a884e9b44a6fd0690ed8ba" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2bd842f3..95bdd022 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a99033075acccd12ecd894dce946f34d863f2bbf" +ESW_REV[2022.2] = "6630e13170b62969e1cfbb8f8f5e1afe64ba99ec" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From ddc098dede81cb23b293bdc9eaacb9138e7f67e1 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 14 Jul 2022 16:35:44 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index dc204d7b..318a8b20 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "782529d063390382abaacec5d4a7f8c138b93715" +SRCREV = "a04ae753061d4bd14bbd92713cbdcb85a84c47c1" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From a9dcff1c8d0bb6215b6693bace58aba22cf9e673 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 12 Jul 2022 12:33:38 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022.2 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 10a86a89..13880e4d 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "b2e8fbfd126f06bbefb55df11772dc310005ba08" +ESW_REV[experimental] = "a2bc0a4286d48b78e43dea4504b7483665d4e148" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 719e7638b04d71015190b9454f2ff0992672401d Mon Sep 17 00:00:00 2001 From: John Toomey Date: Thu, 14 Jul 2022 17:25:19 +0100 Subject: Set QB_KERNEL_ROOT for zynq-generic This value is passed to the kernel in order to choose the correct disk but defaults to /dev/vda which does not boot. Signed-off-by: John Toomey Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynq-generic.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 315a8b97..a0d2802e 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -47,6 +47,8 @@ QB_KERNEL_CMDLINE = "none" QB_DTB = "system.dtb" +QB_KERNEL_ROOT = "/dev/mmcblk0p2" + # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) QB_OPT_APPEND = " \ -nographic -serial null -serial mon:stdio \ -- cgit v1.2.3-54-g00ecf From 28579ea3745c4540f4ab539778b389232731952f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 12 Jul 2022 14:49:58 +0530 Subject: lopper: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 6e19bbcb..ce782759 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "69d88490a6e2a21d80d529b56a5c8f2e1754c28d" +SRCREV = "9159040dab25e2f1e7b447fcbfcd5397b1d618e8" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 821c44d46fca63cbfb690a749eed4fd198248299 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Fri, 8 Jul 2022 03:46:32 +0200 Subject: dfx-mgr: Add firmware detection capability The newly added xlnx-firmware-detect script provides a mechanism for detecting and loading default firmware through dfx-mgr. The script is executed as a pre-step in the dfx-mgr unit file prior to starting the dfx-mgrd. It uses fru-print to read the board ID from an EEPROM and based on that searches for a product specific firmware entry in the firmware search path defined in the dfx-mgr config file. In case the script is able to detect compatible default firmware, it will update the dfx-mgr config file accordingly, otherwise the script will fail but the dfx-mgr daemon is still started and no default firmware will be loaded. Signed-off-by: Christian Kohn Signed-off-by: Shubhangi Mahalle Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service | 1 + .../dfx-mgr/dfx-mgr/xlnx-firmware-detect | 92 ++++++++++++++++++++++ .../recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 8 +- 3 files changed, 100 insertions(+), 1 deletion(-) create mode 100755 meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service index 12239266..d442fd9e 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service @@ -9,6 +9,7 @@ Description=dfx-mgrd Dynamic Function eXchange Documentation=https://github.com/Xilinx/dfx-mgr [Service] +ExecStartPre=-/usr/bin/xlnx-firmware-detect ExecStart=/usr/bin/dfx-mgrd [Install] diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect new file mode 100755 index 00000000..6b843166 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect @@ -0,0 +1,92 @@ +#!/bin/sh + +# (C) Copyright 2022 Xilinx, Inc. +# SPDX-License-Identifier: MIT + +# read values from dfx-mgr conf file +conffile="/etc/dfx-mgrd/daemon.conf" +if [ ! -f "${conffile}" ]; then + echo "dfx-mgrd configuration file not found: ${conffile}" + exit 1 +fi + +fwbasedir=$(grep "firmware_location" ${conffile} | sed 's/.*:.*\[\"\(.*\)\"\],\?/\1/') +if [ -z "${fwbasedir}" ]; then + echo "Property 'firmware_location' not found in ${conffile}" + exit 1 +fi + +fwfile=$(grep "default_accel" ${conffile} | sed 's/.*:.*\"\(.*\)\",\?/\1/') +if [ -z "${fwfile}" ]; then + echo "Property 'default_accel' not found in ${conffile}" + exit 1 +fi + +# check if default firmware is already set and present +if [ -f "${fwfile}" ]; then + fwname=$(cat ${fwfile}) + fwdir="${fwbasedir}/${fwname}" + if [ -n "${fwname}" ] && [ -d "${fwdir}" ]; then + echo "Default firmware detected: ${fwname}" + exit 0 + fi +fi + +# search for firmware based on EEPROM board id +echo "Trying to detect default firmware based on EEPROM..." + +# check if board is a SOM product +eeprom=$(ls /sys/bus/i2c/devices/*50/eeprom 2> /dev/null) +if [ -n "${eeprom}" ]; then + boardid=$(fru-print -d ${eeprom} -f product | awk -F- '{ print tolower($2) }') + validids="k26" + valid=0 + for id in ${validids}; do + if [ "${id}" = "${boardid}" ]; then + echo "Known SOM Board ID found: ${boardid}" + valid=1 + break + fi + done + if [ ${valid} -eq 1 ]; then + fwname="${boardid}-starter-kits" + fwdir="${fwbasedir}/${fwname}" + if [ ! -d "${fwdir}" ]; then + echo "No default firmware named ${fwname} found in ${fwbasedir}" + exit 1 + fi + echo "Default firmware detected: ${fwname}" + echo "${fwname}" > "${fwfile}" + exit 0 + fi +fi + +# check if board is a System Controller product +eeprom=$(ls /sys/bus/i2c/devices/*54/eeprom 2> /dev/null) +if [ -n "${eeprom}" ]; then + boardid=$(fru-print -d ${eeprom} -f product | tr '[:upper:]' '[:lower:]') + revision=$(fru-print -d ${eeprom} -f revision | tr '[:upper:]' '[:lower:]') + validids="vpk120 vpk180 vhk158" + valid=0 + for id in ${validids}; do + if [ "${id}" = "${boardid}" ]; then + echo "Known System Controller Board ID found: ${boardid} rev ${revision}" + valid=1 + break + fi + done + if [ ${valid} -eq 1 ]; then + fwname="${boardid}-${revision}" + fwdir="${fwbasedir}/${fwname}" + if [ ! -d "${fwdir}" ]; then + echo "No default firmware named ${fwname} found in ${fwbasedir}" + exit 1 + fi + echo "Default firmware detected: ${fwname}" + echo "${fwname}" > "${fwfile}" + exit 0 + fi +fi + +echo "No known Board ID found" +exit 1 diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 65b60251..a7013d2a 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -23,13 +23,17 @@ S = "${WORKDIR}/git" inherit cmake update-rc.d systemd DEPENDS += " libwebsockets inotify-tools libdfx zocl libdrm" +RDEPENDS:${PN} += " fru-print" EXTRA_OECMAKE += " \ -DCMAKE_SYSROOT:PATH=${RECIPE_SYSROOT} \ " INITSCRIPT_NAME = "dfx-mgr.sh" INITSCRIPT_PARAMS = "start 99 S ." -SRC_URI:append = " file://dfx-mgr.service" +SRC_URI:append = " \ + file://dfx-mgr.service \ + file://xlnx-firmware-detect \ + " SYSTEMD_PACKAGES="${PN}" SYSTEMD_SERVICE:${PN}="dfx-mgr.service" SYSTEMD_AUTO_ENABLE:${PN}="enable" @@ -58,6 +62,8 @@ do_install(){ fi install -m 0755 ${S}/src/dfx-mgr.sh ${D}${bindir}/ + install -m 0755 ${WORKDIR}/xlnx-firmware-detect ${D}${bindir} + install -d ${D}${systemd_system_unitdir} install -m 0644 ${WORKDIR}/dfx-mgr.service ${D}${systemd_system_unitdir} } -- cgit v1.2.3-54-g00ecf From 685bf31bd51d94ed5bd9b8cf78fba803288037cb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 15 Jul 2022 11:42:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 95bdd022..ed3b3f36 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6630e13170b62969e1cfbb8f8f5e1afe64ba99ec" +ESW_REV[2022.2] = "9c6cb7c9a0c2a38426f1e8e18277fb0938e17e6f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From bec6b680f6f334af9df959dab24b908e249f833c Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 18 Jul 2022 11:34:43 -0700 Subject: meta-microbalze: gdb: Enable gdb and gdbserver on microblaze Replace existing integration with new work that enables target gdb and gdbserver. Signed-off-by: Mark Hatle --- .../recipes-devtools/gdb/gdb-microblaze.inc | 12 +- .../0001-Add-initial-port-of-linux-gdbserver.patch | 505 ------------- .../gdb/gdb/0001-Patch-MicroBlaze.patch | 505 +++++++++++++ ...0002-Initial-port-of-core-reading-support.patch | 2 +- ...ebug-message-when-register-is-unavailable.patch | 2 +- ...Add-build_gdbserver-yes-to-top-level-conf.patch | 2 +- ...005-Fixing-the-issues-related-to-GDB-7.12.patch | 201 +++++ .../gdb/0005-Initial-support-for-native-gdb.patch | 492 ------------ ...006-Fixing-the-issues-related-to-GDB-7.12.patch | 216 ------ ...tch-MicroBlaze-MicroBlaze-native-gdb-port.patch | 831 +++++++++++++++++++++ ...Patch-microblaze-Adding-64-bit-MB-support.patch | 186 +---- ...Blaze-these-changes-will-make-64-bit-vect.patch | 34 + ...8-gdb-Fix-microblaze-target-compilation-3.patch | 288 ------- ...Blaze-Added-m64-abi-for-64-bit-target-des.patch | 279 +++++++ ...Blaze-these-changes-will-make-64-bit-vect.patch | 34 - ...Blaze-Added-m64-abi-for-64-bit-target-des.patch | 279 ------- ...tch-MicroBlaze-Code-changes-for-gdbserver.patch | 401 ++++++++++ .../recipes-devtools/gdb/gdb_%.bbappend | 7 - 18 files changed, 2296 insertions(+), 1980 deletions(-) delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0001-Patch-MicroBlaze.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0005-Fixing-the-issues-related-to-GDB-7.12.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0005-Initial-support-for-native-gdb.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0006-Fixing-the-issues-related-to-GDB-7.12.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0008-gdb-Fix-microblaze-target-compilation-3.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch delete mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc index dddbaf82..da91a1b7 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc +++ b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc @@ -5,14 +5,14 @@ LTTNGUST:microblaze = "" FILESEXTRAPATHS:append := ":${THISDIR}/gdb" SRC_URI:append:microblaze = " \ - file://0001-Add-initial-port-of-linux-gdbserver.patch \ + file://0001-Patch-MicroBlaze.patch \ file://0002-Initial-port-of-core-reading-support.patch \ file://0003-Fix-debug-message-when-register-is-unavailable.patch \ file://0004-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \ - file://0005-Initial-support-for-native-gdb.patch \ - file://0006-Fixing-the-issues-related-to-GDB-7.12.patch \ + file://0005-Fixing-the-issues-related-to-GDB-7.12.patch \ + file://0006-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch \ file://0007-Patch-microblaze-Adding-64-bit-MB-support.patch \ - file://0008-gdb-Fix-microblaze-target-compilation-3.patch \ - file://0009-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch \ - file://0010-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch \ + file://0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch \ + file://0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch \ + file://0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch \ " diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch deleted file mode 100644 index bc1c1a93..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-initial-port-of-linux-gdbserver.patch +++ /dev/null @@ -1,505 +0,0 @@ -From 699248a2fc4b9334f5042e1657116ac6b67b7321 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 23 Jan 2017 19:07:44 +0530 -Subject: [PATCH 01/10] Add initial port of linux gdbserver add - gdb_proc_service_h to gdbserver microblaze-linux - -gdbserver needs to initialise the microblaze registers - -other archs use this step to run a *_arch_setup() to carry out all -architecture specific setup - may need to add in future - - * add linux-ptrace.o to gdbserver configure - * Update breakpoint opcode - * fix segfault on connecting gdbserver - * add microblaze_linux_memory_remove_breakpoint - * add set_solib_svr4_fetch_link_map_offsets - * add set_gdbarch_fetch_tls_load_module_address - * Force reading of r0 as 0, prevent stores - -Signed-off-by: David Holsgrove -Signed-off-by: Nathan Rossi - -Conflicts: - gdbserver/Makefile.in ---- - gdb/configure.host | 3 + - gdb/features/microblaze-linux.xml | 12 ++ - gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++ - gdb/microblaze-linux-tdep.c | 29 +++- - gdb/microblaze-tdep.c | 35 ++++- - gdb/microblaze-tdep.h | 4 +- - gdb/regformats/reg-microblaze.dat | 41 ++++++ - gdbserver/Makefile.in | 6 +- - gdbserver/configure.srv | 8 ++ - 9 files changed, 323 insertions(+), 4 deletions(-) - create mode 100644 gdb/features/microblaze-linux.xml - create mode 100644 gdb/gdbserver/linux-microblaze-low.c - create mode 100644 gdb/regformats/reg-microblaze.dat - -diff --git a/gdb/configure.host b/gdb/configure.host -index ce528237291..cf1a08e8b28 100644 ---- a/gdb/configure.host -+++ b/gdb/configure.host -@@ -65,6 +65,7 @@ hppa*) gdb_host_cpu=pa ;; - i[34567]86*) gdb_host_cpu=i386 ;; - m68*) gdb_host_cpu=m68k ;; - mips*) gdb_host_cpu=mips ;; -+microblaze*) gdb_host_cpu=microblaze ;; - powerpc* | rs6000) gdb_host_cpu=powerpc ;; - sparcv9 | sparc64) gdb_host_cpu=sparc ;; - s390*) gdb_host_cpu=s390 ;; -@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu) - mips*-*-freebsd*) gdb_host=fbsd ;; - mips64*-*-openbsd*) gdb_host=obsd64 ;; - -+microblaze*-*linux*) gdb_host=linux ;; -+ - powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*) - gdb_host=aix ;; - powerpc*-*-freebsd*) gdb_host=fbsd ;; -diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml -new file mode 100644 -index 00000000000..8983e66eb3d ---- /dev/null -+++ b/gdb/features/microblaze-linux.xml -@@ -0,0 +1,12 @@ -+ -+ -+ -+ -+ -+ GNU/Linux -+ -+ -diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c -new file mode 100644 -index 00000000000..cba5d6fc585 ---- /dev/null -+++ b/gdb/gdbserver/linux-microblaze-low.c -@@ -0,0 +1,189 @@ -+/* GNU/Linux/Microblaze specific low level interface, for the remote server for -+ GDB. -+ Copyright (C) 1995-2013 Free Software Foundation, Inc. -+ -+ This file is part of GDB. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+#include "server.h" -+#include "linux-low.h" -+ -+#include -+#include -+#include -+ -+#include "gdb_proc_service.h" -+ -+static int microblaze_regmap[] = -+ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), -+ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), -+ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), -+ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), -+ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), -+ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), -+ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), -+ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), -+ PT_PC, PT_MSR, PT_EAR, PT_ESR, -+ PT_FSR -+ }; -+ -+#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) -+ -+/* Defined in auto-generated file microblaze-linux.c. */ -+void init_registers_microblaze (void); -+ -+static int -+microblaze_cannot_store_register (int regno) -+{ -+ if (microblaze_regmap[regno] == -1 || regno == 0) -+ return 1; -+ -+ return 0; -+} -+ -+static int -+microblaze_cannot_fetch_register (int regno) -+{ -+ return 0; -+} -+ -+static CORE_ADDR -+microblaze_get_pc (struct regcache *regcache) -+{ -+ unsigned long pc; -+ -+ collect_register_by_name (regcache, "pc", &pc); -+ return (CORE_ADDR) pc; -+} -+ -+static void -+microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) -+{ -+ unsigned long newpc = pc; -+ -+ supply_register_by_name (regcache, "pc", &newpc); -+} -+ -+/* dbtrap insn */ -+/* brki r16, 0x18; */ -+static const unsigned long microblaze_breakpoint = 0xba0c0018; -+#define microblaze_breakpoint_len 4 -+ -+static int -+microblaze_breakpoint_at (CORE_ADDR where) -+{ -+ unsigned long insn; -+ -+ (*the_target->read_memory) (where, (unsigned char *) &insn, 4); -+ if (insn == microblaze_breakpoint) -+ return 1; -+ /* If necessary, recognize more trap instructions here. GDB only uses the -+ one. */ -+ return 0; -+} -+ -+static CORE_ADDR -+microblaze_reinsert_addr (struct regcache *regcache) -+{ -+ unsigned long pc; -+ collect_register_by_name (regcache, "r15", &pc); -+ return pc; -+} -+ -+#ifdef HAVE_PTRACE_GETREGS -+ -+static void -+microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) -+{ -+ int size = register_size (regno); -+ -+ memset (buf, 0, sizeof (long)); -+ -+ if (size < sizeof (long)) -+ collect_register (regcache, regno, buf + sizeof (long) - size); -+ else -+ collect_register (regcache, regno, buf); -+} -+ -+static void -+microblaze_supply_ptrace_register (struct regcache *regcache, -+ int regno, const char *buf) -+{ -+ int size = register_size (regno); -+ -+ if (regno == 0) { -+ unsigned long regbuf_0 = 0; -+ /* clobbering r0 so that it is always 0 as enforced by hardware */ -+ supply_register (regcache, regno, (const char*)®buf_0); -+ } else { -+ if (size < sizeof (long)) -+ supply_register (regcache, regno, buf + sizeof (long) - size); -+ else -+ supply_register (regcache, regno, buf); -+ } -+} -+ -+/* Provide only a fill function for the general register set. ps_lgetregs -+ will use this for NPTL support. */ -+ -+static void microblaze_fill_gregset (struct regcache *regcache, void *buf) -+{ -+ int i; -+ -+ for (i = 0; i < 32; i++) -+ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); -+} -+ -+static void -+microblaze_store_gregset (struct regcache *regcache, const void *buf) -+{ -+ int i; -+ -+ for (i = 0; i < 32; i++) -+ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); -+} -+ -+#endif /* HAVE_PTRACE_GETREGS */ -+ -+struct regset_info target_regsets[] = { -+#ifdef HAVE_PTRACE_GETREGS -+ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, -+ { 0, 0, 0, -1, -1, NULL, NULL }, -+#endif /* HAVE_PTRACE_GETREGS */ -+ { 0, 0, 0, -1, -1, NULL, NULL } -+}; -+ -+struct linux_target_ops the_low_target = { -+ init_registers_microblaze, -+ microblaze_num_regs, -+ microblaze_regmap, -+ NULL, -+ microblaze_cannot_fetch_register, -+ microblaze_cannot_store_register, -+ NULL, /* fetch_register */ -+ microblaze_get_pc, -+ microblaze_set_pc, -+ (const unsigned char *) µblaze_breakpoint, -+ microblaze_breakpoint_len, -+ microblaze_reinsert_addr, -+ 0, -+ microblaze_breakpoint_at, -+ NULL, -+ NULL, -+ NULL, -+ NULL, -+ microblaze_collect_ptrace_register, -+ microblaze_supply_ptrace_register, -+}; -diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index 3fc5e768120..0322b4ea813 100644 ---- a/gdb/microblaze-linux-tdep.c -+++ b/gdb/microblaze-linux-tdep.c -@@ -37,6 +37,22 @@ - #include "tramp-frame.h" - #include "linux-tdep.h" - -+static int microblaze_debug_flag = 0; -+ -+static void -+microblaze_debug (const char *fmt, ...) -+{ -+ if (microblaze_debug_flag) -+ { -+ va_list args; -+ -+ va_start (args, fmt); -+ printf_unfiltered ("MICROBLAZE LINUX: "); -+ vprintf_unfiltered (fmt, args); -+ va_end (args); -+ } -+} -+ - static int - microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) -@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, - /* Determine appropriate breakpoint contents and size for this address. */ - bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); - -+ /* Make sure we see the memory breakpoints. */ -+ scoped_restore restore_memory -+ = make_scoped_restore_show_memory_breakpoints (1); -+ - val = target_read_memory (addr, old_contents, bplen); - - /* If our breakpoint is no longer at the address, this means that the - program modified the code on us, so it is wrong to put back the - old value. */ - if (val == 0 && memcmp (bp, old_contents, bplen) == 0) -- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ { -+ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); -+ } - - return val; - } -@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, - /* Trampolines. */ - tramp_frame_prepend_unwinder (gdbarch, - µblaze_linux_sighandler_tramp_frame); -+ -+ /* Enable TLS support. */ -+ set_gdbarch_fetch_tls_load_module_address (gdbarch, -+ svr4_fetch_objfile_link_map); - } - - void _initialize_microblaze_linux_tdep (); -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index c263228856f..28c2ed9a74c 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) - constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; - - typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; -- -+static int -+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, -+ struct bp_target_info *bp_tgt) -+{ -+ CORE_ADDR addr = bp_tgt->placed_address; -+ const unsigned char *bp; -+ int val; -+ int bplen; -+ gdb_byte old_contents[BREAKPOINT_MAX]; -+ -+ /* Determine appropriate breakpoint contents and size for this address. */ -+ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); -+ if (bp == NULL) -+ error (_("Software breakpoints not implemented for this target.")); -+ -+ /* Make sure we see the memory breakpoints. */ -+ scoped_restore restore_memory -+ = make_scoped_restore_show_memory_breakpoints (1); -+ -+ val = target_read_memory (addr, old_contents, bplen); -+ -+ /* If our breakpoint is no longer at the address, this means that the -+ program modified the code on us, so it is wrong to put back the -+ old value. */ -+ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) -+ { -+ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); -+ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); -+ } -+ -+ return val; -+} - - /* Allocate and initialize a frame cache. */ - -@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - microblaze_breakpoint::kind_from_pc); - set_gdbarch_sw_breakpoint_from_kind (gdbarch, - microblaze_breakpoint::bp_from_kind); -+ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); - - set_gdbarch_frame_args_skip (gdbarch, 8); - -@@ -771,4 +803,5 @@ When non-zero, microblaze specific debugging is enabled."), - NULL, - &setdebuglist, &showdebuglist); - -+ - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 08af0d191c5..8a429cbf001 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -117,6 +117,8 @@ struct microblaze_frame_cache - - /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. - Only used for native debugging. */ --#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} -+#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} -+#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} -+ - - #endif /* microblaze-tdep.h */ -diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat -new file mode 100644 -index 00000000000..bd8a4384424 ---- /dev/null -+++ b/gdb/regformats/reg-microblaze.dat -@@ -0,0 +1,41 @@ -+name:microblaze -+expedite:r1,pc -+32:r0 -+32:r1 -+32:r2 -+32:r3 -+32:r4 -+32:r5 -+32:r6 -+32:r7 -+32:r8 -+32:r9 -+32:r10 -+32:r11 -+32:r12 -+32:r13 -+32:r14 -+32:r15 -+32:r16 -+32:r17 -+32:r18 -+32:r19 -+32:r20 -+32:r21 -+32:r22 -+32:r23 -+32:r24 -+32:r25 -+32:r26 -+32:r27 -+32:r28 -+32:r29 -+32:r30 -+32:r31 -+32:pc -+32:msr -+32:ear -+32:esr -+32:fsr -+32:slr -+32:shr -diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in -index 2bd3a578932..7bee1f1894e 100644 ---- a/gdbserver/Makefile.in -+++ b/gdbserver/Makefile.in -@@ -184,7 +184,8 @@ SFILES = \ - $(srcdir)/linux-ia64-low.cc \ - $(srcdir)/linux-low.cc \ - $(srcdir)/linux-m68k-low.cc \ -- $(srcdir)/linux-mips-low.cc \ -+ $(srcdir)/linux-microblaze-low.c \ -+ $(srcdir)/linux-mips-low.cc \ - $(srcdir)/linux-nios2-low.cc \ - $(srcdir)/linux-ppc-low.cc \ - $(srcdir)/linux-riscv-low.cc \ -@@ -221,6 +222,7 @@ SFILES = \ - $(srcdir)/../gdb/nat/linux-namespaces.c \ - $(srcdir)/../gdb/nat/linux-osdata.c \ - $(srcdir)/../gdb/nat/linux-personality.c \ -+ $(srcdir)/../gdb/nat/microblaze-linux.c \ - $(srcdir)/../gdb/nat/mips-linux-watch.c \ - $(srcdir)/../gdb/nat/ppc-linux.c \ - $(srcdir)/../gdb/nat/riscv-linux-tdesc.c \ -@@ -562,6 +564,8 @@ target/%.o: ../gdb/target/%.c - - %-generated.cc: ../gdb/regformats/rs6000/%.dat $(regdat_sh) - $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@ -+microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh) -+ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c - - # - # Dependency tracking. -diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv -index 0cb5072c8ab..9d68c24a92d 100644 ---- a/gdbserver/configure.srv -+++ b/gdbserver/configure.srv -@@ -166,6 +166,14 @@ case "${gdbserver_host}" in - srv_linux_usrregs=yes - srv_linux_thread_db=yes - ;; -+ microblaze*-*-linux*) srv_regobj="microblaze-linux.o" -+ srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " -+ srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" -+ srv_xmlfiles="microblaze-linux.xml" -+ srv_linux_regsets=yes -+ srv_linux_usrregs=yes -+ srv_linux_thread_db=yes -+ ;; - powerpc*-*-linux*) srv_regobj="powerpc-32l.o" - srv_regobj="${srv_regobj} powerpc-altivec32l.o" - srv_regobj="${srv_regobj} powerpc-vsx32l.o" --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0001-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Patch-MicroBlaze.patch new file mode 100644 index 00000000..b5a2726b --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0001-Patch-MicroBlaze.patch @@ -0,0 +1,505 @@ +From b7b3c1eb19b770b2d700dd3c9fa23a7ae225a72b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 16 Jun 2022 09:50:14 +0530 +Subject: [PATCH 01/10] [Patch,MicroBlaze] : Add initial port of linux + gdbserver add gdb_proc_service_h to gdbserver microblaze-linux + +gdbserver needs to initialise the microblaze registers + +other archs use this step to run a *_arch_setup() to carry out all +architecture specific setup - may need to add in future + + * add linux-ptrace.o to gdbserver configure + * Update breakpoint opcode + * fix segfault on connecting gdbserver + * add microblaze_linux_memory_remove_breakpoint + * add set_solib_svr4_fetch_link_map_offsets + * add set_gdbarch_fetch_tls_load_module_address + * Force reading of r0 as 0, prevent stores + +Signed-off-by: David Holsgrove +Signed-off-by: Nathan Rossi + +Conflicts: + gdbserver/Makefile.in +--- + gdb/configure.host | 3 + + gdb/features/microblaze-linux.xml | 12 ++ + gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++ + gdb/microblaze-linux-tdep.c | 29 +++- + gdb/microblaze-tdep.c | 35 ++++- + gdb/microblaze-tdep.h | 4 +- + gdb/regformats/reg-microblaze.dat | 41 ++++++ + gdbserver/Makefile.in | 6 +- + gdbserver/configure.srv | 8 ++ + 9 files changed, 323 insertions(+), 4 deletions(-) + create mode 100644 gdb/features/microblaze-linux.xml + create mode 100644 gdb/gdbserver/linux-microblaze-low.c + create mode 100644 gdb/regformats/reg-microblaze.dat + +diff --git a/gdb/configure.host b/gdb/configure.host +index ce528237291..cf1a08e8b28 100644 +--- a/gdb/configure.host ++++ b/gdb/configure.host +@@ -65,6 +65,7 @@ hppa*) gdb_host_cpu=pa ;; + i[34567]86*) gdb_host_cpu=i386 ;; + m68*) gdb_host_cpu=m68k ;; + mips*) gdb_host_cpu=mips ;; ++microblaze*) gdb_host_cpu=microblaze ;; + powerpc* | rs6000) gdb_host_cpu=powerpc ;; + sparcv9 | sparc64) gdb_host_cpu=sparc ;; + s390*) gdb_host_cpu=s390 ;; +@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu) + mips*-*-freebsd*) gdb_host=fbsd ;; + mips64*-*-openbsd*) gdb_host=obsd64 ;; + ++microblaze*-*linux*) gdb_host=linux ;; ++ + powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*) + gdb_host=aix ;; + powerpc*-*-freebsd*) gdb_host=fbsd ;; +diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml +new file mode 100644 +index 00000000000..8983e66eb3d +--- /dev/null ++++ b/gdb/features/microblaze-linux.xml +@@ -0,0 +1,12 @@ ++ ++ ++ ++ ++ ++ GNU/Linux ++ ++ +diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c +new file mode 100644 +index 00000000000..cba5d6fc585 +--- /dev/null ++++ b/gdb/gdbserver/linux-microblaze-low.c +@@ -0,0 +1,189 @@ ++/* GNU/Linux/Microblaze specific low level interface, for the remote server for ++ GDB. ++ Copyright (C) 1995-2013 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "server.h" ++#include "linux-low.h" ++ ++#include ++#include ++#include ++ ++#include "gdb_proc_service.h" ++ ++static int microblaze_regmap[] = ++ {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), ++ PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), ++ PT_GPR(8), PT_GPR(9), PT_GPR(10), PT_GPR(11), ++ PT_GPR(12), PT_GPR(13), PT_GPR(14), PT_GPR(15), ++ PT_GPR(16), PT_GPR(17), PT_GPR(18), PT_GPR(19), ++ PT_GPR(20), PT_GPR(21), PT_GPR(22), PT_GPR(23), ++ PT_GPR(24), PT_GPR(25), PT_GPR(26), PT_GPR(27), ++ PT_GPR(28), PT_GPR(29), PT_GPR(30), PT_GPR(31), ++ PT_PC, PT_MSR, PT_EAR, PT_ESR, ++ PT_FSR ++ }; ++ ++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) ++ ++/* Defined in auto-generated file microblaze-linux.c. */ ++void init_registers_microblaze (void); ++ ++static int ++microblaze_cannot_store_register (int regno) ++{ ++ if (microblaze_regmap[regno] == -1 || regno == 0) ++ return 1; ++ ++ return 0; ++} ++ ++static int ++microblaze_cannot_fetch_register (int regno) ++{ ++ return 0; ++} ++ ++static CORE_ADDR ++microblaze_get_pc (struct regcache *regcache) ++{ ++ unsigned long pc; ++ ++ collect_register_by_name (regcache, "pc", &pc); ++ return (CORE_ADDR) pc; ++} ++ ++static void ++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) ++{ ++ unsigned long newpc = pc; ++ ++ supply_register_by_name (regcache, "pc", &newpc); ++} ++ ++/* dbtrap insn */ ++/* brki r16, 0x18; */ ++static const unsigned long microblaze_breakpoint = 0xba0c0018; ++#define microblaze_breakpoint_len 4 ++ ++static int ++microblaze_breakpoint_at (CORE_ADDR where) ++{ ++ unsigned long insn; ++ ++ (*the_target->read_memory) (where, (unsigned char *) &insn, 4); ++ if (insn == microblaze_breakpoint) ++ return 1; ++ /* If necessary, recognize more trap instructions here. GDB only uses the ++ one. */ ++ return 0; ++} ++ ++static CORE_ADDR ++microblaze_reinsert_addr (struct regcache *regcache) ++{ ++ unsigned long pc; ++ collect_register_by_name (regcache, "r15", &pc); ++ return pc; ++} ++ ++#ifdef HAVE_PTRACE_GETREGS ++ ++static void ++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) ++{ ++ int size = register_size (regno); ++ ++ memset (buf, 0, sizeof (long)); ++ ++ if (size < sizeof (long)) ++ collect_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ collect_register (regcache, regno, buf); ++} ++ ++static void ++microblaze_supply_ptrace_register (struct regcache *regcache, ++ int regno, const char *buf) ++{ ++ int size = register_size (regno); ++ ++ if (regno == 0) { ++ unsigned long regbuf_0 = 0; ++ /* clobbering r0 so that it is always 0 as enforced by hardware */ ++ supply_register (regcache, regno, (const char*)®buf_0); ++ } else { ++ if (size < sizeof (long)) ++ supply_register (regcache, regno, buf + sizeof (long) - size); ++ else ++ supply_register (regcache, regno, buf); ++ } ++} ++ ++/* Provide only a fill function for the general register set. ps_lgetregs ++ will use this for NPTL support. */ ++ ++static void microblaze_fill_gregset (struct regcache *regcache, void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++static void ++microblaze_store_gregset (struct regcache *regcache, const void *buf) ++{ ++ int i; ++ ++ for (i = 0; i < 32; i++) ++ supply_register (regcache, i, (char *) buf + microblaze_regmap[i]); ++} ++ ++#endif /* HAVE_PTRACE_GETREGS */ ++ ++struct regset_info target_regsets[] = { ++#ifdef HAVE_PTRACE_GETREGS ++ { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, ++ { 0, 0, 0, -1, -1, NULL, NULL }, ++#endif /* HAVE_PTRACE_GETREGS */ ++ { 0, 0, 0, -1, -1, NULL, NULL } ++}; ++ ++struct linux_target_ops the_low_target = { ++ init_registers_microblaze, ++ microblaze_num_regs, ++ microblaze_regmap, ++ NULL, ++ microblaze_cannot_fetch_register, ++ microblaze_cannot_store_register, ++ NULL, /* fetch_register */ ++ microblaze_get_pc, ++ microblaze_set_pc, ++ (const unsigned char *) µblaze_breakpoint, ++ microblaze_breakpoint_len, ++ microblaze_reinsert_addr, ++ 0, ++ microblaze_breakpoint_at, ++ NULL, ++ NULL, ++ NULL, ++ NULL, ++ microblaze_collect_ptrace_register, ++ microblaze_supply_ptrace_register, ++}; +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index 3fc5e768120..0322b4ea813 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,22 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + ++static int microblaze_debug_flag = 0; ++ ++static void ++microblaze_debug (const char *fmt, ...) ++{ ++ if (microblaze_debug_flag) ++ { ++ va_list args; ++ ++ va_start (args, fmt); ++ printf_unfiltered ("MICROBLAZE LINUX: "); ++ vprintf_unfiltered (fmt, args); ++ va_end (args); ++ } ++} ++ + static int + microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, + /* Determine appropriate breakpoint contents and size for this address. */ + bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); + ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ + val = target_read_memory (addr, old_contents, bplen); + + /* If our breakpoint is no longer at the address, this means that the + program modified the code on us, so it is wrong to put back the + old value. */ + if (val == 0 && memcmp (bp, old_contents, bplen) == 0) +- val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } + + return val; + } +@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info, + /* Trampolines. */ + tramp_frame_prepend_unwinder (gdbarch, + µblaze_linux_sighandler_tramp_frame); ++ ++ /* Enable TLS support. */ ++ set_gdbarch_fetch_tls_load_module_address (gdbarch, ++ svr4_fetch_objfile_link_map); + } + + void _initialize_microblaze_linux_tdep (); +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index c263228856f..28c2ed9a74c 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc) + constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; + + typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; +- ++static int ++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, ++ struct bp_target_info *bp_tgt) ++{ ++ CORE_ADDR addr = bp_tgt->placed_address; ++ const unsigned char *bp; ++ int val; ++ int bplen; ++ gdb_byte old_contents[BREAKPOINT_MAX]; ++ ++ /* Determine appropriate breakpoint contents and size for this address. */ ++ bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen); ++ if (bp == NULL) ++ error (_("Software breakpoints not implemented for this target.")); ++ ++ /* Make sure we see the memory breakpoints. */ ++ scoped_restore restore_memory ++ = make_scoped_restore_show_memory_breakpoints (1); ++ ++ val = target_read_memory (addr, old_contents, bplen); ++ ++ /* If our breakpoint is no longer at the address, this means that the ++ program modified the code on us, so it is wrong to put back the ++ old value. */ ++ if (val == 0 && memcmp (bp, old_contents, bplen) == 0) ++ { ++ val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen); ++ microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr); ++ } ++ ++ return val; ++} + + /* Allocate and initialize a frame cache. */ + +@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + microblaze_breakpoint::bp_from_kind); ++ set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + + set_gdbarch_frame_args_skip (gdbarch, 8); + +@@ -771,4 +803,5 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + ++ + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 08af0d191c5..8a429cbf001 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -117,6 +117,8 @@ struct microblaze_frame_cache + + /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used. + Only used for native debugging. */ +-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60} ++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18} ++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba} ++ + + #endif /* microblaze-tdep.h */ +diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat +new file mode 100644 +index 00000000000..bd8a4384424 +--- /dev/null ++++ b/gdb/regformats/reg-microblaze.dat +@@ -0,0 +1,41 @@ ++name:microblaze ++expedite:r1,pc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:pc ++32:msr ++32:ear ++32:esr ++32:fsr ++32:slr ++32:shr +diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in +index 2bd3a578932..46b5a0c7c60 100644 +--- a/gdbserver/Makefile.in ++++ b/gdbserver/Makefile.in +@@ -184,7 +184,8 @@ SFILES = \ + $(srcdir)/linux-ia64-low.cc \ + $(srcdir)/linux-low.cc \ + $(srcdir)/linux-m68k-low.cc \ +- $(srcdir)/linux-mips-low.cc \ ++ $(srcdir)/linux-microblaze-low.c \ ++ $(srcdir)/linux-mips-low.cc \ + $(srcdir)/linux-nios2-low.cc \ + $(srcdir)/linux-ppc-low.cc \ + $(srcdir)/linux-riscv-low.cc \ +@@ -221,6 +222,7 @@ SFILES = \ + $(srcdir)/../gdb/nat/linux-namespaces.c \ + $(srcdir)/../gdb/nat/linux-osdata.c \ + $(srcdir)/../gdb/nat/linux-personality.c \ ++ $(srcdir)/../gdb/nat/microblaze-linux.c \ + $(srcdir)/../gdb/nat/mips-linux-watch.c \ + $(srcdir)/../gdb/nat/ppc-linux.c \ + $(srcdir)/../gdb/nat/riscv-linux-tdesc.c \ +@@ -562,6 +564,8 @@ target/%.o: ../gdb/target/%.c + + %-generated.cc: ../gdb/regformats/rs6000/%.dat $(regdat_sh) + $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@ ++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh) ++ $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c + + # + # Dependency tracking. +diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv +index 0cb5072c8ab..9d68c24a92d 100644 +--- a/gdbserver/configure.srv ++++ b/gdbserver/configure.srv +@@ -166,6 +166,14 @@ case "${gdbserver_host}" in + srv_linux_usrregs=yes + srv_linux_thread_db=yes + ;; ++ microblaze*-*-linux*) srv_regobj="microblaze-linux.o" ++ srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " ++ srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" ++ srv_xmlfiles="microblaze-linux.xml" ++ srv_linux_regsets=yes ++ srv_linux_usrregs=yes ++ srv_linux_thread_db=yes ++ ;; + powerpc*-*-linux*) srv_regobj="powerpc-32l.o" + srv_regobj="${srv_regobj} powerpc-altivec32l.o" + srv_regobj="${srv_regobj} powerpc-vsx32l.o" +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Initial-port-of-core-reading-support.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Initial-port-of-core-reading-support.patch index d49a7fe6..352ed92e 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0002-Initial-port-of-core-reading-support.patch +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0002-Initial-port-of-core-reading-support.patch @@ -1,4 +1,4 @@ -From eae6f2fc7324729056f4bd3bfa66c0c5887d7b94 Mon Sep 17 00:00:00 2001 +From da36639f95d23083088a27c27f631d304ae316f1 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati Date: Tue, 24 Jan 2017 14:55:56 +0530 Subject: [PATCH 02/10] Initial port of core reading support Added support for diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch index 68d90f27..255bb9b5 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0003-Fix-debug-message-when-register-is-unavailable.patch @@ -1,4 +1,4 @@ -From 80c56ef8463c23f51759f5c64ce0165e259a4071 Mon Sep 17 00:00:00 2001 +From da93f5715ff333ac4807b73fe678dde21fb3bd6c Mon Sep 17 00:00:00 2001 From: Nathan Rossi Date: Tue, 8 May 2012 18:11:17 +1000 Subject: [PATCH 03/10] Fix debug message when register is unavailable diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0004-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0004-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch index e63a696d..f1555b8a 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0004-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0004-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch @@ -1,4 +1,4 @@ -From 7d970a0c616063a5095ce3725efed0feb40ceb30 Mon Sep 17 00:00:00 2001 +From 82ee589db2c1191fb274f4a76e217df318f8d6b2 Mon Sep 17 00:00:00 2001 From: David Holsgrove Date: Mon, 16 Dec 2013 16:37:32 +1000 Subject: [PATCH 04/10] microblaze: Add build_gdbserver=yes to top level diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fixing-the-issues-related-to-GDB-7.12.patch new file mode 100644 index 00000000..48e203a9 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fixing-the-issues-related-to-GDB-7.12.patch @@ -0,0 +1,201 @@ +From ca1158d19ab9879167ca9fbe2fdf8d19094cc53f Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Fri, 17 Feb 2017 14:09:40 +0530 +Subject: [PATCH 05/10] Fixing the issues related to GDB-7.12 + +added all the required function which are new in 7.12 and removed +few deprecated functions from 7.6 + +Conflicts: + gdb/config/microblaze/linux.mh +--- + gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++---- + gdb/microblaze-tdep.h | 1 + + gdbserver/configure.srv | 3 +- + 3 files changed, 86 insertions(+), 15 deletions(-) + +diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c +index cba5d6fc585..a2733f3c21c 100644 +--- a/gdb/gdbserver/linux-microblaze-low.c ++++ b/gdb/gdbserver/linux-microblaze-low.c +@@ -39,10 +39,11 @@ static int microblaze_regmap[] = + PT_FSR + }; + +-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) ++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) + + /* Defined in auto-generated file microblaze-linux.c. */ + void init_registers_microblaze (void); ++extern const struct target_desc *tdesc_microblaze; + + static int + microblaze_cannot_store_register (int regno) +@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) + static const unsigned long microblaze_breakpoint = 0xba0c0018; + #define microblaze_breakpoint_len 4 + ++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ ++ ++static const gdb_byte * ++microblaze_sw_breakpoint_from_kind (int kind, int *size) ++{ ++ *size = microblaze_breakpoint_len; ++ return (const gdb_byte *) µblaze_breakpoint; ++} ++ + static int + microblaze_breakpoint_at (CORE_ADDR where) + { +@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache) + static void + microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) + { +- int size = register_size (regno); ++ int size = register_size (regcache->tdesc, regno); + + memset (buf, 0, sizeof (long)); + +@@ -121,7 +131,7 @@ static void + microblaze_supply_ptrace_register (struct regcache *regcache, + int regno, const char *buf) + { +- int size = register_size (regno); ++ int size = register_size (regcache->tdesc, regno); + + if (regno == 0) { + unsigned long regbuf_0 = 0; +@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf) + + #endif /* HAVE_PTRACE_GETREGS */ + +-struct regset_info target_regsets[] = { ++static struct regset_info microblaze_regsets[] = { + #ifdef HAVE_PTRACE_GETREGS + { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, +- { 0, 0, 0, -1, -1, NULL, NULL }, ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, + #endif /* HAVE_PTRACE_GETREGS */ +- { 0, 0, 0, -1, -1, NULL, NULL } ++ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, ++ NULL_REGSET + }; + ++static struct usrregs_info microblaze_usrregs_info = ++ { ++ microblaze_num_regs, ++ microblaze_regmap, ++ }; ++ ++static struct regsets_info microblaze_regsets_info = ++ { ++ microblaze_regsets, /* regsets */ ++ 0, /* num_regsets */ ++ NULL, /* disabled_regsets */ ++ }; ++ ++static struct regs_info regs_info = ++ { ++ NULL, /* regset_bitmap */ ++ µblaze_usrregs_info, ++ µblaze_regsets_info ++ }; ++ ++static const struct regs_info * ++microblaze_regs_info (void) ++{ ++ return ®s_info; ++} ++ ++/* Support for hardware single step. */ ++ ++static int ++microblaze_supports_hardware_single_step (void) ++{ ++ return 1; ++} ++ ++ ++static void ++microblaze_arch_setup (void) ++{ ++ current_process ()->tdesc = tdesc_microblaze; ++} ++ + struct linux_target_ops the_low_target = { +- init_registers_microblaze, +- microblaze_num_regs, +- microblaze_regmap, +- NULL, ++ microblaze_arch_setup, ++ microblaze_regs_info, + microblaze_cannot_fetch_register, + microblaze_cannot_store_register, + NULL, /* fetch_register */ + microblaze_get_pc, + microblaze_set_pc, +- (const unsigned char *) µblaze_breakpoint, +- microblaze_breakpoint_len, +- microblaze_reinsert_addr, ++ NULL, ++ microblaze_sw_breakpoint_from_kind, ++ NULL, + 0, + microblaze_breakpoint_at, + NULL, + NULL, + NULL, + NULL, ++ NULL, + microblaze_collect_ptrace_register, + microblaze_supply_ptrace_register, ++ NULL, /* siginfo_fixup */ ++ NULL, /* new_process */ ++ NULL, /* new_thread */ ++ NULL, /* new_fork */ ++ NULL, /* prepare_to_resume */ ++ NULL, /* process_qsupported */ ++ NULL, /* supports_tracepoints */ ++ NULL, /* get_thread_area */ ++ NULL, /* install_fast_tracepoint_jump_pad */ ++ NULL, /* emit_ops */ ++ NULL, /* get_min_fast_tracepoint_insn_len */ ++ NULL, /* supports_range_stepping */ ++ NULL, /* breakpoint_kind_from_current_state */ ++ microblaze_supports_hardware_single_step, + }; ++ ++void ++initialize_low_arch (void) ++{ ++ init_registers_microblaze (); ++} +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index e91991b8dba..872a3931f20 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -24,6 +24,7 @@ + /* Microblaze architecture-specific information. */ + struct microblaze_gregset + { ++ microblaze_gregset() {} + unsigned int gregs[32]; + unsigned int fpregs[32]; + unsigned int pregs[16]; +diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv +index 9d68c24a92d..af10cb05683 100644 +--- a/gdbserver/configure.srv ++++ b/gdbserver/configure.srv +@@ -167,8 +167,7 @@ case "${gdbserver_host}" in + srv_linux_thread_db=yes + ;; + microblaze*-*-linux*) srv_regobj="microblaze-linux.o" +- srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " +- srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" ++ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o " + srv_xmlfiles="microblaze-linux.xml" + srv_linux_regsets=yes + srv_linux_usrregs=yes +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Initial-support-for-native-gdb.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0005-Initial-support-for-native-gdb.patch deleted file mode 100644 index 3482bcd8..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0005-Initial-support-for-native-gdb.patch +++ /dev/null @@ -1,492 +0,0 @@ -From bac086097dfa813fcc0b978dc32eb9ae469bf4a8 Mon Sep 17 00:00:00 2001 -From: David Holsgrove -Date: Fri, 20 Jul 2012 15:18:35 +1000 -Subject: [PATCH 05/10] Initial support for native gdb - -microblaze: Follow PPC method of getting setting registers -using PTRACE PEEK/POKE - -Signed-off-by: David Holsgrove ---- - gdb/Makefile.in | 2 + - gdb/config/microblaze/linux.mh | 9 + - gdb/microblaze-linux-nat.c | 431 +++++++++++++++++++++++++++++++++ - 3 files changed, 442 insertions(+) - create mode 100644 gdb/config/microblaze/linux.mh - create mode 100644 gdb/microblaze-linux-nat.c - -diff --git a/gdb/Makefile.in b/gdb/Makefile.in -index ec371fc7e52..2e8d4cfe82e 100644 ---- a/gdb/Makefile.in -+++ b/gdb/Makefile.in -@@ -1336,6 +1336,7 @@ HFILES_NO_SRCDIR = \ - memory-map.h \ - memrange.h \ - microblaze-tdep.h \ -+ microblaze-linux-tdep.h \ - mips-linux-tdep.h \ - mips-nbsd-tdep.h \ - mips-tdep.h \ -@@ -2216,6 +2217,7 @@ ALLDEPFILES = \ - m68k-tdep.c \ - microblaze-linux-tdep.c \ - microblaze-tdep.c \ -+ microblaze-linux-nat.c \ - mingw-hdep.c \ - mips-fbsd-nat.c \ - mips-fbsd-tdep.c \ -diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh -new file mode 100644 -index 00000000000..a4eaf540e1d ---- /dev/null -+++ b/gdb/config/microblaze/linux.mh -@@ -0,0 +1,9 @@ -+# Host: Microblaze, running Linux -+ -+NAT_FILE= config/nm-linux.h -+NATDEPFILES= inf-ptrace.o fork-child.o \ -+ microblaze-linux-nat.o proc-service.o linux-thread-db.o \ -+ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o -+NAT_CDEPS = $(srcdir)/proc-service.list -+ -+LOADLIBES = -ldl $(RDYNAMIC) -diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c -new file mode 100644 -index 00000000000..e9b8c9c5221 ---- /dev/null -+++ b/gdb/microblaze-linux-nat.c -@@ -0,0 +1,431 @@ -+/* Microblaze GNU/Linux native support. -+ -+ Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free -+ Software Foundation, Inc. -+ -+ This file is part of GDB. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program. If not, see . */ -+ -+#include "defs.h" -+#include "arch-utils.h" -+#include "dis-asm.h" -+#include "frame.h" -+#include "trad-frame.h" -+#include "symtab.h" -+#include "value.h" -+#include "gdbcmd.h" -+#include "breakpoint.h" -+#include "inferior.h" -+#include "regcache.h" -+#include "target.h" -+#include "frame.h" -+#include "frame-base.h" -+#include "frame-unwind.h" -+#include "dwarf2-frame.h" -+#include "osabi.h" -+ -+#include "gdb_assert.h" -+#include "gdb_string.h" -+#include "target-descriptions.h" -+#include "opcodes/microblaze-opcm.h" -+#include "opcodes/microblaze-dis.h" -+ -+#include "linux-nat.h" -+#include "target-descriptions.h" -+ -+#include -+#include -+#include -+#include -+ -+/* Prototypes for supply_gregset etc. */ -+#include "gregset.h" -+ -+#include "microblaze-tdep.h" -+ -+#include -+#include "auxv.h" -+ -+/* Defines ps_err_e, struct ps_prochandle. */ -+#include "gdb_proc_service.h" -+ -+/* On GNU/Linux, threads are implemented as pseudo-processes, in which -+ case we may be tracing more than one process at a time. In that -+ case, inferior_ptid will contain the main process ID and the -+ individual thread (process) ID. get_thread_id () is used to get -+ the thread id if it's available, and the process id otherwise. */ -+ -+int -+get_thread_id (ptid_t ptid) -+{ -+ int tid = TIDGET (ptid); -+ if (0 == tid) -+ tid = PIDGET (ptid); -+ return tid; -+} -+ -+#define GET_THREAD_ID(PTID) get_thread_id (PTID) -+ -+/* Non-zero if our kernel may support the PTRACE_GETREGS and -+ PTRACE_SETREGS requests, for reading and writing the -+ general-purpose registers. Zero if we've tried one of -+ them and gotten an error. */ -+int have_ptrace_getsetregs = 1; -+ -+static int -+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) -+{ -+ int u_addr = -1; -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace -+ interface, and not the wordsize of the program's ABI. */ -+ int wordsize = sizeof (long); -+ -+ /* General purpose registers occupy 1 slot each in the buffer. */ -+ if (regno >= MICROBLAZE_R0_REGNUM -+ && regno <= MICROBLAZE_FSR_REGNUM) -+ u_addr = (regno * wordsize); -+ -+ return u_addr; -+} -+ -+ -+static void -+fetch_register (struct regcache *regcache, int tid, int regno) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ /* This isn't really an address. But ptrace thinks of it as one. */ -+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); -+ int bytes_transferred; -+ unsigned int offset; /* Offset of registers within the u area. */ -+ char buf[MAX_REGISTER_SIZE]; -+ -+ if (regaddr == -1) -+ { -+ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ -+ regcache_raw_supply (regcache, regno, buf); -+ return; -+ } -+ -+ /* Read the raw register using sizeof(long) sized chunks. On a -+ 32-bit platform, 64-bit floating-point registers will require two -+ transfers. */ -+ for (bytes_transferred = 0; -+ bytes_transferred < register_size (gdbarch, regno); -+ bytes_transferred += sizeof (long)) -+ { -+ long l; -+ -+ errno = 0; -+ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); -+ regaddr += sizeof (long); -+ if (errno != 0) -+ { -+ char message[128]; -+ sprintf (message, "reading register %s (#%d)", -+ gdbarch_register_name (gdbarch, regno), regno); -+ perror_with_name (message); -+ } -+ memcpy (&buf[bytes_transferred], &l, sizeof (l)); -+ } -+ -+ /* Now supply the register. Keep in mind that the regcache's idea -+ of the register's size may not be a multiple of sizeof -+ (long). */ -+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) -+ { -+ /* Little-endian values are always found at the left end of the -+ bytes transferred. */ -+ regcache_raw_supply (regcache, regno, buf); -+ } -+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -+ { -+ /* Big-endian values are found at the right end of the bytes -+ transferred. */ -+ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); -+ regcache_raw_supply (regcache, regno, buf + padding); -+ } -+ else -+ internal_error (__FILE__, __LINE__, -+ _("fetch_register: unexpected byte order: %d"), -+ gdbarch_byte_order (gdbarch)); -+} -+ -+/* This function actually issues the request to ptrace, telling -+ it to get all general-purpose registers and put them into the -+ specified regset. -+ -+ If the ptrace request does not exist, this function returns 0 -+ and properly sets the have_ptrace_* flag. If the request fails, -+ this function calls perror_with_name. Otherwise, if the request -+ succeeds, then the regcache gets filled and 1 is returned. */ -+static int -+fetch_all_gp_regs (struct regcache *regcache, int tid) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ gdb_gregset_t gregset; -+ -+ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) -+ { -+ if (errno == EIO) -+ { -+ have_ptrace_getsetregs = 0; -+ return 0; -+ } -+ perror_with_name (_("Couldn't get general-purpose registers.")); -+ } -+ -+ supply_gregset (regcache, (const gdb_gregset_t *) &gregset); -+ -+ return 1; -+} -+ -+ -+/* This is a wrapper for the fetch_all_gp_regs function. It is -+ responsible for verifying if this target has the ptrace request -+ that can be used to fetch all general-purpose registers at one -+ shot. If it doesn't, then we should fetch them using the -+ old-fashioned way, which is to iterate over the registers and -+ request them one by one. */ -+static void -+fetch_gp_regs (struct regcache *regcache, int tid) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ int i; -+ -+ if (have_ptrace_getsetregs) -+ if (fetch_all_gp_regs (regcache, tid)) -+ return; -+ -+ /* If we've hit this point, it doesn't really matter which -+ architecture we are using. We just need to read the -+ registers in the "old-fashioned way". */ -+ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) -+ fetch_register (regcache, tid, i); -+} -+ -+ -+static void -+store_register (const struct regcache *regcache, int tid, int regno) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ /* This isn't really an address. But ptrace thinks of it as one. */ -+ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); -+ int i; -+ size_t bytes_to_transfer; -+ char buf[MAX_REGISTER_SIZE]; -+ -+ if (regaddr == -1) -+ return; -+ -+ /* First collect the register. Keep in mind that the regcache's -+ idea of the register's size may not be a multiple of sizeof -+ (long). */ -+ memset (buf, 0, sizeof buf); -+ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); -+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) -+ { -+ /* Little-endian values always sit at the left end of the buffer. */ -+ regcache_raw_collect (regcache, regno, buf); -+ } -+ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) -+ { -+ /* Big-endian values sit at the right end of the buffer. */ -+ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); -+ regcache_raw_collect (regcache, regno, buf + padding); -+ } -+ -+ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) -+ { -+ long l; -+ -+ memcpy (&l, &buf[i], sizeof (l)); -+ errno = 0; -+ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); -+ regaddr += sizeof (long); -+ -+ if (errno != 0) -+ { -+ char message[128]; -+ sprintf (message, "writing register %s (#%d)", -+ gdbarch_register_name (gdbarch, regno), regno); -+ perror_with_name (message); -+ } -+ } -+} -+ -+/* This function actually issues the request to ptrace, telling -+ it to store all general-purpose registers present in the specified -+ regset. -+ -+ If the ptrace request does not exist, this function returns 0 -+ and properly sets the have_ptrace_* flag. If the request fails, -+ this function calls perror_with_name. Otherwise, if the request -+ succeeds, then the regcache is stored and 1 is returned. */ -+static int -+store_all_gp_regs (const struct regcache *regcache, int tid, int regno) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ gdb_gregset_t gregset; -+ -+ if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) -+ { -+ if (errno == EIO) -+ { -+ have_ptrace_getsetregs = 0; -+ return 0; -+ } -+ perror_with_name (_("Couldn't get general-purpose registers.")); -+ } -+ -+ fill_gregset (regcache, &gregset, regno); -+ -+ if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) -+ { -+ if (errno == EIO) -+ { -+ have_ptrace_getsetregs = 0; -+ return 0; -+ } -+ perror_with_name (_("Couldn't set general-purpose registers.")); -+ } -+ -+ return 1; -+} -+ -+/* This is a wrapper for the store_all_gp_regs function. It is -+ responsible for verifying if this target has the ptrace request -+ that can be used to store all general-purpose registers at one -+ shot. If it doesn't, then we should store them using the -+ old-fashioned way, which is to iterate over the registers and -+ store them one by one. */ -+static void -+store_gp_regs (const struct regcache *regcache, int tid, int regno) -+{ -+ struct gdbarch *gdbarch = get_regcache_arch (regcache); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ int i; -+ -+ if (have_ptrace_getsetregs) -+ if (store_all_gp_regs (regcache, tid, regno)) -+ return; -+ -+ /* If we hit this point, it doesn't really matter which -+ architecture we are using. We just need to store the -+ registers in the "old-fashioned way". */ -+ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) -+ store_register (regcache, tid, i); -+} -+ -+ -+/* Fetch registers from the child process. Fetch all registers if -+ regno == -1, otherwise fetch all general registers or all floating -+ point registers depending upon the value of regno. */ -+ -+static void -+microblaze_linux_fetch_inferior_registers (struct target_ops *ops, -+ struct regcache *regcache, int regno) -+{ -+ /* Get the thread id for the ptrace call. */ -+ int tid = GET_THREAD_ID (inferior_ptid); -+ -+ if (regno == -1) -+ fetch_gp_regs (regcache, tid); -+ else -+ fetch_register (regcache, tid, regno); -+} -+ -+/* Store registers back into the inferior. Store all registers if -+ regno == -1, otherwise store all general registers or all floating -+ point registers depending upon the value of regno. */ -+ -+static void -+microblaze_linux_store_inferior_registers (struct target_ops *ops, -+ struct regcache *regcache, int regno) -+{ -+ /* Get the thread id for the ptrace call. */ -+ int tid = GET_THREAD_ID (inferior_ptid); -+ -+ if (regno >= 0) -+ store_register (regcache, tid, regno); -+ else -+ store_gp_regs (regcache, tid, -1); -+} -+ -+/* Wrapper functions for the standard regset handling, used by -+ thread debugging. */ -+ -+void -+fill_gregset (const struct regcache *regcache, -+ gdb_gregset_t *gregsetp, int regno) -+{ -+ microblaze_collect_gregset (NULL, regcache, regno, gregsetp); -+} -+ -+void -+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) -+{ -+ microblaze_supply_gregset (NULL, regcache, -1, gregsetp); -+} -+ -+void -+fill_fpregset (const struct regcache *regcache, -+ gdb_fpregset_t *fpregsetp, int regno) -+{ -+ /* FIXME. */ -+} -+ -+void -+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) -+{ -+ /* FIXME. */ -+} -+ -+static const struct target_desc * -+microblaze_linux_read_description (struct target_ops *ops) -+{ -+ CORE_ADDR microblaze_hwcap = 0; -+ -+ if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1) -+ return NULL; -+ -+ return NULL; -+} -+ -+ -+void _initialize_microblaze_linux_nat (void); -+ -+void -+_initialize_microblaze_linux_nat (void) -+{ -+ struct target_ops *t; -+ -+ /* Fill in the generic GNU/Linux methods. */ -+ t = linux_target (); -+ -+ /* Add our register access methods. */ -+ t->to_fetch_registers = microblaze_linux_fetch_inferior_registers; -+ t->to_store_registers = microblaze_linux_store_inferior_registers; -+ -+ t->to_read_description = microblaze_linux_read_description; -+ -+ /* Register the target. */ -+ linux_nat_add_target (t); -+} --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fixing-the-issues-related-to-GDB-7.12.patch deleted file mode 100644 index eb1efa71..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fixing-the-issues-related-to-GDB-7.12.patch +++ /dev/null @@ -1,216 +0,0 @@ -From 41b0d54fa00ce765e9a2ce09136938b72b2b96d7 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Fri, 17 Feb 2017 14:09:40 +0530 -Subject: [PATCH 06/10] Fixing the issues related to GDB-7.12 - -added all the required function which are new in 7.12 and removed -few deprecated functions from 7.6 ---- - gdb/config/microblaze/linux.mh | 4 +- - gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++---- - gdb/microblaze-tdep.h | 1 + - gdbserver/configure.srv | 3 +- - 4 files changed, 89 insertions(+), 16 deletions(-) - -diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh -index a4eaf540e1d..74a53b854a4 100644 ---- a/gdb/config/microblaze/linux.mh -+++ b/gdb/config/microblaze/linux.mh -@@ -1,9 +1,11 @@ - # Host: Microblaze, running Linux - -+#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o - NAT_FILE= config/nm-linux.h - NATDEPFILES= inf-ptrace.o fork-child.o \ - microblaze-linux-nat.o proc-service.o linux-thread-db.o \ -- linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o -+ linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \ -+ linux-waitpid.o linux-personality.o linux-namespaces.o - NAT_CDEPS = $(srcdir)/proc-service.list - - LOADLIBES = -ldl $(RDYNAMIC) -diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c -index cba5d6fc585..a2733f3c21c 100644 ---- a/gdb/gdbserver/linux-microblaze-low.c -+++ b/gdb/gdbserver/linux-microblaze-low.c -@@ -39,10 +39,11 @@ static int microblaze_regmap[] = - PT_FSR - }; - --#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0]) -+#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) - - /* Defined in auto-generated file microblaze-linux.c. */ - void init_registers_microblaze (void); -+extern const struct target_desc *tdesc_microblaze; - - static int - microblaze_cannot_store_register (int regno) -@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) - static const unsigned long microblaze_breakpoint = 0xba0c0018; - #define microblaze_breakpoint_len 4 - -+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ -+ -+static const gdb_byte * -+microblaze_sw_breakpoint_from_kind (int kind, int *size) -+{ -+ *size = microblaze_breakpoint_len; -+ return (const gdb_byte *) µblaze_breakpoint; -+} -+ - static int - microblaze_breakpoint_at (CORE_ADDR where) - { -@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache) - static void - microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) - { -- int size = register_size (regno); -+ int size = register_size (regcache->tdesc, regno); - - memset (buf, 0, sizeof (long)); - -@@ -121,7 +131,7 @@ static void - microblaze_supply_ptrace_register (struct regcache *regcache, - int regno, const char *buf) - { -- int size = register_size (regno); -+ int size = register_size (regcache->tdesc, regno); - - if (regno == 0) { - unsigned long regbuf_0 = 0; -@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf) - - #endif /* HAVE_PTRACE_GETREGS */ - --struct regset_info target_regsets[] = { -+static struct regset_info microblaze_regsets[] = { - #ifdef HAVE_PTRACE_GETREGS - { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, -- { 0, 0, 0, -1, -1, NULL, NULL }, -+ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, - #endif /* HAVE_PTRACE_GETREGS */ -- { 0, 0, 0, -1, -1, NULL, NULL } -+ { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, -+ NULL_REGSET - }; - -+static struct usrregs_info microblaze_usrregs_info = -+ { -+ microblaze_num_regs, -+ microblaze_regmap, -+ }; -+ -+static struct regsets_info microblaze_regsets_info = -+ { -+ microblaze_regsets, /* regsets */ -+ 0, /* num_regsets */ -+ NULL, /* disabled_regsets */ -+ }; -+ -+static struct regs_info regs_info = -+ { -+ NULL, /* regset_bitmap */ -+ µblaze_usrregs_info, -+ µblaze_regsets_info -+ }; -+ -+static const struct regs_info * -+microblaze_regs_info (void) -+{ -+ return ®s_info; -+} -+ -+/* Support for hardware single step. */ -+ -+static int -+microblaze_supports_hardware_single_step (void) -+{ -+ return 1; -+} -+ -+ -+static void -+microblaze_arch_setup (void) -+{ -+ current_process ()->tdesc = tdesc_microblaze; -+} -+ - struct linux_target_ops the_low_target = { -- init_registers_microblaze, -- microblaze_num_regs, -- microblaze_regmap, -- NULL, -+ microblaze_arch_setup, -+ microblaze_regs_info, - microblaze_cannot_fetch_register, - microblaze_cannot_store_register, - NULL, /* fetch_register */ - microblaze_get_pc, - microblaze_set_pc, -- (const unsigned char *) µblaze_breakpoint, -- microblaze_breakpoint_len, -- microblaze_reinsert_addr, -+ NULL, -+ microblaze_sw_breakpoint_from_kind, -+ NULL, - 0, - microblaze_breakpoint_at, - NULL, - NULL, - NULL, - NULL, -+ NULL, - microblaze_collect_ptrace_register, - microblaze_supply_ptrace_register, -+ NULL, /* siginfo_fixup */ -+ NULL, /* new_process */ -+ NULL, /* new_thread */ -+ NULL, /* new_fork */ -+ NULL, /* prepare_to_resume */ -+ NULL, /* process_qsupported */ -+ NULL, /* supports_tracepoints */ -+ NULL, /* get_thread_area */ -+ NULL, /* install_fast_tracepoint_jump_pad */ -+ NULL, /* emit_ops */ -+ NULL, /* get_min_fast_tracepoint_insn_len */ -+ NULL, /* supports_range_stepping */ -+ NULL, /* breakpoint_kind_from_current_state */ -+ microblaze_supports_hardware_single_step, - }; -+ -+void -+initialize_low_arch (void) -+{ -+ init_registers_microblaze (); -+} -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index e91991b8dba..872a3931f20 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -24,6 +24,7 @@ - /* Microblaze architecture-specific information. */ - struct microblaze_gregset - { -+ microblaze_gregset() {} - unsigned int gregs[32]; - unsigned int fpregs[32]; - unsigned int pregs[16]; -diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv -index 9d68c24a92d..af10cb05683 100644 ---- a/gdbserver/configure.srv -+++ b/gdbserver/configure.srv -@@ -167,8 +167,7 @@ case "${gdbserver_host}" in - srv_linux_thread_db=yes - ;; - microblaze*-*-linux*) srv_regobj="microblaze-linux.o" -- srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o " -- srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o" -+ srv_tgtobj="$srv_linux_obj linux-microblaze-low.o " - srv_xmlfiles="microblaze-linux.xml" - srv_linux_regsets=yes - srv_linux_usrregs=yes --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch new file mode 100644 index 00000000..9498e8f7 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0006-Patch-MicroBlaze-MicroBlaze-native-gdb-port.patch @@ -0,0 +1,831 @@ +From b37df6ced77898e8cb7e1c343af005d5bfe1272f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Wed, 15 Jun 2022 10:29:09 +0530 +Subject: [PATCH 06/10] [Patch,MicroBlaze] : MicroBlaze native gdb port. + +--- + gdb/Makefile.in | 2 + + gdb/configure.nat | 4 + + gdb/features/microblaze-linux.c | 79 +++++++ + gdb/microblaze-linux-nat.c | 366 ++++++++++++++++++++++++++++++++ + gdb/microblaze-linux-tdep.c | 2 + + gdb/microblaze-linux-tdep.h | 24 +++ + gdb/microblaze-tdep.c | 151 ++++++++++++- + gdb/microblaze-tdep.h | 15 +- + 8 files changed, 629 insertions(+), 14 deletions(-) + create mode 100755 gdb/features/microblaze-linux.c + create mode 100755 gdb/microblaze-linux-nat.c + create mode 100644 gdb/microblaze-linux-tdep.h + +diff --git a/gdb/Makefile.in b/gdb/Makefile.in +index ec371fc7e52..0449b8e4c2b 100644 +--- a/gdb/Makefile.in ++++ b/gdb/Makefile.in +@@ -1336,6 +1336,7 @@ HFILES_NO_SRCDIR = \ + memory-map.h \ + memrange.h \ + microblaze-tdep.h \ ++ microblaze-linux-tdep.h \ + mips-linux-tdep.h \ + mips-nbsd-tdep.h \ + mips-tdep.h \ +@@ -2214,6 +2215,7 @@ ALLDEPFILES = \ + m68k-linux-nat.c \ + m68k-linux-tdep.c \ + m68k-tdep.c \ ++ microblaze-linux-nat.c \ + microblaze-linux-tdep.c \ + microblaze-tdep.c \ + mingw-hdep.c \ +diff --git a/gdb/configure.nat b/gdb/configure.nat +index bb70e303384..53f19a3d263 100644 +--- a/gdb/configure.nat ++++ b/gdb/configure.nat +@@ -261,6 +261,10 @@ case ${gdb_host} in + # Host: Motorola m68k running GNU/Linux. + NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" + ;; ++ microblaze) ++ # Host: Microblaze running GNU/Linux. ++ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" ++ ;; + mips) + # Host: Linux/MIPS + NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ +diff --git a/gdb/features/microblaze-linux.c b/gdb/features/microblaze-linux.c +new file mode 100755 +index 00000000000..29f681bf2ac +--- /dev/null ++++ b/gdb/features/microblaze-linux.c +@@ -0,0 +1,79 @@ ++/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: ++ Original: microblaze.xml */ ++ ++#include "defs.h" ++#include "osabi.h" ++#include "target-descriptions.h" ++ ++struct target_desc *tdesc_microblaze_linux; ++static void ++initialize_tdesc_microblaze_linux (void) ++{ ++ struct target_desc *result = allocate_target_description (); ++ struct tdesc_feature *feature; ++ set_tdesc_architecture (result, bfd_scan_arch ("microblaze")); ++ set_tdesc_osabi (result, osabi_from_tdesc_string ("GNU/Linux")); ++ ++ feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core"); ++ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int"); ++ tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64"); ++ tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64"); ++ ++ tdesc_microblaze_linux = result; ++} +diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c +new file mode 100755 +index 00000000000..6b9daa23120 +--- /dev/null ++++ b/gdb/microblaze-linux-nat.c +@@ -0,0 +1,366 @@ ++/* Native-dependent code for GNU/Linux MicroBlaze. ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++#include "defs.h" ++#include "arch-utils.h" ++#include "dis-asm.h" ++#include "frame.h" ++#include "trad-frame.h" ++#include "symtab.h" ++#include "value.h" ++#include "gdbcmd.h" ++#include "breakpoint.h" ++#include "inferior.h" ++#include "gdbthread.h" ++#include "gdbcore.h" ++#include "regcache.h" ++#include "regset.h" ++#include "target.h" ++#include "frame.h" ++#include "frame-base.h" ++#include "frame-unwind.h" ++#include "osabi.h" ++#include "gdbsupport/gdb_assert.h" ++#include ++#include "target-descriptions.h" ++#include "opcodes/microblaze-opcm.h" ++#include "opcodes/microblaze-dis.h" ++#include "gregset.h" ++ ++#include "linux-nat.h" ++#include "linux-tdep.h" ++#include "target-descriptions.h" ++ ++#include ++#include ++#include ++#include "gdbsupport/gdb_wait.h" ++#include ++#include ++#include "nat/gdb_ptrace.h" ++#include "nat/linux-ptrace.h" ++#include "inf-ptrace.h" ++#include ++#include ++#include ++#include ++ ++/* Prototypes for supply_gregset etc. */ ++#include "gregset.h" ++ ++#include "microblaze-tdep.h" ++#include "microblaze-linux-tdep.h" ++#include "inferior.h" ++ ++#include "elf/common.h" ++ ++#include "auxv.h" ++#include "linux-tdep.h" ++ ++#include ++ ++ ++//int have_ptrace_getsetregs=1; ++ ++/* MicroBlaze Linux native additions to the default linux support. */ ++ ++class microblaze_linux_nat_target final : public linux_nat_target ++{ ++public: ++ /* Add our register access methods. */ ++ void fetch_registers (struct regcache *regcache, int regnum) override; ++ void store_registers (struct regcache *regcache, int regnum) override; ++ ++ /* Read suitable target description. */ ++ const struct target_desc *read_description () override; ++}; ++ ++static microblaze_linux_nat_target the_microblaze_linux_nat_target; ++ ++static int ++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) ++{ ++ int u_addr = -1; ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace ++ * interface, and not the wordsize of the program's ABI. */ ++ int wordsize = sizeof (long); ++ ++ /* General purpose registers occupy 1 slot each in the buffer. */ ++ if (regno >= MICROBLAZE_R0_REGNUM ++ && regno <= MICROBLAZE_FSR_REGNUM) ++ u_addr = ((regno - MICROBLAZE_R0_REGNUM)* wordsize); ++ ++ return u_addr; ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from regset GREGS into REGCACHE. */ ++ ++static void ++supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs, ++ int regnum) ++{ ++ int i; ++ const elf_greg_t *regp = *gregs; ++ /* Access all registers */ ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_supply (i, regp + i); ++ ++ /* Supply MICROBLAZE_PC_REGNUM from index 32. */ ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ ++ /* Fill the inaccessible zero register with zero. */ ++ regcache->raw_supply_zeroed (0); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ regcache->raw_supply_zeroed (0); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_supply (MICROBLAZE_PC_REGNUM, regp + 32); ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_supply (regnum, regp + regnum); ++} ++ ++/* Copy all general purpose registers from regset GREGS into REGCACHE. */ ++ ++void ++supply_gregset (struct regcache *regcache, const prgregset_t *gregs) ++{ ++ supply_gregset_regnum (regcache, gregs, -1); ++} ++ ++/* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1) ++ from REGCACHE into regset GREGS. */ ++ ++void ++fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum) ++{ ++ elf_greg_t *regp = *gregs; ++ if (regnum == -1) ++ { ++ /* We fill the general purpose registers. */ ++ for (int i = MICROBLAZE_R0_REGNUM + 1; i < MICROBLAZE_FSR_REGNUM; i++) ++ regcache->raw_collect (i, regp + i); ++ ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++ } ++ else if (regnum == MICROBLAZE_R0_REGNUM) ++ /* Nothing to do here. */ ++ ; ++ else if (regnum > MICROBLAZE_R0_REGNUM && regnum < MICROBLAZE_FSR_REGNUM) ++ regcache->raw_collect (regnum, regp + regnum); ++ else if (regnum == MICROBLAZE_PC_REGNUM) ++ regcache->raw_collect (MICROBLAZE_PC_REGNUM, regp + 32); ++} ++ ++/* Transfering floating-point registers between GDB, inferiors and cores. ++ Since MicroBlaze floating-point registers are the same as GPRs these do ++ nothing. */ ++ ++void ++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregs) ++{ ++} ++ ++void ++fill_fpregset (const struct regcache *regcache, ++ gdb_fpregset_t *fpregs, int regno) ++{ ++} ++ ++ ++static void ++fetch_register (struct regcache *regcache, int tid, int regno) ++{ ++ struct gdbarch *gdbarch = regcache->arch (); ++ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int bytes_transferred; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ { ++ memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ ++ regcache->raw_supply (regno, buf); ++ return; ++ } ++ ++ /* Read the raw register using sizeof(long) sized chunks. On a ++ * 32-bit platform, 64-bit floating-point registers will require two ++ * transfers. */ ++ for (bytes_transferred = 0; ++ bytes_transferred < register_size (gdbarch, regno); ++ bytes_transferred += sizeof (long)) ++ { ++ long l; ++ ++ errno = 0; ++ l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); ++ if (errno == EIO) ++ { ++ printf("ptrace io error\n"); ++ } ++ regaddr += sizeof (long); ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "reading register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ memcpy (&buf[bytes_transferred], &l, sizeof (l)); ++ } ++ ++ /* Now supply the register. Keep in mind that the regcache's idea ++ * of the register's size may not be a multiple of sizeof ++ * (long). */ ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values are always found at the left end of the ++ * bytes transferred. */ ++ regcache->raw_supply (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values are found at the right end of the bytes ++ * transferred. */ ++ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); ++ regcache->raw_supply (regno, buf + padding); ++ } ++ else ++ internal_error (__FILE__, __LINE__, ++ _("fetch_register: unexpected byte order: %d"), ++ gdbarch_byte_order (gdbarch)); ++} ++ ++ ++/* This is a wrapper for the fetch_all_gp_regs function. It is ++ * responsible for verifying if this target has the ptrace request ++ * that can be used to fetch all general-purpose registers at one ++ * shot. If it doesn't, then we should fetch them using the ++ * old-fashioned way, which is to iterate over the registers and ++ * request them one by one. */ ++static void ++fetch_gp_regs (struct regcache *regcache, int tid) ++{ ++ int i; ++/* If we've hit this point, it doesn't really matter which ++ architecture we are using. We just need to read the ++ registers in the "old-fashioned way". */ ++ for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++) ++ fetch_register (regcache, tid, i); ++} ++ ++/* Return a target description for the current target. */ ++ ++const struct target_desc * ++microblaze_linux_nat_target::read_description () ++{ ++ return tdesc_microblaze_linux; ++} ++ ++/* Fetch REGNUM (or all registers if REGNUM == -1) from the target ++ into REGCACHE using PTRACE_GETREGSET. */ ++ ++void ++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache, ++ int regno) ++{ ++ /* Get the thread id for the ptrace call. */ ++ int tid = regcache->ptid ().lwp (); ++//int tid = get_ptrace_pid (regcache->ptid()); ++#if 1 ++ if (regno == -1) ++#endif ++ fetch_gp_regs (regcache, tid); ++#if 1 ++ else ++ fetch_register (regcache, tid, regno); ++#endif ++} ++ ++ ++/* Store REGNUM (or all registers if REGNUM == -1) to the target ++ from REGCACHE using PTRACE_SETREGSET. */ ++ ++void ++microblaze_linux_nat_target::store_registers (struct regcache *regcache, int regno) ++{ ++ int tid; ++ ++ tid = get_ptrace_pid (regcache->ptid ()); ++ ++ struct gdbarch *gdbarch = regcache->arch (); ++ /* This isn't really an address. But ptrace thinks of it as one. */ ++ CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); ++ int i; ++ size_t bytes_to_transfer; ++ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; ++ ++ if (regaddr == -1) ++ return; ++ ++ /* First collect the register. Keep in mind that the regcache's ++ * idea of the register's size may not be a multiple of sizeof ++ * (long). */ ++ memset (buf, 0, sizeof buf); ++ bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); ++ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) ++ { ++ /* Little-endian values always sit at the left end of the buffer. */ ++ regcache->raw_collect (regno, buf); ++ } ++ else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) ++ { ++ /* Big-endian values sit at the right end of the buffer. */ ++ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); ++ regcache->raw_collect (regno, buf + padding); ++ } ++ ++ for (i = 0; i < bytes_to_transfer; i += sizeof (long)) ++ { ++ long l; ++ ++ memcpy (&l, &buf[i], sizeof (l)); ++ errno = 0; ++ ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); ++ regaddr += sizeof (long); ++ ++ if (errno != 0) ++ { ++ char message[128]; ++ sprintf (message, "writing register %s (#%d)", ++ gdbarch_register_name (gdbarch, regno), regno); ++ perror_with_name (message); ++ } ++ } ++} ++ ++void _initialize_microblaze_linux_nat (void); ++ ++void ++_initialize_microblaze_linux_nat (void) ++{ ++ /* Register the target. */ ++ linux_target = &the_microblaze_linux_nat_target; ++ add_inf_child_target (linux_target); ++} +diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c +index b8277dfd735..b77acc9dc61 100644 +--- a/gdb/microblaze-linux-tdep.c ++++ b/gdb/microblaze-linux-tdep.c +@@ -37,6 +37,7 @@ + #include "tramp-frame.h" + #include "linux-tdep.h" + #include "glibc-tdep.h" ++#include "features/microblaze-linux.c" + + static int microblaze_debug_flag = 0; + +@@ -179,4 +180,5 @@ _initialize_microblaze_linux_tdep () + { + gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, + microblaze_linux_init_abi); ++ initialize_tdesc_microblaze_linux (); + } +diff --git a/gdb/microblaze-linux-tdep.h b/gdb/microblaze-linux-tdep.h +new file mode 100644 +index 00000000000..a2c744e2961 +--- /dev/null ++++ b/gdb/microblaze-linux-tdep.h +@@ -0,0 +1,24 @@ ++/* Target-dependent code for GNU/Linux on OpenRISC. ++ ++ Copyright (C) 2021 Free Software Foundation, Inc. ++ ++ This file is part of GDB. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++#ifndef MICROBLAZE_LINUX_TDEP_H ++#define MICROBLAZE_LINUX_TDEP_H ++ /* Target descriptions. */ ++ extern struct target_desc *tdesc_microblaze_linux; ++ ++#endif /* MICROBLAZE_LINUX_TDEP_H */ +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 399fa0e3dca..0a5b5ab59cc 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -295,6 +295,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + cache->frameless_p = 0; /* Frame found. */ + save_hidden_pointer_found = 0; + non_stack_instruction_found = 0; ++ cache->register_offsets[rd] = -imm; + continue; + } + else if (IS_SPILL_SP(op, rd, ra)) +@@ -443,15 +444,17 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) + { + sal = find_pc_line (func_start, 0); +- +- if (sal.end < func_end +- && start_pc <= sal.end) ++ ++ if (sal.line !=0 && sal.end <= func_end && start_pc <= sal.end) { + start_pc = sal.end; ++ microblaze_debug("start_pc is %d\t sal.end is %d\t func_end is %d\t",start_pc,sal.end,func_end); ++ } + } + + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + ++ + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -465,6 +468,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) + struct microblaze_frame_cache *cache; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + int rn; ++ CORE_ADDR current_pc; + + if (*this_cache) + return (struct microblaze_frame_cache *) *this_cache; +@@ -478,10 +482,17 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) + cache->register_offsets[rn] = -1; + + /* Call for side effects. */ +- get_frame_func (next_frame); +- +- cache->pc = get_frame_address_in_block (next_frame); +- ++ cache->pc = get_frame_func (next_frame); ++ ++// cache->pc = get_frame_address_in_block (next_frame); ++ current_pc = get_frame_pc (next_frame); ++ if (cache->pc) ++ microblaze_analyze_prologue (gdbarch, cache->pc, current_pc, cache); ++ ++ cache->saved_sp = cache->base + cache->framesize; ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base; ++ cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp; ++ + return cache; + } + +@@ -506,6 +517,25 @@ microblaze_frame_prev_register (struct frame_info *this_frame, + struct microblaze_frame_cache *cache = + microblaze_frame_cache (this_frame, this_cache); + ++if ((regnum == MICROBLAZE_SP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]) ++ || (regnum == MICROBLAZE_FP_REGNUM && ++ cache->register_offsets[MICROBLAZE_SP_REGNUM])) ++ ++ return frame_unwind_got_constant (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_SP_REGNUM]); ++ ++if (regnum == MICROBLAZE_PC_REGNUM) ++{ ++ regnum = 15; ++ return frame_unwind_got_memory (this_frame, regnum, ++ cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]); ++ ++} ++if (regnum == MICROBLAZE_SP_REGNUM) ++ regnum = 1; ++#if 0 ++ + if (cache->frameless_p) + { + if (regnum == MICROBLAZE_PC_REGNUM) +@@ -518,7 +548,9 @@ microblaze_frame_prev_register (struct frame_info *this_frame, + else + return trad_frame_get_prev_register (this_frame, cache->saved_regs, + regnum); +- ++#endif ++ return trad_frame_get_prev_register (this_frame, cache->saved_regs, ++ regnum); + } + + static const struct frame_unwind microblaze_frame_unwind = +@@ -633,7 +665,106 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) + return (TYPE_LENGTH (type) == 16); + } + +- ++#if 1 ++static std::vector ++microblaze_software_single_step (struct regcache *regcache) ++{ ++ struct gdbarch *arch = regcache->arch (); ++ //struct gdbarch_tdep *tdep = gdbarch_tdep (arch); ++ static int le_breakp[] = MICROBLAZE_BREAKPOINT_LE; ++ static int be_breakp[] = MICROBLAZE_BREAKPOINT; ++ enum bfd_endian byte_order = gdbarch_byte_order (arch); ++ int *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; ++// std::vector ret = NULL; ++ ++ /* Save the address and the values of the next_pc and the target */ ++ static struct sstep_breaks ++ { ++ CORE_ADDR address; ++ bfd_boolean valid; ++ /* Shadow contents. */ ++ char data[INST_WORD_SIZE]; ++ } stepbreaks[2]; ++ int ii; ++ ++ CORE_ADDR pc; ++ std::vector next_pcs; ++ long insn; ++ enum microblaze_instr minstr; ++ bfd_boolean isunsignednum; ++ enum microblaze_instr_type insn_type; ++ short delay_slots; ++ int imm; ++ bfd_boolean immfound = FALSE; ++ ++ /* Set a breakpoint at the next instruction */ ++ /* If the current instruction is an imm, set it at the inst after */ ++ /* If the instruction has a delay slot, skip the delay slot */ ++ pc = regcache_read_pc (regcache); ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ if (insn_type == immediate_inst) ++ { ++ int rd, ra, rb; ++ immfound = TRUE; ++ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); ++ pc = pc + INST_WORD_SIZE; ++ insn = microblaze_fetch_instruction (pc); ++ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); ++ } ++ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; ++ if (insn_type != return_inst) { ++ stepbreaks[0].valid = TRUE; ++ } else { ++ stepbreaks[0].valid = FALSE; ++ } ++ ++ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); ++ /* Now check for branch or return instructions */ ++ if (insn_type == branch_inst || insn_type == return_inst) { ++ int limm; ++ int lrd, lra, lrb; ++ int ra, rb; ++ bfd_boolean targetvalid; ++ bfd_boolean unconditionalbranch; ++ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); ++ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) ++ ra = regcache_raw_get_unsigned(regcache, lra); ++ else ++ ra = 0; ++ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) ++ rb = regcache_raw_get_unsigned(regcache, lrb); ++ else ++ rb = 0; ++ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); ++ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); ++ if (unconditionalbranch) ++ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ ++ if (targetvalid && (stepbreaks[0].valid == FALSE || ++ (stepbreaks[0].address != stepbreaks[1].address)) ++ && (stepbreaks[1].address != pc)) { ++ stepbreaks[1].valid = TRUE; ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ } else { ++ stepbreaks[1].valid = FALSE; ++ } ++ ++ /* Insert the breakpoints */ ++ for (ii = 0; ii < 2; ++ii) ++ { ++ ++ /* ignore invalid breakpoint. */ ++ if (stepbreaks[ii].valid) { ++ // VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; ++ next_pcs.push_back (stepbreaks[ii].address); ++ } ++ } ++ return next_pcs; ++} ++#endif ++ + static int dwarf2_to_reg_map[78] = + { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ + 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ +@@ -805,6 +936,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + microblaze_breakpoint::bp_from_kind); + set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint); + ++ set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); ++ + set_gdbarch_frame_args_skip (gdbarch, 8); + + set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index 872a3931f20..7f75c693b74 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -59,11 +59,11 @@ enum microblaze_regnum + MICROBLAZE_R12_REGNUM, + MICROBLAZE_R13_REGNUM, + MICROBLAZE_R14_REGNUM, +- MICROBLAZE_R15_REGNUM, ++ MICROBLAZE_R15_REGNUM,MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM, + MICROBLAZE_R16_REGNUM, + MICROBLAZE_R17_REGNUM, + MICROBLAZE_R18_REGNUM, +- MICROBLAZE_R19_REGNUM, ++ MICROBLAZE_R19_REGNUM,MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM, + MICROBLAZE_R20_REGNUM, + MICROBLAZE_R21_REGNUM, + MICROBLAZE_R22_REGNUM, +@@ -76,7 +76,8 @@ enum microblaze_regnum + MICROBLAZE_R29_REGNUM, + MICROBLAZE_R30_REGNUM, + MICROBLAZE_R31_REGNUM, +- MICROBLAZE_PC_REGNUM, ++ MICROBLAZE_MAX_GPR_REGS, ++ MICROBLAZE_PC_REGNUM=32, + MICROBLAZE_MSR_REGNUM, + MICROBLAZE_EAR_REGNUM, + MICROBLAZE_ESR_REGNUM, +@@ -101,17 +102,21 @@ enum microblaze_regnum + MICROBLAZE_RTLBSX_REGNUM, + MICROBLAZE_RTLBLO_REGNUM, + MICROBLAZE_RTLBHI_REGNUM, +- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, ++ MICROBLAZE_SLR_REGNUM, + MICROBLAZE_SHR_REGNUM, +- MICROBLAZE_NUM_REGS ++ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS + }; + ++/* Big enough to hold the size of the largest register in bytes. */ ++#define MICROBLAZE_MAX_REGISTER_SIZE 64 ++ + struct microblaze_frame_cache + { + /* Base address. */ + CORE_ADDR base; + CORE_ADDR pc; + ++ CORE_ADDR saved_sp; + /* Do we have a frame? */ + int frameless_p; + +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-microblaze-Adding-64-bit-MB-support.patch index 6536c22d..564562da 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-microblaze-Adding-64-bit-MB-support.patch +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0007-Patch-microblaze-Adding-64-bit-MB-support.patch @@ -1,4 +1,4 @@ -From f9e5f9f884470d0a216126b347b4699d6051fcdd Mon Sep 17 00:00:00 2001 +From 0eea9a3f068837d4792719a8f9ba15736938eea4 Mon Sep 17 00:00:00 2001 From: Nagaraju Mekala Date: Thu, 31 Jan 2019 14:36:00 +0530 Subject: [PATCH 07/10] [Patch, microblaze]: Adding 64 bit MB support Added new @@ -16,6 +16,9 @@ Conflicts: Conflicts: bfd/configure opcodes/microblaze-opcm.h + +Conflicts: + gdb/microblaze-tdep.c --- bfd/Makefile.am | 2 + bfd/Makefile.in | 3 + @@ -41,8 +44,8 @@ Conflicts: gdb/features/microblaze64.c | 77 + gdb/features/microblaze64.xml | 11 + gdb/microblaze-linux-tdep.c | 36 +- - gdb/microblaze-tdep.c | 210 +- - gdb/microblaze-tdep.h | 8 +- + gdb/microblaze-tdep.c | 102 +- + gdb/microblaze-tdep.h | 4 +- .../microblaze-with-stack-protect.dat | 4 +- .../linux-microblaze-low.c | 0 include/elf/common.h | 1 + @@ -50,7 +53,7 @@ Conflicts: opcodes/microblaze-dis.c | 51 +- opcodes/microblaze-opc.h | 180 +- opcodes/microblaze-opcm.h | 36 +- - 41 files changed, 5454 insertions(+), 248 deletions(-) + 41 files changed, 5345 insertions(+), 245 deletions(-) create mode 100755 bfd/elf64-microblaze.c create mode 100644 gdb/features/microblaze64-core.xml create mode 100644 gdb/features/microblaze64-stack-protect.xml @@ -4880,18 +4883,18 @@ index 00000000000..515d18e65cf + + diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c -index b8277dfd735..0c9ec82cee5 100644 +index b77acc9dc61..ba87d0bbd63 100644 --- a/gdb/microblaze-linux-tdep.c +++ b/gdb/microblaze-linux-tdep.c -@@ -39,6 +39,7 @@ - #include "glibc-tdep.h" +@@ -40,6 +40,7 @@ + #include "features/microblaze-linux.c" static int microblaze_debug_flag = 0; +int MICROBLAZE_REGISTER_SIZE=4; static void microblaze_debug (const char *fmt, ...) -@@ -54,6 +55,7 @@ microblaze_debug (const char *fmt, ...) +@@ -55,6 +56,7 @@ microblaze_debug (const char *fmt, ...) } } @@ -4899,7 +4902,7 @@ index b8277dfd735..0c9ec82cee5 100644 static int microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, struct bp_target_info *bp_tgt) -@@ -85,6 +87,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, +@@ -86,6 +88,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, return val; } @@ -4908,7 +4911,7 @@ index b8277dfd735..0c9ec82cee5 100644 static void microblaze_linux_sigtramp_cache (struct frame_info *next_frame, struct trad_frame_cache *this_cache, -@@ -146,8 +150,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, +@@ -147,8 +151,8 @@ microblaze_linux_init_abi (struct gdbarch_info info, linux_init_abi (info, gdbarch); @@ -4919,7 +4922,7 @@ index b8277dfd735..0c9ec82cee5 100644 /* Shared library handling. */ set_solib_svr4_fetch_link_map_offsets (gdbarch, -@@ -159,10 +163,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, +@@ -160,10 +164,30 @@ microblaze_linux_init_abi (struct gdbarch_info info, /* BFD target for core files. */ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) @@ -4952,7 +4955,7 @@ index b8277dfd735..0c9ec82cee5 100644 /* Shared library handling. */ set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); -@@ -177,6 +201,8 @@ void _initialize_microblaze_linux_tdep (); +@@ -178,7 +202,9 @@ void _initialize_microblaze_linux_tdep (); void _initialize_microblaze_linux_tdep () { @@ -4961,9 +4964,10 @@ index b8277dfd735..0c9ec82cee5 100644 + microblaze_linux_init_abi); + gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, microblaze_linux_init_abi); + initialize_tdesc_microblaze_linux (); } diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index 399fa0e3dca..e51c022c1ba 100644 +index 0a5b5ab59cc..667d658adfd 100644 --- a/gdb/microblaze-tdep.c +++ b/gdb/microblaze-tdep.c @@ -40,7 +40,9 @@ @@ -5023,7 +5027,7 @@ index 399fa0e3dca..e51c022c1ba 100644 /* Allocate and initialize a frame cache. */ static struct microblaze_frame_cache * -@@ -556,17 +568,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, +@@ -588,17 +600,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache, gdb_byte *valbuf) { gdb_byte buf[8]; @@ -5043,118 +5047,10 @@ index 399fa0e3dca..e51c022c1ba 100644 return; case 4: /* for sizes 4 or 8, copy the required length. */ case 8: -@@ -633,7 +644,119 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) - return (TYPE_LENGTH (type) == 16); +@@ -765,6 +776,12 @@ microblaze_software_single_step (struct regcache *regcache) } + #endif -- -+#if 0 -+static std::vector -+microblaze_software_single_step (struct regcache *regcache) -+{ -+// struct gdbarch *arch = get_frame_arch(frame); -+ struct gdbarch *arch = get_regcache_arch (regcache); -+ struct address_space *aspace = get_regcache_aspace (regcache); -+// struct address_space *aspace = get_frame_address_space (frame); -+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch); -+ static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE; -+ static char be_breakp[] = MICROBLAZE_BREAKPOINT; -+ enum bfd_endian byte_order = gdbarch_byte_order (arch); -+ char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp; -+ std::vector ret = 0; -+ -+ /* Save the address and the values of the next_pc and the target */ -+ static struct sstep_breaks -+ { -+ CORE_ADDR address; -+ bfd_boolean valid; -+ /* Shadow contents. */ -+ char data[INST_WORD_SIZE]; -+ } stepbreaks[2]; -+ int ii; -+ -+ if (1) -+ { -+ CORE_ADDR pc; -+ std::vector *next_pcs = NULL; -+ long insn; -+ enum microblaze_instr minstr; -+ bfd_boolean isunsignednum; -+ enum microblaze_instr_type insn_type; -+ short delay_slots; -+ int imm; -+ bfd_boolean immfound = FALSE; -+ -+ /* Set a breakpoint at the next instruction */ -+ /* If the current instruction is an imm, set it at the inst after */ -+ /* If the instruction has a delay slot, skip the delay slot */ -+ pc = regcache_read_pc (regcache); -+ insn = microblaze_fetch_instruction (pc); -+ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); -+ if (insn_type == immediate_inst) -+ { -+ int rd, ra, rb; -+ immfound = TRUE; -+ minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); -+ pc = pc + INST_WORD_SIZE; -+ insn = microblaze_fetch_instruction (pc); -+ minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); -+ } -+ stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE; -+ if (insn_type != return_inst) { -+ stepbreaks[0].valid = TRUE; -+ } else { -+ stepbreaks[0].valid = FALSE; -+ } -+ -+ microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn); -+ /* Now check for branch or return instructions */ -+ if (insn_type == branch_inst || insn_type == return_inst) { -+ int limm; -+ int lrd, lra, lrb; -+ int ra, rb; -+ bfd_boolean targetvalid; -+ bfd_boolean unconditionalbranch; -+ microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm); -+ if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) -+ ra = regcache_raw_get_unsigned(regcache, lra); -+ else -+ ra = 0; -+ if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) -+ rb = regcache_raw_get_unsigned(regcache, lrb); -+ else -+ rb = 0; -+ stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); -+ microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address); -+ if (unconditionalbranch) -+ stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */ -+ if (targetvalid && (stepbreaks[0].valid == FALSE || -+ (stepbreaks[0].address != stepbreaks[1].address)) -+ && (stepbreaks[1].address != pc)) { -+ stepbreaks[1].valid = TRUE; -+ } else { -+ stepbreaks[1].valid = FALSE; -+ } -+ } else { -+ stepbreaks[1].valid = FALSE; -+ } -+ -+ /* Insert the breakpoints */ -+ for (ii = 0; ii < 2; ++ii) -+ { -+ -+ /* ignore invalid breakpoint. */ -+ if (stepbreaks[ii].valid) { -+ VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);; -+// insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address); -+ ret = next_pcs; -+ } -+ } -+ } -+ return ret; -+} -+#endif -+ +static void +microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) +{ @@ -5164,7 +5060,7 @@ index 399fa0e3dca..e51c022c1ba 100644 static int dwarf2_to_reg_map[78] = { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ -@@ -668,13 +791,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) +@@ -799,13 +816,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) static void microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) { @@ -5182,7 +5078,7 @@ index 399fa0e3dca..e51c022c1ba 100644 } void -@@ -682,7 +806,7 @@ microblaze_supply_gregset (const struct regset *regset, +@@ -813,7 +831,7 @@ microblaze_supply_gregset (const struct regset *regset, struct regcache *regcache, int regnum, const void *gregs) { @@ -5191,7 +5087,7 @@ index 399fa0e3dca..e51c022c1ba 100644 if (regnum >= 0) regcache->raw_supply (regnum, regs + regnum); -@@ -690,7 +814,7 @@ microblaze_supply_gregset (const struct regset *regset, +@@ -821,7 +839,7 @@ microblaze_supply_gregset (const struct regset *regset, int i; for (i = 0; i < 50; i++) { @@ -5200,7 +5096,7 @@ index 399fa0e3dca..e51c022c1ba 100644 } } } -@@ -713,6 +837,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, +@@ -844,6 +862,17 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch, } @@ -5218,7 +5114,7 @@ index 399fa0e3dca..e51c022c1ba 100644 static struct gdbarch * microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) -@@ -727,8 +862,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -858,8 +887,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) if (arches != NULL) return arches->gdbarch; if (tdesc == NULL) @@ -5236,7 +5132,7 @@ index 399fa0e3dca..e51c022c1ba 100644 /* Check any target description for validity. */ if (tdesc_has_registers (tdesc)) { -@@ -736,27 +878,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -867,27 +903,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) int valid_p; int i; @@ -5277,7 +5173,7 @@ index 399fa0e3dca..e51c022c1ba 100644 } if (!valid_p) -@@ -764,6 +914,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -895,6 +939,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdesc_data_cleanup (tdesc_data); return NULL; } @@ -5285,7 +5181,7 @@ index 399fa0e3dca..e51c022c1ba 100644 } /* Allocate space for the new architecture. */ -@@ -783,7 +934,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -914,7 +959,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Register numbers of various important registers. */ set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); @@ -5303,7 +5199,7 @@ index 399fa0e3dca..e51c022c1ba 100644 /* Map Dwarf2 registers to GDB registers. */ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); -@@ -803,13 +964,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -934,7 +989,9 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) microblaze_breakpoint::kind_from_pc); set_gdbarch_sw_breakpoint_from_kind (gdbarch, microblaze_breakpoint::bp_from_kind); @@ -5312,7 +5208,9 @@ index 399fa0e3dca..e51c022c1ba 100644 + +// set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); - set_gdbarch_frame_args_skip (gdbarch, 8); + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + +@@ -942,7 +999,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); @@ -5321,7 +5219,7 @@ index 399fa0e3dca..e51c022c1ba 100644 frame_base_set_default (gdbarch, µblaze_frame_base); -@@ -824,12 +987,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +@@ -957,12 +1014,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdesc_use_registers (gdbarch, tdesc, tdesc_data); //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer); @@ -5336,7 +5234,7 @@ index 399fa0e3dca..e51c022c1ba 100644 return gdbarch; } -@@ -841,6 +1003,8 @@ _initialize_microblaze_tdep () +@@ -974,6 +1030,8 @@ _initialize_microblaze_tdep () initialize_tdesc_microblaze_with_stack_protect (); initialize_tdesc_microblaze (); @@ -5346,7 +5244,7 @@ index 399fa0e3dca..e51c022c1ba 100644 add_setshow_zuinteger_cmd ("microblaze", class_maintenance, µblaze_debug_flag, _("\ diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index 872a3931f20..dc1d4686914 100644 +index 7f75c693b74..e0fa7ef9b12 100644 --- a/gdb/microblaze-tdep.h +++ b/gdb/microblaze-tdep.h @@ -27,7 +27,7 @@ struct microblaze_gregset @@ -5358,19 +5256,7 @@ index 872a3931f20..dc1d4686914 100644 }; struct gdbarch_tdep -@@ -101,9 +101,9 @@ enum microblaze_regnum - MICROBLAZE_RTLBSX_REGNUM, - MICROBLAZE_RTLBLO_REGNUM, - MICROBLAZE_RTLBHI_REGNUM, -- MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM, -+ MICROBLAZE_SLR_REGNUM, - MICROBLAZE_SHR_REGNUM, -- MICROBLAZE_NUM_REGS -+ MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS - }; - - struct microblaze_frame_cache -@@ -128,7 +128,7 @@ struct microblaze_frame_cache +@@ -133,7 +133,7 @@ struct microblaze_frame_cache struct trad_frame_saved_reg *saved_regs; }; /* All registers are 32 bits. */ diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch new file mode 100644 index 00000000..abbea266 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch @@ -0,0 +1,34 @@ +From cc8ee172b9145ce488c556a2eb50f931f0676eea Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Mon, 19 Apr 2021 14:33:27 +0530 +Subject: [PATCH 08/10] [Patch,MicroBlaze] : these changes will make 64 bit + vectors as default target types when we built gdb with microblaze 64 bit type + targets,for instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64 + +--- + bfd/config.bfd | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/bfd/config.bfd b/bfd/config.bfd +index 0f752de267b..4945e7fa3b5 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -823,7 +823,15 @@ case "${targ}" in + targ_defvec=metag_elf32_vec + targ_underscore=yes + ;; ++ microblazeel*-*64) ++ targ_defvec=microblaze_elf64_le_vec ++ targ_selvecs=microblaze_elf64_vec ++ ;; + ++ microblaze*-*64) ++ targ_defvec=microblaze_elf64_vec ++ targ_selvecs=microblaze_elf64_le_vec ++ ;; + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0008-gdb-Fix-microblaze-target-compilation-3.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0008-gdb-Fix-microblaze-target-compilation-3.patch deleted file mode 100644 index 6a570b6a..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0008-gdb-Fix-microblaze-target-compilation-3.patch +++ /dev/null @@ -1,288 +0,0 @@ -From 306ca46b3f330ee39601b9aede6b53c9cdbe9f86 Mon Sep 17 00:00:00 2001 -From: Mark Hatle -Date: Wed, 9 Dec 2020 23:35:35 -0600 -Subject: [PATCH 08/10] gdb: Fix microblaze target compilation (#3) - -Add microblaze-linux-nat.c to configure.nat - -Transition microblaze-linux-nat.c to use the new gdb C++ style functions. - -Signed-off-by: Mark Hatle ---- - gdb/configure.nat | 5 ++ - gdb/microblaze-linux-nat.c | 96 ++++++++++++++------------------------ - gdb/microblaze-tdep.h | 3 ++ - 3 files changed, 43 insertions(+), 61 deletions(-) - -diff --git a/gdb/configure.nat b/gdb/configure.nat -index bb70e303384..d8548a6b666 100644 ---- a/gdb/configure.nat -+++ b/gdb/configure.nat -@@ -261,6 +261,11 @@ case ${gdb_host} in - # Host: Motorola m68k running GNU/Linux. - NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o" - ;; -+ microblaze) -+ # Host: Microblaze running GNU/Linux. -+ NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o" -+ NAT_CDEPS= -+ ;; - mips) - # Host: Linux/MIPS - NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \ -diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c -index e9b8c9c5221..bac4697e1e6 100644 ---- a/gdb/microblaze-linux-nat.c -+++ b/gdb/microblaze-linux-nat.c -@@ -36,13 +36,14 @@ - #include "dwarf2-frame.h" - #include "osabi.h" - --#include "gdb_assert.h" --#include "gdb_string.h" -+#include "gdbsupport/gdb_assert.h" -+#include - #include "target-descriptions.h" - #include "opcodes/microblaze-opcm.h" - #include "opcodes/microblaze-dis.h" - - #include "linux-nat.h" -+#include "linux-tdep.h" - #include "target-descriptions.h" - - #include -@@ -61,22 +62,17 @@ - /* Defines ps_err_e, struct ps_prochandle. */ - #include "gdb_proc_service.h" - --/* On GNU/Linux, threads are implemented as pseudo-processes, in which -- case we may be tracing more than one process at a time. In that -- case, inferior_ptid will contain the main process ID and the -- individual thread (process) ID. get_thread_id () is used to get -- the thread id if it's available, and the process id otherwise. */ -- --int --get_thread_id (ptid_t ptid) -+class microblaze_linux_nat_target final : public linux_nat_target - { -- int tid = TIDGET (ptid); -- if (0 == tid) -- tid = PIDGET (ptid); -- return tid; --} -+public: -+ /* Add our register access methods. */ -+ void fetch_registers (struct regcache *, int) override; -+ void store_registers (struct regcache *, int) override; -+ -+ const struct target_desc *read_description () override; -+}; - --#define GET_THREAD_ID(PTID) get_thread_id (PTID) -+static microblaze_linux_nat_target the_microblaze_linux_nat_target; - - /* Non-zero if our kernel may support the PTRACE_GETREGS and - PTRACE_SETREGS requests, for reading and writing the -@@ -88,7 +84,6 @@ static int - microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) - { - int u_addr = -1; -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace - interface, and not the wordsize of the program's ABI. */ - int wordsize = sizeof (long); -@@ -105,18 +100,16 @@ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno) - static void - fetch_register (struct regcache *regcache, int tid, int regno) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ struct gdbarch *gdbarch = regcache->arch (); - /* This isn't really an address. But ptrace thinks of it as one. */ - CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); - int bytes_transferred; -- unsigned int offset; /* Offset of registers within the u area. */ -- char buf[MAX_REGISTER_SIZE]; -+ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; - - if (regaddr == -1) - { - memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ -- regcache_raw_supply (regcache, regno, buf); -+ regcache->raw_supply (regno, buf); - return; - } - -@@ -149,14 +142,14 @@ fetch_register (struct regcache *regcache, int tid, int regno) - { - /* Little-endian values are always found at the left end of the - bytes transferred. */ -- regcache_raw_supply (regcache, regno, buf); -+ regcache->raw_supply (regno, buf); - } - else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) - { - /* Big-endian values are found at the right end of the bytes - transferred. */ - size_t padding = (bytes_transferred - register_size (gdbarch, regno)); -- regcache_raw_supply (regcache, regno, buf + padding); -+ regcache->raw_supply (regno, buf + padding); - } - else - internal_error (__FILE__, __LINE__, -@@ -175,8 +168,6 @@ fetch_register (struct regcache *regcache, int tid, int regno) - static int - fetch_all_gp_regs (struct regcache *regcache, int tid) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_gregset_t gregset; - - if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) -@@ -204,8 +195,6 @@ fetch_all_gp_regs (struct regcache *regcache, int tid) - static void - fetch_gp_regs (struct regcache *regcache, int tid) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int i; - - if (have_ptrace_getsetregs) -@@ -223,13 +212,12 @@ fetch_gp_regs (struct regcache *regcache, int tid) - static void - store_register (const struct regcache *regcache, int tid, int regno) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); -+ struct gdbarch *gdbarch = regcache->arch (); - /* This isn't really an address. But ptrace thinks of it as one. */ - CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno); - int i; - size_t bytes_to_transfer; -- char buf[MAX_REGISTER_SIZE]; -+ char buf[MICROBLAZE_MAX_REGISTER_SIZE]; - - if (regaddr == -1) - return; -@@ -242,13 +230,13 @@ store_register (const struct regcache *regcache, int tid, int regno) - if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) - { - /* Little-endian values always sit at the left end of the buffer. */ -- regcache_raw_collect (regcache, regno, buf); -+ regcache->raw_collect (regno, buf); - } - else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) - { - /* Big-endian values sit at the right end of the buffer. */ - size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); -- regcache_raw_collect (regcache, regno, buf + padding); -+ regcache->raw_collect (regno, buf + padding); - } - - for (i = 0; i < bytes_to_transfer; i += sizeof (long)) -@@ -281,8 +269,6 @@ store_register (const struct regcache *regcache, int tid, int regno) - static int - store_all_gp_regs (const struct regcache *regcache, int tid, int regno) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_gregset_t gregset; - - if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) -@@ -319,8 +305,6 @@ store_all_gp_regs (const struct regcache *regcache, int tid, int regno) - static void - store_gp_regs (const struct regcache *regcache, int tid, int regno) - { -- struct gdbarch *gdbarch = get_regcache_arch (regcache); -- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int i; - - if (have_ptrace_getsetregs) -@@ -339,12 +323,12 @@ store_gp_regs (const struct regcache *regcache, int tid, int regno) - regno == -1, otherwise fetch all general registers or all floating - point registers depending upon the value of regno. */ - --static void --microblaze_linux_fetch_inferior_registers (struct target_ops *ops, -- struct regcache *regcache, int regno) -+void -+microblaze_linux_nat_target::fetch_registers (struct regcache * regcache, -+ int regno) - { - /* Get the thread id for the ptrace call. */ -- int tid = GET_THREAD_ID (inferior_ptid); -+ int tid = regcache->ptid ().lwp (); - - if (regno == -1) - fetch_gp_regs (regcache, tid); -@@ -356,12 +340,12 @@ microblaze_linux_fetch_inferior_registers (struct target_ops *ops, - regno == -1, otherwise store all general registers or all floating - point registers depending upon the value of regno. */ - --static void --microblaze_linux_store_inferior_registers (struct target_ops *ops, -- struct regcache *regcache, int regno) -+void -+microblaze_linux_nat_target::store_registers (struct regcache *regcache, -+ int regno) - { - /* Get the thread id for the ptrace call. */ -- int tid = GET_THREAD_ID (inferior_ptid); -+ int tid = regcache->ptid ().lwp (); - - if (regno >= 0) - store_register (regcache, tid, regno); -@@ -398,12 +382,12 @@ supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) - /* FIXME. */ - } - --static const struct target_desc * --microblaze_linux_read_description (struct target_ops *ops) -+const struct target_desc * -+microblaze_linux_nat_target::read_description () - { -- CORE_ADDR microblaze_hwcap = 0; -+ CORE_ADDR microblaze_hwcap = linux_get_hwcap (this); - -- if (target_auxv_search (ops, AT_HWCAP, µblaze_hwcap) != 1) -+ if (microblaze_hwcap != 1) - return NULL; - - return NULL; -@@ -415,17 +399,7 @@ void _initialize_microblaze_linux_nat (void); - void - _initialize_microblaze_linux_nat (void) - { -- struct target_ops *t; -- -- /* Fill in the generic GNU/Linux methods. */ -- t = linux_target (); -- -- /* Add our register access methods. */ -- t->to_fetch_registers = microblaze_linux_fetch_inferior_registers; -- t->to_store_registers = microblaze_linux_store_inferior_registers; -- -- t->to_read_description = microblaze_linux_read_description; -- - /* Register the target. */ -- linux_nat_add_target (t); -+ linux_target = &the_microblaze_linux_nat_target; -+ add_inf_child_target (&the_microblaze_linux_nat_target); - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index dc1d4686914..a5c12c10e0b 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -106,6 +106,9 @@ enum microblaze_regnum - MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS - }; - -+/* Big enough to hold the size of the largest register in bytes. */ -+#define MICROBLAZE_MAX_REGISTER_SIZE 64 -+ - struct microblaze_frame_cache - { - /* Base address. */ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch new file mode 100644 index 00000000..35466e8f --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch @@ -0,0 +1,279 @@ +From a721a7063f829ccaf6cf8273be04b763b53a735d Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Tue, 9 Nov 2021 16:19:17 +0530 +Subject: [PATCH 09/10] [Patch,MicroBlaze] : Added m64 abi for 64 bit target + descriptions. set m64 abi for 64 bit elf. + +--- + gdb/features/microblaze64.xml | 1 + + gdb/microblaze-tdep.c | 150 ++++++++++++++++++++++++++++++++-- + gdb/microblaze-tdep.h | 11 +++ + 3 files changed, 155 insertions(+), 7 deletions(-) + +diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml +index 515d18e65cf..9c1b7d22003 100644 +--- a/gdb/features/microblaze64.xml ++++ b/gdb/features/microblaze64.xml +@@ -7,5 +7,6 @@ + + + ++ microblaze64 + + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index 667d658adfd..aad6a9cae6e 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -65,8 +65,94 @@ + #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ + ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) + ++static const char *microblaze_abi_string; ++ ++static const char *const microblaze_abi_strings[] = { ++ "auto", ++ "m64", ++}; ++ ++enum microblaze_abi ++microblaze_abi (struct gdbarch *gdbarch) ++{ ++ return gdbarch_tdep (gdbarch)->microblaze_abi; ++} + /* The registers of the Xilinx microblaze processor. */ + ++ static struct cmd_list_element *setmicroblazecmdlist = NULL; ++ static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++static void ++microblaze_abi_update (const char *ignore_args, ++ int from_tty, struct cmd_list_element *c) ++{ ++ struct gdbarch_info info; ++ ++ /* Force the architecture to update, and (if it's a microblaze architecture) ++ * microblaze_gdbarch_init will take care of the rest. */ ++ gdbarch_info_init (&info); ++ gdbarch_update_p (info); ++} ++ ++ ++static enum microblaze_abi ++global_microblaze_abi (void) ++{ ++ int i; ++ ++ for (i = 0; microblaze_abi_strings[i] != NULL; i++) ++ if (microblaze_abi_strings[i] == microblaze_abi_string) ++ return (enum microblaze_abi) i; ++ ++// internal_error (__FILE__, __LINE__, _("unknown ABI string")); ++} ++ ++static void ++show_microblaze_abi (struct ui_file *file, ++ int from_tty, ++ struct cmd_list_element *ignored_cmd, ++ const char *ignored_value) ++{ ++ enum microblaze_abi global_abi = global_microblaze_abi (); ++ enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); ++ const char *actual_abi_str = microblaze_abi_strings[actual_abi]; ++ ++#if 1 ++ if (global_abi == MICROBLAZE_ABI_AUTO) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is set automatically (currently \"%s\").\n", ++ actual_abi_str); ++ else if (global_abi == actual_abi) ++ fprintf_filtered ++ (file, ++ "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", ++ actual_abi_str); ++ else ++ { ++#endif ++ /* Probably shouldn't happen... */ ++ fprintf_filtered (file, ++ "The (auto detected) microblaze ABI \"%s\" is in use " ++ "even though the user setting was \"%s\".\n", ++ actual_abi_str, microblaze_abi_strings[global_abi]); ++ } ++} ++ ++static void ++show_microblaze_command (const char *args, int from_tty) ++{ ++ help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout); ++} ++ ++static void ++set_microblaze_command (const char *args, int from_tty) ++{ ++ printf_unfiltered ++ ("\"set microblaze\" must be followed by an appropriate subcommand.\n"); ++ help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout); ++} ++ + static const char *microblaze_register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", +@@ -85,6 +171,18 @@ static const char *microblaze_register_names[] = + static unsigned int microblaze_debug_flag = 0; + int reg_size = 4; + ++unsigned int ++microblaze_abi_regsize (struct gdbarch *gdbarch) ++{ ++ switch (microblaze_abi (gdbarch)) ++ { ++ case MICROBLAZE_ABI_M64: ++ return 8; ++ default: ++ return 4; ++ } ++} ++ + static void ATTRIBUTE_PRINTF (1, 2) + microblaze_debug (const char *fmt, ...) + { +@@ -880,15 +978,30 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + struct gdbarch_tdep *tdep; + struct gdbarch *gdbarch; + struct tdesc_arch_data *tdesc_data = NULL; ++ enum microblaze_abi microblaze_abi, found_abi, wanted_abi; + const struct target_desc *tdesc = info.target_desc; + ++ /* What has the user specified from the command line? */ ++ wanted_abi = global_microblaze_abi (); ++ if (gdbarch_debug) ++ fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", ++ wanted_abi); ++ if (wanted_abi != MICROBLAZE_ABI_AUTO) ++ microblaze_abi = wanted_abi; ++ + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); +- if (arches != NULL) ++ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) + return arches->gdbarch; ++ ++ if (microblaze_abi == MICROBLAZE_ABI_M64) ++ { ++ tdesc = tdesc_microblaze64; ++ reg_size = 8; ++ } + if (tdesc == NULL) + { +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + { + tdesc = tdesc_microblaze64; + reg_size = 8; +@@ -903,7 +1016,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + int valid_p; + int i; + +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.core"); + else +@@ -917,7 +1030,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + for (i = 0; i < MICROBLAZE_NUM_REGS; i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data, i, + microblaze_register_names[i]); +- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) ++ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.microblaze64.stack-protect"); + else +@@ -968,7 +1081,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + set_gdbarch_ptr_bit (gdbarch, 64); + break; + } +- ++ if(microblaze_abi == MICROBLAZE_ABI_M64) ++ set_gdbarch_ptr_bit (gdbarch, 64); + + /* Map Dwarf2 registers to GDB registers. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); +@@ -1027,7 +1141,30 @@ void + _initialize_microblaze_tdep () + { + register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); +- ++// static struct cmd_list_element *setmicroblazecmdlist = NULL; ++// static struct cmd_list_element *showmicroblazecmdlist = NULL; ++ ++ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ ++ add_prefix_cmd ("microblaze", no_class, set_microblaze_command, ++ _("Various microblaze specific commands."), ++ &setmicroblazecmdlist, "set microblaze ", 0, &setlist); ++ ++ add_prefix_cmd ("microblaze", no_class, show_microblaze_command, ++ _("Various microblaze specific commands."), ++ &showmicroblazecmdlist, "show microblaze ", 0, &showlist); ++ ++ /* Allow the user to override the ABI. */ ++ add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, ++ µblaze_abi_string, _("\ ++Set the microblaze ABI used by this program."), _("\ ++Show the microblaze ABI used by this program."), _("\ ++This option can be set to one of:\n\ ++ auto - the default ABI associated with the current binary\n\ ++ m64"), ++ microblaze_abi_update, ++ show_microblaze_abi, ++ &setmicroblazecmdlist, &showmicroblazecmdlist); ++ + initialize_tdesc_microblaze_with_stack_protect (); + initialize_tdesc_microblaze (); + initialize_tdesc_microblaze64_with_stack_protect (); +@@ -1042,5 +1179,4 @@ When non-zero, microblaze specific debugging is enabled."), + NULL, + &setdebuglist, &showdebuglist); + +- + } +diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h +index e0fa7ef9b12..9cb9628295f 100644 +--- a/gdb/microblaze-tdep.h ++++ b/gdb/microblaze-tdep.h +@@ -19,8 +19,16 @@ + + #ifndef MICROBLAZE_TDEP_H + #define MICROBLAZE_TDEP_H 1 ++#include "objfiles.h" + ++struct gdbarch; ++enum microblaze_abi ++ { ++ MICROBLAZE_ABI_AUTO = 0, ++ MICROBLAZE_ABI_M64, ++ }; + ++enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch); + /* Microblaze architecture-specific information. */ + struct microblaze_gregset + { +@@ -34,11 +42,14 @@ struct gdbarch_tdep + { + int dummy; // declare something. + ++ enum microblaze_abi microblaze_abi; ++ enum microblaze_abi found_abi; + /* Register sets. */ + struct regset *gregset; + size_t sizeof_gregset; + struct regset *fpregset; + size_t sizeof_fpregset; ++ int register_size; + }; + + /* Register numbers. */ +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch deleted file mode 100644 index fca85fa2..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0009-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9ab0a0a551902e5196d46178b57fa1b33b587092 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Mon, 19 Apr 2021 14:33:27 +0530 -Subject: [PATCH 09/10] [Patch,MicroBlaze] : these changes will make 64 bit - vectors as default target types when we built gdb with microblaze 64 bit type - targets,for instance microblaze-xilinx-elf64/microblazeel-xilinx-elf64 - ---- - bfd/config.bfd | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/bfd/config.bfd b/bfd/config.bfd -index 0f752de267b..4945e7fa3b5 100644 ---- a/bfd/config.bfd -+++ b/bfd/config.bfd -@@ -823,7 +823,15 @@ case "${targ}" in - targ_defvec=metag_elf32_vec - targ_underscore=yes - ;; -+ microblazeel*-*64) -+ targ_defvec=microblaze_elf64_le_vec -+ targ_selvecs=microblaze_elf64_vec -+ ;; - -+ microblaze*-*64) -+ targ_defvec=microblaze_elf64_vec -+ targ_selvecs=microblaze_elf64_le_vec -+ ;; - microblazeel*-*) - targ_defvec=microblaze_elf32_le_vec - targ_selvecs=microblaze_elf32_vec --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch deleted file mode 100644 index 78ef9202..00000000 --- a/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch +++ /dev/null @@ -1,279 +0,0 @@ -From 67fd78c3fa5894e0038c09a858cb518c20340abf Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati -Date: Tue, 9 Nov 2021 16:19:17 +0530 -Subject: [PATCH 10/10] [Patch,MicroBlaze] : Added m64 abi for 64 bit target - descriptions. set m64 abi for 64 bit elf. - ---- - gdb/features/microblaze64.xml | 1 + - gdb/microblaze-tdep.c | 150 ++++++++++++++++++++++++++++++++-- - gdb/microblaze-tdep.h | 11 +++ - 3 files changed, 155 insertions(+), 7 deletions(-) - -diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml -index 515d18e65cf..9c1b7d22003 100644 ---- a/gdb/features/microblaze64.xml -+++ b/gdb/features/microblaze64.xml -@@ -7,5 +7,6 @@ - - - -+ microblaze64 - - -diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c -index e51c022c1ba..3bffbbe4b3d 100644 ---- a/gdb/microblaze-tdep.c -+++ b/gdb/microblaze-tdep.c -@@ -65,8 +65,94 @@ - #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ - ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) - -+static const char *microblaze_abi_string; -+ -+static const char *const microblaze_abi_strings[] = { -+ "auto", -+ "m64", -+}; -+ -+enum microblaze_abi -+microblaze_abi (struct gdbarch *gdbarch) -+{ -+ return gdbarch_tdep (gdbarch)->microblaze_abi; -+} - /* The registers of the Xilinx microblaze processor. */ - -+ static struct cmd_list_element *setmicroblazecmdlist = NULL; -+ static struct cmd_list_element *showmicroblazecmdlist = NULL; -+ -+static void -+microblaze_abi_update (const char *ignore_args, -+ int from_tty, struct cmd_list_element *c) -+{ -+ struct gdbarch_info info; -+ -+ /* Force the architecture to update, and (if it's a microblaze architecture) -+ * microblaze_gdbarch_init will take care of the rest. */ -+ gdbarch_info_init (&info); -+ gdbarch_update_p (info); -+} -+ -+ -+static enum microblaze_abi -+global_microblaze_abi (void) -+{ -+ int i; -+ -+ for (i = 0; microblaze_abi_strings[i] != NULL; i++) -+ if (microblaze_abi_strings[i] == microblaze_abi_string) -+ return (enum microblaze_abi) i; -+ -+// internal_error (__FILE__, __LINE__, _("unknown ABI string")); -+} -+ -+static void -+show_microblaze_abi (struct ui_file *file, -+ int from_tty, -+ struct cmd_list_element *ignored_cmd, -+ const char *ignored_value) -+{ -+ enum microblaze_abi global_abi = global_microblaze_abi (); -+ enum microblaze_abi actual_abi = microblaze_abi (target_gdbarch ()); -+ const char *actual_abi_str = microblaze_abi_strings[actual_abi]; -+ -+#if 1 -+ if (global_abi == MICROBLAZE_ABI_AUTO) -+ fprintf_filtered -+ (file, -+ "The microblaze ABI is set automatically (currently \"%s\").\n", -+ actual_abi_str); -+ else if (global_abi == actual_abi) -+ fprintf_filtered -+ (file, -+ "The microblaze ABI is assumed to be \"%s\" (due to user setting).\n", -+ actual_abi_str); -+ else -+ { -+#endif -+ /* Probably shouldn't happen... */ -+ fprintf_filtered (file, -+ "The (auto detected) microblaze ABI \"%s\" is in use " -+ "even though the user setting was \"%s\".\n", -+ actual_abi_str, microblaze_abi_strings[global_abi]); -+ } -+} -+ -+static void -+show_microblaze_command (const char *args, int from_tty) -+{ -+ help_list (showmicroblazecmdlist, "show microblaze ", all_commands, gdb_stdout); -+} -+ -+static void -+set_microblaze_command (const char *args, int from_tty) -+{ -+ printf_unfiltered -+ ("\"set microblaze\" must be followed by an appropriate subcommand.\n"); -+ help_list (setmicroblazecmdlist, "set microblaze ", all_commands, gdb_stdout); -+} -+ - static const char *microblaze_register_names[] = - { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", -@@ -85,6 +171,18 @@ static const char *microblaze_register_names[] = - static unsigned int microblaze_debug_flag = 0; - int reg_size = 4; - -+unsigned int -+microblaze_abi_regsize (struct gdbarch *gdbarch) -+{ -+ switch (microblaze_abi (gdbarch)) -+ { -+ case MICROBLAZE_ABI_M64: -+ return 8; -+ default: -+ return 4; -+ } -+} -+ - static void ATTRIBUTE_PRINTF (1, 2) - microblaze_debug (const char *fmt, ...) - { -@@ -855,15 +953,30 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - struct gdbarch_tdep *tdep; - struct gdbarch *gdbarch; - struct tdesc_arch_data *tdesc_data = NULL; -+ enum microblaze_abi microblaze_abi, found_abi, wanted_abi; - const struct target_desc *tdesc = info.target_desc; - -+ /* What has the user specified from the command line? */ -+ wanted_abi = global_microblaze_abi (); -+ if (gdbarch_debug) -+ fprintf_unfiltered (gdb_stdlog, "microblaze_gdbarch_init: wanted_abi = %d\n", -+ wanted_abi); -+ if (wanted_abi != MICROBLAZE_ABI_AUTO) -+ microblaze_abi = wanted_abi; -+ - /* If there is already a candidate, use it. */ - arches = gdbarch_list_lookup_by_info (arches, &info); -- if (arches != NULL) -+ if ((arches != NULL) && (microblaze_abi != MICROBLAZE_ABI_M64)) - return arches->gdbarch; -+ -+ if (microblaze_abi == MICROBLAZE_ABI_M64) -+ { -+ tdesc = tdesc_microblaze64; -+ reg_size = 8; -+ } - if (tdesc == NULL) - { -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - { - tdesc = tdesc_microblaze64; - reg_size = 8; -@@ -878,7 +991,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - int valid_p; - int i; - -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - feature = tdesc_find_feature (tdesc, - "org.gnu.gdb.microblaze64.core"); - else -@@ -892,7 +1005,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - for (i = 0; i < MICROBLAZE_NUM_REGS; i++) - valid_p &= tdesc_numbered_register (feature, tdesc_data, i, - microblaze_register_names[i]); -- if (info.bfd_arch_info->mach == bfd_mach_microblaze64) -+ if ((info.bfd_arch_info->mach == bfd_mach_microblaze64) || (microblaze_abi == MICROBLAZE_ABI_M64)) - feature = tdesc_find_feature (tdesc, - "org.gnu.gdb.microblaze64.stack-protect"); - else -@@ -943,7 +1056,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - set_gdbarch_ptr_bit (gdbarch, 64); - break; - } -- -+ if(microblaze_abi == MICROBLAZE_ABI_M64) -+ set_gdbarch_ptr_bit (gdbarch, 64); - - /* Map Dwarf2 registers to GDB registers. */ - set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); -@@ -1000,7 +1114,30 @@ void - _initialize_microblaze_tdep () - { - register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); -- -+// static struct cmd_list_element *setmicroblazecmdlist = NULL; -+// static struct cmd_list_element *showmicroblazecmdlist = NULL; -+ -+ /* Add root prefix command for all "set microblaze"/"show microblaze" commands. */ -+ add_prefix_cmd ("microblaze", no_class, set_microblaze_command, -+ _("Various microblaze specific commands."), -+ &setmicroblazecmdlist, "set microblaze ", 0, &setlist); -+ -+ add_prefix_cmd ("microblaze", no_class, show_microblaze_command, -+ _("Various microblaze specific commands."), -+ &showmicroblazecmdlist, "show microblaze ", 0, &showlist); -+ -+ /* Allow the user to override the ABI. */ -+ add_setshow_enum_cmd ("abi", class_obscure, microblaze_abi_strings, -+ µblaze_abi_string, _("\ -+Set the microblaze ABI used by this program."), _("\ -+Show the microblaze ABI used by this program."), _("\ -+This option can be set to one of:\n\ -+ auto - the default ABI associated with the current binary\n\ -+ m64"), -+ microblaze_abi_update, -+ show_microblaze_abi, -+ &setmicroblazecmdlist, &showmicroblazecmdlist); -+ - initialize_tdesc_microblaze_with_stack_protect (); - initialize_tdesc_microblaze (); - initialize_tdesc_microblaze64_with_stack_protect (); -@@ -1015,5 +1152,4 @@ When non-zero, microblaze specific debugging is enabled."), - NULL, - &setdebuglist, &showdebuglist); - -- - } -diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h -index a5c12c10e0b..29da6d29dcb 100644 ---- a/gdb/microblaze-tdep.h -+++ b/gdb/microblaze-tdep.h -@@ -19,8 +19,16 @@ - - #ifndef MICROBLAZE_TDEP_H - #define MICROBLAZE_TDEP_H 1 -+#include "objfiles.h" - -+struct gdbarch; -+enum microblaze_abi -+ { -+ MICROBLAZE_ABI_AUTO = 0, -+ MICROBLAZE_ABI_M64, -+ }; - -+enum microblaze_abi microblaze_abi (struct gdbarch *gdbarch); - /* Microblaze architecture-specific information. */ - struct microblaze_gregset - { -@@ -34,11 +42,14 @@ struct gdbarch_tdep - { - int dummy; // declare something. - -+ enum microblaze_abi microblaze_abi; -+ enum microblaze_abi found_abi; - /* Register sets. */ - struct regset *gregset; - size_t sizeof_gregset; - struct regset *fpregset; - size_t sizeof_fpregset; -+ int register_size; - }; - - /* Register numbers. */ --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch new file mode 100644 index 00000000..dc38b480 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch @@ -0,0 +1,401 @@ +From 01e16382c8fce4448c911a4c5780259e181e83dd Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Fri, 8 Jul 2022 12:53:51 +0530 +Subject: [PATCH 10/10] [Patch,MicroBlaze]: Code changes for gdbserver. + +--- + gdb/features/Makefile | 1 + + gdb/features/microblaze-linux.xml | 1 + + gdb/regformats/microblaze-linux.dat | 64 +++++++++ + gdbserver/Makefile.in | 5 +- + gdbserver/configure.srv | 1 + + ...croblaze-low.c => linux-microblaze-low.cc} | 132 ++++++++++-------- + 6 files changed, 138 insertions(+), 66 deletions(-) + create mode 100644 gdb/regformats/microblaze-linux.dat + rename gdbserver/{linux-microblaze-low.c => linux-microblaze-low.cc} (72%) + +diff --git a/gdb/features/Makefile b/gdb/features/Makefile +index 131fc14adbf..1b15305862e 100644 +--- a/gdb/features/Makefile ++++ b/gdb/features/Makefile +@@ -47,6 +47,7 @@ + WHICH = mips-linux mips-dsp-linux \ + microblaze-with-stack-protect \ + microblaze64-with-stack-protect \ ++ microblaze-linux \ + mips64-linux mips64-dsp-linux \ + nios2-linux \ + rs6000/powerpc-32 \ +diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml +index 8983e66eb3d..688a3f83d1e 100644 +--- a/gdb/features/microblaze-linux.xml ++++ b/gdb/features/microblaze-linux.xml +@@ -7,6 +7,7 @@ + + + ++ microblaze + GNU/Linux + + +diff --git a/gdb/regformats/microblaze-linux.dat b/gdb/regformats/microblaze-linux.dat +new file mode 100644 +index 00000000000..b5b49f485cd +--- /dev/null ++++ b/gdb/regformats/microblaze-linux.dat +@@ -0,0 +1,64 @@ ++# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro: ++# Generated from: microblaze-linux.xml ++name:microblaze_linux ++xmltarget:microblaze-linux.xml ++expedite:r1,rpc ++32:r0 ++32:r1 ++32:r2 ++32:r3 ++32:r4 ++32:r5 ++32:r6 ++32:r7 ++32:r8 ++32:r9 ++32:r10 ++32:r11 ++32:r12 ++32:r13 ++32:r14 ++32:r15 ++32:r16 ++32:r17 ++32:r18 ++32:r19 ++32:r20 ++32:r21 ++32:r22 ++32:r23 ++32:r24 ++32:r25 ++32:r26 ++32:r27 ++32:r28 ++32:r29 ++32:r30 ++32:r31 ++32:rpc ++32:rmsr ++32:rear ++32:resr ++32:rfsr ++32:rbtr ++32:rpvr0 ++32:rpvr1 ++32:rpvr2 ++32:rpvr3 ++32:rpvr4 ++32:rpvr5 ++32:rpvr6 ++32:rpvr7 ++32:rpvr8 ++32:rpvr9 ++32:rpvr10 ++32:rpvr11 ++32:redr ++32:rpid ++32:rzpr ++32:rtlbx ++32:rtlbsx ++32:rtlblo ++32:rtlbhi ++32:slr ++32:shr +diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in +index 46b5a0c7c60..eaaf6820fe0 100644 +--- a/gdbserver/Makefile.in ++++ b/gdbserver/Makefile.in +@@ -184,7 +184,7 @@ SFILES = \ + $(srcdir)/linux-ia64-low.cc \ + $(srcdir)/linux-low.cc \ + $(srcdir)/linux-m68k-low.cc \ +- $(srcdir)/linux-microblaze-low.c \ ++ $(srcdir)/linux-microblaze-low.cc \ + $(srcdir)/linux-mips-low.cc \ + $(srcdir)/linux-nios2-low.cc \ + $(srcdir)/linux-ppc-low.cc \ +@@ -222,7 +222,6 @@ SFILES = \ + $(srcdir)/../gdb/nat/linux-namespaces.c \ + $(srcdir)/../gdb/nat/linux-osdata.c \ + $(srcdir)/../gdb/nat/linux-personality.c \ +- $(srcdir)/../gdb/nat/microblaze-linux.c \ + $(srcdir)/../gdb/nat/mips-linux-watch.c \ + $(srcdir)/../gdb/nat/ppc-linux.c \ + $(srcdir)/../gdb/nat/riscv-linux-tdesc.c \ +@@ -564,8 +563,6 @@ target/%.o: ../gdb/target/%.c + + %-generated.cc: ../gdb/regformats/rs6000/%.dat $(regdat_sh) + $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@ +-microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh) +- $(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c + + # + # Dependency tracking. +diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv +index af10cb05683..026b156bd60 100644 +--- a/gdbserver/configure.srv ++++ b/gdbserver/configure.srv +@@ -169,6 +169,7 @@ case "${gdbserver_host}" in + microblaze*-*-linux*) srv_regobj="microblaze-linux.o" + srv_tgtobj="$srv_linux_obj linux-microblaze-low.o " + srv_xmlfiles="microblaze-linux.xml" ++ srv_xmlfiles="${srv_xmlfiles} microblaze-core.xml" + srv_linux_regsets=yes + srv_linux_usrregs=yes + srv_linux_thread_db=yes +diff --git a/gdbserver/linux-microblaze-low.c b/gdbserver/linux-microblaze-low.cc +similarity index 72% +rename from gdbserver/linux-microblaze-low.c +rename to gdbserver/linux-microblaze-low.cc +index a2733f3c21c..d30fa102b5e 100644 +--- a/gdbserver/linux-microblaze-low.c ++++ b/gdbserver/linux-microblaze-low.cc +@@ -20,12 +20,17 @@ + #include "server.h" + #include "linux-low.h" + ++#include "elf/common.h" ++#include "nat/gdb_ptrace.h" ++#include ++ + #include + #include + #include + + #include "gdb_proc_service.h" + ++ + static int microblaze_regmap[] = + {PT_GPR(0), PT_GPR(1), PT_GPR(2), PT_GPR(3), + PT_GPR(4), PT_GPR(5), PT_GPR(6), PT_GPR(7), +@@ -39,14 +44,46 @@ static int microblaze_regmap[] = + PT_FSR + }; + ++ ++ ++class microblaze_target : public linux_process_target ++{ ++public: ++ ++ const regs_info *get_regs_info () override; ++ ++ const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; ++ // CORE_ADDR microblaze_reinsert_addr (regcache *regcache); ++ ++protected: ++ ++ void low_arch_setup () override; ++ ++ bool low_cannot_fetch_register (int regno) override; ++ ++ bool low_cannot_store_register (int regno) override; ++ ++ // bool low_supports_breakpoints () override; ++ ++ CORE_ADDR low_get_pc (regcache *regcache) override; ++ ++ void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; ++ ++ bool low_breakpoint_at (CORE_ADDR pc) override; ++}; ++ ++/* The singleton target ops object. */ ++ ++static microblaze_target the_microblaze_target; ++ + #define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0])) + + /* Defined in auto-generated file microblaze-linux.c. */ +-void init_registers_microblaze (void); +-extern const struct target_desc *tdesc_microblaze; ++void init_registers_microblaze_linux (void); ++extern const struct target_desc *tdesc_microblaze_linux; + +-static int +-microblaze_cannot_store_register (int regno) ++bool ++microblaze_target::low_cannot_store_register (int regno) + { + if (microblaze_regmap[regno] == -1 || regno == 0) + return 1; +@@ -54,14 +91,14 @@ microblaze_cannot_store_register (int regno) + return 0; + } + +-static int +-microblaze_cannot_fetch_register (int regno) ++bool ++microblaze_target::low_cannot_fetch_register (int regno) + { + return 0; + } + +-static CORE_ADDR +-microblaze_get_pc (struct regcache *regcache) ++CORE_ADDR ++microblaze_target::low_get_pc (struct regcache *regcache) + { + unsigned long pc; + +@@ -69,8 +106,8 @@ microblaze_get_pc (struct regcache *regcache) + return (CORE_ADDR) pc; + } + +-static void +-microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc) ++void ++microblaze_target::low_set_pc (struct regcache *regcache, CORE_ADDR pc) + { + unsigned long newpc = pc; + +@@ -84,34 +121,35 @@ static const unsigned long microblaze_breakpoint = 0xba0c0018; + + /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ + +-static const gdb_byte * +-microblaze_sw_breakpoint_from_kind (int kind, int *size) ++const gdb_byte * ++microblaze_target::sw_breakpoint_from_kind (int kind, int *size) + { + *size = microblaze_breakpoint_len; + return (const gdb_byte *) µblaze_breakpoint; + } + +-static int +-microblaze_breakpoint_at (CORE_ADDR where) ++bool ++microblaze_target::low_breakpoint_at (CORE_ADDR where) + { + unsigned long insn; + +- (*the_target->read_memory) (where, (unsigned char *) &insn, 4); ++ read_memory (where, (unsigned char *) &insn, 4); + if (insn == microblaze_breakpoint) + return 1; + /* If necessary, recognize more trap instructions here. GDB only uses the + one. */ + return 0; + } +- +-static CORE_ADDR +-microblaze_reinsert_addr (struct regcache *regcache) ++#if 0 ++CORE_ADDR ++microblaze_target::microblaze_reinsert_addr (struct regcache *regcache) + { + unsigned long pc; + collect_register_by_name (regcache, "r15", &pc); + return pc; + } +- ++#endif ++#if 0 + #ifdef HAVE_PTRACE_GETREGS + + static void +@@ -166,12 +204,15 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf) + } + + #endif /* HAVE_PTRACE_GETREGS */ ++#endif + + static struct regset_info microblaze_regsets[] = { ++#if 0 + #ifdef HAVE_PTRACE_GETREGS + { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset }, + { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, + #endif /* HAVE_PTRACE_GETREGS */ ++#endif + { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL }, + NULL_REGSET + }; +@@ -189,17 +230,17 @@ static struct regsets_info microblaze_regsets_info = + NULL, /* disabled_regsets */ + }; + +-static struct regs_info regs_info = ++static struct regs_info microblaze_regs_info = + { + NULL, /* regset_bitmap */ + µblaze_usrregs_info, + µblaze_regsets_info + }; + +-static const struct regs_info * +-microblaze_regs_info (void) ++const regs_info * ++microblaze_target::get_regs_info (void) + { +- return ®s_info; ++ return µblaze_regs_info; + } + + /* Support for hardware single step. */ +@@ -211,50 +252,17 @@ microblaze_supports_hardware_single_step (void) + } + + +-static void +-microblaze_arch_setup (void) ++void ++microblaze_target::low_arch_setup (void) + { +- current_process ()->tdesc = tdesc_microblaze; ++ current_process ()->tdesc = tdesc_microblaze_linux; + } + +-struct linux_target_ops the_low_target = { +- microblaze_arch_setup, +- microblaze_regs_info, +- microblaze_cannot_fetch_register, +- microblaze_cannot_store_register, +- NULL, /* fetch_register */ +- microblaze_get_pc, +- microblaze_set_pc, +- NULL, +- microblaze_sw_breakpoint_from_kind, +- NULL, +- 0, +- microblaze_breakpoint_at, +- NULL, +- NULL, +- NULL, +- NULL, +- NULL, +- microblaze_collect_ptrace_register, +- microblaze_supply_ptrace_register, +- NULL, /* siginfo_fixup */ +- NULL, /* new_process */ +- NULL, /* new_thread */ +- NULL, /* new_fork */ +- NULL, /* prepare_to_resume */ +- NULL, /* process_qsupported */ +- NULL, /* supports_tracepoints */ +- NULL, /* get_thread_area */ +- NULL, /* install_fast_tracepoint_jump_pad */ +- NULL, /* emit_ops */ +- NULL, /* get_min_fast_tracepoint_insn_len */ +- NULL, /* supports_range_stepping */ +- NULL, /* breakpoint_kind_from_current_state */ +- microblaze_supports_hardware_single_step, +-}; ++linux_process_target *the_linux_target = &the_microblaze_target; + + void + initialize_low_arch (void) + { +- init_registers_microblaze (); ++ init_registers_microblaze_linux (); ++ initialize_regsets_info (µblaze_regsets_info); + } +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend b/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend index 23866471..33fbe158 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend +++ b/meta-microblaze/recipes-devtools/gdb/gdb_%.bbappend @@ -1,11 +1,4 @@ MICROBLAZEPATCHES = "" MICROBLAZEPATCHES:microblaze = "gdb-microblaze.inc" -# We don't have ptrace support for on-target microblaze GDB currently. Need -# to use tcf-agent or other external debug interface. -MB_DOES_NOT_WORK = "" -MB_DOES_NOT_WORK:microblaze = "GDB is not currently supported on Microblaze." - -PNBLACKLIST[gdb] = "${MB_DOES_NOT_WORK}" - require ${MICROBLAZEPATCHES} -- cgit v1.2.3-54-g00ecf From 88e7855bc6988f4cd77e379a4b52ca50650bba4e Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Mon, 18 Jul 2022 12:35:18 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb index a0102fe9..92279e31 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb @@ -8,7 +8,7 @@ BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -SRCREV = "1a1454ed0c3a56912250182f591c051f355fbf47" +SRCREV = "cb36032844b3845ad28007404d0566184504c03f" COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE:zynqmp = "zynqmp" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb index ac864bb3..5f2dea6e 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb @@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" BRANCH ?= "master" REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV = "57ddd9c066fa622044fdef74b4605e9fbcc4ebfb" +SRCREV = "9956b4a1229fc667e2a71164fc21e0b2a1aab4de" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 3842ce01dba6024ace5a58e098569eea782dc77d Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 18 Jul 2022 21:40:54 +0530 Subject: lopper: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index ce782759..06417199 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "9159040dab25e2f1e7b447fcbfcd5397b1d618e8" +SRCREV = "e1429f59d27ac54749efe3c8cfe9ced348a339ca" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 35ec17764fd0884aeeadb3bf76074e8fe434e6e2 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 20 Jul 2022 14:16:20 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index f5e88b4b..5ca278e8 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "682674d3286122c2ff74e438d30daa455b174d0a" +SRCREV = "38aecb0fe734d83f5c6857cceaa2cdd6083d667e" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 318a8b20..c572d4cb 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "a04ae753061d4bd14bbd92713cbdcb85a84c47c1" +SRCREV = "b3b5f8537c3c64e98cc7a093b41aec5afa9cd110" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index ed3b3f36..5786a7ae 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "9c6cb7c9a0c2a38426f1e8e18277fb0938e17e6f" +ESW_REV[2022.2] = "da6412643745289264dd2b5df517e8302ab6508d" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 685cb9b3315265488135ad2a8b0ed1a79f9adb41 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 20 Jul 2022 15:18:15 +0530 Subject: Updated for MD5SUM for ESW license Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 5786a7ae..a516cde8 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -36,7 +36,7 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' -LIC_FILES_CHKSUM[master-next] = 'e62cb7a722c4430999e0a55a7234035d' +LIC_FILES_CHKSUM[master-next] = '7b5fc0b2a22e2882e1506436b3293e5d' LIC_FILES_CHKSUM[master] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" -- cgit v1.2.3-54-g00ecf From 03f4e86110aa9e442250b947400827b528259f39 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 19 Jul 2022 08:58:04 -0700 Subject: meta-microblaze: gdb is now available Signed-off-by: Mark Hatle --- meta-microblaze/recipes-extended/ltp/ltp_%.bbappend | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 meta-microblaze/recipes-extended/ltp/ltp_%.bbappend diff --git a/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend b/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend deleted file mode 100644 index 85bcc731..00000000 --- a/meta-microblaze/recipes-extended/ltp/ltp_%.bbappend +++ /dev/null @@ -1,2 +0,0 @@ -# gdb on-target is not supported on Microblaze -RDEPENDS:${PN}:remove:microblaze = "gdb" -- cgit v1.2.3-54-g00ecf From 062387f1bcc450e84a4ea9e1f86706e6dd2329d4 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 20 Jul 2022 14:25:55 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 13880e4d..b5b724ee 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "a2bc0a4286d48b78e43dea4504b7483665d4e148" +ESW_REV[experimental] = "74445062bbc79dd3ac2fe4fe6ecbc50034b7c472" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 1b9eb52ff36db393b989a90a381d7795be7c6a9f Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 21 Jul 2022 15:59:36 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 5ca278e8..c362d1d4 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "38aecb0fe734d83f5c6857cceaa2cdd6083d667e" +SRCREV = "221e6b9accca2e6caba05044572e83b5f3e77185" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index a516cde8..10b38464 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "da6412643745289264dd2b5df517e8302ab6508d" +ESW_REV[2022.2] = "7e0347e888f53195291950772e5392dc627d0698" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 0485f134db913ddbfb1ab1b1cd31d8244c9547b9 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 22 Jul 2022 13:36:10 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c572d4cb..e111b754 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "b3b5f8537c3c64e98cc7a093b41aec5afa9cd110" +SRCREV = "03d631bcb6caa363eb2f34e46ad8726509cc72a7" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 10b38464..0f7bb838 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "7e0347e888f53195291950772e5392dc627d0698" +ESW_REV[2022.2] = "70357611ddfeb791c08645fb53a158267067f2f9" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 4dd53057341c8a88a0e89f623330f4f9a1915561 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 22 Jul 2022 09:29:13 -0700 Subject: libdfx_1.0.bb: Manually specify that 'libdfx' package is being replaced The commit a64ff0bf015adcefbe691a94ac3e8ecf1a2ba911 updated the upstream source to include correct soname/soversion. Packaging was then modified to follow this example. The end result was that 'libdfx' was replaced by the automatic "libdfx1.0" package. This could result in: Error: Transaction test error: file /usr/lib/libdfx.so from install of libdfx-dev-1.0-r0.1.cortexa72_cortexa53 conflicts with file from package libdfx-1.0-r0.0.cortexa72_cortexa53 The cause was that libdfx wasn't upgraded when libdfx-dev was being installed. To resolve this we use RREPLACES, may look strange but this will instruct the system that "libdfx" is to be replaced by the dynamically generated package based on the soname. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb index 92279e31..c0f2fb97 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_1.0.bb @@ -18,3 +18,6 @@ S = "${WORKDIR}/git" inherit cmake +# Due to an update where the soname/version was defined, we need to use an RREPLACES +# so updates will work properly. +RREPLACES:${PN} = "libdfx" -- cgit v1.2.3-54-g00ecf From ebbc93a645b87036fe4f226dff0e081b1a57d411 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 25 Jul 2022 14:30:48 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 0f7bb838..095422bf 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "70357611ddfeb791c08645fb53a158267067f2f9" +ESW_REV[2022.2] = "bd988a26e444e74566535b5a47c78cb9638270f3" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 2035958a5f1a8b409b1b50a2dfce8916ca76785a Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Sat, 23 Jul 2022 15:58:54 -0500 Subject: meta-xilinx-pynq: Add missing meta-python dependency Signed-off-by: Mark Hatle --- meta-xilinx-pynq/conf/layer.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-pynq/conf/layer.conf b/meta-xilinx-pynq/conf/layer.conf index 5c0d3e77..4beedc2b 100644 --- a/meta-xilinx-pynq/conf/layer.conf +++ b/meta-xilinx-pynq/conf/layer.conf @@ -9,7 +9,7 @@ BBFILE_COLLECTIONS += "xilinx-pynq" BBFILE_PATTERN_xilinx-pynq = "^${LAYERDIR}/" BBFILE_PRIORITY_xilinx-pynq = "5" -LAYERDEPENDS_xilinx-pynq = "core xilinx" +LAYERDEPENDS_xilinx-pynq = "core xilinx meta-python" LAYERSERIES_COMPAT_xilinx-pynq = "honister" -- cgit v1.2.3-54-g00ecf From d2fc12ecfddb84520f2fd9c2aa0eceee93263626 Mon Sep 17 00:00:00 2001 From: Corey Thompson Date: Mon, 2 May 2022 13:56:52 -0400 Subject: extract-cdo: Avoid directly populating ${DEPLOY_DIR_IMAGE} This creates problems when images are deployed from sstate cache. Avoid it by extracting the xilinx-bootbin boot.bin file into the extract-cdo build dir ${B}. Then deploy from the output from ${B}. (Original commit submitted by Corey Thompson ) Commit adjusted to change extraction directory vs copying the boot.bin. Update the summary to better reflect what this is doing, as well as the do_compile comment. Disable (noexec) the do_install as this isn't a target package. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb b/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb index 37c284ad..8b1e52ac 100644 --- a/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb @@ -1,4 +1,4 @@ -DESCRIPTION = "Recipe to copy external cdos" +DESCRIPTION = "Recipe to extract pmc_cdo for qemu usage" LICENSE = "CLOSED" @@ -21,14 +21,19 @@ BOOTGEN_CMD ?= "bootgen" BOOTGEN_ARGS ?= "-arch versal" BOOTGEN_OUTFILE ?= "${DEPLOY_DIR_IMAGE}/boot.bin" -#The following line creates the pmc_cdo.bin file at the same dir as the boot.bin which is DEPLOY_DIR_IMAGE +# bootgen extracts the pmc_cdo file from the boot.bin. By default this +# happens in the same directory as the boot.bin. We need to move it to +# this directory, as do_compile should never write into a deploy dir do_compile() { - ${BOOTGEN_CMD} ${BOOTGEN_ARGS} -dump ${BOOTGEN_OUTFILE} pmc_cdo + ${BOOTGEN_CMD} ${BOOTGEN_ARGS} -dump_dir ${B} -dump ${BOOTGEN_OUTFILE} pmc_cdo } +do_install[noexec] = '1' + do_deploy() { install -d ${DEPLOYDIR}/CDO - install -m 0644 ${DEPLOY_DIR_IMAGE}/pmc_cdo.bin ${DEPLOYDIR}/CDO/pmc_cdo.bin + install -m 0644 ${B}/pmc_cdo.bin ${DEPLOYDIR}/CDO/pmc_cdo.bin + install -m 0644 ${B}/pmc_cdo.bin ${DEPLOYDIR}/pmc_cdo.bin } -addtask do_deploy after do_install +addtask do_deploy after do_compile -- cgit v1.2.3-54-g00ecf From 13e1a00011e48dc20dae3e7f452590a3789a5d7f Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Mon, 25 Jul 2022 22:20:58 -0700 Subject: dfx-mgr: SRCREV: dfxmgr_uio_by_name and examples The SRCREV is for commits to fix SEGV on Ububtu apt install, DFX_ERR, DFX_DBG macros, listUIO option, dfxmgr_uio_by_name, firmware detection, a few compiler warnings. Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index a7013d2a..7040284c 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "0b15aa49b4af64449bd859a025bb3c97c0e9a64e" +SRCREV = "4135349fd3c8daeabbd4504546b64bfed200337e" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From 7b36af1062e9e6e3450cb10554c3f8793cb83486 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 27 Jul 2022 15:17:58 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index c362d1d4..1808794e 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "221e6b9accca2e6caba05044572e83b5f3e77185" +SRCREV = "0526f9197344a78e73cc3c96a1faada825f818b6" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index e111b754..7caeafed 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "03d631bcb6caa363eb2f34e46ad8726509cc72a7" +SRCREV = "66563d3cfa2cefa11ea7160f7fb6ba499c1fc8a1" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 095422bf..06ee9e49 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "bd988a26e444e74566535b5a47c78cb9638270f3" +ESW_REV[2022.2] = "6a2f9457f27c184e2629bb1d31ff55446e95d327" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 4515fa9d600b18d937f11aaa0b7120eb30b6dbac Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 28 Jul 2022 13:13:13 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 06ee9e49..adbaa66f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "6a2f9457f27c184e2629bb1d31ff55446e95d327" +ESW_REV[2022.2] = "e494d2eb8476245f8e45330c39a7e324f106d9d7" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From c33f7cca2a739a9b6ce49cdff310f925c6f5b4d8 Mon Sep 17 00:00:00 2001 From: Jeremy Puhlman Date: Wed, 4 May 2022 14:29:13 -0400 Subject: qemu-xilinx-native.inc: add meson and ninja | ERROR: Cannot find Ninja Signed-off-by: Jeremy A. Puhlman Signed-off-by: Mark Hatle (cherry picked from commit c3acb3cc3f7672cc958848da30d6e1fb4224e807) Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc index 3faabe5b..b22ab432 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc @@ -1,7 +1,7 @@ require recipes-devtools/qemu/qemu-native.inc require qemu-xilinx.inc -DEPENDS = "glib-2.0-native zlib-native" +DEPENDS = "glib-2.0-native zlib-native ninja-native meson-native" SRC_URI:remove = "file://0012-fix-libcap-header-issue-on-some-distro.patch" SRC_URI:remove = "file://0013-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch" -- cgit v1.2.3-54-g00ecf From 02d25b33e88f593f01142183cd2291098b985d18 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 4 May 2022 19:32:53 -0500 Subject: xrt_git.bb: Cleanup += usage Resolve the following warning WARNING: .../meta-xilinx/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb: EXTRA_OECMAKE:append:versal-ai-core += is not a recommended operator combination, please replace it. Signed-off-by: Mark Hatle (cherry picked from commit ef9c8af437edf770d983800c58c5e32df4a740d6) Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index 4a697bf4..96aac96f 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -25,14 +25,14 @@ EXTRA_OECMAKE += " \ -DCMAKE_EXPORT_COMPILE_COMANDS=ON \ " PACKAGE_ARCH:versal-ai-core = "${SOC_VARIANT_ARCH}" -EXTRA_OECMAKE:append:versal-ai-core += "-DXRT_AIE_BUILD=true" -TARGET_CXXFLAGS:append:versal-ai-core += "-DXRT_ENABLE_AIE" -DEPENDS:append:versal-ai-core += " libmetal libxaiengine aiefal" -RDEPENDS:${PN}:append:versal-ai-core += " libxaiengine aiefal" -EXTRA_OECMAKE:append:versal += "-DXRT_LIBDFX=true" -EXTRA_OECMAKE:append:zynqmp += "-DXRT_LIBDFX=true" -DEPENDS:append:versal += "libdfx" -DEPENDS:append:zynqmp += "libdfx" +EXTRA_OECMAKE:append:versal-ai-core = " -DXRT_AIE_BUILD=true" +TARGET_CXXFLAGS:append:versal-ai-core = " -DXRT_ENABLE_AIE" +DEPENDS:append:versal-ai-core = " libmetal libxaiengine aiefal" +RDEPENDS:${PN}:append:versal-ai-core = " libxaiengine aiefal" +EXTRA_OECMAKE:append:versal = " -DXRT_LIBDFX=true" +EXTRA_OECMAKE:append:zynqmp = " -DXRT_LIBDFX=true" +DEPENDS:append:versal = " libdfx" +DEPENDS:append:zynqmp = " libdfx" FILES_SOLIBSDEV = "" -- cgit v1.2.3-54-g00ecf From d7056523ec7d65ecf0f680f4c6379f064e256698 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Wed, 27 Jul 2022 17:34:12 +0530 Subject: qemu-devicetrees: Update SRCREV and remove qemu patch from layers Removing the patch which replaces the python -> python3 as it was fixed in qemu/dts repo. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Mark Hatle --- .../recipes-devtools/qemu/qemu-devicetrees.inc | 3 -- ...01-Makefile-Use-python3-instead-of-python.patch | 37 ---------------------- .../qemu/qemu-devicetrees_2022.2.bb | 3 +- 3 files changed, 2 insertions(+), 41 deletions(-) delete mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc index 6d834297..9ee8174a 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc @@ -9,9 +9,6 @@ LIC_FILES_CHKSUM = "file://Makefile;beginline=1;endline=27;md5=7348b6cbcae69912c PV = "xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" -FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" -SRC_URI:append = " file://0001-Makefile-Use-python3-instead-of-python.patch" - REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch deleted file mode 100644 index 425145d0..00000000 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch +++ /dev/null @@ -1,37 +0,0 @@ -From e80324e3497e5768c9fdbde3c0660a03d0dcc3ee Mon Sep 17 00:00:00 2001 -From: Sai Hari Chandana Kalluri -Date: Mon, 8 Feb 2021 16:32:34 -0800 -Subject: [PATCH] Makefile:Use python3 instead of python - -Signed-off-by: Sai Hari Chandana Kalluri ---- - Makefile | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/Makefile b/Makefile -index a110483..fd8868c 100644 ---- a/Makefile -+++ b/Makefile -@@ -91,13 +91,13 @@ $(LQSPI_XIP_OUTDIR)/%.dts: %.dts $(DTSI_FILES) $(HEADER_FILES) - # TODO: Add support for auto-generated dependency list - versal-pmc-npi.dtsi: versal-pmc-npi-nxx.dtsi versal-h10-pmc-npi-nxx.dtsi - versal-pmc-npi-nxx.dtsi: Makefile -- @python -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ -- @python -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -- @python -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ -+ @python3 -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ - versal-h10-pmc-npi-nxx.dtsi: Makefile -- @python -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@ -- @python -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -- @python -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@ -+ @python3 -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@ -+ @python3 -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@ - - clean: - $(RM) versal-pmc-npi-nxx.dtsi --- -2.7.4 - diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index fa03e3e0..f65f3d21 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,4 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "ba78633a5aef6fe279ec90d1429480bb75365452" +SRCREV ?= "fac9ca0c139c2f6496c879138e5a83221835ae26" + -- cgit v1.2.3-54-g00ecf From 6f235b5fdb7ddd60abf5cb9850b9f699a789760e Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 27 Jul 2022 19:05:34 +0530 Subject: lopper: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 06417199..731e9dc7 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "e1429f59d27ac54749efe3c8cfe9ced348a339ca" +SRCREV = "b7d116f385b6a990a4cc4ca633477345cb142969" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From d928363b4b70f49c855a9348025f198d0b8f517d Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Wed, 27 Jul 2022 14:45:04 -0700 Subject: meta-xilinx-standalone-experimental: esw.bbclass: Add var XLNX_CMAKE_BSP_VARS Add a variable that can be used to add BSP flags Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/classes/esw.bbclass | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meta-xilinx-standalone-experimental/classes/esw.bbclass b/meta-xilinx-standalone-experimental/classes/esw.bbclass index 78cb289c..0b179a61 100644 --- a/meta-xilinx-standalone-experimental/classes/esw.bbclass +++ b/meta-xilinx-standalone-experimental/classes/esw.bbclass @@ -64,6 +64,7 @@ def get_xlnx_cmake_processor(tune, machine, d): XLNX_CMAKE_MACHINE = "${@get_xlnx_cmake_machine(d.getVar('SOC_FAMILY'), d)}" XLNX_CMAKE_PROCESSOR = "${@get_xlnx_cmake_processor(d.getVar('DEFAULTTUNE'), d.getVar('ESW_MACHINE'), d)}" XLNX_CMAKE_SYSTEM_NAME ?= "Generic" +XLNX_CMAKE_BSP_VARS ?= "" cmake_do_generate_toolchain_file:append() { cat >> ${WORKDIR}/toolchain.cmake < Date: Sat, 23 Jul 2022 20:52:44 -0500 Subject: machine-xilinx-qemu.inc: Adjust function to verify fstype is valid Simplify the function to treat microblaze as a soc_family. If we do not have initramfs_image defined, then verify wic.qemu-sd is available before returning that value, otherwise fall back to the dictionary. Signed-off-by: Mark Hatle (cherry picked from commit 67e5e1ab7176c5aa3e4c6d903287f16a521f7d41) Signed-off-by: Mark Hatle --- .../conf/machine/include/machine-xilinx-qemu.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc index 8cf9d4ed..0fcc5087 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc @@ -54,13 +54,14 @@ def qemu_rootfs_params(d,param): "zynqmp": "cpio.gz.u-boot", "versal": "cpio.gz.u-boot.qemu-sd-fatimg" } - if initramfs_image: - if 'microblaze' in tune_features: - return fstype_dict['microblaze'] - else: - return fstype_dict[soc_family] - else: + if 'microblaze' in tune_features: + soc_family = 'microblaze' + if not initramfs_image: + image_fs = d.getVar('IMAGE_FSTYPES') + if 'wic.qemu-sd' in image_fs: return 'wic.qemu-sd' + return fstype_dict[soc_family] + elif param == 'rootfs-opt': if not initramfs_image or soc_family == 'versal': sd_index = "1" -- cgit v1.2.3-54-g00ecf From c5ca57d93fbbce3d337f5de691f3c849a3145b6d Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Sat, 23 Jul 2022 20:58:13 -0500 Subject: zynq-generic: use default QB_DTB value Signed-off-by: Mark Hatle (cherry picked from commit 9b0fbd1dc351a98442e602ee32d99e02668f3402) Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynq-generic.conf | 2 -- 1 file changed, 2 deletions(-) diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index a0d2802e..899cc462 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -45,8 +45,6 @@ QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" QB_KERNEL_CMDLINE = "none" -QB_DTB = "system.dtb" - QB_KERNEL_ROOT = "/dev/mmcblk0p2" # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -- cgit v1.2.3-54-g00ecf From 4f6cc76efa4ed90a5397c886d08b661785e8f134 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Sat, 23 Jul 2022 20:58:45 -0500 Subject: microblaze-generic: microblaze requires a device tree Add the device-tree as a dependency and kc705-microblazeel is defined as the default HDF_MACHINE. Also simplify by removing the QB_DTB and using the default value. Signed-off-by: Mark Hatle (cherry picked from commit bb1bf5b198104441b5391e5327981a668a103384) Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 4bf519df..7f2f0cfc 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -34,11 +34,18 @@ KERNEL_IMAGETYPES = "" SERIAL_CONSOLES ?= "115200;ttyS0" +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" + +IMAGE_BOOT_FILES += " \ + ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \ + " + EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" UBOOT_MACHINE ?= "microblaze-generic_defconfig" UBOOT_INITIAL_ENV = "" +HDF_MACHINE = "kc705-microblazeel" IMAGE_FSTYPES += "cpio.gz" QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" @@ -50,7 +57,6 @@ QB_OPT_APPEND = " \ -nographic -serial mon:stdio \ " -QB_DTB = "system.dtb" QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE}" #### No additional settings should be after the Postamble #### Postamble -- cgit v1.2.3-54-g00ecf From f53c36df8f151ae31eba02dbb79bc905fa54487b Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 25 Jul 2022 15:41:15 -0500 Subject: qemu-system-aarch64-multiarch: Add --help support --help may need to be passed in and should be directed to the main APU handler. runqemu may use --help for various reasons. Signed-off-by: Mark Hatle (cherry picked from commit c8eb35a80313ce857ab5556f1acf384433cf51bd) Signed-off-by: Mark Hatle --- .../recipes-devtools/qemu/files/qemu-system-aarch64-multiarch | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch b/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch index 6f7fb522..370e694b 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch +++ b/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch @@ -28,6 +28,8 @@ elif '-plm-args' in APU_args: APU_args.remove(MB_args) MB_args = MB_args.split() mbtype='PLM' +elif '--help' in APU_args: + mbtype='help' else: error_msg = '\nMultiarch not setup properly.' sys.exit(error_msg) -- cgit v1.2.3-54-g00ecf From bc4d3fda38cd7b14214aac2a9bb3e8a0f0fac71b Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 4 May 2022 22:09:26 -0500 Subject: *-generic.conf: Update qemu config to remove duplicate options runqemu now appears to set -serial mon:stdio by default. This can conflict with the built in parameters. Reported by: Jeremy Puhlman It may look unusual, but the remaining -serial null are still required for booting. Signed-off-by: Mark Hatle (cherry picked from commit 72754d63ce7552d9b67f907ec82bb540e060435b) Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 4 +--- meta-xilinx-core/conf/machine/versal-generic.conf | 2 +- meta-xilinx-core/conf/machine/zynq-generic.conf | 4 ++-- meta-xilinx-core/conf/machine/zynqmp-generic.conf | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 7f2f0cfc..6611d529 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -53,9 +53,7 @@ QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" QB_KERNEL_CMDLINE = "none" -QB_OPT_APPEND = " \ - -nographic -serial mon:stdio \ - " +QB_OPT_APPEND ?= "" QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE}" #### No additional settings should be after the Postamble diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index 8d17c3af..53b20cb8 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -72,7 +72,7 @@ QEMU_HW_DTB_PMC_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-pmc-vir QB_OPT_APPEND:append:qemuboot-xilinx = " \ -hw-dtb ${QEMU_HW_DTB_PS} \ - -serial null -serial null -serial mon:stdio -serial null -display none \ + -serial null -serial null \ ${@qemu_add_extra_args(d)} \ " diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 899cc462..1a7425e6 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -48,8 +48,8 @@ QB_KERNEL_CMDLINE = "none" QB_KERNEL_ROOT = "/dev/mmcblk0p2" # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND = " \ - -nographic -serial null -serial mon:stdio \ +QB_OPT_APPEND ?= " \ + -serial null \ -gdb tcp::9000 \ -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \ -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \ diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf index 164a7c9c..98615661 100644 --- a/meta-xilinx-core/conf/machine/zynqmp-generic.conf +++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf @@ -63,7 +63,7 @@ IMAGE_BOOT_FILES += " \ # This machine has a QEMU model, runqemu setup: QB_MEM = "-m 4096" -QB_OPT_APPEND ?= "-nographic -serial mon:stdio -serial null" +QB_OPT_APPEND ?= "" QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@" # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -- cgit v1.2.3-54-g00ecf From d12d092afe68c7077993771e12dc5c74f1700cf3 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 26 Jul 2022 09:15:31 -0500 Subject: *-generic.conf: Fix QB_NETWORK_DEVICE to use default settings runqemu will pass in the correct network choice for the user. Signed-off-by: Mark Hatle (cherry picked from commit 5c11d939c12685207e46550401edaa2acdd8f9cc) Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 3 ++- meta-xilinx-core/conf/machine/zynq-generic.conf | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 6611d529..3fcc453d 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -55,7 +55,8 @@ QB_KERNEL_CMDLINE = "none" QB_OPT_APPEND ?= "" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE}" +QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" + #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' ${MB_MACHINE_ARCH}']['microblaze-generic' != "${MACHINE}"]}" diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 1a7425e6..71bfda61 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -37,7 +37,8 @@ IMAGE_FSTYPES += "${@'wic.qemu-sd' if (d.getVar('INITRAMFS_IMAGE') or '') == '' WKS_FILES ?= "sdimage-bootpart.wks" QB_MEM = "-m 1024" -QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=${DEPLOY_DIR_IMAGE} -net nic" +QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" + QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" -- cgit v1.2.3-54-g00ecf From 2b2f635369366e009acb80bf03d768bc06edb0f8 Mon Sep 17 00:00:00 2001 From: John Toomey Date: Tue, 26 Jul 2022 17:36:13 +0100 Subject: qemu-xilinx cleanup Refactor qemuboot-xilinx.bbclass and machine-xilinx-qemu.inc. Following the example of the core version of qemu.bbclass and match inc file. Refactor some of the functions to make them more readable. Specifically around qemu_rootfs_params. Code may not be as compact, but it'll be easier to read (and update) in the future. Add mising qemu-system-native PREFERRED_PROVIDER (and recipe PROVIDE). This resolves the issue where occasionally you use runqemu and the qemu binary appears to be missing. *-generic.conf: Remove overrides that are the same as the default qemu settings. Remove :append operations on QB_OPT_APPEND, this allows easy override when someone includes a generic machine. Signed-off-by: John Toomey Signed-off-by: Mark Hatle Signed-off-by: Mark Hatle (cherry picked from commit b0baa647143aab6815af13cc9e66061c9e25a07c) Signed-off-by: Mark Hatle --- meta-xilinx-core/classes/qemuboot-xilinx.bbclass | 119 ++++++++++++++++++++- .../conf/machine/include/machine-xilinx-qemu.inc | 108 ++----------------- .../conf/machine/microblaze-generic.conf | 5 +- meta-xilinx-core/conf/machine/versal-generic.conf | 11 +- meta-xilinx-core/conf/machine/zynq-generic.conf | 5 - meta-xilinx-core/conf/machine/zynqmp-generic.conf | 9 +- .../qemu/qemu-xilinx-system-native_2022.2.bb | 2 + 7 files changed, 134 insertions(+), 125 deletions(-) diff --git a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass index 59d3f0ab..0f7c75ed 100644 --- a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass +++ b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass @@ -10,6 +10,12 @@ QB_MACHINE_XILINX:aarch64 = "-machine arm-generic-fdt" QB_MACHINE_XILINX:arm = "-M arm-generic-fdt-7series" QB_MACHINE_XILINX:microblaze = "-M microblaze-fdt-plnx" +QB_SYSTEM_NAME = "${@qemu_target_binary(d)}" +QB_DEFAULT_FSTYPE = "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS = "${@qemu_rootfs_params(d,'rootfs')}" +QB_ROOTFS_OPT = "${@qemu_rootfs_params(d,'rootfs-opt')}" +QB_DTB = "${@qemu_default_dtb(d)}" + # defaults QB_DEFAULT_KERNEL ?= "none" QB_DEFAULT_KERNEL:zynq ?= "${@'zImage' if \ @@ -19,6 +25,118 @@ QB_DEFAULT_KERNEL:microblaze ?= "${@'simpleImage.mb' if \ inherit qemuboot +def qemu_target_binary(data): + package_arch = data.getVar("PACKAGE_ARCH") + qemu_target_binary = (data.getVar("QEMU_TARGET_BINARY_%s" % package_arch) or "") + if qemu_target_binary: + return qemu_target_binary + + target_arch = data.getVar("TARGET_ARCH") + if target_arch == "microblazeeb": + target_arch = "microblaze" + elif target_arch == "aarch64": + target_arch += "-multiarch" + elif target_arch == "arm": + target_arch = "aarch64" + return "qemu-system-%s" % target_arch + +def qemu_add_extra_args(data): + initramfs_image = data.getVar('INITRAMFS_IMAGE') or "" + bundle_image = data.getVar('INITRAMFS_IMAGE_BUNDLE') or "" + deploy_dir = data.getVar('DEPLOY_DIR_IMAGE') or "" + machine_name = data.getVar('MACHINE') or "" + soc_family = data.getVar('SOC_FAMILY') or "" + qb_extra_args = '' + # Add kernel image and boot.scr to qemu boot command when initramfs_image supplied + kernel_name = '' + bootscr_image = '%s/boot.scr' % deploy_dir + if soc_family in ('zynqmp', 'versal'): + kernel_name = 'Image' + bootscr_loadaddr = '0x20000000' + if initramfs_image: + kernel_image = '%s/%s' % (deploy_dir, kernel_name) + if bundle_image == "1": + kernel_image = '%s/%s-initramfs-%s.bin' % (deploy_dir, kernel_name, machine_name) + kernel_loadaddr = '0x200000' + if kernel_name: + qb_extra_args = ' -device loader,file=%s,addr=%s,force-raw=on' % (kernel_image, kernel_loadaddr) + qb_extra_args += ' -device loader,file=%s,addr=%s,force-raw=on' % (bootscr_image, bootscr_loadaddr) + if soc_family == 'versal': + qb_extra_args += ' -boot mode=5' + else: + if soc_family in ('zynqmp', 'versal'): + qb_extra_args = ' -boot mode=5' + return qb_extra_args + +def qemu_rootfs_params(data, param): + initramfs_image = data.getVar('INITRAMFS_IMAGE') or "" + bundle_image = data.getVar('INITRAMFS_IMAGE_BUNDLE') or "" + soc_family = data.getVar('SOC_FAMILY') or "" + tune_features = (data.getVar('TUNE_FEATURES') or []).split() + if 'microblaze' in tune_features: + soc_family = 'microblaze' + soc_variant = data.getVar('SOC_VARIANT') or "" + + if param == 'rootfs': + return 'none' if bundle_image == "1" else '' + + elif param == 'fstype': + fstype_dict = { + "microblaze": "cpio.gz", + "zynq": "cpio.gz", + "zynqmp": "cpio.gz.u-boot", + "versal": "cpio.gz.u-boot.qemu-sd-fatimg" + } + if not initramfs_image: + image_fs = data.getVar('IMAGE_FSTYPES') + if 'wic.qemu-sd' in image_fs: + return 'wic.qemu-sd' + return fstype_dict[soc_family] + + elif param == 'rootfs-opt': + sd_index = "1" + if soc_family == 'zynq': + sd_index = "0" + if soc_family == 'versal' and soc_variant == 'net': + sd_index = "0" + + # Device is using a disk + if not initramfs_image: + return ' -drive if=sd,index=%s,file=@ROOTFS@,format=raw' % (sd_index) + + # Device is using a ramdisk + if soc_family not in ('zynq', 'microblaze'): + return ' -device loader,file=@ROOTFS@,addr=0x04000000,force-raw=on' + + # Ramdisk must be compiled into the kernel + return '' + +def qemu_default_dtb(data): + if data.getVar("IMAGE_BOOT_FILES", True): + dtbs = data.getVar("IMAGE_BOOT_FILES", True).split(" ") + # IMAGE_BOOT_FILES has extra renaming info in the format ';' + # Note: Wildcard sources work here only because runqemu expands them at run time + dtbs = [f.split(";")[0] for f in dtbs] + dtbs = [f for f in dtbs if f.endswith(".dtb")] + if len(dtbs) != 0: + return dtbs[0] + return "" + +def qemu_default_serial(data): + if data.getVar("SERIAL_CONSOLES", True): + first_console = data.getVar("SERIAL_CONSOLES", True).split(" ")[0] + speed, console = first_console.split(";", 1) + # zynqmp uses earlycon and stdout (in dtb) + if "zynqmp" in data.getVar("MACHINEOVERRIDES", True).split(":"): + return "" + return "console=%s,%s earlyprintk" % (console, speed) + return "" + +def qemu_zynqmp_unhalt(data, multiarch): + if multiarch: + return "-global xlnx,zynqmp-boot.cpu-num=0 -global xlnx,zynqmp-boot.use-pmufw=true" + return "-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4" + # rewrite the qemuboot with the custom sysroot bindir python do_write_qemuboot_conf:append() { val = os.path.join(d.getVar('BASE_WORKDIR'), d.getVar('BUILD_SYS'), 'qemu-xilinx-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/') @@ -28,4 +146,3 @@ python do_write_qemuboot_conf:append() { with open(qemuboot, 'w') as f: cf.write(f) } - diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc index 0fcc5087..7b953975 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc @@ -1,111 +1,17 @@ # This include is used to setup default QEMU and qemuboot config for meta-xilinx # machines. -# Use the xilinx specific version for these users -IMAGE_CLASSES += "qemuboot-xilinx" - -# depend on qemu-helper-native, which will depend on QEMU -EXTRA_IMAGEDEPENDS += "qemu-helper-native:do_addto_recipe_sysroot" - PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native" PREFERRED_PROVIDER_qemu = "qemu-xilinx" PREFERRED_PROVIDER_qemu-native = "qemu-xilinx-native" +PREFERRED_PROVIDER_qemu-system-native = "qemu-xilinx-system-native" PREFERRED_PROVIDER_nativesdk-qemu = "nativesdk-qemu-xilinx" -def qemu_add_extra_args(d): - initramfs_image = d.getVar('INITRAMFS_IMAGE') or "" - bundle_image = d.getVar('INITRAMFS_IMAGE_BUNDLE') or "" - deploy_dir = d.getVar('DEPLOY_DIR_IMAGE') or "" - machine_name = d.getVar('MACHINE') or "" - soc_family = d.getVar('SOC_FAMILY') or "" - qb_extra_args = '' - # Add kernel image and boot.scr to qemu boot command when initramfs_image supplied - kernel_name = '' - bootscr_image = '%s/boot.scr' % deploy_dir - if soc_family in ('zynqmp', 'versal'): - kernel_name = 'Image' - bootscr_loadaddr = '0x20000000' - if initramfs_image: - kernel_image = '%s/%s' % (deploy_dir, kernel_name) - if bundle_image == "1": - kernel_image = '%s/%s-initramfs-%s.bin' % (deploy_dir, kernel_name, machine_name) - kernel_loadaddr = '0x200000' - if kernel_name: - qb_extra_args = ' -device loader,file=%s,addr=%s,force-raw=on' % (kernel_image, kernel_loadaddr) - qb_extra_args += ' -device loader,file=%s,addr=%s,force-raw=on' % (bootscr_image, bootscr_loadaddr) - if soc_family == 'versal': - qb_extra_args += ' -boot mode=5' - else: - if soc_family in ('zynqmp', 'versal'): - qb_extra_args = ' -boot mode=5' - return qb_extra_args - -def qemu_rootfs_params(d,param): - initramfs_image = d.getVar('INITRAMFS_IMAGE') or "" - bundle_image = d.getVar('INITRAMFS_IMAGE_BUNDLE') or "" - soc_family = d.getVar('SOC_FAMILY') or "" - tune_features = (d.getVar('TUNE_FEATURES') or []).split() - if param == 'rootfs': - return 'none' if bundle_image == "1" else '' - elif param == 'fstype': - fstype_dict = { - "microblaze": "cpio.gz", - "zynq": "cpio.gz", - "zynqmp": "cpio.gz.u-boot", - "versal": "cpio.gz.u-boot.qemu-sd-fatimg" - } - if 'microblaze' in tune_features: - soc_family = 'microblaze' - if not initramfs_image: - image_fs = d.getVar('IMAGE_FSTYPES') - if 'wic.qemu-sd' in image_fs: - return 'wic.qemu-sd' - return fstype_dict[soc_family] - - elif param == 'rootfs-opt': - if not initramfs_image or soc_family == 'versal': - sd_index = "1" - if soc_family == 'zynq': sd_index = "0" - return ' -drive if=sd,index=%s,file=@ROOTFS@,format=raw' % (sd_index) - elif soc_family not in ('zynq') or 'microblaze' in tune_features: - return ' -device loader,file=@ROOTFS@,addr=0x04000000,force-raw=on' +# enable the overrides for the context of the conf only +MACHINEOVERRIDES =. "qemuboot-xilinx:" -def qemu_default_dtb(d): - if d.getVar("IMAGE_BOOT_FILES", True): - dtbs = d.getVar("IMAGE_BOOT_FILES", True).split(" ") - # IMAGE_BOOT_FILES has extra renaming info in the format ';' - # Note: Wildcard sources work here only because runqemu expands them at run time - dtbs = [f.split(";")[0] for f in dtbs] - dtbs = [f for f in dtbs if f.endswith(".dtb")] - if len(dtbs) != 0: - return dtbs[0] - return "" - -def qemu_default_serial(d): - if d.getVar("SERIAL_CONSOLES", True): - first_console = d.getVar("SERIAL_CONSOLES", True).split(" ")[0] - speed, console = first_console.split(";", 1) - # zynqmp uses earlycon and stdout (in dtb) - if "zynqmp" in d.getVar("MACHINEOVERRIDES", True).split(":"): - return "" - return "console=%s,%s earlyprintk" % (console, speed) - return "" - -def qemu_target_binary(d): - ta = d.getVar("TARGET_ARCH", True) - if ta == "microblazeeb": - ta = "microblaze" - elif ta == "arm": - ta = "aarch64" - return "qemu-system-%s" % ta - -def qemu_zynqmp_unhalt(d, multiarch): - if multiarch: - return "-global xlnx,zynqmp-boot.cpu-num=0 -global xlnx,zynqmp-boot.use-pmufw=true" - return "-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4" +# depend on qemu-helper-native, which will depend on QEMU +EXTRA_IMAGEDEPENDS += "qemu-system-native qemu-helper-native:do_addto_recipe_sysroot" -# For qemuboot, default setup across all machines in meta-xilinx -QB_SYSTEM_NAME:aarch64 ?= "${@qemu_target_binary(d)}-multiarch" -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE ?= "cpio" -QB_DTB ?= "${@qemu_default_dtb(d)}" +# Use the xilinx specific version for these users +IMAGE_CLASSES += "qemuboot-xilinx" diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index 3fcc453d..c0e41948 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -47,13 +47,10 @@ UBOOT_INITIAL_ENV = "" HDF_MACHINE = "kc705-microblazeel" IMAGE_FSTYPES += "cpio.gz" -QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" -QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" QB_KERNEL_CMDLINE = "none" -QB_OPT_APPEND ?= "" +QB_OPT_APPEND = "" QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index 53b20cb8..b737f1d1 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -60,17 +60,14 @@ QB_NETWORK_DEVICE = "" QB_KERNEL_CMDLINE_APPEND ?= "" QB_NET = "none" -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" -QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" - QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch" -QEMU_HW_DTB_PS ?="${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" -QEMU_HW_DTB_PMC ?="${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" +QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb" QEMU_HW_DTB_PS_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-ps-virt.dtb" QEMU_HW_DTB_PMC_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-pmc-virt.dtb" -QB_OPT_APPEND:append:qemuboot-xilinx = " \ +QB_OPT_APPEND = " \ -hw-dtb ${QEMU_HW_DTB_PS} \ -serial null -serial null \ ${@qemu_add_extra_args(d)} \ @@ -89,7 +86,7 @@ QB_PLM_OPT = " \ -hw-dtb ${QEMU_HW_DTB_PMC} \ -display none \ " -QB_OPT_APPEND:append:qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'" +QB_OPT_APPEND += " -plm-args '${QB_PLM_OPT}'" #### No additional settings should be after the Postamble #### Postamble diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 71bfda61..3c30c362 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -39,11 +39,6 @@ WKS_FILES ?= "sdimage-bootpart.wks" QB_MEM = "-m 1024" QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" -QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" -QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" -QB_ROOTFS_OPT:qemuboot-xilinx = " ${@qemu_rootfs_params(d,'rootfs-opt')}" - QB_KERNEL_CMDLINE = "none" QB_KERNEL_ROOT = "/dev/mmcblk0p2" diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf index 98615661..15fe9d11 100644 --- a/meta-xilinx-core/conf/machine/zynqmp-generic.conf +++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf @@ -63,11 +63,10 @@ IMAGE_BOOT_FILES += " \ # This machine has a QEMU model, runqemu setup: QB_MEM = "-m 4096" -QB_OPT_APPEND ?= "" QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@" # Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW) -QB_OPT_APPEND:append:qemuboot-xilinx = " \ +QB_OPT_APPEND = " \ -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zcu102-arm.dtb \ ${@qemu_zynqmp_unhalt(d, True)} \ -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \ @@ -76,10 +75,6 @@ QB_OPT_APPEND:append:qemuboot-xilinx = " \ ${@qemu_add_extra_args(d)} \ " -QB_ROOTFS:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs')}" -QB_DEFAULT_FSTYPE:qemuboot-xilinx = "${@qemu_rootfs_params(d,'fstype')}" -QB_ROOTFS_OPT:qemuboot-xilinx = "${@qemu_rootfs_params(d,'rootfs-opt')}" - QB_PMU_OPT = " \ -M microblaze-fdt \ -display none \ @@ -89,7 +84,7 @@ QB_PMU_OPT = " \ -device loader,addr=0xfd1a0074,data=0x1011003,data-len=4 \ -device loader,addr=0xfd1a007C,data=0x1010f03,data-len=4 \ " -QB_OPT_APPEND:append:qemuboot-xilinx = " -pmu-args '${QB_PMU_OPT}'" +QB_OPT_APPEND += " -pmu-args '${QB_PMU_OPT}'" do_write_qemuboot_conf[depends] += "u-boot-zynq-uenv:do_deploy" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb index f5b89f05..f177872a 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2022.2.bb @@ -1,5 +1,7 @@ require qemu-xilinx-native.inc +PROVIDES = "qemu-system-native" + EXTRA_OECONF:append = " --target-list=${@get_qemu_system_target_list(d)}" PACKAGECONFIG ??= "fdt alsa kvm pie" -- cgit v1.2.3-54-g00ecf From 603cfc87fb17c9cc0bd260bbaee46103c73ea76a Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 28 Jul 2022 09:29:44 -0700 Subject: qemuboot-xilinx.bbclass: Defaults should be ?= as classes load after conf The conf file(s) should specify board specific defaults, but if left not set should fall back to what is implemented here. Since the load order is: machine.conf -> *-generic.conf -> xilinx-machine-qemu.conf ---| |--> inherits -> qemuboot-xilinx.bbclass Signed-off-by: Mark Hatle --- meta-xilinx-core/classes/qemuboot-xilinx.bbclass | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass index 0f7c75ed..58ade1b9 100644 --- a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass +++ b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass @@ -10,11 +10,11 @@ QB_MACHINE_XILINX:aarch64 = "-machine arm-generic-fdt" QB_MACHINE_XILINX:arm = "-M arm-generic-fdt-7series" QB_MACHINE_XILINX:microblaze = "-M microblaze-fdt-plnx" -QB_SYSTEM_NAME = "${@qemu_target_binary(d)}" -QB_DEFAULT_FSTYPE = "${@qemu_rootfs_params(d,'fstype')}" -QB_ROOTFS = "${@qemu_rootfs_params(d,'rootfs')}" -QB_ROOTFS_OPT = "${@qemu_rootfs_params(d,'rootfs-opt')}" -QB_DTB = "${@qemu_default_dtb(d)}" +QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}" +QB_DEFAULT_FSTYPE ?= "${@qemu_rootfs_params(d,'fstype')}" +QB_ROOTFS ?= "${@qemu_rootfs_params(d,'rootfs')}" +QB_ROOTFS_OPT ?= "${@qemu_rootfs_params(d,'rootfs-opt')}" +QB_DTB ?= "${@qemu_default_dtb(d)}" # defaults QB_DEFAULT_KERNEL ?= "none" -- cgit v1.2.3-54-g00ecf From acc26822de0a6a16646c3c70fc8555e463b133cc Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 29 Jul 2022 13:16:21 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index adbaa66f..cf4c8e23 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "e494d2eb8476245f8e45330c39a7e324f106d9d7" +ESW_REV[2022.2] = "131fdc4c545302c7c88ba8aaa3a63a76346e6480" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From dd7947cba9289e70b840aac3b62a8626b13df54c Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 28 Jul 2022 11:33:50 -0700 Subject: gdb: Fix error in inline_frame_sniffer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Depth: Total number of inline functions [refer inline-frame.c] state->skipped_frames : Number of inline functions skipped. the current unwind_pc is causing an issue when we try to step into inline functions[Depth is becoming 0]. It’s incrementing pc by 8 even with si instruction. Signed-off-by: Mark Hatle --- .../recipes-devtools/gdb/gdb-microblaze.inc | 1 + .../0011-Patch-Microblaze-Depth-Total-number.patch | 61 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 meta-microblaze/recipes-devtools/gdb/gdb/0011-Patch-Microblaze-Depth-Total-number.patch diff --git a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc index da91a1b7..1df17062 100644 --- a/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc +++ b/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc @@ -15,4 +15,5 @@ SRC_URI:append:microblaze = " \ file://0008-Patch-MicroBlaze-these-changes-will-make-64-bit-vect.patch \ file://0009-Patch-MicroBlaze-Added-m64-abi-for-64-bit-target-des.patch \ file://0010-Patch-MicroBlaze-Code-changes-for-gdbserver.patch \ + file://0011-Patch-Microblaze-Depth-Total-number.patch \ " diff --git a/meta-microblaze/recipes-devtools/gdb/gdb/0011-Patch-Microblaze-Depth-Total-number.patch b/meta-microblaze/recipes-devtools/gdb/gdb/0011-Patch-Microblaze-Depth-Total-number.patch new file mode 100644 index 00000000..0e9c1a74 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gdb/gdb/0011-Patch-Microblaze-Depth-Total-number.patch @@ -0,0 +1,61 @@ +From 1f6eef2eb2e6974ba9989977d1b1c8dfdeca94f4 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati +Date: Thu, 21 Jul 2022 11:45:01 +0530 +Subject: [PATCH] =?UTF-8?q?[Patch,MicroBlaze]:=20Depth:=20=20Total=20numbe?= + =?UTF-8?q?r=20of=20inline=20functions=20[refer=20inline-frame.c]=20state-?= + =?UTF-8?q?>skipped=5Fframes=20:=20Number=20of=20inline=20functions=20skip?= + =?UTF-8?q?ped.=20the=20current=20unwind=5Fpc=20is=20causing=20an=20issue?= + =?UTF-8?q?=20when=20we=20try=20to=20step=20into=20inline=20functions[Dept?= + =?UTF-8?q?h=20is=20becoming=200].=20It=E2=80=99s=20incrementing=20pc=20by?= + =?UTF-8?q?=208=20even=20with=20si=20instruction.?= +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +--- + gdb/microblaze-tdep.c | 14 +++----------- + 1 file changed, 3 insertions(+), 11 deletions(-) + +diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c +index aad6a9cae6e..41a2eb511d6 100644 +--- a/gdb/microblaze-tdep.c ++++ b/gdb/microblaze-tdep.c +@@ -524,16 +524,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + static CORE_ADDR + microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) + { +- gdb_byte buf[4]; + CORE_ADDR pc; +- +- frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); +- pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); +- /* For sentinel frame, return address is actual PC. For other frames, +- return address is pc+8. This is a workaround because gcc does not +- generate correct return address in CIE. */ +- if (frame_relative_level (next_frame) >= 0) +- pc += 8; ++ pc=frame_unwind_register_unsigned (next_frame, MICROBLAZE_PC_REGNUM); + return pc; + } + +@@ -564,7 +556,6 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) + ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, + &cache); + +- + if (ostart_pc > start_pc) + return ostart_pc; + return start_pc; +@@ -670,7 +661,8 @@ static const struct frame_unwind microblaze_frame_unwind = + microblaze_frame_this_id, + microblaze_frame_prev_register, + NULL, +- default_frame_sniffer ++ default_frame_sniffer, ++ NULL, + }; + + static CORE_ADDR +-- +2.17.1 + -- cgit v1.2.3-54-g00ecf From 980c0efb9298fff4805d3ccbe1e67e5464de91db Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 28 Jul 2022 12:41:05 -0700 Subject: u-boot-xlnx.inc: Fix conditional check EXTRA_OEMAKE needs to be blank, unless a specific DTB_NAME or user specified DTS is listed. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index fe819ba6..5a9a0868 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -29,7 +29,8 @@ DTB_NAME ?= "" # Example: UBOOT_USER_SPECIFIED_DTS = "versal-vck190-revA-x-ebm-01-revA" UBOOT_USER_SPECIFIED_DTS ?= "" -EXTRA_OEMAKE += "${@'EXT_DTB=${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME}' if (d.getVar('DTB_NAME') != '' and d.getVar('UBOOT_USER_SPECIFIED_DTS') == '') else 'DEVICE_TREE=${UBOOT_USER_SPECIFIED_DTS}'}" +EXTRA_OEMAKE += "${@'EXT_DTB=${RECIPE_SYSROOT}/${DTB_PATH}/${DTB_NAME}' if (d.getVar('DTB_NAME') != '' and d.getVar('UBOOT_USER_SPECIFIED_DTS') == '') else '' }" +EXTRA_OEMAKE += "${@'DEVICE_TREE=${UBOOT_USER_SPECIFIED_DTS}' if (d.getVar('UBOOT_USER_SPECIFIED_DTS') != '') else '' }" python __anonymous () { #check if there are any dtb providers -- cgit v1.2.3-54-g00ecf From eb536acbf5623d57b98fe9e45cb410d5097f40e0 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Fri, 29 Jul 2022 04:04:42 +0200 Subject: dfx-mgr: Use source files from repo Use the firmware detection script and systemd unit file from the source repo instead of local files. Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- .../recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service | 16 ---- .../dfx-mgr/dfx-mgr/xlnx-firmware-detect | 92 ---------------------- .../recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 14 ++-- 3 files changed, 5 insertions(+), 117 deletions(-) delete mode 100644 meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service delete mode 100755 meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service deleted file mode 100644 index d442fd9e..00000000 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/dfx-mgr.service +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: MIT -# -# DFX manager daemon is used to demonstrate Dynamic Function eXchange (DFX) -# or partial reconfiguration feature on Xilinx Zynq UltraScale+ and newer. -# See: UG909 "Vivado Design Suite User Guide Dynamic Function eXchange" - -[Unit] -Description=dfx-mgrd Dynamic Function eXchange -Documentation=https://github.com/Xilinx/dfx-mgr - -[Service] -ExecStartPre=-/usr/bin/xlnx-firmware-detect -ExecStart=/usr/bin/dfx-mgrd - -[Install] -WantedBy=multi-user.target diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect deleted file mode 100755 index 6b843166..00000000 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr/xlnx-firmware-detect +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/sh - -# (C) Copyright 2022 Xilinx, Inc. -# SPDX-License-Identifier: MIT - -# read values from dfx-mgr conf file -conffile="/etc/dfx-mgrd/daemon.conf" -if [ ! -f "${conffile}" ]; then - echo "dfx-mgrd configuration file not found: ${conffile}" - exit 1 -fi - -fwbasedir=$(grep "firmware_location" ${conffile} | sed 's/.*:.*\[\"\(.*\)\"\],\?/\1/') -if [ -z "${fwbasedir}" ]; then - echo "Property 'firmware_location' not found in ${conffile}" - exit 1 -fi - -fwfile=$(grep "default_accel" ${conffile} | sed 's/.*:.*\"\(.*\)\",\?/\1/') -if [ -z "${fwfile}" ]; then - echo "Property 'default_accel' not found in ${conffile}" - exit 1 -fi - -# check if default firmware is already set and present -if [ -f "${fwfile}" ]; then - fwname=$(cat ${fwfile}) - fwdir="${fwbasedir}/${fwname}" - if [ -n "${fwname}" ] && [ -d "${fwdir}" ]; then - echo "Default firmware detected: ${fwname}" - exit 0 - fi -fi - -# search for firmware based on EEPROM board id -echo "Trying to detect default firmware based on EEPROM..." - -# check if board is a SOM product -eeprom=$(ls /sys/bus/i2c/devices/*50/eeprom 2> /dev/null) -if [ -n "${eeprom}" ]; then - boardid=$(fru-print -d ${eeprom} -f product | awk -F- '{ print tolower($2) }') - validids="k26" - valid=0 - for id in ${validids}; do - if [ "${id}" = "${boardid}" ]; then - echo "Known SOM Board ID found: ${boardid}" - valid=1 - break - fi - done - if [ ${valid} -eq 1 ]; then - fwname="${boardid}-starter-kits" - fwdir="${fwbasedir}/${fwname}" - if [ ! -d "${fwdir}" ]; then - echo "No default firmware named ${fwname} found in ${fwbasedir}" - exit 1 - fi - echo "Default firmware detected: ${fwname}" - echo "${fwname}" > "${fwfile}" - exit 0 - fi -fi - -# check if board is a System Controller product -eeprom=$(ls /sys/bus/i2c/devices/*54/eeprom 2> /dev/null) -if [ -n "${eeprom}" ]; then - boardid=$(fru-print -d ${eeprom} -f product | tr '[:upper:]' '[:lower:]') - revision=$(fru-print -d ${eeprom} -f revision | tr '[:upper:]' '[:lower:]') - validids="vpk120 vpk180 vhk158" - valid=0 - for id in ${validids}; do - if [ "${id}" = "${boardid}" ]; then - echo "Known System Controller Board ID found: ${boardid} rev ${revision}" - valid=1 - break - fi - done - if [ ${valid} -eq 1 ]; then - fwname="${boardid}-${revision}" - fwdir="${fwbasedir}/${fwname}" - if [ ! -d "${fwdir}" ]; then - echo "No default firmware named ${fwname} found in ${fwbasedir}" - exit 1 - fi - echo "Default firmware detected: ${fwname}" - echo "${fwname}" > "${fwfile}" - exit 0 - fi -fi - -echo "No known Board ID found" -exit 1 diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 7040284c..4be67b09 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -30,10 +30,6 @@ EXTRA_OECMAKE += " \ INITSCRIPT_NAME = "dfx-mgr.sh" INITSCRIPT_PARAMS = "start 99 S ." -SRC_URI:append = " \ - file://dfx-mgr.service \ - file://xlnx-firmware-detect \ - " SYSTEMD_PACKAGES="${PN}" SYSTEMD_SERVICE:${PN}="dfx-mgr.service" SYSTEMD_AUTO_ENABLE:${PN}="enable" @@ -51,7 +47,7 @@ do_install(){ chrpath -d ${D}${bindir}/dfx-mgrd chrpath -d ${D}${bindir}/dfx-mgr-client install -m 0644 ${S}/src/dfxmgr_client.h ${D}${includedir} - + oe_soinstall ${B}/src/libdfx-mgr.so.${SOVERSION} ${D}${libdir} install -m 0755 ${S}/src/daemon.conf ${D}${sysconfdir}/dfx-mgrd/ @@ -61,11 +57,11 @@ do_install(){ install -m 0755 ${S}/src/dfx-mgr.sh ${D}${sysconfdir}/init.d/ fi - install -m 0755 ${S}/src/dfx-mgr.sh ${D}${bindir}/ - install -m 0755 ${WORKDIR}/xlnx-firmware-detect ${D}${bindir} + install -m 0755 ${S}/src/dfx-mgr.sh ${D}${bindir} + install -m 0755 ${S}/src/scripts/xlnx-firmware-detect ${D}${bindir} - install -d ${D}${systemd_system_unitdir} - install -m 0644 ${WORKDIR}/dfx-mgr.service ${D}${systemd_system_unitdir} + install -d ${D}${systemd_system_unitdir} + install -m 0644 ${S}/src/dfx-mgr.service ${D}${systemd_system_unitdir} } PACKAGES =+ "libdfx-mgr" -- cgit v1.2.3-54-g00ecf From 15e8e7ed939ce5f6e95ff3dc8bf68242cadfca12 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 29 Jul 2022 12:18:40 +0530 Subject: meta-xilinx-standalone-experimental: recipes-core: meta: files: dt-processor.sh: Add relative path support for system device-tree and domain file With the existing dt-processor.sh fails if relative paths of system-top.dts or domains yaml have been provided, this commit fixes this issue. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index c1f076d8..aa4696d2 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -34,8 +34,8 @@ usage() { cat < Location of the build conf directory - -s Full path to system DTB - -d Full path to domain file (.yml/.dts) + -s Path to system DTB + -d Path to domain file (.yml/.dts) [-o ] Generate overlay dts [-e ] Apply a partial overlay [-m ] zynqmp or versal @@ -77,6 +77,11 @@ parse_args() { if [ -z "$pdi_path" ]; then pdi_path=$(dirname ${system_dtb}) fi + system_dtb=$(realpath ${system_dtb}) + if [ "$domain_file" ]; then + domain_file=$(realpath ${domain_file}) + fi + } detect_machine() { -- cgit v1.2.3-54-g00ecf From d0494a338a784cae0df89b997e65d3a70383406a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 2 Aug 2022 13:16:49 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 7caeafed..7beaae2d 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "66563d3cfa2cefa11ea7160f7fb6ba499c1fc8a1" +SRCREV = "10e4941ae67bb0abc9de1b02bf9e0c87b939d219" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 8304f58dedfd981f16a57ef7432cc5a61b58fb22 Mon Sep 17 00:00:00 2001 From: Christian Kohn Date: Sat, 30 Jul 2022 02:00:41 +0200 Subject: fpgamanager_custom: Remove LICENSE and LIC_FILES_CHKSUM Don't set the LICENSE and LIC_FILES_CHKSUM variables as otherwise the values set at the recipe or inc file level don't get honored, depending on where the inherit line is placed in the file. The user shall explicitely set the LICENSE at the inc file or recipe level. Signed-off-by: Christian Kohn Signed-off-by: Mark Hatle --- meta-xilinx-core/classes/fpgamanager_custom.bbclass | 3 --- 1 file changed, 3 deletions(-) diff --git a/meta-xilinx-core/classes/fpgamanager_custom.bbclass b/meta-xilinx-core/classes/fpgamanager_custom.bbclass index 848727fb..555e2a66 100644 --- a/meta-xilinx-core/classes/fpgamanager_custom.bbclass +++ b/meta-xilinx-core/classes/fpgamanager_custom.bbclass @@ -1,6 +1,3 @@ -LICENSE = "MIT" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" - inherit devicetree DEPENDS = "dtc-native bootgen-native" -- cgit v1.2.3-54-g00ecf From 85716ceb6f281a6a7d4015f4c4c580095f0675b5 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Mon, 1 Aug 2022 21:27:58 +0530 Subject: lopper: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 731e9dc7..10035f84 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "b7d116f385b6a990a4cc4ca633477345cb142969" +SRCREV = "64482a5587617167055e1e167dbb082af2d5b043" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From d47bf4c28f767c1c3b1c67a61f8f6f252dca6162 Mon Sep 17 00:00:00 2001 From: rbramand Date: Tue, 2 Aug 2022 13:48:37 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index e825c88c..1a35c211 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "004ea23733e63b9ab5f704609e6821824106a051" +SRCREV= "278bdce2d25ef26b79fbf833582550b9c1561dcc" PV = "202220.2.14.0" -- cgit v1.2.3-54-g00ecf From a81924a6284d5c6988e063e907b9a1b658a6400e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 3 Aug 2022 12:56:49 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 7beaae2d..317063ff 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "10e4941ae67bb0abc9de1b02bf9e0c87b939d219" +SRCREV = "2bacd2b7f359481b2c79d905750cdb3b527a403a" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index cf4c8e23..529bdbbb 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "131fdc4c545302c7c88ba8aaa3a63a76346e6480" +ESW_REV[2022.2] = "16e032e4a701e7e7236e7b9eff5088f76aad5c1d" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 8417ce27448e1529ba550a833cb0f2ff1918c36a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 4 Aug 2022 12:50:46 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 317063ff..18dcbd95 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "2bacd2b7f359481b2c79d905750cdb3b527a403a" +SRCREV = "d9a7c40b572e7dd4b369dccb4199d01c97120f53" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 64f0298bed939b228c2ad65ae135f9b95c47fff6 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 5 Aug 2022 16:16:17 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 18dcbd95..7036a8af 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "d9a7c40b572e7dd4b369dccb4199d01c97120f53" +SRCREV = "86e63ba3941dcd378d7626b21ad31e779b40fa73" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From f5e84234d7b7c3c842c4e39fd1e9f3e9c70d27c3 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 3 Aug 2022 19:50:36 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index b5b724ee..4a07563f 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -7,6 +7,6 @@ ESW_VER = "experimental" REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" -ESW_REV[experimental] = "74445062bbc79dd3ac2fe4fe6ecbc50034b7c472" +ESW_REV[experimental] = "2f93defe078000965c8f7203da11817c9f0982d1" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From 31f984cf394ae3c61ea49c37d3e9240d50008f7f Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 8 Aug 2022 16:39:39 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 1808794e..be8d112b 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "0526f9197344a78e73cc3c96a1faada825f818b6" +SRCREV = "3b81afa0483360286905c319bad06611ac9c0864" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc -- cgit v1.2.3-54-g00ecf From 3d7776b5b0bcccc1a1ee66daca04a5d82058d9e5 Mon Sep 17 00:00:00 2001 From: rbramand Date: Mon, 8 Aug 2022 16:55:41 +0530 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 1a35c211..27135209 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "278bdce2d25ef26b79fbf833582550b9c1561dcc" +SRCREV= "57c655bf98d1c9bc3dc4ba5e3bf7cf80a5e5ecc3" PV = "202220.2.14.0" -- cgit v1.2.3-54-g00ecf From 79898c433f7a66d336c9ab52bf90a3bc49474aec Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 10 Aug 2022 13:58:17 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 7036a8af..8cfb61ba 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "86e63ba3941dcd378d7626b21ad31e779b40fa73" +SRCREV = "21166ad7451381519714ed9b7ca928667ea4cd44" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From b095ecd0252e8736c2b02a694a333947d5ad8c9c Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Wed, 10 Aug 2022 18:01:10 +0530 Subject: lopper: Update srcrev for 2022 Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 10035f84..4a348726 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -6,7 +6,7 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "64482a5587617167055e1e167dbb082af2d5b043" +SRCREV = "f5ee4aefb8771077533f1273fdd18e7c2ea801f1" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 456155901d402e25cc8f9f35338511792f6daab2 Mon Sep 17 00:00:00 2001 From: Swagath Gadde Date: Wed, 10 Aug 2022 10:39:19 +0530 Subject: device-tree.bbappend:wire vek280 board dts This patch will wire the vek280 board dts wrt yocto MACHINEOVERRIDES. Signed-off-by: Swagath Gadde Signed-off-by: Mark Hatle --- .../meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index 130dd5f9..0b41fb1f 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -34,3 +34,4 @@ YAML_DT_BOARD_FLAGS:vpk120 ?= "{BOARD versal-vpk120-reva}" YAML_DT_BOARD_FLAGS:vpk-sc ?= "{BOARD zynqmp-vpk120-reva}" YAML_DT_BOARD_FLAGS:vpk180 ?= "{BOARD versal-vpk180-reva}" YAML_DT_BOARD_FLAGS:vhk158 ?= "{BOARD versal-vhk158-reva}" +YAML_DT_BOARD_FLAGS:vek280 ?= "{BOARD versal-vek280-reva}" -- cgit v1.2.3-54-g00ecf From 6173d1c8c832e1a57a59e4a89b851c6d1b3ef13c Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 16 Aug 2022 08:56:36 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index be8d112b..6cbe94b0 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "3b81afa0483360286905c319bad06611ac9c0864" +SRCREV = "a7b5b9baf31032fa47a67d63b2337b5ef10bf4ff" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 2b70bf4e..5ff8cb2f 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "6408fce60f3b2dac12a884e9b44a6fd0690ed8ba" +SRCREV = "ad8bf8b1a1241e7d1a1c16d945eb293c46d6eee2" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 8cfb61ba..921ef207 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "21166ad7451381519714ed9b7ca928667ea4cd44" +SRCREV = "32a31b33e66956fb2c0956c683530498fd1ebacd" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 529bdbbb..39b838c1 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "16e032e4a701e7e7236e7b9eff5088f76aad5c1d" +ESW_REV[2022.2] = "ea9149e05dc7e9a8a7ad20bb91625aeba1417131" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 180e0b446de0d89044c117ca5f6c5ad8b0e9f18f Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 17 Aug 2022 12:46:37 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 39b838c1..2cfba756 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "ea9149e05dc7e9a8a7ad20bb91625aeba1417131" +ESW_REV[2022.2] = "26c74c8bc33519a1abc26604d76fcc296c1c2619" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From ac13c9714585deab3c6c8e815b9750e8a4e1f0b0 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 17 Aug 2022 10:44:00 -0500 Subject: dt-processor.sh: Move BASE_TMPDIR from = to ?= The build directory may be on an NFS server, while it's easy for a user to modify the BASE_TMPDIR to a local device, this is difficult for an automated build to do via another configuration file. Switching to ?= will allow site.conf (or a similar file) to set a custom value for BASE_TMPDIR to a local disk. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index aa4696d2..e10148bf 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -937,7 +937,7 @@ parse_cpus() { gen_local_conf() { echo "# Adjust BASE_TMPDIR if you want to move the tmpdirs elsewhere" >> $1 - echo "BASE_TMPDIR = \"\${TOPDIR}\"" >> $1 + echo "BASE_TMPDIR ?= \"\${TOPDIR}\"" >> $1 [ -n "${system_conf}" ] && echo "require ${system_conf}" >> $1 echo "SYSTEM_DTFILE = \"${system_dtb}\"" >> $1 echo "BBMULTICONFIG += \"${multiconf}\"" >> $1 -- cgit v1.2.3-54-g00ecf From 18697112e78598bf3b5c5f58abcfca1b5de330ed Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Fri, 12 Aug 2022 10:34:43 +0530 Subject: lopper: Update branch and srcrev for beta release Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper.bbappend | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend index 4a348726..51c3f79e 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper.bbappend @@ -5,8 +5,8 @@ SECTION = "bootloader" FILESEXTRAPATHS:append := ":${THISDIR}/lopper" -SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" -SRCREV = "f5ee4aefb8771077533f1273fdd18e7c2ea801f1" +SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2022.x;protocol=https" +SRCREV = "cdb1a7b55c375f5237683a512257e0fc573063a2" S = "${WORKDIR}/git" PV="v1.0.2+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 4cffeeacad51f18a77429b1ebd948578729e2a0a Mon Sep 17 00:00:00 2001 From: John Toomey Date: Tue, 16 Aug 2022 15:27:48 +0100 Subject: Add Versal Net support to meta-xilinx-core Initial support for Versal Net devices including new machine config, bootbin and QEMU changes. Signed-off-by: John Toomey Refactor the versal-net-generic.conf file bootbin changes already existed due to prior cleanups Signed-off-by: Mark Hatle --- .../conf/machine/include/soc-versal.inc | 1 + .../conf/machine/versal-net-generic.conf | 32 ++++++++++++++++++++++ .../qemu/qemu-devicetrees_2022.2.bb | 2 +- 3 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 meta-xilinx-core/conf/machine/versal-net-generic.conf diff --git a/meta-xilinx-core/conf/machine/include/soc-versal.inc b/meta-xilinx-core/conf/machine/include/soc-versal.inc index 40145963..dcf3796e 100644 --- a/meta-xilinx-core/conf/machine/include/soc-versal.inc +++ b/meta-xilinx-core/conf/machine/include/soc-versal.inc @@ -7,6 +7,7 @@ SOC_FAMILY ?= "versal" # "hbm" - Versal HMB Devices # "ai-core" - Versal AI-core Devices # "ai-edge" - Versal AI-Edge Devices +# "net" - Versal Net Devices SOC_VARIANT ?= "prime" diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf new file mode 100644 index 00000000..e079f2c3 --- /dev/null +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -0,0 +1,32 @@ +#@TYPE: Machine +#@NAME: Versal Net Generic +##@DESCRIPTION: Versal Net + +#### Preamble +MACHINEOVERRIDES =. "${@['', 'versal-net-generic:']['versal-net-generic' != '${MACHINE}']}" +#### Regular settings follow + +SOC_VARIANT = "net" + +require conf/machine/versal-generic.conf + +#### REMOVE THE FOLLOWING WHEN BOOTGEN IS SYNCED +# required for bootgen native/nativesdk +MACHINEOVERRIDES:class-native = "versal-net" +MACHINEOVERRIDES:class-nativesdk = "versal-net" +#### REMOVE THE ABOVE + +# TODO: Should this be moved to device-tree recipe? +YAML_DT_BOARD_FLAGS ?= "{BOARD versal-net-ipp-rev1.5}" + +UBOOT_MACHINE ?= "xilinx_versal_net_virt_defconfig" + +HDF_MACHINE = "versal-net-generic" + +QEMU_HW_DTB_PS ="${QEMU_HW_DTB_PATH}/board-versal-ksb-psx-virt.dtb" +QEMU_HW_DTB_PMC ="${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" + +#### No additional settings should be after the Postamble +#### Postamble +PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_net_generic']['versal-net-generic' != "${MACHINE}"]}" + diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index f65f3d21..77b2d9a2 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "fac9ca0c139c2f6496c879138e5a83221835ae26" +SRCREV ?= "6be6f201d8e795afcb4e4f7a5fc83704dfe6fc11" -- cgit v1.2.3-54-g00ecf From 8f5af19ad208342b3f882f52fb976591100ab8e5 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 19 Aug 2022 13:52:56 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2cfba756..fcdf689f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "26c74c8bc33519a1abc26604d76fcc296c1c2619" +ESW_REV[2022.2] = "056cd6786b4ac46ce1194c672a68a57629c588ac" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 5ad2bcd17de7993a32560b4590d640c3b1773cb6 Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Wed, 17 Aug 2022 21:06:52 -0700 Subject: dfx-mgr: SRCREV: unload SIHA base The SRCREV is for a commit to unload SIHA base. Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 4be67b09..1088679b 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "4135349fd3c8daeabbd4504546b64bfed200337e" +SRCREV = "62982e7091f5bd73687ec5e1c9f51cdce65c8927" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From 4914145ca3944763b7171367ee056f97b213ff30 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 19 Aug 2022 11:54:35 -0700 Subject: dt-process.sh: Ensure the psu_init has the full path By move system_dtb real path earlier, we ensure that the default psu_init (and other users) of system_dtb path will get the full path. Also ensure if the user passes in a psu_init or pdi path, it is expanded as well. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index e10148bf..e91e9d34 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -71,14 +71,18 @@ parse_args() { [ -f "${config_dir}/local.conf" ] || error "Invalid config dir: ${config_dir}" [ -f "${system_dtb}" ] || error "Unable to find: ${system_dtb}" + system_dtb=$(realpath ${system_dtb}) if [ -z "$psu_init_path" ]; then psu_init_path=$(dirname ${system_dtb}) + else + psu_init_path=$(realpath ${psu_init_path}) fi if [ -z "$pdi_path" ]; then pdi_path=$(dirname ${system_dtb}) + else + pdi_path=$(realpath ${pdi_path}) fi - system_dtb=$(realpath ${system_dtb}) - if [ "$domain_file" ]; then + if [ -n "$domain_file" ]; then domain_file=$(realpath ${domain_file}) fi -- cgit v1.2.3-54-g00ecf From c6f917c289be96ca030a275e0c4d92384ca5bb16 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Fri, 19 Aug 2022 11:54:36 -0700 Subject: dt-processor.sh: Ignore TOPDIR in the CONFIG_DTFILE sstate-cache re-use is affected by the value of CONFIG_DTFILE as used by the device-tree recipe. If we are setting CONFIG_DTFILE, be sure to exclude TOPDIR from the hash calculations to avoid unnecessary rebuilds. Signed-off-by: Mark Hatle --- .../recipes-core/meta/files/dt-processor.sh | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh index e91e9d34..fab16393 100755 --- a/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh +++ b/meta-xilinx-standalone-experimental/recipes-core/meta/files/dt-processor.sh @@ -168,6 +168,8 @@ cortex_a53_linux() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + MACHINE = "${machine}-generic" # We don't want the kernel to build us a device-tree KERNEL_DEVICETREE:${machine}-generic = "" @@ -249,6 +251,8 @@ EOF fi cat <>"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexa53-${machine}" DEFAULTTUNE = "cortexa53" @@ -305,6 +309,8 @@ cortex_a53_freertos() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexa53-${machine}" DEFAULTTUNE = "cortexa53" @@ -388,6 +394,8 @@ cortex_a72_linux() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + MACHINE = "${machine}-generic" # We don't want the kernel to build us a device-tree KERNEL_DEVICETREE:${machine}-generic = "" @@ -440,6 +448,8 @@ cortex_a72_baremetal() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexa72-${machine}" DEFAULTTUNE = "cortexa72" @@ -496,6 +506,8 @@ cortex_a72_freertos() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexa72-${machine}" DEFAULTTUNE = "cortexa72" @@ -581,6 +593,8 @@ EOF fi cat <>"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexr5-${machine}" DEFAULTTUNE = "cortexr5" @@ -637,6 +651,8 @@ cortex_r5_freertos() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "cortexr5-${machine}" DEFAULTTUNE = "cortexr5" @@ -705,6 +721,8 @@ pmu-microblaze() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "microblaze-pmu" require conf/microblaze.conf @@ -761,6 +779,8 @@ pmc-microblaze() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "microblaze-plm" require conf/microblaze.conf @@ -817,6 +837,8 @@ psm-microblaze() { cat <"${conf_file}" CONFIG_DTFILE = "\${TOPDIR}/conf/dtb/${dtb_file}" +CONFIG_DTFILE[vardepsexclude] += "TOPDIR" + ESW_MACHINE = "microblaze-psm" require conf/microblaze.conf -- cgit v1.2.3-54-g00ecf From 9b2443f479fb2d8e7e706c8fc18662235c38405c Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Fri, 19 Aug 2022 15:13:51 -0600 Subject: boot.cmd.sd.versal: Use SDBOOTDEV variable for SD device When you have both SD controllers enabled, user can boot from either mmc0 or mmc1 by setting the SDBOOTDEV variable. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal index 10e83cd0..8eff483a 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal @@ -1,3 +1,5 @@ -setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused +setenv sdbootdev @@SDBOOTDEV@@ +setenv bootargs $bootargs root=/dev/mmcblk${sdbootdev}p2 rw rootwait earlycon clk_ignore_unused +fatload mmc $sdbootdev @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@ fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ -- cgit v1.2.3-54-g00ecf From d80f83d15c66d0971f9c93153539d88844b63668 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 22 Aug 2022 16:33:55 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 5ff8cb2f..bdde05c9 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "ad8bf8b1a1241e7d1a1c16d945eb293c46d6eee2" +SRCREV = "8c705ed56684721ca6eef018dba0c9a89d25c60b" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index fcdf689f..2a6c929d 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "056cd6786b4ac46ce1194c672a68a57629c588ac" +ESW_REV[2022.2] = "8cf2d886c98ef757bb842a68d6b865cf9f962fe9" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 9562fd0968ae1ec22ed078d5c3c2d7cfb3a7a067 Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Tue, 23 Aug 2022 12:24:08 +0530 Subject: meta-xilinx-standalone-experimental: conf: dtb-embeddedsw: Update repo for beta release Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Mark Hatle --- meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc index 4a07563f..2b461993 100644 --- a/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc +++ b/meta-xilinx-standalone-experimental/conf/dtb-embeddedsw.inc @@ -4,9 +4,9 @@ # Make it clear decoupling is 'experimental' in the version ESW_VER = "experimental" -REPO = "git://gitenterprise.xilinx.com/decoupling/embeddedsw-experimental-dt-support.git;protocol=https" +REPO = "git://github.com/Xilinx/embeddedsw-experimental-dt-support.git;protocol=https" -ESW_BRANCH[experimental] = "xilinx-v2022.1-sdt-experimental" +ESW_BRANCH[experimental] = "xlnx_rel_v2022.1_sdt_experimental_beta" ESW_REV[experimental] = "2f93defe078000965c8f7203da11817c9f0982d1" LIC_FILES_CHKSUM[master] = '7c92de7a21a6613265035c28f4a92f48' -LIC_FILES_CHKSUM[xilinx-v2022.1-sdt-experimental] = 'e26f53a7d6f58f4b1a9687099417225c' +LIC_FILES_CHKSUM[xlnx_rel_v2022.1_sdt_experimental_beta] = 'e26f53a7d6f58f4b1a9687099417225c' -- cgit v1.2.3-54-g00ecf From bdd8f6a2626c0552782d26999203eb08211cfa15 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 24 Aug 2022 14:11:04 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 6cbe94b0..94fca3f9 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "a7b5b9baf31032fa47a67d63b2337b5ef10bf4ff" +SRCREV = "65cca926a3f4860b041eae1e62168f90c0b506a1" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index bdde05c9..60bc2ff3 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "8c705ed56684721ca6eef018dba0c9a89d25c60b" +SRCREV = "de92de0a3cef8affbf256d8930817bf8765cce21" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 2a6c929d..f0e5df2b 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "8cf2d886c98ef757bb842a68d6b865cf9f962fe9" +ESW_REV[2022.2] = "a5ede6b10b538904d66fcf4ffff53071aa3a4b57" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 87a2ce68b71c3c92117d15ff7b220f644fd7c0e0 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:27 -0600 Subject: boot.cmd.generic.root: Add new boot script with root params Add new boot script with kernel root parameters which is appended in boot.scr for all the boot modes when the root parameters is not defined in DTB file. This boot script is set as default in the yocto generic machine configuration file. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../u-boot/u-boot-zynq-scr/boot.cmd.generic.root | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root new file mode 100644 index 00000000..f4244493 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root @@ -0,0 +1,91 @@ +# This is a boot script for U-Boot with generic root parameters used by yocto machine configuration file. +# Generate boot.scr: +# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr +# +################ +fitimage_name=@@FIT_IMAGE@@ +kernel_name=@@KERNEL_IMAGE@@ +ramdisk_name=@@RAMDISK_IMAGE1@@ +rootfs_name=@@RAMDISK_IMAGE@@ +@@PRE_BOOTENV@@ + +for boot_target in ${boot_targets}; +do + echo "Trying to load boot images from ${boot_target}" + if test "${boot_target}" = "jtag" ; then + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_RAMDISK@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + fi + if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" || test "${boot_target}" = "usb0" || test "${boot_target}" = "usb1"; then + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@UENV_TEXTFILE@@; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@UENV_MMC_LOAD_ADDRESS@@ @@UENV_TEXTFILE@@; + echo "Importing environment(@@UENV_TEXTFILE@@) from ${boot_target}..." + env import -t @@UENV_MMC_LOAD_ADDRESS@@ $filesize + if test -n $uenvcmd; then + echo "Running uenvcmd ..."; + run uenvcmd; + fi + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /${fitimage_name}; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ ${fitimage_name}; + echo "Kernel root filesystem parameter needs to be set for FITIMAGE boot if not defined in DTB" + bootm @@FIT_IMAGE_LOAD_ADDRESS@@; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /${kernel_name}; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ ${kernel_name}; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb; + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /${ramdisk_name} && test "${skip_tinyramdisk}" != "yes"; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${ramdisk_name}; + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_RAMDISK@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /${rootfs_name} && test "${skip_ramdisk}" != "yes"; then + fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${rootfs_name}; + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_RAMDISK@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ + fi + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_SD@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ + fi + if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then + sf probe 0 0 0; + sf read @@FIT_IMAGE_LOAD_ADDRESS@@ @@QSPI_FIT_IMAGE_OFFSET@@ @@QSPI_FIT_IMAGE_SIZE@@ + echo "Kernel root filesystem parameter needs to be set for FITIMAGE boot if not defined in DTB" + bootm @@FIT_IMAGE_LOAD_ADDRESS@@; + echo "Booting using Fit image failed" + + sf read @@KERNEL_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_KERNEL_SIZE@@ + sf read @@RAMDISK_IMAGE_ADDRESS@@ @@QSPI_RAMDISK_OFFSET@@ @@QSPI_RAMDISK_SIZE@@ + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_RAMDISK@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@; + echo "Booting using Separate images failed" + fi + if test "${boot_target}" = "nand" || test "${boot_target}" = "nand0"; then + nand info; + nand read @@FIT_IMAGE_LOAD_ADDRESS@@ @@NAND_FIT_IMAGE_OFFSET@@ @@NAND_FIT_IMAGE_SIZE@@ + echo "Kernel root filesystem parameter needs to be set for FITIMAGE boot if not defined in DTB" + bootm @@FIT_IMAGE_LOAD_ADDRESS@@; + echo "Booting using Fit image failed" + + nand read @@KERNEL_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_KERNEL_SIZE@@ + nand read @@RAMDISK_IMAGE_ADDRESS@@ @@NAND_RAMDISK_OFFSET@@ @@NAND_RAMDISK_SIZE@@ + fdt addr @@DEVICETREE_ADDRESS@@ + fdt get value bootargs /chosen bootargs + setenv bootargs $bootargs @@KERNEL_ROOT_RAMDISK@@ + @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@; + echo "Booting using Separate images failed" + fi +done -- cgit v1.2.3-54-g00ecf From 499596b5b330fc80e5bcd80f645399de1a8f9bba Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:28 -0600 Subject: u-boot-zynq-scr: Add new uboot generic boot script Add new boot.cmd.generic.root boot script with root params. The root param is defined for both SD/eMMC and other boot modes. Uboot script recipe has SDBOOTDEV set to 0 and PARTNUM to 2 as default. User can switch this to MMC 1 controller and associated rootfs partition number by tuning this variable. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb index cf1ba209..50a08919 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb @@ -27,7 +27,7 @@ KERNEL_BOOTCMD:zynq ?= "bootm" KERNEL_BOOTCMD:versal ?= "booti" KERNEL_BOOTCMD:microblaze ?= "bootm" -BOOTMODE ?= "generic" +BOOTMODE ??= "generic" BOOTFILE_EXT ?= "" #Make this value to "1" to skip appending base address to ddr offsets. @@ -43,6 +43,7 @@ SRC_URI = " \ file://boot.cmd.sd.versal \ file://boot.cmd.qspi.versal \ file://boot.cmd.generic \ + file://boot.cmd.generic.root \ file://boot.cmd.ubifs \ file://pxeboot.pxe \ " @@ -159,8 +160,18 @@ NAND_FIT_IMAGE_OFFSET ?= "0x4180000" NAND_FIT_IMAGE_OFFSET:zynq ?= "0x1080000" NAND_FIT_IMAGE_SIZE ?= "0x6400000" +# Set SD/eMMC Controller Device Number as 0 SDBOOTDEV ?= "0" +# Default to booting with the rootfs device being partition 2 for SD/eMMC +PARTNUM ?= "2" + +# Set Kernel root filesystem parameter for SD/eMMC boot +KERNEL_ROOT_SD ?= "root=/dev/mmcblk${SDBOOTDEV}p${PARTNUM} rw rootwait" + +# Set Kernel root filesystem parameter for JTAG/QSPI/OSPI/NAND(using RAMDISK) boot +KERNEL_ROOT_RAMDISK ?= "root=/dev/ram0 rw" + BITSTREAM_LOAD_ADDRESS ?= "0x100000" do_configure[noexec] = "1" @@ -217,6 +228,9 @@ do_compile() { -e 's/@@UENV_MMC_LOAD_ADDRESS@@/${UENV_MMC_LOAD_ADDRESS}/' \ -e 's/@@UENV_TEXTFILE@@/${UENV_TEXTFILE}/' \ -e 's/@@RAMDISK_IMAGE1@@/${RAMDISK_IMAGE1}/' \ + -e 's/@@PARTNUM@@/${PARTNUM}/' \ + -e 's:@@KERNEL_ROOT_SD@@:${KERNEL_ROOT_SD}:' \ + -e 's:@@KERNEL_ROOT_RAMDISK@@:${KERNEL_ROOT_RAMDISK}:' \ "${WORKDIR}/boot.cmd.${BOOTMODE}${BOOTFILE_EXT}" > "${WORKDIR}/boot.cmd" mkimage -A arm -T script -C none -n "Boot script" -d "${WORKDIR}/boot.cmd" boot.scr sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \ -- cgit v1.2.3-54-g00ecf From ca0ca861395656fe00652b263beccdd0470ca998 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:29 -0600 Subject: versal-generic.conf: Use generic root boot script Use boot.cmd.generic.root boot script for versal generic configuration file. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-generic.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index b737f1d1..9b9ebf31 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -20,6 +20,7 @@ MACHINE_FEATURES += "rtc ext2 ext3 vfat usbhost" EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig" +BOOTMODE ?= "generic.root" SERIAL_CONSOLES ?= "115200;ttyAMA0" -- cgit v1.2.3-54-g00ecf From eb2786786ae68912adeef34b815084d6f437495b Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:30 -0600 Subject: zynqmp-generic.conf: Use generic root boot script Use boot.cmd.generic.root boot script for zynqmp generic configuration file. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynqmp-generic.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf index 15fe9d11..32de4d50 100644 --- a/meta-xilinx-core/conf/machine/zynqmp-generic.conf +++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf @@ -31,6 +31,7 @@ EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-nativ UBOOT_MACHINE ?= "xilinx_zynqmp_virt_defconfig" SPL_BINARY ?= "spl/boot.bin" +BOOTMODE ?= "generic.root" # Default SD image build onfiguration, use qemu-sd to pad IMAGE_CLASSES += "image-types-xilinx-qemu" -- cgit v1.2.3-54-g00ecf From 448dd4e452a57b1ad733571da7d9337c6641cd0c Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:31 -0600 Subject: zynq-generic.conf: Use generic root boot script Use boot.cmd.generic.root boot script for zynq generic machine configuration file. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/zynq-generic.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf index 3c30c362..6ad00d72 100644 --- a/meta-xilinx-core/conf/machine/zynq-generic.conf +++ b/meta-xilinx-core/conf/machine/zynq-generic.conf @@ -20,6 +20,7 @@ MACHINE_FEATURES += "rtc ext2 ext3 vfat usbhost usbgadget" EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native" UBOOT_MACHINE ?= "xilinx_zynq_virt_defconfig" +BOOTMODE ?= "generic.root" SERIAL_CONSOLES ?= "115200;ttyPS0" -- cgit v1.2.3-54-g00ecf From b3dd7a54e38566b3a413d4184af34acc49b3748e Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 23 Aug 2022 12:35:32 -0600 Subject: microblaze-generic.conf: Use generic root boot script Use boot.cmd.generic.root boot script for microblaze generic machine configuration file. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index c0e41948..e85f9a9c 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -44,6 +44,7 @@ EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-nativ UBOOT_MACHINE ?= "microblaze-generic_defconfig" UBOOT_INITIAL_ENV = "" +BOOTMODE ?= "generic.root" HDF_MACHINE = "kc705-microblazeel" IMAGE_FSTYPES += "cpio.gz" -- cgit v1.2.3-54-g00ecf From 5e6033ff41196c4be9a9438e6f6b95eab76ab933 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 23 Aug 2022 11:38:47 -0700 Subject: versal-net-generic: Fix u-boot defconfig The defconfig, due to being set with ?=, but be set BEFORE the inclusion of the default versal settings, otherwise the version defconfig will be used. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-net-generic.conf | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf index e079f2c3..1b7aa590 100644 --- a/meta-xilinx-core/conf/machine/versal-net-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -8,6 +8,9 @@ MACHINEOVERRIDES =. "${@['', 'versal-net-generic:']['versal-net-generic' != '${M SOC_VARIANT = "net" +# Must be set first, or versal-generic will set it +UBOOT_MACHINE ?= "xilinx_versal_net_virt_defconfig" + require conf/machine/versal-generic.conf #### REMOVE THE FOLLOWING WHEN BOOTGEN IS SYNCED @@ -19,12 +22,10 @@ MACHINEOVERRIDES:class-nativesdk = "versal-net" # TODO: Should this be moved to device-tree recipe? YAML_DT_BOARD_FLAGS ?= "{BOARD versal-net-ipp-rev1.5}" -UBOOT_MACHINE ?= "xilinx_versal_net_virt_defconfig" - HDF_MACHINE = "versal-net-generic" -QEMU_HW_DTB_PS ="${QEMU_HW_DTB_PATH}/board-versal-ksb-psx-virt.dtb" -QEMU_HW_DTB_PMC ="${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ksb-psx-virt.dtb" +QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" #### No additional settings should be after the Postamble #### Postamble -- cgit v1.2.3-54-g00ecf From a583c938068d5b1db9d0cfbf12b17791f845b4dc Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 25 Aug 2022 15:56:41 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 94fca3f9..9005c90b 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "65cca926a3f4860b041eae1e62168f90c0b506a1" +SRCREV = "752455f235305286e672d10800cffcc0c0a3b8cd" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 921ef207..a25f12da 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "32a31b33e66956fb2c0956c683530498fd1ebacd" +SRCREV = "a1926f72cee6144bb70e1ad59f381178e41ee65d" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index f0e5df2b..b4a49391 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a5ede6b10b538904d66fcf4ffff53071aa3a4b57" +ESW_REV[2022.2] = "426b65e087ecbe5cab833be2c813a09bd25b8632" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From cfdb9d82f5dbbe4954744ea99605c89c7eb1df89 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 26 Aug 2022 14:57:00 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 77b2d9a2..43be5437 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "6be6f201d8e795afcb4e4f7a5fc83704dfe6fc11" +SRCREV ?= "aec07daf197f1853ee1a1d905e1eff4fe160f408" -- cgit v1.2.3-54-g00ecf From b9cdeb105f8865bc8d53e61501f0f25f22e526d6 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 26 Aug 2022 17:57:29 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 9b4a7ce1..6e4b7d0f 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "c7e8c327df53e97e1ad5e52e3b8ae2ba57f6565d" +SRCREV = "7c85661015b70f6b9aa821e6ebeea0dd96a59287" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index b4a49391..462e2542 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "426b65e087ecbe5cab833be2c813a09bd25b8632" +ESW_REV[2022.2] = "9f260a78f3e1a7f13bfb4859b9850e21ff7eab4c" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From e6671e6ec0e2e66ac82c5ed3675b9d33ba41bff4 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 25 Aug 2022 09:37:19 -0700 Subject: versal-net-generic.conf: Move to different psm DTB Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-net-generic.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf index 1b7aa590..bcda7c9b 100644 --- a/meta-xilinx-core/conf/machine/versal-net-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -24,7 +24,7 @@ YAML_DT_BOARD_FLAGS ?= "{BOARD versal-net-ipp-rev1.5}" HDF_MACHINE = "versal-net-generic" -QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ksb-psx-virt.dtb" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" #### No additional settings should be after the Postamble -- cgit v1.2.3-54-g00ecf From 3b679a0e52234fe4fa933e9ea060e5ba2f663b3e Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 25 Aug 2022 09:38:19 -0700 Subject: versal-net-generic.conf: Disable psmfw on versal net *** TEMPORARY *** Currently the psmfw is not working properly, fall back to the version embedded into the XSA. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-net-generic.conf | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf index bcda7c9b..4230c620 100644 --- a/meta-xilinx-core/conf/machine/versal-net-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -24,9 +24,13 @@ YAML_DT_BOARD_FLAGS ?= "{BOARD versal-net-ipp-rev1.5}" HDF_MACHINE = "versal-net-generic" -QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" +# Workaround: building PSM doesn't result in a working PSM, use the XSA provided one +# Affects bootbin generation +BIF_FSBL_ATTR = "base-pdi plmfw" + #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_net_generic']['versal-net-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From 4e816c7a95cbe8d0e832b6d092c0231397259702 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 25 Aug 2022 09:43:25 -0700 Subject: machine-xilinx-default.inc: Add WKS_FILE_DEPENDS based on IMAGE_BOOT_FILES When the files pointed to by IMAGE_BOOT_FILES change, we need to let the wic system know a new rootfs is required. Do this via WKS_FILE_DEPENDS. A number of automatic ones have been added to the system, if additional files are added (or ones that use different names) it is up to the machine.conf file [or configuration] to add the necessary dependencies. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc index a4b0c59a..aa91f771 100644 --- a/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc +++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc @@ -38,6 +38,13 @@ XSERVER ?= " \ ${XSERVER_EXT} \ " +# Automatically add WKS_FILE_DEPENDS based on the configuration +WKS_FILE_DEPENDS:append = "${@bb.utils.contains('IMAGE_BOOT_FILES', 'boot.bin', ' xilinx-bootbin', '', d)}" +WKS_FILE_DEPENDS:append = "${@bb.utils.contains('IMAGE_BOOT_FILES', 'system.dtb', ' virtual/dtb', '', d)}" +WKS_FILE_DEPENDS:append = "${@bb.utils.contains('IMAGE_BOOT_FILES', 'boot.scr', ' u-boot-zynq-scr', '', d)}" +WKS_FILE_DEPENDS:append = "${@bb.utils.contains('IMAGE_BOOT_FILES', 'uEnv.txt', ' u-boot-zynq-uenv', '', d)}" +WKS_FILE_DEPENDS:append = "${@bb.utils.contains('IMAGE_BOOT_FILES', 'atf-uboot.ub', ' arm-trusted-firmware', '', d)}" + IMAGE_BOOT_FILES ?= "${@get_default_image_boot_files(d)}" def get_default_image_boot_files(d): -- cgit v1.2.3-54-g00ecf From 8df2cd9ae564beae8bc3ee299ae300918ec4316d Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 24 Aug 2022 21:43:58 -0600 Subject: versal-net-generic.conf: Move Board DT Flags to dynamic layers Move YAML_DT_BOARD_FLAGS to meta-xilinx-tools dynamic layers else build fails when meta-xilinx-tools layers is not part of bblayers. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-net-generic.conf | 3 --- 1 file changed, 3 deletions(-) diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf index 4230c620..9d912395 100644 --- a/meta-xilinx-core/conf/machine/versal-net-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -19,9 +19,6 @@ MACHINEOVERRIDES:class-native = "versal-net" MACHINEOVERRIDES:class-nativesdk = "versal-net" #### REMOVE THE ABOVE -# TODO: Should this be moved to device-tree recipe? -YAML_DT_BOARD_FLAGS ?= "{BOARD versal-net-ipp-rev1.5}" - HDF_MACHINE = "versal-net-generic" QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" -- cgit v1.2.3-54-g00ecf From bfafa8ba837c4399bd575aee4a6405a074237c7a Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 24 Aug 2022 21:43:59 -0600 Subject: device-tree.bbappend: Add board dt flags for generic machine conf Add YAML_DT_BOARD_FLAGS for all the generic machine configuration files. Below table provides machine conf, xsa and associated dtsi files details. Machine Conf XSA Board DTSI ------------ --- --------- microbalze-generic kc705-microblazeel kc705-full zynq-generic zc702-zynq7 zc702 zynqmp-generic zcu102-zynqmp zcu102-rev1.0 versal-generic vck190-versal versal-vck190-reva-x-ebm-01-reva versal-net-generic versal-net-generic versal-net-ipp-rev1.5 For ZC702 and ZCU102 eval boards linux kernel source has a copy of zc702 and zcu102-rev1.0 dts files but for VCK190 and KC705 kernel doesn't have a board dtsi files. Hence for Versal and MicroBlaze generic machine use VCK190 and KC705 board dtsi files from DTG which is synced from u-boot-xlnx repo. Signed-off-by: Sandeep Gundlupet Raju Moved from meta-xilinx-bsp to meta-xilinux-core, as the machines are defined in core. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/layer.conf | 2 ++ .../recipes-bsp/device-tree/device-tree.bbappend | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf index e8b5ebd4..bdf14ee9 100644 --- a/meta-xilinx-core/conf/layer.conf +++ b/meta-xilinx-core/conf/layer.conf @@ -18,6 +18,8 @@ meta-python:${LAYERDIR}/dynamic-layers/meta-python/recipes-*/*/*.bb \ meta-python:${LAYERDIR}/dynamic-layers/meta-python/recipes-*/*/*.bbappend \ virtualization-layer:${LAYERDIR}/dynamic-layers/virtualization-layer/recipes-*/*/*.bb \ virtualization-layer:${LAYERDIR}/dynamic-layers/virtualization-layer/recipes-*/*/*.bbappend \ +xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bb \ +xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bbappend \ " LAYERDEPENDS_xilinx = "core" diff --git a/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..a3dedd85 --- /dev/null +++ b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,18 @@ +# Set Board DTSI files for generic manchine configuration files based on HDF_MACHINE. + +# microblaze-generic.conf uses HDF_MACHINE = "kc705-microblazeel", Hence set kc705-full dtsi file. +YAML_MAIN_MEMORY_CONFIG:microblaze-generic ?= "mig_7series_0" +YAML_CONSOLE_DEVICE_CONFIG:microblaze-generic ?= "axi_uartlite_0" +YAML_DT_BOARD_FLAGS:microblaze-generic ?= "{BOARD kc705-full}" + +# zynq-generic.conf uses HDF_MACHINE = "zc702-zynq7", Hence set zc702 dtsi file. +YAML_DT_BOARD_FLAGS:zynq-generic ?= "{BOARD zc702}" + +# zynqmp-generic.conf uses HDF_MACHINE = "zcu102-zynqmp", Hence set zcu102-rev1.0 dtsi file. +YAML_DT_BOARD_FLAGS:zynqmp-generic ?= "{BOARD zcu102-rev1.0}" + +# versal-generic.conf file uses HDF_MACHINE = "vck190-versal", Hence set versal-vck190-reva-x-ebm-01-reva dtsi file. +YAML_DT_BOARD_FLAGS:versal-generic ?= "{BOARD versal-vck190-reva-x-ebm-01-reva}" + +# versal-net-generic.conf uses HDF_MACHINE = "versal-net-generic", Hence set versal-net-ipp-rev1.5 dtsi file. +YAML_DT_BOARD_FLAGS:versal-net-generic ?= "{BOARD versal-net-ipp-rev1.5}" -- cgit v1.2.3-54-g00ecf From 0f380c295f9bc12205c257cf44b3188d1b2b6f79 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Thu, 25 Aug 2022 12:28:15 -0700 Subject: u-boot-zynq-scr: Update boot.cmd.generic.root to auto select mmc or usb Autoselect the root device as mmcblk0/1p, or sda. This allows the partition to be appended as well as other overrides to be selected from the Yocto Project configuration. Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb | 6 ++---- .../recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root | 7 +++++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb index 50a08919..8a3a5db6 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb @@ -160,14 +160,12 @@ NAND_FIT_IMAGE_OFFSET ?= "0x4180000" NAND_FIT_IMAGE_OFFSET:zynq ?= "0x1080000" NAND_FIT_IMAGE_SIZE ?= "0x6400000" -# Set SD/eMMC Controller Device Number as 0 -SDBOOTDEV ?= "0" - # Default to booting with the rootfs device being partition 2 for SD/eMMC PARTNUM ?= "2" # Set Kernel root filesystem parameter for SD/eMMC boot -KERNEL_ROOT_SD ?= "root=/dev/mmcblk${SDBOOTDEV}p${PARTNUM} rw rootwait" +# Bootdev will automatically be set to 'sda' or 'mmcblkXp' +KERNEL_ROOT_SD ?= "root=/dev/\${bootdev}${PARTNUM} ro rootwait" # Set Kernel root filesystem parameter for JTAG/QSPI/OSPI/NAND(using RAMDISK) boot KERNEL_ROOT_RAMDISK ?= "root=/dev/ram0 rw" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root index f4244493..ca90cbe1 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic.root @@ -19,6 +19,13 @@ do @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ fi if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" || test "${boot_target}" = "usb0" || test "${boot_target}" = "usb1"; then + if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1"; then + setenv bootdev mmcblk${devnum}p + fi + if test "${boot_target}" = "usb0" || test "${boot_target}" = "usb1"; then + setenv bootdev sda + fi + if test -e ${devtype} ${devnum}:${distro_bootpart} /@@UENV_TEXTFILE@@; then fatload ${devtype} ${devnum}:${distro_bootpart} @@UENV_MMC_LOAD_ADDRESS@@ @@UENV_TEXTFILE@@; echo "Importing environment(@@UENV_TEXTFILE@@) from ${boot_target}..." -- cgit v1.2.3-54-g00ecf From 7e8e46df8596415024a5f0b56056955e0b720696 Mon Sep 17 00:00:00 2001 From: Sergei Korneichuk Date: Thu, 25 Aug 2022 23:58:05 -0700 Subject: dfx-mgr: SRCREV: remove unused websockets The SRCREV is for a commit to remove unused websockets code Signed-off-by: Sergei Korneichuk Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb index 1088679b..6bd24fdf 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_1.0.bb @@ -9,7 +9,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH = "master" -SRCREV = "62982e7091f5bd73687ec5e1c9f51cdce65c8927" +SRCREV = "b7fe333513edda99cd84f3a2d26e01aaf4bd5e02" SOMAJOR = "1" SOMINOR = "0" SOVERSION = "${SOMAJOR}.${SOMINOR}" -- cgit v1.2.3-54-g00ecf From df5f09ebf023756f5c8825d9d05e530a92e03ede Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 30 Aug 2022 14:16:16 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 9005c90b..9d1ff13a 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "752455f235305286e672d10800cffcc0c0a3b8cd" +SRCREV = "f7c1e7084dcb5ed9653e2fa89081f266ba02dfb8" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index a25f12da..e521f42e 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "a1926f72cee6144bb70e1ad59f381178e41ee65d" +SRCREV = "7e41fe9f1663e176fca4e76fef0c7e3057aee43b" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From ce3a1c175c0e703fd18a8092e844a4d5fc9897ef Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 29 Aug 2022 12:22:51 -0500 Subject: xlnx-embeddedsw: Move to 2022.2 branch Signed-off-by: Mark Hatle --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 462e2542..f9c37b68 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -10,7 +10,7 @@ ESW_BRANCH[2020.2] = "master-rel-2020.2" ESW_BRANCH[2021.1] = "xlnx_rel_v2021.1" ESW_BRANCH[2021.2] = "xlnx_rel_v2021.2" ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1" -ESW_BRANCH[2022.2] = "master-next" +ESW_BRANCH[2022.2] = "xlnx_rel_v2022.2-next" ESW_BRANCH[git] = "master-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" @@ -36,6 +36,7 @@ LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' +LIC_FILES_CHKSUM[xlnx_rel_v2022.2-next] = '7b5fc0b2a22e2882e1506436b3293e5d' LIC_FILES_CHKSUM[master-next] = '7b5fc0b2a22e2882e1506436b3293e5d' LIC_FILES_CHKSUM[master] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" -- cgit v1.2.3-54-g00ecf From 6beb6bcde0604ce5646d80e4100a619cf6b7c778 Mon Sep 17 00:00:00 2001 From: "Bramandlapalli, Rahul" Date: Tue, 30 Aug 2022 11:14:44 +0000 Subject: xrt_git:zocl_git:update commitid [AMD Official Use Only - General] Signed-off-by: rbramand rbramand@xilinx.com Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 27135209..51455162 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "57c655bf98d1c9bc3dc4ba5e3bf7cf80a5e5ecc3" +SRCREV= "6af05b317093d0c38184322585ac21617f4789c5" PV = "202220.2.14.0" diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb index 96aac96f..7b87e217 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb @@ -40,7 +40,8 @@ FILES:${PN} += "\ ${libdir}/lib*.so \ ${libdir}/lib*.so.* \ ${libdir}/ps_kernels_lib \ - /lib/*.so* " + /lib/*.so* \ + ${datadir}" INSANE_SKIP:${PN} += "dev-so" pkg_postinst_ontarget:${PN}() { -- cgit v1.2.3-54-g00ecf From 84c6b5b662950c3b7cfa921fe964a2ffbcd4ce72 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 29 Aug 2022 23:39:35 -0600 Subject: device-tree: Remove kc705 static dts files Obsolete kc705 static device tree files and use DTG generated one based on xsa parsing. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-bsp/device-tree/device-tree.bbappend | 6 - .../kc705-microblazeel/kc705-microblazeel.dts | 56 --- .../device-tree/files/kc705-microblazeel/pl.dtsi | 445 --------------------- .../files/kc705-microblazeel/system-conf.dtsi | 43 -- 4 files changed, 550 deletions(-) delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend index 83f8c57b..9ab3f24e 100644 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend @@ -4,12 +4,6 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" COMPATIBLE_MACHINE:qemu-zynq7 = ".*" SRC_URI:append:qemu-zynq7 = " file://qemu-zynq7.dts" -COMPATIBLE_MACHINE:kc705-microblazeel = ".*" -SRC_URI:append:kc705-microblazeel = " \ - file://kc705-microblazeel.dts \ - file://pl.dtsi \ - file://system-conf.dtsi \ - " SRC_URI:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' file://pnc.dtsi', '', d)}" do_configure:append() { diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts deleted file mode 100644 index 45e488c1..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts +++ /dev/null @@ -1,56 +0,0 @@ -/dts-v1/; -/include/ "pl.dtsi" -/include/ "system-conf.dtsi" -/ { - hard-reset-gpios = <&reset_gpio 0 1>; - aliases { - ethernet0 = &axi_ethernet; - i2c0 = &iic_main; - serial0 = &rs232_uart; - }; - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; -}; - -&iic_main { - i2cswitch@74 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - si570: clock-generator@5d { - #clock-cells = <0>; - compatible = "silabs,si570"; - temperature-stability = <50>; - reg = <0x5d>; - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - eeprom@54 { - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - }; -}; - -&axi_ethernet { - phy-handle = <&phy0>; - axi_ethernet_mdio: mdio { - phy0: phy@7 { - device_type = "ethernet-phy"; - reg = <7>; - }; - }; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi deleted file mode 100644 index 43bc2ab7..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,microblaze"; - model = "Xilinx MicroBlaze"; - cpus { - #address-cells = <1>; - #cpus = <1>; - #size-cells = <0>; - microblaze_0: cpu@0 { - bus-handle = <&amba_pl>; - clock-frequency = <200000000>; - clocks = <&clk_cpu>; - compatible = "xlnx,microblaze-10.0"; - d-cache-baseaddr = <0x0000000080000000>; - d-cache-highaddr = <0x00000000bfffffff>; - d-cache-line-size = <0x20>; - d-cache-size = <0x4000>; - device_type = "cpu"; - i-cache-baseaddr = <0x0000000080000000>; - i-cache-highaddr = <0x00000000bfffffff>; - i-cache-line-size = <0x10>; - i-cache-size = <0x4000>; - interrupt-handle = <µblaze_0_axi_intc>; - model = "microblaze,10.0"; - timebase-frequency = <200000000>; - xlnx,addr-size = <0x20>; - xlnx,addr-tag-bits = <0x10>; - xlnx,allow-dcache-wr = <0x1>; - xlnx,allow-icache-wr = <0x1>; - xlnx,area-optimized = <0x0>; - xlnx,async-interrupt = <0x1>; - xlnx,async-wakeup = <0x3>; - xlnx,avoid-primitives = <0x0>; - xlnx,base-vectors = <0x0000000000000000>; - xlnx,branch-target-cache-size = <0x0>; - xlnx,cache-byte-size = <0x4000>; - xlnx,d-axi = <0x1>; - xlnx,d-lmb = <0x1>; - xlnx,d-lmb-mon = <0x0>; - xlnx,daddr-size = <0x20>; - xlnx,data-size = <0x20>; - xlnx,dc-axi-mon = <0x0>; - xlnx,dcache-addr-tag = <0x10>; - xlnx,dcache-always-used = <0x1>; - xlnx,dcache-byte-size = <0x4000>; - xlnx,dcache-data-width = <0x0>; - xlnx,dcache-force-tag-lutram = <0x0>; - xlnx,dcache-line-len = <0x8>; - xlnx,dcache-use-writeback = <0x0>; - xlnx,dcache-victims = <0x0>; - xlnx,debug-counter-width = <0x20>; - xlnx,debug-enabled = <0x1>; - xlnx,debug-event-counters = <0x5>; - xlnx,debug-external-trace = <0x0>; - xlnx,debug-interface = <0x0>; - xlnx,debug-latency-counters = <0x1>; - xlnx,debug-profile-size = <0x0>; - xlnx,debug-trace-async-reset = <0x0>; - xlnx,debug-trace-size = <0x2000>; - xlnx,div-zero-exception = <0x1>; - xlnx,dp-axi-mon = <0x0>; - xlnx,dynamic-bus-sizing = <0x0>; - xlnx,ecc-use-ce-exception = <0x0>; - xlnx,edge-is-positive = <0x1>; - xlnx,enable-discrete-ports = <0x0>; - xlnx,endianness = <0x1>; - xlnx,fault-tolerant = <0x0>; - xlnx,fpu-exception = <0x0>; - xlnx,freq = <0xbebc200>; - xlnx,fsl-exception = <0x0>; - xlnx,fsl-links = <0x0>; - xlnx,i-axi = <0x0>; - xlnx,i-lmb = <0x1>; - xlnx,i-lmb-mon = <0x0>; - xlnx,iaddr-size = <0x20>; - xlnx,ic-axi-mon = <0x0>; - xlnx,icache-always-used = <0x1>; - xlnx,icache-data-width = <0x0>; - xlnx,icache-force-tag-lutram = <0x0>; - xlnx,icache-line-len = <0x4>; - xlnx,icache-streams = <0x1>; - xlnx,icache-victims = <0x8>; - xlnx,ill-opcode-exception = <0x1>; - xlnx,imprecise-exceptions = <0x0>; - xlnx,instr-size = <0x20>; - xlnx,interconnect = <0x2>; - xlnx,interrupt-is-edge = <0x0>; - xlnx,interrupt-mon = <0x0>; - xlnx,ip-axi-mon = <0x0>; - xlnx,lockstep-master = <0x0>; - xlnx,lockstep-select = <0x0>; - xlnx,lockstep-slave = <0x0>; - xlnx,mmu-dtlb-size = <0x4>; - xlnx,mmu-itlb-size = <0x2>; - xlnx,mmu-privileged-instr = <0x0>; - xlnx,mmu-tlb-access = <0x3>; - xlnx,mmu-zones = <0x2>; - xlnx,num-sync-ff-clk = <0x2>; - xlnx,num-sync-ff-clk-debug = <0x2>; - xlnx,num-sync-ff-clk-irq = <0x1>; - xlnx,num-sync-ff-dbg-clk = <0x1>; - xlnx,num-sync-ff-dbg-trace-clk = <0x2>; - xlnx,number-of-pc-brk = <0x1>; - xlnx,number-of-rd-addr-brk = <0x0>; - xlnx,number-of-wr-addr-brk = <0x0>; - xlnx,opcode-0x0-illegal = <0x1>; - xlnx,optimization = <0x0>; - xlnx,pc-width = <0x20>; - xlnx,piaddr-size = <0x20>; - xlnx,pvr = <0x2>; - xlnx,pvr-user1 = <0x00>; - xlnx,pvr-user2 = <0x00000000>; - xlnx,reset-msr = <0x00000000>; - xlnx,reset-msr-bip = <0x0>; - xlnx,reset-msr-dce = <0x0>; - xlnx,reset-msr-ee = <0x0>; - xlnx,reset-msr-eip = <0x0>; - xlnx,reset-msr-ice = <0x0>; - xlnx,reset-msr-ie = <0x0>; - xlnx,sco = <0x0>; - xlnx,trace = <0x0>; - xlnx,unaligned-exceptions = <0x1>; - xlnx,use-barrel = <0x1>; - xlnx,use-branch-target-cache = <0x0>; - xlnx,use-config-reset = <0x0>; - xlnx,use-dcache = <0x1>; - xlnx,use-div = <0x1>; - xlnx,use-ext-brk = <0x0>; - xlnx,use-ext-nm-brk = <0x0>; - xlnx,use-extended-fsl-instr = <0x0>; - xlnx,use-fpu = <0x0>; - xlnx,use-hw-mul = <0x2>; - xlnx,use-icache = <0x1>; - xlnx,use-interrupt = <0x2>; - xlnx,use-mmu = <0x3>; - xlnx,use-msr-instr = <0x1>; - xlnx,use-non-secure = <0x0>; - xlnx,use-pcmp-instr = <0x1>; - xlnx,use-reorder-instr = <0x1>; - xlnx,use-stack-protection = <0x0>; - }; - }; - clocks { - #address-cells = <1>; - #size-cells = <0>; - clk_cpu: clk_cpu@0 { - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "clk_cpu"; - compatible = "fixed-clock"; - reg = <0>; - }; - clk_bus_0: clk_bus_0@1 { - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "clk_bus_0"; - compatible = "fixed-clock"; - reg = <1>; - }; - }; - amba_pl: amba_pl { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges ; - axi_ethernet: ethernet@40c00000 { - axistream-connected = <&axi_ethernet_dma>; - axistream-control-connected = <&axi_ethernet_dma>; - clock-frequency = <100000000>; - compatible = "xlnx,axi-ethernet-1.00.a"; - device_type = "network"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <4 2>; - phy-mode = "gmii"; - reg = <0x40c00000 0x40000>; - xlnx = <0x0>; - xlnx,axiliteclkrate = <0x0>; - xlnx,axisclkrate = <0x0>; - xlnx,clockselection = <0x0>; - xlnx,enableasyncsgmii = <0x0>; - xlnx,gt-type = <0x0>; - xlnx,gtinex = <0x0>; - xlnx,gtlocation = <0x0>; - xlnx,gtrefclksrc = <0x0>; - xlnx,include-dre ; - xlnx,instantiatebitslice0 = <0x0>; - xlnx,phy-type = <0x1>; - xlnx,phyaddr = <0x1>; - xlnx,rable = <0x0>; - xlnx,rxcsum = <0x0>; - xlnx,rxlane0-placement = <0x0>; - xlnx,rxlane1-placement = <0x0>; - xlnx,rxmem = <0x1000>; - xlnx,rxnibblebitslice0used = <0x0>; - xlnx,tx-in-upper-nibble = <0x1>; - xlnx,txcsum = <0x0>; - xlnx,txlane0-placement = <0x0>; - xlnx,txlane1-placement = <0x0>; - axi_ethernet_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - axi_ethernet_dma: dma@41e00000 { - #dma-cells = <1>; - axistream-connected = <&axi_ethernet>; - axistream-control-connected = <&axi_ethernet>; - clock-frequency = <200000000>; - clock-names = "s_axi_lite_aclk"; - clocks = <&clk_bus_0>; - compatible = "xlnx,eth-dma"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <3 2 2 2>; - reg = <0x41e00000 0x10000>; - xlnx,include-dre ; - }; - axi_timer_0: timer@41c00000 { - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-timer-1.00.a"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <5 2>; - reg = <0x41c00000 0x10000>; - xlnx,count-width = <0x20>; - xlnx,gen0-assert = <0x1>; - xlnx,gen1-assert = <0x1>; - xlnx,one-timer-only = <0x0>; - xlnx,trig0-assert = <0x1>; - xlnx,trig1-assert = <0x1>; - }; - calib_complete_gpio: gpio@40010000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40010000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - dip_switches_4bits: gpio@40020000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40020000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - iic_main: i2c@40800000 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <1 2>; - reg = <0x40800000 0x10000>; - }; - led_8bits: gpio@40030000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40030000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x8>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - linear_flash: flash@60000000 { - bank-width = <2>; - compatible = "cfi-flash"; - reg = <0x60000000 0x8000000>; - xlnx,axi-clk-period-ps = <0x1388>; - xlnx,include-datawidth-matching-0 = <0x1>; - xlnx,include-datawidth-matching-1 = <0x1>; - xlnx,include-datawidth-matching-2 = <0x1>; - xlnx,include-datawidth-matching-3 = <0x1>; - xlnx,include-negedge-ioregs = <0x0>; - xlnx,lflash-period-ps = <0x1388>; - xlnx,linear-flash-sync-burst = <0x0>; - xlnx,max-mem-width = <0x10>; - xlnx,mem-a-lsb = <0x0>; - xlnx,mem-a-msb = <0x1f>; - xlnx,mem0-type = <0x2>; - xlnx,mem0-width = <0x10>; - xlnx,mem1-type = <0x0>; - xlnx,mem1-width = <0x10>; - xlnx,mem2-type = <0x0>; - xlnx,mem2-width = <0x10>; - xlnx,mem3-type = <0x0>; - xlnx,mem3-width = <0x10>; - xlnx,num-banks-mem = <0x1>; - xlnx,page-size = <0x10>; - xlnx,parity-type-mem-0 = <0x0>; - xlnx,parity-type-mem-1 = <0x0>; - xlnx,parity-type-mem-2 = <0x0>; - xlnx,parity-type-mem-3 = <0x0>; - xlnx,port-diff = <0x0>; - xlnx,s-axi-en-reg = <0x0>; - xlnx,s-axi-mem-addr-width = <0x20>; - xlnx,s-axi-mem-data-width = <0x20>; - xlnx,s-axi-mem-id-width = <0x1>; - xlnx,s-axi-reg-addr-width = <0x5>; - xlnx,s-axi-reg-data-width = <0x20>; - xlnx,synch-pipedelay-0 = <0x1>; - xlnx,synch-pipedelay-1 = <0x1>; - xlnx,synch-pipedelay-2 = <0x1>; - xlnx,synch-pipedelay-3 = <0x1>; - xlnx,tavdv-ps-mem-0 = <0x1fbd0>; - xlnx,tavdv-ps-mem-1 = <0x3a98>; - xlnx,tavdv-ps-mem-2 = <0x3a98>; - xlnx,tavdv-ps-mem-3 = <0x3a98>; - xlnx,tcedv-ps-mem-0 = <0x1fbd0>; - xlnx,tcedv-ps-mem-1 = <0x3a98>; - xlnx,tcedv-ps-mem-2 = <0x3a98>; - xlnx,tcedv-ps-mem-3 = <0x3a98>; - xlnx,thzce-ps-mem-0 = <0x88b8>; - xlnx,thzce-ps-mem-1 = <0x1b58>; - xlnx,thzce-ps-mem-2 = <0x1b58>; - xlnx,thzce-ps-mem-3 = <0x1b58>; - xlnx,thzoe-ps-mem-0 = <0x1b58>; - xlnx,thzoe-ps-mem-1 = <0x1b58>; - xlnx,thzoe-ps-mem-2 = <0x1b58>; - xlnx,thzoe-ps-mem-3 = <0x1b58>; - xlnx,tlzwe-ps-mem-0 = <0xc350>; - xlnx,tlzwe-ps-mem-1 = <0x0>; - xlnx,tlzwe-ps-mem-2 = <0x0>; - xlnx,tlzwe-ps-mem-3 = <0x0>; - xlnx,tpacc-ps-flash-0 = <0x61a8>; - xlnx,tpacc-ps-flash-1 = <0x61a8>; - xlnx,tpacc-ps-flash-2 = <0x61a8>; - xlnx,tpacc-ps-flash-3 = <0x61a8>; - xlnx,twc-ps-mem-0 = <0x11170>; - xlnx,twc-ps-mem-1 = <0x3a98>; - xlnx,twc-ps-mem-2 = <0x3a98>; - xlnx,twc-ps-mem-3 = <0x3a98>; - xlnx,twp-ps-mem-0 = <0x13880>; - xlnx,twp-ps-mem-1 = <0x2ee0>; - xlnx,twp-ps-mem-2 = <0x2ee0>; - xlnx,twp-ps-mem-3 = <0x2ee0>; - xlnx,twph-ps-mem-0 = <0x13880>; - xlnx,twph-ps-mem-1 = <0x2ee0>; - xlnx,twph-ps-mem-2 = <0x2ee0>; - xlnx,twph-ps-mem-3 = <0x2ee0>; - xlnx,use-startup = <0x0>; - xlnx,use-startup-int = <0x0>; - xlnx,wr-rec-time-mem-0 = <0x186a0>; - xlnx,wr-rec-time-mem-1 = <0x6978>; - xlnx,wr-rec-time-mem-2 = <0x6978>; - xlnx,wr-rec-time-mem-3 = <0x6978>; - }; - microblaze_0_axi_intc: interrupt-controller@41200000 { - #interrupt-cells = <2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = <0x41200000 0x10000>; - xlnx,kind-of-intr = <0x0>; - xlnx,num-intr-inputs = <0x6>; - }; - push_buttons_5bits: gpio@40040000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40040000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x5>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - reset_gpio: gpio@40000000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x40000000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - rs232_uart: serial@44a00000 { - clock-frequency = <200000000>; - clocks = <&clk_bus_0>; - compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; - current-speed = <115200>; - device_type = "serial"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <0 2>; - port-number = <0>; - reg = <0x44a00000 0x10000>; - reg-offset = <0x1000>; - reg-shift = <2>; - xlnx,external-xin-clk-hz = <0x17d7840>; - xlnx,external-xin-clk-hz-d = <0x19>; - xlnx,has-external-rclk = <0x0>; - xlnx,has-external-xin = <0x0>; - xlnx,is-a-16550 = <0x1>; - xlnx,s-axi-aclk-freq-hz-d = "200.0"; - xlnx,use-modem-ports = <0x1>; - xlnx,use-user-ports = <0x1>; - }; - }; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi deleted file mode 100644 index 09b26c6a..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -/* - * CAUTION: This file is automatically generated by PetaLinux SDK. - * DO NOT modify this file - */ - - -/ { - chosen { - bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = "serial0:115200n8"; - }; -}; - -&axi_ethernet { - local-mac-address = [00 0a 35 00 22 01]; -}; - -&linear_flash { - reg = <0x60000000 0x08000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0x00000000 { - label = "fpga"; - reg = <0x00000000 0x00b00000>; - }; - partition@0x00b00000 { - label = "boot"; - reg = <0x00b00000 0x00080000>; - }; - partition@0x00b80000 { - label = "bootenv"; - reg = <0x00b80000 0x00020000>; - }; - partition@0x00ba0000 { - label = "kernel"; - reg = <0x00ba0000 0x00c00000>; - }; - partition@0x017a0000 { - label = "spare"; - reg = <0x017a0000 0x00000000>; - }; -}; - -- cgit v1.2.3-54-g00ecf From e9db8467054630f2226f5aa575426ef017e23613 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 29 Aug 2022 23:39:36 -0600 Subject: linux-xlnx: Add new kernel fragment for microblaze machine Add new kernel fragment configuration for microblaze-generic machine configuration file. This fixes QEMU boot issue for microblaze-generic images. This kernel fragment is set for Kintex7 microblaze family and user can override this to required family. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../recipes-kernel/linux/linux-microblaze.inc | 5 ++++- .../linux/linux-xlnx/microblaze_generic.cfg | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 meta-xilinx-core/recipes-kernel/linux/linux-xlnx/microblaze_generic.cfg diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc b/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc index 4555bc28..efd21a18 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc +++ b/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc @@ -1,4 +1,7 @@ -SRC_URI += "file://mb-no-tree-loop-distribute-patterns.patch" +SRC_URI += " \ + file://mb-no-tree-loop-distribute-patterns.patch \ + file://microblaze_generic.cfg \ + " # MicroBlaze is a uImage target, but its not called 'uImage' instead it is called 'linux.bin.ub' python () { diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/microblaze_generic.cfg b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/microblaze_generic.cfg new file mode 100644 index 00000000..6ec6a997 --- /dev/null +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/microblaze_generic.cfg @@ -0,0 +1,18 @@ +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_DP83867_PHY=y +CONFIG_EARLY_PRINTK=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_NET_CORE=y +CONFIG_XILINX_PHY=y +CONFIG_XILINX_MICROBLAZE0_FAMILY="kintex7" +CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 +CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1 +CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 +CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 +CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2 +CONFIG_XILINX_MICROBLAZE0_USE_FPU=1 +CONFIG_XILINX_MICROBLAZE0_HW_VER="11.0" +CONFIG_KERNEL_BASE_ADDR=0x80000000 +CONFIG_CMDLINE="console=ttyUL0,115200 earlycon root=/dev/ram0 rw" +CONFIG_BLK_DEV_INITRD=y \ No newline at end of file -- cgit v1.2.3-54-g00ecf From 7aeb8f34d59a9016293b32472a6b2cfc5b2b9831 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 29 Aug 2022 23:39:37 -0600 Subject: microblaze-generic.conf: Fix Serial console device name Microblaze generic use AXI Uart Lite serial device, Hence change the serial console device to ttyUL0 as default serial device. This also fixes INIT freeze issue. Starting syslogd/klogd: done Starting tcf-agent: OK INIT: Id "S0" respawning too fast: disabled for 5 minutes INIT: no more processes left in this runlevel Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/microblaze-generic.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf index e85f9a9c..92412681 100644 --- a/meta-xilinx-core/conf/machine/microblaze-generic.conf +++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf @@ -32,7 +32,7 @@ MACHINE_FEATURES = "" KERNEL_IMAGETYPE ?= "linux.bin.ub" KERNEL_IMAGETYPES = "" -SERIAL_CONSOLES ?= "115200;ttyS0" +SERIAL_CONSOLES ?= "115200;ttyUL0" MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" -- cgit v1.2.3-54-g00ecf From 6cd4b336aaf726e63b14f25f54a99e7e992bb775 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 31 Aug 2022 09:29:47 -0500 Subject: Revert "versal-net-generic.conf: Disable psmfw on versal net *** TEMPORARY ***" This reverts commit 3b679a0e52234fe4fa933e9ea060e5ba2f663b3e. Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-net-generic.conf | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/meta-xilinx-core/conf/machine/versal-net-generic.conf b/meta-xilinx-core/conf/machine/versal-net-generic.conf index 9d912395..1941235a 100644 --- a/meta-xilinx-core/conf/machine/versal-net-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-net-generic.conf @@ -21,13 +21,9 @@ MACHINEOVERRIDES:class-nativesdk = "versal-net" HDF_MACHINE = "versal-net-generic" -QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-net-psx-spp-1.4.dtb" QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmx-virt.dtb" -# Workaround: building PSM doesn't result in a working PSM, use the XSA provided one -# Affects bootbin generation -BIF_FSBL_ATTR = "base-pdi plmfw" - #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_net_generic']['versal-net-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From 944edbcc9a88d4c795f20a1b2fde9a58fc6aa8d2 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 31 Aug 2022 09:30:17 -0500 Subject: Updated SRCREV for 2022.2 Signed-off-by: Mark Hatle --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index f9c37b68..d96165f8 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "9f260a78f3e1a7f13bfb4859b9850e21ff7eab4c" +ESW_REV[2022.2] = "366c60db25d4b06f9567cf8de34d08259e35d12f" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From c180877b43d42d74464657366ee86b87d205c27d Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 31 Aug 2022 14:39:45 -0600 Subject: MAINTAINERS.md: Update maintainers email address Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- MAINTAINERS.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS.md b/MAINTAINERS.md index d14b73e5..6a61ba3b 100644 --- a/MAINTAINERS.md +++ b/MAINTAINERS.md @@ -17,9 +17,9 @@ https://www.openembedded.org/wiki/How_to_submit_a_patch_to_OpenEmbedded **Maintainers:** - Mark Hatle - Sandeep Gundlupet Raju - John Toomey + Mark Hatle + Sandeep Gundlupet Raju + John Toomey > **Note:** -- cgit v1.2.3-54-g00ecf From 8528ba1ed3eb51f4cf1a73d65095366dab46821f Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 1 Sep 2022 11:53:55 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d96165f8..0efa2584 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "366c60db25d4b06f9567cf8de34d08259e35d12f" +ESW_REV[2022.2] = "bb5156c80f1a6af87c5270c373cc0240d72a4c65" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 188fe2561b7dc8563f15fb06a75a8fe1bf8840cd Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 1 Sep 2022 16:26:09 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index e521f42e..c41e5df2 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "7e41fe9f1663e176fca4e76fef0c7e3057aee43b" +SRCREV = "0666ebfb0c32e2af2e2e943ca1561a9a0f83ee9f" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 0efa2584..a0402546 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "bb5156c80f1a6af87c5270c373cc0240d72a4c65" +ESW_REV[2022.2] = "f9503dcf194083da984776e51dc9c07f8cb6d498" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From cc3f3dde5c0da8a46334bee195c4713bcb2903cb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 2 Sep 2022 21:05:48 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index c41e5df2..78fdfecd 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "0666ebfb0c32e2af2e2e943ca1561a9a0f83ee9f" +SRCREV = "ca083075cd0c44d59496167de0af5d4859723f35" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index a0402546..14430aa4 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "f9503dcf194083da984776e51dc9c07f8cb6d498" +ESW_REV[2022.2] = "dec64619bf39121290deb926a5a2e05b7a859b93" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 8d2a7bb187077ae5b4c7829e023ec4fb2df1a74a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sat, 3 Sep 2022 20:21:44 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 6e4b7d0f..891e6b5a 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "7c85661015b70f6b9aa821e6ebeea0dd96a59287" +SRCREV = "8ba0d59bdbf83b3db8deb4402e2e5a04468abdb8" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 14430aa4..02837ed3 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "dec64619bf39121290deb926a5a2e05b7a859b93" +ESW_REV[2022.2] = "a490879f01d882c096d389c53b7aaefde8089a65" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 486e59debabca42b44ea372cc29ba911f3c0dfeb Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 5 Sep 2022 12:21:48 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 02837ed3..d0097f62 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "a490879f01d882c096d389c53b7aaefde8089a65" +ESW_REV[2022.2] = "4c7ada679c0f7793966a51fd8edee4f90462d5d9" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 886bd04c2b1a5f74331dbd014285e20b34131c68 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 6 Sep 2022 13:07:11 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb | 2 +- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb index 891e6b5a..7e423b9c 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.2.bb @@ -1,5 +1,5 @@ ATF_VERSION = "2.6" -SRCREV = "8ba0d59bdbf83b3db8deb4402e2e5a04468abdb8" +SRCREV = "85544c0159e216935e40174dadfed1296b6042bd" BRANCH = "xlnx_rebase_v2.6" LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index 9d1ff13a..b58fbd96 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "f7c1e7084dcb5ed9653e2fa89081f266ba02dfb8" +SRCREV = "3411b335bb7a0717da34bb4358c8d57f87deefab" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 43be5437..5c5ae787 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "aec07daf197f1853ee1a1d905e1eff4fe160f408" +SRCREV ?= "f165edfcf3618f936e46127199f69ff2cb4090d1" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 78fdfecd..a2c36f5a 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "ca083075cd0c44d59496167de0af5d4859723f35" +SRCREV = "64992c116e5ab0b7f31c96e8719a36e7da3a0ba2" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From be329ba462899936732f473e49d2b362593f29f2 Mon Sep 17 00:00:00 2001 From: "Manne, Nava kishore" Date: Mon, 5 Sep 2022 23:01:07 -0600 Subject: fpgautil: Update the fpgautil help This patch updates the fpgautil help to align with the full bitstream loading default behavior. Signed-off-by: Nava kishore Manne Add AMD Copyright notice. Signed-off-by: Sandeep Gundlupet Raju --- .../recipes-bsp/fpga-manager-script/files/fpgautil.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c index e4fb1d2f..04777a91 100644 --- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c +++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/files/fpgautil.c @@ -1,6 +1,7 @@ /****************************************************************************** * - * Copyright (C) 2019-2020 Xilinx, Inc. All rights reserved. + * Copyright (C) 2019-2022 Xilinx, Inc. All rights reserved. + * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy of * this software and associated documentation files (the "Software"), to deal in @@ -91,7 +92,7 @@ void print_usage(char *prg) fprintf(stderr, " Device Tree\n"); if (iszynqmp) { - fprintf(stderr, " Default: \n"); + fprintf(stderr, " Default: \n"); fprintf(stderr, " -s Optional: \n"); fprintf(stderr, " s := \n"); fprintf(stderr, " -k Optional: \n"); @@ -107,7 +108,7 @@ void print_usage(char *prg) fprintf(stderr, " \n"); fprintf(stderr, "Examples:\n"); fprintf(stderr, "(Load Full bitstream using Overlay)\n"); - fprintf(stderr, "%s -b top.bit.bin -o can.dtbo -f Full -n Full \n", prg); + fprintf(stderr, "%s -b top.bit.bin -o can.dtbo -f Full -n full \n", prg); fprintf(stderr, "(Load Partial bitstream using Overlay)\n"); fprintf(stderr, "%s -b rm0.bit.bin -o rm0.dtbo -f Partial -n PR0\n", prg); fprintf(stderr, "(Load Full bitstream using sysfs interface)\n"); @@ -127,7 +128,7 @@ void print_usage(char *prg) fprintf(stderr, "(Remove Partial Overlay)\n"); fprintf(stderr, "%s -R -n PR0\n", prg); fprintf(stderr, "(Remove Full Overlay)\n"); - fprintf(stderr, "%s -R -n Full\n", prg); + fprintf(stderr, "%s -R -n full\n", prg); fprintf(stderr, "Note: %s -R is responsible for only removing the dtbo file from the livetree. it will not remove the PL logic from the FPGA region.\n", prg); fprintf(stderr, " \n"); } -- cgit v1.2.3-54-g00ecf From 3912547c7ea7c4a08add44693412e8485c57f935 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Tue, 6 Sep 2022 23:03:05 -0600 Subject: fpga-manager-script: Update md5 checksum Signed-off-by: Sandeep Gundlupet Raju --- .../recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb index 416edf17..d22c995c 100644 --- a/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/fpga-manager-script/fpga-manager-script_1.0.bb @@ -1,7 +1,7 @@ SUMMARY = "Install user script to support fpga-manager" DESCRIPTION = "Install user script that loads and unloads overlays using kernel fpga-manager" LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://${WORKDIR}/fpgautil.c;beginline=1;endline=24;md5=8010e59a286b1e3a73a9fdd93bd18778" +LIC_FILES_CHKSUM = "file://${WORKDIR}/fpgautil.c;beginline=1;endline=24;md5=0c02eabf57dba52842c5df9b96bccfae" SRC_URI = "\ file://fpgautil.c \ -- cgit v1.2.3-54-g00ecf From 821bd8608ba88fff83846ae230394f5918e42c58 Mon Sep 17 00:00:00 2001 From: Ramya Darapuneni Date: Tue, 6 Sep 2022 10:47:09 -0600 Subject: Update to bootgen SRCREV to point to latest commit. Signed-off-by: Mark Hatle Signed-off-by: Sandeep Gundlupet Raju --- meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb index 85880158..f80e1feb 100644 --- a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb @@ -11,7 +11,7 @@ RDEPENDS:${PN} += "openssl" REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" BRANCH ?= "master" -SRCREV = "4eac958eb6c831ffa5768a0e2cd4be23c5efe2e0" +SRCREV = "d890ba298685b73307a01a9dbcc8702f9afcdbcc" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -- cgit v1.2.3-54-g00ecf From 6bcece6b076713597a00730df1457dfee6719853 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 6 Sep 2022 10:47:10 -0600 Subject: arm-trusted-firmware: Enable versal-net platform Signed-off-by: Mark Hatle Signed-off-by: Sandeep Gundlupet Raju --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 4b076444..a45b5ce5 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -36,6 +36,7 @@ PACKAGE_ARCH = "${MACHINE_ARCH}" PLATFORM:zynqmp = "zynqmp" PLATFORM:versal = "versal" +PLATFORM:versal-net = "versal_net" # requires CROSS_COMPILE set by hand as there is no configure script export CROSS_COMPILE="${TARGET_PREFIX}" @@ -55,6 +56,7 @@ DEBUG_ATF:versal ?= "1" EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" +EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}" OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" @@ -68,6 +70,9 @@ EXTRA_OEMAKE:append:zynqmp = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.get EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" +EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" +EXTRA_OEMAKE:append:versal-net = "${@' VERSAL_NET_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" + ATF_PROVENCORE = "SPD=pncd SPD_PNCD_NS_IRQ=51 ZYNQMP_BL32_MEM_BASE=0x70000000 ZYNQMP_BL32_MEM_SIZE=0x0FF00000" EXTRA_OEMAKE:append = "${@bb.utils.contains('MACHINE_FEATURES', 'provencore', ' ${ATF_PROVENCORE}', '', d)}" -- cgit v1.2.3-54-g00ecf From 24eb976bb5970b5bb59476d973dd4f75183f636b Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Tue, 6 Sep 2022 10:47:11 -0600 Subject: linux-xlnx: Enable versal-net platform Signed-off-by: Mark Hatle Signed-off-by: Sandeep Gundlupet Raju --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc index adefabea..08755b26 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc @@ -53,6 +53,7 @@ KBUILD_DEFCONFIG:zynqmp ?= "xilinx_defconfig" KBUILD_DEFCONFIG:zynq ?= "xilinx_zynq_defconfig" KBUILD_DEFCONFIG:microblaze ?= "mmu_defconfig" KBUILD_DEFCONFIG:versal ?= "xilinx_defconfig" +KBUILD_DEFCONFIG:versal-net ?= "xilinx_versal_net_defconfig" KERNEL_FEATURES:append:zynqmp = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)}" -- cgit v1.2.3-54-g00ecf From bd3fadca6140cb3d01250f92382e336bd6034c3f Mon Sep 17 00:00:00 2001 From: rbramand Date: Tue, 6 Sep 2022 22:52:17 -0600 Subject: xrt_git:zocl_git:update commitid Signed-off-by: rbramand Signed-off-by: Sandeep Gundlupet Raju --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 51455162..ba42fd5f 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,8 +3,6 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "6af05b317093d0c38184322585ac21617f4789c5" +SRCREV= "910828b3abdbf66b10cb6efc952e75df64962340" PV = "202220.2.14.0" - - -- cgit v1.2.3-54-g00ecf From 0cd10ebe181b39a14765b734c98e8457b510d7cb Mon Sep 17 00:00:00 2001 From: Siva Addepalli Date: Wed, 7 Sep 2022 06:44:31 -0600 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc | 2 +- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb index b58fbd96..46bfd5b9 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.2.bb @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2021.01" UBRANCH ?= "master" -SRCREV = "3411b335bb7a0717da34bb4358c8d57f87deefab" +SRCREV = "f2402773e2d82aafc08ac39c03f3bc430c014703" include u-boot-xlnx.inc include u-boot-spl-zynq-init.inc diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb index 5c5ae787..c7719866 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.2.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "f165edfcf3618f936e46127199f69ff2cb4090d1" +SRCREV ?= "42d0b7e24fbd1adc72fb2d0e70e06ff332278468" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 60bc2ff3..555f18f9 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -12,7 +12,7 @@ DEPENDS = "glib-2.0 zlib pixman bison-native ninja-native meson-native" XILINX_QEMU_VERSION ?= "v6.1.0" BRANCH ?= "master" -SRCREV = "de92de0a3cef8affbf256d8930817bf8765cce21" +SRCREV = "fbcb55665e9f5f91110ba2a44f62be9bc72752ee" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index a2c36f5a..8acc0547 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "64992c116e5ab0b7f31c96e8719a36e7da3a0ba2" +SRCREV = "1bec24d4465c2688299941234444875e3e7581c1" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d0097f62..b831783d 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "4c7ada679c0f7793966a51fd8edee4f90462d5d9" +ESW_REV[2022.2] = "3b9ed39c078a7b669db6dbea7ee826656a036246" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 101db563d83f9029c3ee43745b56520ca29d5a6d Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 8 Sep 2022 18:07:30 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index 8acc0547..e86d28f5 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "1bec24d4465c2688299941234444875e3e7581c1" +SRCREV = "40f939ae6c5c279a8f6a2d5ae83feeae556460ef" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index b831783d..5e2dd8ae 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "3b9ed39c078a7b669db6dbea7ee826656a036246" +ESW_REV[2022.2] = "bc810efa60b305b9ebfbd9b56098036ed26326d0" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From 0fa723086b00f772ed235de087faa0425ffbf9f6 Mon Sep 17 00:00:00 2001 From: Raju Kumar Pothuraju Date: Thu, 8 Sep 2022 08:06:25 -0600 Subject: device-tree: Update versal-net dts file Use versal-net-ipp-rev1.9.dtsi as DT board file for versal-net. Signed-off-by: Raju Kumar Pothuraju Signed-off-by: Sandeep Gundlupet Raju --- .../meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index a3dedd85..151bd0e0 100644 --- a/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-core/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -14,5 +14,5 @@ YAML_DT_BOARD_FLAGS:zynqmp-generic ?= "{BOARD zcu102-rev1.0}" # versal-generic.conf file uses HDF_MACHINE = "vck190-versal", Hence set versal-vck190-reva-x-ebm-01-reva dtsi file. YAML_DT_BOARD_FLAGS:versal-generic ?= "{BOARD versal-vck190-reva-x-ebm-01-reva}" -# versal-net-generic.conf uses HDF_MACHINE = "versal-net-generic", Hence set versal-net-ipp-rev1.5 dtsi file. -YAML_DT_BOARD_FLAGS:versal-net-generic ?= "{BOARD versal-net-ipp-rev1.5}" +# versal-net-generic.conf uses HDF_MACHINE = "versal-net-generic", Hence set versal-net-ipp-rev1.9 dtsi file. +YAML_DT_BOARD_FLAGS:versal-net-generic ?= "{BOARD versal-net-ipp-rev1.9}" -- cgit v1.2.3-54-g00ecf From a4e0d6fe62e9a33a02e521f6d549a6e9dc307506 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 12 Sep 2022 13:12:01 +0530 Subject: Updated SRCREV for 2022.2 Signed-off-by: Siva Addepalli --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb | 2 +- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb index e86d28f5..3551fb8b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.2.bb @@ -1,6 +1,6 @@ LINUX_VERSION = "5.15.36" KBRANCH="xlnx_rebase_v5.15_LTS" -SRCREV = "40f939ae6c5c279a8f6a2d5ae83feeae556460ef" +SRCREV = "2ddbacde6539be25b5717af5705a0d0009d6b2d3" KCONF_AUDIT_LEVEL="0" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 5e2dd8ae..820b209f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -21,7 +21,7 @@ ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" -ESW_REV[2022.2] = "bc810efa60b305b9ebfbd9b56098036ed26326d0" +ESW_REV[2022.2] = "72f6e3d45fb4dd9d6cd4a7581b935b39cf8ce96d" ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" -- cgit v1.2.3-54-g00ecf From de61f42d18dd61af1278f549ade595049243c1ed Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:02:00 -0700 Subject: vcu: Version vcu components Only the SRCREV and BRANCH is different between version Signed-off-by: Mark Hatle --- .../recipes-multimedia/vcu/kernel-module-vcu.bb | 40 ----------------- .../vcu/kernel-module-vcu_2022.1.bb | 40 +++++++++++++++++ .../vcu/kernel-module-vcu_2022.2.bb | 40 +++++++++++++++++ .../recipes-multimedia/vcu/libomxil-xlnx.bb | 50 ---------------------- .../recipes-multimedia/vcu/libomxil-xlnx_2022.1.bb | 50 ++++++++++++++++++++++ .../recipes-multimedia/vcu/libomxil-xlnx_2022.2.bb | 50 ++++++++++++++++++++++ .../recipes-multimedia/vcu/libvcu-xlnx.bb | 42 ------------------ .../recipes-multimedia/vcu/libvcu-xlnx_2022.1.bb | 42 ++++++++++++++++++ .../recipes-multimedia/vcu/libvcu-xlnx_2022.2.bb | 42 ++++++++++++++++++ .../recipes-multimedia/vcu/vcu-firmware.bb | 39 ----------------- .../recipes-multimedia/vcu/vcu-firmware_2022.1.bb | 39 +++++++++++++++++ .../recipes-multimedia/vcu/vcu-firmware_2022.2.bb | 39 +++++++++++++++++ 12 files changed, 342 insertions(+), 171 deletions(-) delete mode 100644 meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.1.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.1.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.1.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.2.bb delete mode 100644 meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.1.bb create mode 100644 meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.2.bb diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb deleted file mode 100644 index 505b54db..00000000 --- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb +++ /dev/null @@ -1,40 +0,0 @@ -SUMMARY = "Linux kernel module for Video Code Unit" -DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices" -SECTION = "kernel/modules" -LICENSE = "GPLv2" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -S = "${WORKDIR}/git" - -FILESEXTRAPATHS:prepend := "${THISDIR}/files:" - -BRANCH = "master" -REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" -SRCREV = "9d2657550eccebccce08cacfcdd369367b9f6be4" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = " \ - ${REPO};${BRANCHARG} \ - file://99-vcu-enc-dec.rules \ - " - -inherit module - -EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" - -RDEPENDS:${PN} = "vcu-firmware" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE:zynqmp = "zynqmp" - -KERNEL_MODULE_AUTOLOAD += "dmaproxy" - -do_install:append() { - install -d ${D}${sysconfdir}/udev/rules.d - install -m 0644 ${WORKDIR}/99-vcu-enc-dec.rules ${D}${sysconfdir}/udev/rules.d/ -} - -FILES:${PN} = "${sysconfdir}/udev/rules.d/*" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.1.bb new file mode 100644 index 00000000..77f00534 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.1.bb @@ -0,0 +1,40 @@ +SUMMARY = "Linux kernel module for Video Code Unit" +DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices" +SECTION = "kernel/modules" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +S = "${WORKDIR}/git" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +BRANCH = "xlnx_rel_v2022.1" +REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" +SRCREV = "9d2657550eccebccce08cacfcdd369367b9f6be4" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = " \ + ${REPO};${BRANCHARG} \ + file://99-vcu-enc-dec.rules \ + " + +inherit module + +EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" + +RDEPENDS:${PN} = "vcu-firmware" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +KERNEL_MODULE_AUTOLOAD += "dmaproxy" + +do_install:append() { + install -d ${D}${sysconfdir}/udev/rules.d + install -m 0644 ${WORKDIR}/99-vcu-enc-dec.rules ${D}${sysconfdir}/udev/rules.d/ +} + +FILES:${PN} = "${sysconfdir}/udev/rules.d/*" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.2.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.2.bb new file mode 100644 index 00000000..77f00534 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2022.2.bb @@ -0,0 +1,40 @@ +SUMMARY = "Linux kernel module for Video Code Unit" +DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices" +SECTION = "kernel/modules" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +S = "${WORKDIR}/git" + +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +BRANCH = "xlnx_rel_v2022.1" +REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" +SRCREV = "9d2657550eccebccce08cacfcdd369367b9f6be4" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = " \ + ${REPO};${BRANCHARG} \ + file://99-vcu-enc-dec.rules \ + " + +inherit module + +EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" + +RDEPENDS:${PN} = "vcu-firmware" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +KERNEL_MODULE_AUTOLOAD += "dmaproxy" + +do_install:append() { + install -d ${D}${sysconfdir}/udev/rules.d + install -m 0644 ${WORKDIR}/99-vcu-enc-dec.rules ${D}${sysconfdir}/udev/rules.d/ +} + +FILES:${PN} = "${sysconfdir}/udev/rules.d/*" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb deleted file mode 100644 index dbe52de9..00000000 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb +++ /dev/null @@ -1,50 +0,0 @@ -SUMMARY = "OpenMAX Integration layer for VCU" -DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -BRANCH ?= "master" -REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" -SRCREV = "6752f5da88a8783f689ae762065295b89902d6d4" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -S = "${WORKDIR}/git" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE:zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -DEPENDS = "libvcu-xlnx" -RDEPENDS:${PN} = "kernel-module-vcu libvcu-xlnx" - -EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include" - -EXTRA_OEMAKE = " \ - CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \ - EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \ - " - -do_install() { - install -d ${D}${libdir} - install -d ${D}${includedir}/vcu-omx-il - - install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il - - install -Dm 0755 ${S}/bin/omx_decoder ${D}/${bindir}/omx_decoder - install -Dm 0755 ${S}/bin/omx_encoder ${D}/${bindir}/omx_encoder - - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/ -} - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. - -EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.1.bb new file mode 100644 index 00000000..b4460a38 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.1.bb @@ -0,0 +1,50 @@ +SUMMARY = "OpenMAX Integration layer for VCU" +DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" +SRCREV = "b3308c608be7ed9250b9c6732f6e0a02b1a2e985" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +S = "${WORKDIR}/git" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +DEPENDS = "libvcu-xlnx" +RDEPENDS:${PN} = "kernel-module-vcu libvcu-xlnx" + +EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include" + +EXTRA_OEMAKE = " \ + CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \ + EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \ + " + +do_install() { + install -d ${D}${libdir} + install -d ${D}${includedir}/vcu-omx-il + + install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il + + install -Dm 0755 ${S}/bin/omx_decoder ${D}/${bindir}/omx_decoder + install -Dm 0755 ${S}/bin/omx_encoder ${D}/${bindir}/omx_encoder + + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/ +} + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. + +EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.2.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.2.bb new file mode 100644 index 00000000..b4460a38 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2022.2.bb @@ -0,0 +1,50 @@ +SUMMARY = "OpenMAX Integration layer for VCU" +DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" +SRCREV = "b3308c608be7ed9250b9c6732f6e0a02b1a2e985" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +S = "${WORKDIR}/git" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +DEPENDS = "libvcu-xlnx" +RDEPENDS:${PN} = "kernel-module-vcu libvcu-xlnx" + +EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include" + +EXTRA_OEMAKE = " \ + CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \ + EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \ + " + +do_install() { + install -d ${D}${libdir} + install -d ${D}${includedir}/vcu-omx-il + + install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il + + install -Dm 0755 ${S}/bin/omx_decoder ${D}/${bindir}/omx_decoder + install -Dm 0755 ${S}/bin/omx_encoder ${D}/${bindir}/omx_encoder + + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/ +} + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. + +EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb deleted file mode 100644 index 5f2dea6e..00000000 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb +++ /dev/null @@ -1,42 +0,0 @@ -SUMMARY = "Control Software for VCU" -DESCRIPTION = "Control software libraries, test applications and headers provider for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -BRANCH ?= "master" -REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV = "9956b4a1229fc667e2a71164fc21e0b2a1aab4de" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -S = "${WORKDIR}/git" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE:zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -RDEPENDS:${PN} = "kernel-module-vcu" - -EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'" - -do_install() { - install -d ${D}${libdir} - install -d ${D}${includedir}/vcu-ctrl-sw/include - - install -Dm 0755 ${S}/bin/ctrlsw_encoder ${D}/${bindir}/ctrlsw_encoder - install -Dm 0755 ${S}/bin/ctrlsw_decoder ${D}/${bindir}/ctrlsw_decoder - - oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include - oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/ - oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/ -} - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. - -EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.1.bb new file mode 100644 index 00000000..91f15cc2 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.1.bb @@ -0,0 +1,42 @@ +SUMMARY = "Control Software for VCU" +DESCRIPTION = "Control software libraries, test applications and headers provider for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" +SRCREV = "5bf158af204b181f00ac009c8745557642ecfe5f" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +S = "${WORKDIR}/git" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +RDEPENDS:${PN} = "kernel-module-vcu" + +EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'" + +do_install() { + install -d ${D}${libdir} + install -d ${D}${includedir}/vcu-ctrl-sw/include + + install -Dm 0755 ${S}/bin/ctrlsw_encoder ${D}/${bindir}/ctrlsw_encoder + install -Dm 0755 ${S}/bin/ctrlsw_decoder ${D}/${bindir}/ctrlsw_decoder + + oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include + oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/ +} + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. + +EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.2.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.2.bb new file mode 100644 index 00000000..91f15cc2 --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2022.2.bb @@ -0,0 +1,42 @@ +SUMMARY = "Control Software for VCU" +DESCRIPTION = "Control software libraries, test applications and headers provider for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" +SRCREV = "5bf158af204b181f00ac009c8745557642ecfe5f" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +S = "${WORKDIR}/git" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +RDEPENDS:${PN} = "kernel-module-vcu" + +EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'" + +do_install() { + install -d ${D}${libdir} + install -d ${D}${includedir}/vcu-ctrl-sw/include + + install -Dm 0755 ${S}/bin/ctrlsw_encoder ${D}/${bindir}/ctrlsw_encoder + install -Dm 0755 ${S}/bin/ctrlsw_decoder ${D}/${bindir}/ctrlsw_decoder + + oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include + oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/ + oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/ +} + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. + +EXCLUDE_FROM_WORLD = "1" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb deleted file mode 100644 index 930cf0d8..00000000 --- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb +++ /dev/null @@ -1,39 +0,0 @@ -SUMMARY = "Firmware for VCU" -DESCRIPTION = "Firmware binaries provider for VCU" -LICENSE = "Proprietary" -LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" - -XILINX_VCU_VERSION = "1.0.0" -PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" - -S = "${WORKDIR}/git" - -BRANCH ?= "xlnx_rel_v2022.1" -REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" -SRCREV = "3980c778d71fa51a15e89bf70fd8fb28d5cb12e0" - -BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -SRC_URI = "${REPO};${BRANCHARG}" - -COMPATIBLE_MACHINE = "^$" -COMPATIBLE_MACHINE:zynqmp = "zynqmp" - -PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" - -do_install() { - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw - install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw -} - -# Inhibit warnings about files being stripped -INHIBIT_PACKAGE_DEBUG_SPLIT = "1" -INHIBIT_PACKAGE_STRIP = "1" -FILES:${PN} = "/lib/firmware/*" - -# These libraries shouldn't get installed in world builds unless something -# explicitly depends upon them. -EXCLUDE_FROM_WORLD = "1" - -INSANE_SKIP:${PN} = "ldflags" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.1.bb new file mode 100644 index 00000000..fc9f34ca --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.1.bb @@ -0,0 +1,39 @@ +SUMMARY = "Firmware for VCU" +DESCRIPTION = "Firmware binaries provider for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +S = "${WORKDIR}/git" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" +SRCREV = "569f980527fd58f43baf16bd0b294bf8c7cdf963" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +do_install() { + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw +} + +# Inhibit warnings about files being stripped +INHIBIT_PACKAGE_DEBUG_SPLIT = "1" +INHIBIT_PACKAGE_STRIP = "1" +FILES:${PN} = "/lib/firmware/*" + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. +EXCLUDE_FROM_WORLD = "1" + +INSANE_SKIP:${PN} = "ldflags" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.2.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.2.bb new file mode 100644 index 00000000..fc9f34ca --- /dev/null +++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2022.2.bb @@ -0,0 +1,39 @@ +SUMMARY = "Firmware for VCU" +DESCRIPTION = "Firmware binaries provider for VCU" +LICENSE = "Proprietary" +LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" + +XILINX_VCU_VERSION = "1.0.0" +PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" + +S = "${WORKDIR}/git" + +BRANCH ?= "xlnx_rel_v2022.1" +REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" +SRCREV = "569f980527fd58f43baf16bd0b294bf8c7cdf963" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE:zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" + +do_install() { + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw + install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw +} + +# Inhibit warnings about files being stripped +INHIBIT_PACKAGE_DEBUG_SPLIT = "1" +INHIBIT_PACKAGE_STRIP = "1" +FILES:${PN} = "/lib/firmware/*" + +# These libraries shouldn't get installed in world builds unless something +# explicitly depends upon them. +EXCLUDE_FROM_WORLD = "1" + +INSANE_SKIP:${PN} = "ldflags" -- cgit v1.2.3-54-g00ecf From 1243552796558a00b4f0d7ed9c9c3d41d7031a7a Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:04:57 -0700 Subject: xlnx-embeddedsw: Cleanup and remove old versions, no longer supported Signed-off-by: Mark Hatle --- .../classes/xlnx-embeddedsw.bbclass | 22 ---------------------- .../recipes-bsp/embeddedsw/fsbl-firmware_2021.2.bb | 11 ----------- .../recipes-bsp/embeddedsw/plm-firmware_2020.1.bb | 1 - .../recipes-bsp/embeddedsw/plm-firmware_2021.2.bb | 16 ---------------- .../recipes-bsp/embeddedsw/pmu-firmware_2020.1.bb | 9 --------- .../recipes-bsp/embeddedsw/pmu-firmware_2021.2.bb | 16 ---------------- .../recipes-bsp/embeddedsw/psm-firmware_2021.2.bb | 16 ---------------- 7 files changed, 91 deletions(-) delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2021.2.bb delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2020.1.bb delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2021.2.bb delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2020.1.bb delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2021.2.bb delete mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2021.2.bb diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 5dc2cc18..403369b1 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -3,43 +3,21 @@ ESW_VER ?= "${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or 'master' REPO ??= "git://github.com/Xilinx/embeddedsw.git;protocol=https" -ESW_BRANCH[2019.1] = "release-2019.1" -ESW_BRANCH[2019.2] = "release-2019.2" -ESW_BRANCH[2020.1] = "release-2020.1" -ESW_BRANCH[2020.2] = "master-rel-2020.2" -ESW_BRANCH[2021.1] = "xlnx_rel_v2021.1" -ESW_BRANCH[2021.2] = "xlnx_rel_v2021.2" ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1_update" ESW_BRANCH[2022.2] = "xlnx_rel_v2022.2-next" -ESW_BRANCH[git] = "master-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" -ESW_REV[2019.1] = "26c14d9861010a0e3a55c73fb79efdb816eb42ca" -ESW_REV[2019.2] = "e8db5fb118229fdc621e0ec7848641a23bf60998" -ESW_REV[2020.1] = "338150ab3628a1ea6b06e964b16e712b131882dd" -ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" -ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" -ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" ESW_REV[2022.1] = "0cfb554e841f0837cabbb40a2481f5f7e5f2ddc0" ESW_REV[2022.2] = "72f6e3d45fb4dd9d6cd4a7581b935b39cf8ce96d" -ESW_REV[git] = "7ec60e1c0e25bfa9c5e8c77d6d063876f6670770" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" EMBEDDEDSW_SRCURI ?= "${REPO};${EMBEDDEDSW_BRANCHARG}" LICENSE = "MIT" -LIC_FILES_CHKSUM[release-2019.1] = 'e9b6d01d45faccfbf05d8caea53f0a35' -LIC_FILES_CHKSUM[release-2019.2] = '39ab6ab638f4d1836ba994ec6852de94' -LIC_FILES_CHKSUM[release-2020.1] = '8b565227e1264d677db8f841c2948cba' -LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' -LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" -LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM[xlnx_rel_v2022.1_update] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM[xlnx_rel_v2022.2-next] = '7b5fc0b2a22e2882e1506436b3293e5d' -LIC_FILES_CHKSUM[master-next] = '7b5fc0b2a22e2882e1506436b3293e5d' -LIC_FILES_CHKSUM[master] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2021.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2021.2.bb deleted file mode 100644 index 3f9740a0..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2021.2.bb +++ /dev/null @@ -1,11 +0,0 @@ -require fsbl-firmware.inc - -FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" - -SRC_URI += " \ - file://makefile-skip-copy_bsp.sh.patch \ - file://fsbl-fixups.patch \ - " - -# This version does not build for zynq -COMPATIBLE_MACHINE:zynq = "none" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2020.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2020.1.bb deleted file mode 100644 index 782c9dc4..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2020.1.bb +++ /dev/null @@ -1 +0,0 @@ -require plm-firmware.inc diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2021.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2021.2.bb deleted file mode 100644 index cc810241..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2021.2.bb +++ /dev/null @@ -1,16 +0,0 @@ -require plm-firmware.inc - -FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" - -SRC_URI += " \ - file://makefile-skip-copy_bsp.sh.patch \ - file://0001-versal_fw-Fixup-core-makefiles.patch \ - " - -EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" - -do_compile() { - oe_runmake - - ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin -} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2020.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2020.1.bb deleted file mode 100644 index 6b90f496..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2020.1.bb +++ /dev/null @@ -1,9 +0,0 @@ -require pmu-firmware.inc - -FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" - -SRC_URI += " \ - file://0001-zynqmp_pmufw-Fix-reset-ops-for-assert.patch \ - file://0001-zynqmp_pmufw-Correct-structure-header-of-PmResetOps.patch \ - " - diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2021.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2021.2.bb deleted file mode 100644 index 2c554d6d..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2021.2.bb +++ /dev/null @@ -1,16 +0,0 @@ -require pmu-firmware.inc - -FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" - -SRC_URI += " \ - file://makefile-skip-copy_bsp.sh.patch \ - file://0001-zynqmp_pmufw-Fixup-core-makefiles.patch \ - " - -EXTRA_COMPILER_FLAGS = "-ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" - -do_compile() { - oe_runmake - - ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin -} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2021.2.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2021.2.bb deleted file mode 100644 index d861fb1c..00000000 --- a/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2021.2.bb +++ /dev/null @@ -1,16 +0,0 @@ -require psm-firmware.inc - -FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" - -SRC_URI += " \ - file://makefile-skip-copy_bsp.sh.patch \ - file://0001-versal_fw-Fixup-core-makefiles.patch \ - " - -EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra" - -do_compile() { - oe_runmake - - ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin -} -- cgit v1.2.3-54-g00ecf From 359451278d48e4c3149bd026b978d29e77a25592 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:06:18 -0700 Subject: qemu-devicetrees: Restore 2022.1 version This was accidently broken as part of the 2022.2 merge, restore original behavior Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb index e2f134fe..7c734cd6 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2022.1.bb @@ -3,3 +3,6 @@ require qemu-devicetrees.inc BRANCH ?= "xlnx_rel_v2022.1" SRCREV ?= "0499324af1178057c3730b0989c8fb5c5bbc4cf8" + +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" +SRC_URI:append = " file://0001-Makefile-Use-python3-instead-of-python.patch" -- cgit v1.2.3-54-g00ecf From c350c58a84391ed52a370010b2edf9853d67cf64 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:07:09 -0700 Subject: qemu-*: Use recipe version in the extended PV Signed-off-by: Mark Hatle --- .../recipes-devtools/qemu/qemu-devicetrees.inc | 2 +- ...01-Makefile-Use-python3-instead-of-python.patch | 37 ++++++++++++++++++++++ .../recipes-devtools/qemu/qemu-xilinx.inc | 2 +- 3 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc index 9ee8174a..3be623ac 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc @@ -7,7 +7,7 @@ inherit deploy LIC_FILES_CHKSUM = "file://Makefile;beginline=1;endline=27;md5=7348b6cbcae69912cb1dee68d6c68d99" -PV = "xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" +PV = "xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch new file mode 100644 index 00000000..425145d0 --- /dev/null +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch @@ -0,0 +1,37 @@ +From e80324e3497e5768c9fdbde3c0660a03d0dcc3ee Mon Sep 17 00:00:00 2001 +From: Sai Hari Chandana Kalluri +Date: Mon, 8 Feb 2021 16:32:34 -0800 +Subject: [PATCH] Makefile:Use python3 instead of python + +Signed-off-by: Sai Hari Chandana Kalluri +--- + Makefile | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/Makefile b/Makefile +index a110483..fd8868c 100644 +--- a/Makefile ++++ b/Makefile +@@ -91,13 +91,13 @@ $(LQSPI_XIP_OUTDIR)/%.dts: %.dts $(DTSI_FILES) $(HEADER_FILES) + # TODO: Add support for auto-generated dependency list + versal-pmc-npi.dtsi: versal-pmc-npi-nxx.dtsi versal-h10-pmc-npi-nxx.dtsi + versal-pmc-npi-nxx.dtsi: Makefile +- @python -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ +- @python -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ +- @python -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ ++ @python3 -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@ ++ @python3 -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@ ++ @python3 -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@ + versal-h10-pmc-npi-nxx.dtsi: Makefile +- @python -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@ +- @python -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@ +- @python -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@ ++ @python3 -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@ ++ @python3 -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@ ++ @python3 -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@ + + clean: + $(RM) versal-pmc-npi-nxx.dtsi +-- +2.7.4 + diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc index 555f18f9..a5557959 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc @@ -16,7 +16,7 @@ SRCREV = "fbcb55665e9f5f91110ba2a44f62be9bc72752ee" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" +PV = "${XILINX_QEMU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" REPO ?= "gitsm://github.com/Xilinx/qemu.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" -- cgit v1.2.3-54-g00ecf From e859586f3432f9ef5f4c2930cd2821a0075868e8 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:08:02 -0700 Subject: various: Use recipe version instead of XILINX_RELEASE_VERSION in PV Signed-off-by: Mark Hatle --- .../recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 3 +-- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc | 4 ++-- meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc | 5 ++--- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index a45b5ce5..bbbeb507 100644 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -14,9 +14,8 @@ B = "${WORKDIR}/build" SYSROOT_DIRS += "/boot" -XILINX_RELEASE_VERSION ?= "" ATF_VERSION ?= "2.2" -ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" +ATF_VERSION_EXTENSION ?= "-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}" PV = "${ATF_VERSION}${ATF_VERSION_EXTENSION}+git${SRCPV}" BRANCH ?= "" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc index 5a9a0868..8971d58f 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc @@ -2,8 +2,8 @@ require recipes-bsp/u-boot/u-boot.inc DEPENDS += "bc-native dtc-native bison-native xxd-native" -XILINX_RELEASE_VERSION ?= "" -UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" +# Use the name of the .bb for the extension +UBOOT_VERSION_EXTENSION ?= "-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}" PV = "${UBOOT_VERSION}${UBOOT_VERSION_EXTENSION}+git${SRCPV}" UBOOTURI ?= "git://github.com/Xilinx/u-boot-xlnx.git;protocol=https" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc index 08755b26..2edebe8e 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc @@ -1,13 +1,12 @@ # This version extension should match CONFIG_LOCALVERSION in defconfig -XILINX_RELEASE_VERSION ?= "" -LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" +LINUX_VERSION_EXTENSION ?= "-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}" PV = "${LINUX_VERSION}+git${SRCPV}" # Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits KBRANCH ?= "xlnx_rebase_v5.15_LTS" SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}" -FILESOVERRIDES:append = ":${XILINX_RELEASE_VERSION}" +FILESOVERRIDES:append := ":${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}" KERNELURI ?= "git://github.com/Xilinx/linux-xlnx.git;protocol=https;name=machine" YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.15;destsuffix=yocto-kmeta" SRC_URI = "${KERNELURI};${SRCBRANCHARG} ${YOCTO_META}" -- cgit v1.2.3-54-g00ecf From fb44a4e29a40c2653735358da4668c6ae2736fab Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 12 Sep 2022 17:14:45 -0700 Subject: User can now set XILINX_RELEASE_VERSION to either 'v2022.1' or 'v2022.2' This will in-turn select the preferred version for various components to match a given release. It is advise that the user use the latest version whenever possible, but if they are stuck on an older version of Vivado they may need to select the older release. Signed-off-by: Mark Hatle --- meta-xilinx-bsp/conf/layer.conf | 2 ++ meta-xilinx-contrib/conf/layer.conf | 2 -- meta-xilinx-core/conf/layer.conf | 13 ++++++++++++- meta-xilinx-core/conf/local.conf.sample | 2 +- meta-xilinx-standalone/conf/layer.conf | 7 ++++++- 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/meta-xilinx-bsp/conf/layer.conf b/meta-xilinx-bsp/conf/layer.conf index b5bb3b19..ef9e1a1d 100644 --- a/meta-xilinx-bsp/conf/layer.conf +++ b/meta-xilinx-bsp/conf/layer.conf @@ -17,3 +17,5 @@ BBFILE_PRIORITY_xilinx-bsp = "5" LAYERDEPENDS_xilinx-bsp = "xilinx" LAYERSERIES_COMPAT_xilinx-bsp = "honister" + +PREFERRED_VERSION_kc705-bitstream ?= "${XILINX_RELEASE_VERSION}" diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf index 253d64d1..4b813365 100644 --- a/meta-xilinx-contrib/conf/layer.conf +++ b/meta-xilinx-contrib/conf/layer.conf @@ -13,5 +13,3 @@ LAYERDEPENDS_xilinx-contrib = "core" LAYERDEPENDS_xilinx-contrib = "xilinx" LAYERSERIES_COMPAT_xilinx-contrib = "honister" - -XILINX_RELEASE_VERSION = "v2022.2" diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf index bdf14ee9..9090abe6 100644 --- a/meta-xilinx-core/conf/layer.conf +++ b/meta-xilinx-core/conf/layer.conf @@ -44,4 +44,15 @@ SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS += " \ *->xserver-xorg \ " -XILINX_RELEASE_VERSION = "v2022.2" +XILINX_RELEASE_VERSION ??= "v2022.2" + +BUILDCFG_VARS:append = " XILINX_RELEASE_VERSION" + +PREFERRED_VERSION_qemu-xilinx ?= "v6.1.0-xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_qemu-xilinx-native ?= "v6.1.0-xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_qemu-xilinx-system-native ?= "v6.1.0-xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_qemu-devicetrees ?= "xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_arm-trusted-firmware ?= "2.6-xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_u-boot-xlnx ?= "v2021.01-xilinx-${XILINX_RELEASE_VERSION}%" +PREFERRED_VERSION_pmu-rom-native ?= "${@d.getVar("XILINX_RELEASE_VERSION").replace('v','')}" +PREFERRED_VERSION_linux-xlnx ?= "${@'5.15.19' if d.getVar("XILINX_RELEASE_VERSION") == 'v2022.1' else '5.15.36'}%" diff --git a/meta-xilinx-core/conf/local.conf.sample b/meta-xilinx-core/conf/local.conf.sample index b907b072..10134d53 100644 --- a/meta-xilinx-core/conf/local.conf.sample +++ b/meta-xilinx-core/conf/local.conf.sample @@ -206,7 +206,7 @@ BB_DISKMON_DIRS ??= "\ #file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \ #file://.* file:///some/local/dir/sstate/PATH" -XILINX_VER_MAIN = "2022.2" +XILINX_RELEASE_VERSION = "v2022.2" # Uncomment below lines to provide path for custom xsct trim # diff --git a/meta-xilinx-standalone/conf/layer.conf b/meta-xilinx-standalone/conf/layer.conf index 79997d24..492dda6f 100644 --- a/meta-xilinx-standalone/conf/layer.conf +++ b/meta-xilinx-standalone/conf/layer.conf @@ -16,4 +16,9 @@ LAYERDEPENDS_xilinx-standalone = "core xilinx" LAYERRECOMMENDS_xilinx-standalone = "xilinx-microblaze" LAYERSERIES_COMPAT_xilinx-standalone = "honister" -XILINX_RELEASE_VERSION = "v2022.2" + +PREFERRED_VERSION_plm-firmware ?= "${@d.getVar("XILINX_RELEASE_VERSION").replace('v','')}%" +PREFERRED_VERSION_psm-firmware ?= "${@d.getVar("XILINX_RELEASE_VERSION").replace('v','')}%" +PREFERRED_VERSION_pmu-firmware ?= "${@d.getVar("XILINX_RELEASE_VERSION").replace('v','')}%" +PREFERRED_VERSION_fsbl-firmware ?= "${@d.getVar("XILINX_RELEASE_VERSION").replace('v','')}%" + -- cgit v1.2.3-54-g00ecf