From 4bd51b2617fe6e62901ec6804b56dde004fba583 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Mon, 2 May 2022 18:01:14 -0500 Subject: Move from 2021.2 to 2022.1 Rename recipes from 2021.2 to 2022.1 as necessary. Move internal references to 2022.1 (layer.conf and local.conf.sample) Move kernel to 2022.1 branch, as well as various kernel modules. Signed-off-by: Mark Hatle --- .../reference-design/kc705-bitstream_2022.1.bb | 48 ++ .../reference-design/kc705-bitstream_2021.2.bb | 48 -- meta-xilinx-contrib/conf/layer.conf | 2 +- ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 305 ----------- ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 --------------------- ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 -- .../v2021.2/0004-minized-wifi-bluetooth.cfg | 33 -- ...rm-xilinx-Add-encoder-for-Digilent-boards.patch | 305 +++++++++++ ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | 607 +++++++++++++++++++++ ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | 54 ++ .../v2022.1/0004-minized-wifi-bluetooth.cfg | 33 ++ .../linux/linux-xlnx_2021.2.bbappend | 9 - .../linux/linux-xlnx_2022.1.bbappend | 9 + meta-xilinx-core/conf/local.conf.sample | 4 +- .../arm-trusted-firmware_2021.2.bb | 8 - .../arm-trusted-firmware_2022.1.bb | 8 + .../recipes-bsp/bootgen/bootgen_1.0.bb | 4 +- .../recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb | 19 - .../recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb | 19 + .../recipes-graphics/libgles/libmali-xlnx.bb | 2 +- .../recipes-kernel/dp/kernel-module-dp_git.bb | 6 +- .../recipes-kernel/hdmi/kernel-module-hdmi_git.bb | 6 +- .../recipes-kernel/linux/linux-xlnx-dev.bb | 2 +- .../recipes-kernel/linux/linux-xlnx.inc | 6 +- .../recipes-kernel/linux/linux-xlnx_2021.2.bb | 9 - .../recipes-kernel/linux/linux-xlnx_2022.1.bb | 9 + .../recipes-multimedia/vcu/kernel-module-vcu.bb | 4 +- .../recipes-multimedia/vcu/libomxil-xlnx.bb | 4 +- .../recipes-multimedia/vcu/libvcu-xlnx.bb | 4 +- .../recipes-multimedia/vcu/vcu-firmware.bb | 4 +- .../classes/xlnx-embeddedsw.bbclass | 8 +- meta-xilinx-standalone/conf/layer.conf | 2 +- .../recipes-bsp/embeddedsw/fsbl-firmware_2022.1.bb | 11 + .../recipes-bsp/embeddedsw/plm-firmware_2022.1.bb | 16 + .../recipes-bsp/embeddedsw/pmu-firmware_2022.1.bb | 16 + .../recipes-bsp/embeddedsw/psm-firmware_2022.1.bb | 16 + 36 files changed, 1181 insertions(+), 1120 deletions(-) create mode 100644 meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb delete mode 100644 meta-xilinx-bsp/reference-design/kc705-bitstream_2021.2.bb delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0004-minized-wifi-bluetooth.cfg create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2021.2.bbappend create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend delete mode 100644 meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb create mode 100644 meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb delete mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb create mode 100644 meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb delete mode 100644 meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb create mode 100644 meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.1.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.1.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.1.bb create mode 100644 meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.1.bb diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb new file mode 100644 index 00000000..e512777c --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2022.1.bb @@ -0,0 +1,48 @@ +SUMMARY = "KC705 Pre-built Bitstream" +DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." +HOMEPAGE = "http://www.xilinx.com" +SECTION = "bsp" + +# The BSP package does not include any license information. +LICENSE = "Proprietary" +LICENSE_FLAGS = "xilinx" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" + +COMPATIBLE_MACHINE = "kc705-microblazeel" + +inherit deploy +inherit xilinx-fetch-restricted + +BSP_NAME = "xilinx-kc705" +BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" +SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" +SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" +SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" + +PROVIDES = "virtual/bitstream" + +FILES:${PN} += "/boot/download.bit" + +INHIBIT_DEFAULT_DEPS = "1" +PACKAGE_ARCH = "${MACHINE_ARCH}" + +# deps needed to extract content from the .bsp file +DEPENDS += "tar-native gzip-native" + +do_compile() { + # Extract the bitstream into workdir + tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} + # move the bit file to ${S}/ as it is in a subdir in the tar file + for i in $(find -type f -name download.bit); do mv $i ${S}; done +} + +do_install() { + install -D ${S}/download.bit ${D}/boot/download.bit +} + +do_deploy () { + install -D ${S}/download.bit ${DEPLOYDIR}/download.bit +} + +addtask deploy before do_build after do_install + diff --git a/meta-xilinx-bsp/reference-design/kc705-bitstream_2021.2.bb b/meta-xilinx-bsp/reference-design/kc705-bitstream_2021.2.bb deleted file mode 100644 index e512777c..00000000 --- a/meta-xilinx-bsp/reference-design/kc705-bitstream_2021.2.bb +++ /dev/null @@ -1,48 +0,0 @@ -SUMMARY = "KC705 Pre-built Bitstream" -DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." -HOMEPAGE = "http://www.xilinx.com" -SECTION = "bsp" - -# The BSP package does not include any license information. -LICENSE = "Proprietary" -LICENSE_FLAGS = "xilinx" -LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" - -COMPATIBLE_MACHINE = "kc705-microblazeel" - -inherit deploy -inherit xilinx-fetch-restricted - -BSP_NAME = "xilinx-kc705" -BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" -SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" -SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" -SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" - -PROVIDES = "virtual/bitstream" - -FILES:${PN} += "/boot/download.bit" - -INHIBIT_DEFAULT_DEPS = "1" -PACKAGE_ARCH = "${MACHINE_ARCH}" - -# deps needed to extract content from the .bsp file -DEPENDS += "tar-native gzip-native" - -do_compile() { - # Extract the bitstream into workdir - tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} - # move the bit file to ${S}/ as it is in a subdir in the tar file - for i in $(find -type f -name download.bit); do mv $i ${S}; done -} - -do_install() { - install -D ${S}/download.bit ${D}/boot/download.bit -} - -do_deploy () { - install -D ${S}/download.bit ${DEPLOYDIR}/download.bit -} - -addtask deploy before do_build after do_install - diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf index b33fb0a5..026d79d2 100644 --- a/meta-xilinx-contrib/conf/layer.conf +++ b/meta-xilinx-contrib/conf/layer.conf @@ -14,4 +14,4 @@ LAYERDEPENDS_xilinx-contrib = "xilinx" LAYERSERIES_COMPAT_xilinx-contrib = "honister" -XILINX_RELEASE_VERSION = "v2021.2" +XILINX_RELEASE_VERSION = "v2022.1" diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch deleted file mode 100644 index 660bc218..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch +++ /dev/null @@ -1,305 +0,0 @@ -From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:14:13 +1000 -Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards - -Add the dglnt_encoder driver that enables DRM support for the VGA and -HDMI output ports found on many Digilent boards. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ - drivers/gpu/drm/xilinx/Kconfig | 6 + - drivers/gpu/drm/xilinx/Makefile | 1 + - drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ - 4 files changed, 247 insertions(+) - create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt - create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c - -diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -new file mode 100644 -index 0000000..242b24e ---- /dev/null -+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt -@@ -0,0 +1,23 @@ -+Device-Tree bindings for Digilent DRM Encoder Slave -+ -+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. -+The VGA or HDMI port must be connected to a Xilinx display pipeline via an -+axi2vid IP core. -+ -+Required properties: -+ - compatible: Should be "digilent,drm-encoder". -+ -+Optional properties: -+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video -+ connector. This is used to obtain the supported resolutions -+ of an attached monitor. If not defined, then a default -+ set of resolutions is used and the display will initialize -+ to 720p. Note most VGA connectors on Digilent boards do -+ not have the DDC bus routed out. -+ -+Example: -+ -+ encoder_0: digilent_encoder { -+ compatible = "digilent,drm-encoder"; -+ dglnt,edid-i2c = <&i2c1>; -+ }; -diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig -index 57e18a9..d9ecff2 100644 ---- a/drivers/gpu/drm/xilinx/Kconfig -+++ b/drivers/gpu/drm/xilinx/Kconfig -@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB - help - DRM driver for Xilinx Display Port Subsystem. - -+config DRM_DIGILENT_ENCODER -+ tristate "Digilent VGA/HDMI DRM Encoder Driver" -+ depends on DRM_XILINX -+ help -+ DRM slave encoder for Video-out on Digilent boards. -+ - config DRM_XILINX_DP_SUB_DEBUG_FS - bool "Xilinx DRM DPSUB debugfs" - depends on DEBUG_FS && DRM_XILINX_DP_SUB -diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile -index 19bc154..c2717e40 100644 ---- a/drivers/gpu/drm/xilinx/Makefile -+++ b/drivers/gpu/drm/xilinx/Makefile -@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ - xilinx_drm_plane.o - xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o - -+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o - obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o - obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o - obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o -diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c -new file mode 100644 -index 0000000..cb9fc7d ---- /dev/null -+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c -@@ -0,0 +1,217 @@ -+/* -+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. -+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DGLNT_ENC_MAX_FREQ 150000 -+#define DGLNT_ENC_MAX_H 1920 -+#define DGLNT_ENC_MAX_V 1080 -+#define DGLNT_ENC_PREF_H 1280 -+#define DGLNT_ENC_PREF_V 720 -+ -+struct dglnt_encoder { -+ struct drm_encoder *encoder; -+ struct i2c_adapter *i2c_bus; -+ bool i2c_present; -+}; -+ -+static inline struct dglnt_encoder *to_dglnt_encoder( -+ struct drm_encoder *encoder) -+{ -+ return to_encoder_slave(encoder)->slave_priv; -+} -+ -+static bool dglnt_mode_fixup(struct drm_encoder *encoder, -+ const struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+ return true; -+} -+ -+static void dglnt_encoder_mode_set(struct drm_encoder *encoder, -+ struct drm_display_mode *mode, -+ struct drm_display_mode *adjusted_mode) -+{ -+} -+ -+static void -+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) -+{ -+} -+ -+static void dglnt_encoder_save(struct drm_encoder *encoder) -+{ -+} -+ -+static void dglnt_encoder_restore(struct drm_encoder *encoder) -+{ -+} -+ -+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, -+ struct drm_display_mode *mode) -+{ -+ if (mode && -+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | -+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && -+ (mode->clock <= DGLNT_ENC_MAX_FREQ) && -+ (mode->hdisplay <= DGLNT_ENC_MAX_H) && -+ (mode->vdisplay <= DGLNT_ENC_MAX_V)) -+ return MODE_OK; -+ return MODE_BAD; -+} -+ -+static int dglnt_encoder_get_modes(struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ struct edid *edid; -+ int num_modes = 0; -+ -+ if (dglnt->i2c_present) { -+ edid = drm_get_edid(connector, dglnt->i2c_bus); -+ drm_connector_update_edid_property(connector, edid); -+ if (edid) { -+ num_modes = drm_add_edid_modes(connector, edid); -+ kfree(edid); -+ } -+ } else { -+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, -+ DGLNT_ENC_MAX_V); -+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, -+ DGLNT_ENC_PREF_V); -+ } -+ return num_modes; -+} -+ -+static enum drm_connector_status dglnt_encoder_detect( -+ struct drm_encoder *encoder, -+ struct drm_connector *connector) -+{ -+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); -+ -+ if (dglnt->i2c_present) { -+ if (drm_probe_ddc(dglnt->i2c_bus)) -+ return connector_status_connected; -+ return connector_status_disconnected; -+ } else -+ return connector_status_unknown; -+} -+ -+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { -+ .dpms = dglnt_encoder_dpms, -+ .save = dglnt_encoder_save, -+ .restore = dglnt_encoder_restore, -+ .mode_fixup = dglnt_mode_fixup, -+ .mode_valid = dglnt_encoder_mode_valid, -+ .mode_set = dglnt_encoder_mode_set, -+ .detect = dglnt_encoder_detect, -+ .get_modes = dglnt_encoder_get_modes, -+}; -+ -+static int dglnt_encoder_encoder_init(struct platform_device *pdev, -+ struct drm_device *dev, -+ struct drm_encoder_slave *encoder) -+{ -+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); -+ struct device_node *sub_node; -+ -+ encoder->slave_priv = dglnt; -+ encoder->slave_funcs = &dglnt_encoder_slave_funcs; -+ -+ dglnt->encoder = &encoder->base; -+ -+ /* get i2c adapter for edid */ -+ dglnt->i2c_present = false; -+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); -+ if (sub_node) { -+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); -+ if (!dglnt->i2c_bus) -+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); -+ else -+ dglnt->i2c_present = true; -+ of_node_put(sub_node); -+ } -+ -+ return 0; -+} -+ -+static int dglnt_encoder_probe(struct platform_device *pdev) -+{ -+ struct dglnt_encoder *dglnt; -+ -+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); -+ if (!dglnt) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, dglnt); -+ -+ return 0; -+} -+ -+static int dglnt_encoder_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+static const struct of_device_id dglnt_encoder_of_match[] = { -+ { .compatible = "digilent,drm-encoder", }, -+ { /* end of table */ }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); -+ -+static struct drm_platform_encoder_driver dglnt_encoder_driver = { -+ .platform_driver = { -+ .probe = dglnt_encoder_probe, -+ .remove = dglnt_encoder_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "dglnt-drm-enc", -+ .of_match_table = dglnt_encoder_of_match, -+ }, -+ }, -+ -+ .encoder_init = dglnt_encoder_encoder_init, -+}; -+ -+static int __init dglnt_encoder_init(void) -+{ -+ return platform_driver_register(&dglnt_encoder_driver.platform_driver); -+} -+ -+static void __exit dglnt_encoder_exit(void) -+{ -+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); -+} -+ -+module_init(dglnt_encoder_init); -+module_exit(dglnt_encoder_exit); -+ -+MODULE_AUTHOR("Digilent, Inc."); -+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); -+MODULE_LICENSE("GPL v2"); --- -2.7.4 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch deleted file mode 100644 index 9b6229db..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch +++ /dev/null @@ -1,607 +0,0 @@ -From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 -From: Jason Wu -Date: Sun, 10 Apr 2016 13:16:06 +1000 -Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core - -Add support for the axi_dynclk IP Core available from Digilent. This IP -core dynamically configures the clock resources inside a Xilinx FPGA to -generate a clock with a software programmable frequency. - -Upstream-Status: Pending - -Signed-off-by: Sam Bobrowicz -Signed-off-by: Jason Wu ---- - drivers/clk/Kconfig | 8 + - drivers/clk/Makefile | 1 + - drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 556 insertions(+) - create mode 100644 drivers/clk/clk-dglnt-dynclk.c - -diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index dccb111100..7fe65a702b 100644 ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -148,6 +148,14 @@ config CLK_QORIQ - This adds the clock driver support for Freescale QorIQ platforms - using common clock framework. - -+config COMMON_CLK_DGLNT_DYNCLK -+ tristate "Digilent axi_dynclk Driver" -+ depends on ARCH_ZYNQ || MICROBLAZE -+ help -+ ---help--- -+ Support for the Digilent AXI Dynamic Clock core for Xilinx -+ FPGAs. -+ - config COMMON_CLK_XGENE - bool "Clock driver for APM XGene SoC" - default y -diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index 0760449dde..45ce97d053 100644 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o - obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o - obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o - obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o -+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o - obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o - obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o - obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o -diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c -new file mode 100644 -index 0000000000..496ad5fc90 ---- /dev/null -+++ b/drivers/clk/clk-dglnt-dynclk.c -@@ -0,0 +1,547 @@ -+/* -+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver -+ * -+ * Copyright (C) 2015 Digilent -+ * Author: Sam Bobrowicz -+ * -+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLK_BIT_WEDGE 13 -+#define CLK_BIT_NOCOUNT 12 -+ -+/* This value is used to signal an error */ -+#define ERR_CLKCOUNTCALC 0xFFFFFFFF -+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) -+ -+#define DYNCLK_DIV_1_REGMASK 0x1041 -+/* 25 MHz (125 KHz / 5) */ -+#define DYNCLK_DEFAULT_FREQ 125000 -+ -+#define MMCM_FREQ_VCOMIN 600000 -+#define MMCM_FREQ_VCOMAX 1200000 -+#define MMCM_FREQ_PFDMIN 10000 -+#define MMCM_FREQ_PFDMAX 450000 -+#define MMCM_FREQ_OUTMIN 4000 -+#define MMCM_FREQ_OUTMAX 800000 -+#define MMCM_DIV_MAX 106 -+#define MMCM_FB_MIN 2 -+#define MMCM_FB_MAX 64 -+#define MMCM_CLKDIV_MAX 128 -+#define MMCM_CLKDIV_MIN 1 -+ -+#define OFST_DISPLAY_CTRL 0x0 -+#define OFST_DISPLAY_STATUS 0x4 -+#define OFST_DISPLAY_CLK_L 0x8 -+#define OFST_DISPLAY_FB_L 0x0C -+#define OFST_DISPLAY_FB_H_CLK_H 0x10 -+#define OFST_DISPLAY_DIV 0x14 -+#define OFST_DISPLAY_LOCK_L 0x18 -+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C -+ -+static const u64 lock_lookup[64] = { -+ 0b0011000110111110100011111010010000000001, -+ 0b0011000110111110100011111010010000000001, -+ 0b0100001000111110100011111010010000000001, -+ 0b0101101011111110100011111010010000000001, -+ 0b0111001110111110100011111010010000000001, -+ 0b1000110001111110100011111010010000000001, -+ 0b1001110011111110100011111010010000000001, -+ 0b1011010110111110100011111010010000000001, -+ 0b1100111001111110100011111010010000000001, -+ 0b1110011100111110100011111010010000000001, -+ 0b1111111111111000010011111010010000000001, -+ 0b1111111111110011100111111010010000000001, -+ 0b1111111111101110111011111010010000000001, -+ 0b1111111111101011110011111010010000000001, -+ 0b1111111111101000101011111010010000000001, -+ 0b1111111111100111000111111010010000000001, -+ 0b1111111111100011111111111010010000000001, -+ 0b1111111111100010011011111010010000000001, -+ 0b1111111111100000110111111010010000000001, -+ 0b1111111111011111010011111010010000000001, -+ 0b1111111111011101101111111010010000000001, -+ 0b1111111111011100001011111010010000000001, -+ 0b1111111111011010100111111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111011001000011111010010000000001, -+ 0b1111111111010111011111111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010101111011111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010100010111111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010010110011111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111010001001111111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001, -+ 0b1111111111001111101011111010010000000001 -+}; -+ -+static const u32 filter_lookup_low[64] = { -+ 0b0001011111, -+ 0b0001010111, -+ 0b0001111011, -+ 0b0001011011, -+ 0b0001101011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001110011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0001001011, -+ 0b0010110011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001010011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0001100011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010010011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011, -+ 0b0010100011 -+}; -+ -+struct dglnt_dynclk_reg; -+struct dglnt_dynclk_mode; -+struct dglnt_dynclk; -+ -+struct dglnt_dynclk_reg { -+ u32 clk0L; -+ u32 clkFBL; -+ u32 clkFBH_clk0H; -+ u32 divclk; -+ u32 lockL; -+ u32 fltr_lockH; -+}; -+ -+struct dglnt_dynclk_mode { -+ u32 freq; -+ u32 fbmult; -+ u32 clkdiv; -+ u32 maindiv; -+}; -+ -+struct dglnt_dynclk { -+ void __iomem *base; -+ struct clk_hw clk_hw; -+ unsigned long freq; -+}; -+ -+u32 dglnt_dynclk_divider(u32 divide) -+{ -+ u32 output = 0; -+ u32 highTime = 0; -+ u32 lowTime = 0; -+ -+ if ((divide < 1) || (divide > 128)) -+ return ERR_CLKDIVIDER; -+ -+ if (divide == 1) -+ return DYNCLK_DIV_1_REGMASK; -+ -+ highTime = divide / 2; -+ /* if divide is odd */ -+ if (divide & 0x1) { -+ lowTime = highTime + 1; -+ output = 1 << CLK_BIT_WEDGE; -+ } else { -+ lowTime = highTime; -+ } -+ -+ output |= 0x03F & lowTime; -+ output |= 0xFC0 & (highTime << 6); -+ return output; -+} -+ -+u32 dglnt_dynclk_count_calc(u32 divide) -+{ -+ u32 output = 0; -+ u32 divCalc = 0; -+ -+ divCalc = dglnt_dynclk_divider(divide); -+ if (divCalc == ERR_CLKDIVIDER) -+ output = ERR_CLKCOUNTCALC; -+ else -+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); -+ return output; -+} -+ -+ -+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, -+ struct dglnt_dynclk_mode *clkParams) -+{ -+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) -+ return -EINVAL; -+ -+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); -+ if (regValues->clk0L == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); -+ if (regValues->clkFBL == ERR_CLKCOUNTCALC) -+ return -EINVAL; -+ -+ regValues->clkFBH_clk0H = 0; -+ -+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); -+ if (regValues->divclk == ERR_CLKDIVIDER) -+ return -EINVAL; -+ -+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & -+ 0xFFFFFFFF); -+ -+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> -+ 32) & 0x000000FF); -+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << -+ 16) & 0x03FF0000); -+ -+ return 0; -+} -+ -+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, -+ void __iomem *baseaddr) -+{ -+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); -+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); -+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); -+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); -+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); -+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); -+} -+ -+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, -+ struct dglnt_dynclk_mode *bestPick) -+{ -+ u32 bestError = MMCM_FREQ_OUTMAX; -+ u32 curError; -+ u32 curClkMult; -+ u32 curFreq; -+ u32 divVal; -+ u32 curFb, curClkDiv; -+ u32 minFb = 0; -+ u32 maxFb = 0; -+ u32 curDiv = 1; -+ u32 maxDiv; -+ bool freq_found = false; -+ -+ bestPick->freq = 0; -+ if (parentFreq == 0) -+ return 0; -+ -+ /* minimum frequency is actually dictated by VCOmin */ -+ if (freq < MMCM_FREQ_OUTMIN) -+ freq = MMCM_FREQ_OUTMIN; -+ if (freq > MMCM_FREQ_OUTMAX) -+ freq = MMCM_FREQ_OUTMAX; -+ -+ if (parentFreq > MMCM_FREQ_PFDMAX) -+ curDiv = 2; -+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; -+ if (maxDiv > MMCM_DIV_MAX) -+ maxDiv = MMCM_DIV_MAX; -+ -+ while (curDiv <= maxDiv && !freq_found) { -+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); -+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); -+ if (maxFb > MMCM_FB_MAX) -+ maxFb = MMCM_FB_MAX; -+ if (minFb < MMCM_FB_MIN) -+ minFb = MMCM_FB_MIN; -+ -+ divVal = curDiv * freq; -+ /* -+ * This multiplier is used to find the best clkDiv value for -+ * each FB value -+ */ -+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; -+ -+ curFb = minFb; -+ while (curFb <= maxFb && !freq_found) { -+ curClkDiv = ((curClkMult * curFb) + 500) / 1000; -+ if (curClkDiv > MMCM_CLKDIV_MAX) -+ curClkDiv = MMCM_CLKDIV_MAX; -+ if (curClkDiv < MMCM_CLKDIV_MIN) -+ curClkDiv = MMCM_CLKDIV_MIN; -+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); -+ if (curFreq >= freq) -+ curError = curFreq - freq; -+ else -+ curError = freq - curFreq; -+ if (curError < bestError) { -+ bestError = curError; -+ bestPick->clkdiv = curClkDiv; -+ bestPick->fbmult = curFb; -+ bestPick->maindiv = curDiv; -+ bestPick->freq = curFreq; -+ } -+ if (!curError) -+ freq_found = true; -+ curFb++; -+ } -+ curDiv++; -+ } -+ return bestPick->freq; -+} -+ -+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) -+{ -+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); -+} -+ -+ -+static int dglnt_dynclk_enable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ unsigned int clock_state; -+ -+ if (dglnt_dynclk->freq) { -+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+ do { -+ clock_state = readl(dglnt_dynclk->base + -+ OFST_DISPLAY_STATUS); -+ } while (!clock_state); -+ } -+ return 0; -+} -+ -+static void dglnt_dynclk_disable(struct clk_hw *clk_hw) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); -+} -+ -+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, -+ unsigned long rate, unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ struct dglnt_dynclk_reg clkReg; -+ struct dglnt_dynclk_mode clkMode; -+ -+ if (parent_rate == 0 || rate == 0) -+ return -EINVAL; -+ if (rate == dglnt_dynclk->freq) -+ return 0; -+ -+ /* -+ * Convert from Hz to KHz, then multiply by five to account for -+ * BUFR division -+ */ -+ rate = (rate + 100) / 200; -+ /* convert from Hz to KHz */ -+ parent_rate = (parent_rate + 500) / 1000; -+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) -+ return -EINVAL; -+ -+ /* -+ * Write to the PLL dynamic configuration registers to configure it -+ * with the calculated parameters. -+ */ -+ dglnt_dynclk_find_reg(&clkReg, &clkMode); -+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); -+ dglnt_dynclk->freq = clkMode.freq * 200; -+ dglnt_dynclk_disable(clk_hw); -+ dglnt_dynclk_enable(clk_hw); -+ -+ return 0; -+} -+ -+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ struct dglnt_dynclk_mode clkMode; -+ -+ dglnt_dynclk_find_mode(((rate + 100) / 200), -+ ((*parent_rate) + 500) / 1000, &clkMode); -+ -+ return (clkMode.freq * 200); -+} -+ -+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, -+ unsigned long parent_rate) -+{ -+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); -+ -+ return dglnt_dynclk->freq; -+} -+ -+ -+static const struct clk_ops dglnt_dynclk_ops = { -+ .recalc_rate = dglnt_dynclk_recalc_rate, -+ .round_rate = dglnt_dynclk_round_rate, -+ .set_rate = dglnt_dynclk_set_rate, -+ .enable = dglnt_dynclk_enable, -+ .disable = dglnt_dynclk_disable, -+}; -+ -+static const struct of_device_id dglnt_dynclk_ids[] = { -+ { .compatible = "digilent,axi-dynclk", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); -+ -+static int dglnt_dynclk_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *id; -+ struct dglnt_dynclk *dglnt_dynclk; -+ struct clk_init_data init; -+ const char *parent_name; -+ const char *clk_name; -+ struct resource *mem; -+ struct clk *clk; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); -+ if (!id) -+ return -ENODEV; -+ -+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), -+ GFP_KERNEL); -+ if (!dglnt_dynclk) -+ return -ENOMEM; -+ -+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); -+ if (IS_ERR(dglnt_dynclk->base)) -+ return PTR_ERR(dglnt_dynclk->base); -+ -+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); -+ if (!parent_name) -+ return -EINVAL; -+ -+ clk_name = pdev->dev.of_node->name; -+ of_property_read_string(pdev->dev.of_node, "clock-output-names", -+ &clk_name); -+ -+ init.name = clk_name; -+ init.ops = &dglnt_dynclk_ops; -+ init.flags = 0; -+ init.parent_names = &parent_name; -+ init.num_parents = 1; -+ -+ dglnt_dynclk->freq = 0; -+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); -+ -+ dglnt_dynclk->clk_hw.init = &init; -+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); -+ if (IS_ERR(clk)) -+ return PTR_ERR(clk); -+ -+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, -+ clk); -+} -+ -+static int dglnt_dynclk_remove(struct platform_device *pdev) -+{ -+ of_clk_del_provider(pdev->dev.of_node); -+ -+ return 0; -+} -+ -+static struct platform_driver dglnt_dynclk_driver = { -+ .driver = { -+ .name = "dglnt-dynclk", -+ .owner = THIS_MODULE, -+ .of_match_table = dglnt_dynclk_ids, -+ }, -+ .probe = dglnt_dynclk_probe, -+ .remove = dglnt_dynclk_remove, -+}; -+module_platform_driver(dglnt_dynclk_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Sam Bobrowicz "); -+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch deleted file mode 100644 index a98d84c5..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 -From: Nathan Rossi -Date: Mon, 2 May 2016 23:46:42 +1000 -Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on - -Fix the issues where the VTC is reset (losing its timing config). - -Also fix the issue where the plane destroys its DMA descriptors and -marks the DMA channels as inactive but never recreates the descriptors -and never updates the active state when turning DPMS back on. - -Signed-off-by: Nathan Rossi -Upstream-Status: Pending [This is a workaround] ---- - drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - - drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -index 631d35b921..93dbd4b58a 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c -@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) - default: - if (crtc->vtc) { - xilinx_vtc_disable(crtc->vtc); -- xilinx_vtc_reset(crtc->vtc); - } - if (crtc->cresample) { - xilinx_cresample_disable(crtc->cresample); -diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -index 6a248b72d4..d2518a4bdf 100644 ---- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c -@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { - struct xilinx_drm_plane_dma *dma = &plane->dma[i]; - -- if (dma->chan && dma->is_active) { -+ if (dma->chan) { - flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; - desc = dmaengine_prep_interleaved_dma(dma->chan, - &dma->xt, -@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) - dmaengine_submit(desc); - - dma_async_issue_pending(dma->chan); -+ dma->is_active = true; - } - } - } --- -2.14.2 - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0004-minized-wifi-bluetooth.cfg deleted file mode 100644 index f71e53ab..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2021.2/0004-minized-wifi-bluetooth.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# -# Bluetooth config -# -CONFIG_BT=y -CONFIG_BT_BREDR=y -CONFIG_BT_HS=y -CONFIG_BT_LE=y -CONFIG_BT_BCM=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HIDP=y -CONFIG_CFG80211=y -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_CRDA_SUPPORT=y -CONFIG_BRCMUTIL=y -CONFIG_BRCMFMAC=y -CONFIG_BRCMFMAC_PROTO_BCDC=y -CONFIG_BRCMFMAC_SDIO=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_SHA256=y - -# -# Regulator config -# -CONFIG_REGMAP_IRQ=y -CONFIG_I2C_XILINX=y -CONFIG_MFD_DA9062=y -CONFIG_REGULATOR_DA9062=y - diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch new file mode 100644 index 00000000..660bc218 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch @@ -0,0 +1,305 @@ +From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:14:13 +1000 +Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards + +Add the dglnt_encoder driver that enables DRM support for the VGA and +HDMI output ports found on many Digilent boards. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++ + drivers/gpu/drm/xilinx/Kconfig | 6 + + drivers/gpu/drm/xilinx/Makefile | 1 + + drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++ + 4 files changed, 247 insertions(+) + create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt + create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c + +diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +new file mode 100644 +index 0000000..242b24e +--- /dev/null ++++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt +@@ -0,0 +1,23 @@ ++Device-Tree bindings for Digilent DRM Encoder Slave ++ ++This driver provides support for VGA and HDMI outputs on Digilent FPGA boards. ++The VGA or HDMI port must be connected to a Xilinx display pipeline via an ++axi2vid IP core. ++ ++Required properties: ++ - compatible: Should be "digilent,drm-encoder". ++ ++Optional properties: ++ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video ++ connector. This is used to obtain the supported resolutions ++ of an attached monitor. If not defined, then a default ++ set of resolutions is used and the display will initialize ++ to 720p. Note most VGA connectors on Digilent boards do ++ not have the DDC bus routed out. ++ ++Example: ++ ++ encoder_0: digilent_encoder { ++ compatible = "digilent,drm-encoder"; ++ dglnt,edid-i2c = <&i2c1>; ++ }; +diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig +index 57e18a9..d9ecff2 100644 +--- a/drivers/gpu/drm/xilinx/Kconfig ++++ b/drivers/gpu/drm/xilinx/Kconfig +@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB + help + DRM driver for Xilinx Display Port Subsystem. + ++config DRM_DIGILENT_ENCODER ++ tristate "Digilent VGA/HDMI DRM Encoder Driver" ++ depends on DRM_XILINX ++ help ++ DRM slave encoder for Video-out on Digilent boards. ++ + config DRM_XILINX_DP_SUB_DEBUG_FS + bool "Xilinx DRM DPSUB debugfs" + depends on DEBUG_FS && DRM_XILINX_DP_SUB +diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile +index 19bc154..c2717e40 100644 +--- a/drivers/gpu/drm/xilinx/Makefile ++++ b/drivers/gpu/drm/xilinx/Makefile +@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \ + xilinx_drm_plane.o + xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o + ++obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o + obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o + obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o + obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o +diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c +new file mode 100644 +index 0000000..cb9fc7d +--- /dev/null ++++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c +@@ -0,0 +1,217 @@ ++/* ++ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat. ++ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DGLNT_ENC_MAX_FREQ 150000 ++#define DGLNT_ENC_MAX_H 1920 ++#define DGLNT_ENC_MAX_V 1080 ++#define DGLNT_ENC_PREF_H 1280 ++#define DGLNT_ENC_PREF_V 720 ++ ++struct dglnt_encoder { ++ struct drm_encoder *encoder; ++ struct i2c_adapter *i2c_bus; ++ bool i2c_present; ++}; ++ ++static inline struct dglnt_encoder *to_dglnt_encoder( ++ struct drm_encoder *encoder) ++{ ++ return to_encoder_slave(encoder)->slave_priv; ++} ++ ++static bool dglnt_mode_fixup(struct drm_encoder *encoder, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++static void dglnt_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++} ++ ++static void ++dglnt_encoder_dpms(struct drm_encoder *encoder, int mode) ++{ ++} ++ ++static void dglnt_encoder_save(struct drm_encoder *encoder) ++{ ++} ++ ++static void dglnt_encoder_restore(struct drm_encoder *encoder) ++{ ++} ++ ++static int dglnt_encoder_mode_valid(struct drm_encoder *encoder, ++ struct drm_display_mode *mode) ++{ ++ if (mode && ++ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE | ++ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) && ++ (mode->clock <= DGLNT_ENC_MAX_FREQ) && ++ (mode->hdisplay <= DGLNT_ENC_MAX_H) && ++ (mode->vdisplay <= DGLNT_ENC_MAX_V)) ++ return MODE_OK; ++ return MODE_BAD; ++} ++ ++static int dglnt_encoder_get_modes(struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ struct edid *edid; ++ int num_modes = 0; ++ ++ if (dglnt->i2c_present) { ++ edid = drm_get_edid(connector, dglnt->i2c_bus); ++ drm_connector_update_edid_property(connector, edid); ++ if (edid) { ++ num_modes = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ } else { ++ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H, ++ DGLNT_ENC_MAX_V); ++ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H, ++ DGLNT_ENC_PREF_V); ++ } ++ return num_modes; ++} ++ ++static enum drm_connector_status dglnt_encoder_detect( ++ struct drm_encoder *encoder, ++ struct drm_connector *connector) ++{ ++ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder); ++ ++ if (dglnt->i2c_present) { ++ if (drm_probe_ddc(dglnt->i2c_bus)) ++ return connector_status_connected; ++ return connector_status_disconnected; ++ } else ++ return connector_status_unknown; ++} ++ ++static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = { ++ .dpms = dglnt_encoder_dpms, ++ .save = dglnt_encoder_save, ++ .restore = dglnt_encoder_restore, ++ .mode_fixup = dglnt_mode_fixup, ++ .mode_valid = dglnt_encoder_mode_valid, ++ .mode_set = dglnt_encoder_mode_set, ++ .detect = dglnt_encoder_detect, ++ .get_modes = dglnt_encoder_get_modes, ++}; ++ ++static int dglnt_encoder_encoder_init(struct platform_device *pdev, ++ struct drm_device *dev, ++ struct drm_encoder_slave *encoder) ++{ ++ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev); ++ struct device_node *sub_node; ++ ++ encoder->slave_priv = dglnt; ++ encoder->slave_funcs = &dglnt_encoder_slave_funcs; ++ ++ dglnt->encoder = &encoder->base; ++ ++ /* get i2c adapter for edid */ ++ dglnt->i2c_present = false; ++ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0); ++ if (sub_node) { ++ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node); ++ if (!dglnt->i2c_bus) ++ DRM_INFO("failed to get the edid i2c adapter, using default modes\n"); ++ else ++ dglnt->i2c_present = true; ++ of_node_put(sub_node); ++ } ++ ++ return 0; ++} ++ ++static int dglnt_encoder_probe(struct platform_device *pdev) ++{ ++ struct dglnt_encoder *dglnt; ++ ++ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL); ++ if (!dglnt) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, dglnt); ++ ++ return 0; ++} ++ ++static int dglnt_encoder_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static const struct of_device_id dglnt_encoder_of_match[] = { ++ { .compatible = "digilent,drm-encoder", }, ++ { /* end of table */ }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match); ++ ++static struct drm_platform_encoder_driver dglnt_encoder_driver = { ++ .platform_driver = { ++ .probe = dglnt_encoder_probe, ++ .remove = dglnt_encoder_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "dglnt-drm-enc", ++ .of_match_table = dglnt_encoder_of_match, ++ }, ++ }, ++ ++ .encoder_init = dglnt_encoder_encoder_init, ++}; ++ ++static int __init dglnt_encoder_init(void) ++{ ++ return platform_driver_register(&dglnt_encoder_driver.platform_driver); ++} ++ ++static void __exit dglnt_encoder_exit(void) ++{ ++ platform_driver_unregister(&dglnt_encoder_driver.platform_driver); ++} ++ ++module_init(dglnt_encoder_init); ++module_exit(dglnt_encoder_exit); ++ ++MODULE_AUTHOR("Digilent, Inc."); ++MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards"); ++MODULE_LICENSE("GPL v2"); +-- +2.7.4 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch new file mode 100644 index 00000000..9b6229db --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch @@ -0,0 +1,607 @@ +From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001 +From: Jason Wu +Date: Sun, 10 Apr 2016 13:16:06 +1000 +Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core + +Add support for the axi_dynclk IP Core available from Digilent. This IP +core dynamically configures the clock resources inside a Xilinx FPGA to +generate a clock with a software programmable frequency. + +Upstream-Status: Pending + +Signed-off-by: Sam Bobrowicz +Signed-off-by: Jason Wu +--- + drivers/clk/Kconfig | 8 + + drivers/clk/Makefile | 1 + + drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 556 insertions(+) + create mode 100644 drivers/clk/clk-dglnt-dynclk.c + +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index dccb111100..7fe65a702b 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -148,6 +148,14 @@ config CLK_QORIQ + This adds the clock driver support for Freescale QorIQ platforms + using common clock framework. + ++config COMMON_CLK_DGLNT_DYNCLK ++ tristate "Digilent axi_dynclk Driver" ++ depends on ARCH_ZYNQ || MICROBLAZE ++ help ++ ---help--- ++ Support for the Digilent AXI Dynamic Clock core for Xilinx ++ FPGAs. ++ + config COMMON_CLK_XGENE + bool "Clock driver for APM XGene SoC" + default y +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index 0760449dde..45ce97d053 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o + obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o ++obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o + obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o + obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o + obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c +new file mode 100644 +index 0000000000..496ad5fc90 +--- /dev/null ++++ b/drivers/clk/clk-dglnt-dynclk.c +@@ -0,0 +1,547 @@ ++/* ++ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver ++ * ++ * Copyright (C) 2015 Digilent ++ * Author: Sam Bobrowicz ++ * ++ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLK_BIT_WEDGE 13 ++#define CLK_BIT_NOCOUNT 12 ++ ++/* This value is used to signal an error */ ++#define ERR_CLKCOUNTCALC 0xFFFFFFFF ++#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT) ++ ++#define DYNCLK_DIV_1_REGMASK 0x1041 ++/* 25 MHz (125 KHz / 5) */ ++#define DYNCLK_DEFAULT_FREQ 125000 ++ ++#define MMCM_FREQ_VCOMIN 600000 ++#define MMCM_FREQ_VCOMAX 1200000 ++#define MMCM_FREQ_PFDMIN 10000 ++#define MMCM_FREQ_PFDMAX 450000 ++#define MMCM_FREQ_OUTMIN 4000 ++#define MMCM_FREQ_OUTMAX 800000 ++#define MMCM_DIV_MAX 106 ++#define MMCM_FB_MIN 2 ++#define MMCM_FB_MAX 64 ++#define MMCM_CLKDIV_MAX 128 ++#define MMCM_CLKDIV_MIN 1 ++ ++#define OFST_DISPLAY_CTRL 0x0 ++#define OFST_DISPLAY_STATUS 0x4 ++#define OFST_DISPLAY_CLK_L 0x8 ++#define OFST_DISPLAY_FB_L 0x0C ++#define OFST_DISPLAY_FB_H_CLK_H 0x10 ++#define OFST_DISPLAY_DIV 0x14 ++#define OFST_DISPLAY_LOCK_L 0x18 ++#define OFST_DISPLAY_FLTR_LOCK_H 0x1C ++ ++static const u64 lock_lookup[64] = { ++ 0b0011000110111110100011111010010000000001, ++ 0b0011000110111110100011111010010000000001, ++ 0b0100001000111110100011111010010000000001, ++ 0b0101101011111110100011111010010000000001, ++ 0b0111001110111110100011111010010000000001, ++ 0b1000110001111110100011111010010000000001, ++ 0b1001110011111110100011111010010000000001, ++ 0b1011010110111110100011111010010000000001, ++ 0b1100111001111110100011111010010000000001, ++ 0b1110011100111110100011111010010000000001, ++ 0b1111111111111000010011111010010000000001, ++ 0b1111111111110011100111111010010000000001, ++ 0b1111111111101110111011111010010000000001, ++ 0b1111111111101011110011111010010000000001, ++ 0b1111111111101000101011111010010000000001, ++ 0b1111111111100111000111111010010000000001, ++ 0b1111111111100011111111111010010000000001, ++ 0b1111111111100010011011111010010000000001, ++ 0b1111111111100000110111111010010000000001, ++ 0b1111111111011111010011111010010000000001, ++ 0b1111111111011101101111111010010000000001, ++ 0b1111111111011100001011111010010000000001, ++ 0b1111111111011010100111111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111011001000011111010010000000001, ++ 0b1111111111010111011111111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010101111011111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010100010111111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010010110011111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111010001001111111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001, ++ 0b1111111111001111101011111010010000000001 ++}; ++ ++static const u32 filter_lookup_low[64] = { ++ 0b0001011111, ++ 0b0001010111, ++ 0b0001111011, ++ 0b0001011011, ++ 0b0001101011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001110011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0001001011, ++ 0b0010110011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001010011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0001100011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010010011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011, ++ 0b0010100011 ++}; ++ ++struct dglnt_dynclk_reg; ++struct dglnt_dynclk_mode; ++struct dglnt_dynclk; ++ ++struct dglnt_dynclk_reg { ++ u32 clk0L; ++ u32 clkFBL; ++ u32 clkFBH_clk0H; ++ u32 divclk; ++ u32 lockL; ++ u32 fltr_lockH; ++}; ++ ++struct dglnt_dynclk_mode { ++ u32 freq; ++ u32 fbmult; ++ u32 clkdiv; ++ u32 maindiv; ++}; ++ ++struct dglnt_dynclk { ++ void __iomem *base; ++ struct clk_hw clk_hw; ++ unsigned long freq; ++}; ++ ++u32 dglnt_dynclk_divider(u32 divide) ++{ ++ u32 output = 0; ++ u32 highTime = 0; ++ u32 lowTime = 0; ++ ++ if ((divide < 1) || (divide > 128)) ++ return ERR_CLKDIVIDER; ++ ++ if (divide == 1) ++ return DYNCLK_DIV_1_REGMASK; ++ ++ highTime = divide / 2; ++ /* if divide is odd */ ++ if (divide & 0x1) { ++ lowTime = highTime + 1; ++ output = 1 << CLK_BIT_WEDGE; ++ } else { ++ lowTime = highTime; ++ } ++ ++ output |= 0x03F & lowTime; ++ output |= 0xFC0 & (highTime << 6); ++ return output; ++} ++ ++u32 dglnt_dynclk_count_calc(u32 divide) ++{ ++ u32 output = 0; ++ u32 divCalc = 0; ++ ++ divCalc = dglnt_dynclk_divider(divide); ++ if (divCalc == ERR_CLKDIVIDER) ++ output = ERR_CLKCOUNTCALC; ++ else ++ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000); ++ return output; ++} ++ ++ ++int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues, ++ struct dglnt_dynclk_mode *clkParams) ++{ ++ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64) ++ return -EINVAL; ++ ++ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv); ++ if (regValues->clk0L == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult); ++ if (regValues->clkFBL == ERR_CLKCOUNTCALC) ++ return -EINVAL; ++ ++ regValues->clkFBH_clk0H = 0; ++ ++ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv); ++ if (regValues->divclk == ERR_CLKDIVIDER) ++ return -EINVAL; ++ ++ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] & ++ 0xFFFFFFFF); ++ ++ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >> ++ 32) & 0x000000FF); ++ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] << ++ 16) & 0x03FF0000); ++ ++ return 0; ++} ++ ++void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues, ++ void __iomem *baseaddr) ++{ ++ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L); ++ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L); ++ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H); ++ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV); ++ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L); ++ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H); ++} ++ ++u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq, ++ struct dglnt_dynclk_mode *bestPick) ++{ ++ u32 bestError = MMCM_FREQ_OUTMAX; ++ u32 curError; ++ u32 curClkMult; ++ u32 curFreq; ++ u32 divVal; ++ u32 curFb, curClkDiv; ++ u32 minFb = 0; ++ u32 maxFb = 0; ++ u32 curDiv = 1; ++ u32 maxDiv; ++ bool freq_found = false; ++ ++ bestPick->freq = 0; ++ if (parentFreq == 0) ++ return 0; ++ ++ /* minimum frequency is actually dictated by VCOmin */ ++ if (freq < MMCM_FREQ_OUTMIN) ++ freq = MMCM_FREQ_OUTMIN; ++ if (freq > MMCM_FREQ_OUTMAX) ++ freq = MMCM_FREQ_OUTMAX; ++ ++ if (parentFreq > MMCM_FREQ_PFDMAX) ++ curDiv = 2; ++ maxDiv = parentFreq / MMCM_FREQ_PFDMIN; ++ if (maxDiv > MMCM_DIV_MAX) ++ maxDiv = MMCM_DIV_MAX; ++ ++ while (curDiv <= maxDiv && !freq_found) { ++ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq); ++ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq); ++ if (maxFb > MMCM_FB_MAX) ++ maxFb = MMCM_FB_MAX; ++ if (minFb < MMCM_FB_MIN) ++ minFb = MMCM_FB_MIN; ++ ++ divVal = curDiv * freq; ++ /* ++ * This multiplier is used to find the best clkDiv value for ++ * each FB value ++ */ ++ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal; ++ ++ curFb = minFb; ++ while (curFb <= maxFb && !freq_found) { ++ curClkDiv = ((curClkMult * curFb) + 500) / 1000; ++ if (curClkDiv > MMCM_CLKDIV_MAX) ++ curClkDiv = MMCM_CLKDIV_MAX; ++ if (curClkDiv < MMCM_CLKDIV_MIN) ++ curClkDiv = MMCM_CLKDIV_MIN; ++ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv); ++ if (curFreq >= freq) ++ curError = curFreq - freq; ++ else ++ curError = freq - curFreq; ++ if (curError < bestError) { ++ bestError = curError; ++ bestPick->clkdiv = curClkDiv; ++ bestPick->fbmult = curFb; ++ bestPick->maindiv = curDiv; ++ bestPick->freq = curFreq; ++ } ++ if (!curError) ++ freq_found = true; ++ curFb++; ++ } ++ curDiv++; ++ } ++ return bestPick->freq; ++} ++ ++static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw) ++{ ++ return container_of(clk_hw, struct dglnt_dynclk, clk_hw); ++} ++ ++ ++static int dglnt_dynclk_enable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ unsigned int clock_state; ++ ++ if (dglnt_dynclk->freq) { ++ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++ do { ++ clock_state = readl(dglnt_dynclk->base + ++ OFST_DISPLAY_STATUS); ++ } while (!clock_state); ++ } ++ return 0; ++} ++ ++static void dglnt_dynclk_disable(struct clk_hw *clk_hw) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL); ++} ++ ++static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ struct dglnt_dynclk_reg clkReg; ++ struct dglnt_dynclk_mode clkMode; ++ ++ if (parent_rate == 0 || rate == 0) ++ return -EINVAL; ++ if (rate == dglnt_dynclk->freq) ++ return 0; ++ ++ /* ++ * Convert from Hz to KHz, then multiply by five to account for ++ * BUFR division ++ */ ++ rate = (rate + 100) / 200; ++ /* convert from Hz to KHz */ ++ parent_rate = (parent_rate + 500) / 1000; ++ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode)) ++ return -EINVAL; ++ ++ /* ++ * Write to the PLL dynamic configuration registers to configure it ++ * with the calculated parameters. ++ */ ++ dglnt_dynclk_find_reg(&clkReg, &clkMode); ++ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base); ++ dglnt_dynclk->freq = clkMode.freq * 200; ++ dglnt_dynclk_disable(clk_hw); ++ dglnt_dynclk_enable(clk_hw); ++ ++ return 0; ++} ++ ++static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct dglnt_dynclk_mode clkMode; ++ ++ dglnt_dynclk_find_mode(((rate + 100) / 200), ++ ((*parent_rate) + 500) / 1000, &clkMode); ++ ++ return (clkMode.freq * 200); ++} ++ ++static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw, ++ unsigned long parent_rate) ++{ ++ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw); ++ ++ return dglnt_dynclk->freq; ++} ++ ++ ++static const struct clk_ops dglnt_dynclk_ops = { ++ .recalc_rate = dglnt_dynclk_recalc_rate, ++ .round_rate = dglnt_dynclk_round_rate, ++ .set_rate = dglnt_dynclk_set_rate, ++ .enable = dglnt_dynclk_enable, ++ .disable = dglnt_dynclk_disable, ++}; ++ ++static const struct of_device_id dglnt_dynclk_ids[] = { ++ { .compatible = "digilent,axi-dynclk", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids); ++ ++static int dglnt_dynclk_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct dglnt_dynclk *dglnt_dynclk; ++ struct clk_init_data init; ++ const char *parent_name; ++ const char *clk_name; ++ struct resource *mem; ++ struct clk *clk; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node); ++ if (!id) ++ return -ENODEV; ++ ++ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk), ++ GFP_KERNEL); ++ if (!dglnt_dynclk) ++ return -ENOMEM; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem); ++ if (IS_ERR(dglnt_dynclk->base)) ++ return PTR_ERR(dglnt_dynclk->base); ++ ++ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0); ++ if (!parent_name) ++ return -EINVAL; ++ ++ clk_name = pdev->dev.of_node->name; ++ of_property_read_string(pdev->dev.of_node, "clock-output-names", ++ &clk_name); ++ ++ init.name = clk_name; ++ init.ops = &dglnt_dynclk_ops; ++ init.flags = 0; ++ init.parent_names = &parent_name; ++ init.num_parents = 1; ++ ++ dglnt_dynclk->freq = 0; ++ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw); ++ ++ dglnt_dynclk->clk_hw.init = &init; ++ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, ++ clk); ++} ++ ++static int dglnt_dynclk_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver dglnt_dynclk_driver = { ++ .driver = { ++ .name = "dglnt-dynclk", ++ .owner = THIS_MODULE, ++ .of_match_table = dglnt_dynclk_ids, ++ }, ++ .probe = dglnt_dynclk_probe, ++ .remove = dglnt_dynclk_remove, ++}; ++module_platform_driver(dglnt_dynclk_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Sam Bobrowicz "); ++MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core"); +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch new file mode 100644 index 00000000..a98d84c5 --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch @@ -0,0 +1,54 @@ +From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001 +From: Nathan Rossi +Date: Mon, 2 May 2016 23:46:42 +1000 +Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on + +Fix the issues where the VTC is reset (losing its timing config). + +Also fix the issue where the plane destroys its DMA descriptors and +marks the DMA channels as inactive but never recreates the descriptors +and never updates the active state when turning DPMS back on. + +Signed-off-by: Nathan Rossi +Upstream-Status: Pending [This is a workaround] +--- + drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 - + drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +index 631d35b921..93dbd4b58a 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c +@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms) + default: + if (crtc->vtc) { + xilinx_vtc_disable(crtc->vtc); +- xilinx_vtc_reset(crtc->vtc); + } + if (crtc->cresample) { + xilinx_cresample_disable(crtc->cresample); +diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +index 6a248b72d4..d2518a4bdf 100644 +--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c ++++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c +@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { + struct xilinx_drm_plane_dma *dma = &plane->dma[i]; + +- if (dma->chan && dma->is_active) { ++ if (dma->chan) { + flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; + desc = dmaengine_prep_interleaved_dma(dma->chan, + &dma->xt, +@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane) + dmaengine_submit(desc); + + dma_async_issue_pending(dma->chan); ++ dma->is_active = true; + } + } + } +-- +2.14.2 + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg new file mode 100644 index 00000000..f71e53ab --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2022.1/0004-minized-wifi-bluetooth.cfg @@ -0,0 +1,33 @@ +# +# Bluetooth config +# +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_BCM=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HIDP=y +CONFIG_CFG80211=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_BRCMUTIL=y +CONFIG_BRCMFMAC=y +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA256=y + +# +# Regulator config +# +CONFIG_REGMAP_IRQ=y +CONFIG_I2C_XILINX=y +CONFIG_MFD_DA9062=y +CONFIG_REGULATOR_DA9062=y + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2021.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2021.2.bbappend deleted file mode 100644 index 2ce919ac..00000000 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2021.2.bbappend +++ /dev/null @@ -1,9 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" - -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ - file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ - file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ - " - -SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend new file mode 100644 index 00000000..2ce919ac --- /dev/null +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.1.bbappend @@ -0,0 +1,9 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" + +SRC_URI:append:zybo-linux-bd-zynq7 = " \ + file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ + file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ + file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ + " + +SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-core/conf/local.conf.sample b/meta-xilinx-core/conf/local.conf.sample index 5518196e..a7173fb8 100644 --- a/meta-xilinx-core/conf/local.conf.sample +++ b/meta-xilinx-core/conf/local.conf.sample @@ -206,11 +206,11 @@ BB_DISKMON_DIRS ??= "\ #file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \ #file://.* file:///some/local/dir/sstate/PATH" -XILINX_VER_MAIN = "2021.2" +XILINX_VER_MAIN = "2022.1" # Uncomment below lines to provide path for custom xsct trim # -#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2021.2_xsct_daily_latest" +#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2022.1_xsct_daily_latest" #VALIDATE_XSCT_CHECKSUM = '0' # diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb deleted file mode 100644 index f69ed50c..00000000 --- a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb +++ /dev/null @@ -1,8 +0,0 @@ -ATF_VERSION = "2.4" -SRCREV = "9188496b9b23a665782bb3d2c2b9e3b29b7fb4e2" -BRANCH = "xlnx_rebase_v2.4" -LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" - - -include arm-trusted-firmware.inc - diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb new file mode 100644 index 00000000..f02bb879 --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2022.1.bb @@ -0,0 +1,8 @@ +ATF_VERSION = "2.6" +SRCREV = "67ca59c67f542322554d78820bf9ddaa736d6a84" +BRANCH = "xlnx_rebase_v2.6" +LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" + + +include arm-trusted-firmware.inc + diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb index 236da302..101d4ca2 100644 --- a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb @@ -10,8 +10,8 @@ DEPENDS += "openssl" RDEPENDS:${PN} += "openssl" REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" -BRANCH ?= "xlnx_rel_v2021.2" -SRCREV = "5b6fe16a2bfd7ced4d90b70b0ba6fbf325e81e97" +BRANCH ?= "xlnx_rel_v2022.1" +SRCREV = "4eac958eb6c831ffa5768a0e2cd4be23c5efe2e0" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb deleted file mode 100644 index a4fedbe2..00000000 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb +++ /dev/null @@ -1,19 +0,0 @@ -UBOOT_VERSION = "v2021.01" - -UBRANCH ?= "xlnx_rebase_v2021.01" - -SRCREV = "63b6d260dbe64a005407439e2caeb32da9025954" - -include u-boot-xlnx.inc -include u-boot-spl-zynq-init.inc - -LICENSE = "GPLv2+" -LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" - -# u-boot-xlnx has support for these -HAS_PLATFORM_INIT ?= " \ - xilinx_zynqmp_virt_config \ - xilinx_zynq_virt_defconfig \ - xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ - " - diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb new file mode 100644 index 00000000..e309783f --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb @@ -0,0 +1,19 @@ +UBOOT_VERSION = "v2021.01" + +UBRANCH ?= "xlnx_rebase_v2022.01" + +SRCREV = "c50d6c48f4e1368cd38699278e35563cb4b0e444" + +include u-boot-xlnx.inc +include u-boot-spl-zynq-init.inc + +LICENSE = "GPLv2+" +LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" + +# u-boot-xlnx has support for these +HAS_PLATFORM_INIT ?= " \ + xilinx_zynqmp_virt_config \ + xilinx_zynq_virt_defconfig \ + xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ + " + diff --git a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb index 79e0d90b..4acce149 100644 --- a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb +++ b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb @@ -12,7 +12,7 @@ PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" SRCREV ?= "a1a22c9f03b20d8cb70b91727fe51c1db7f4b061" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb index 4d8bd265..ae11f694 100755 --- a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb +++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb @@ -4,14 +4,14 @@ SECTION = "kernel/modules" LICENSE = "GPLv2" LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" -XLNX_DP_VERSION = "5.10.0" +XLNX_DP_VERSION = "5.15.19" PV = "${XLNX_DP_VERSION}" S = "${WORKDIR}/git" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" -SRCREV ?= "46d4790c3d37ad4b878c5a1704df26edb56314f5" +SRCREV ?= "9a025fdb7134a8af12de8d69f5a428c8284ae9b3" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb index 65484fca..27a5ffdb 100644 --- a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb +++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb @@ -4,14 +4,14 @@ SECTION = "kernel/modules" LICENSE = "GPLv2" LIC_FILES_CHKSUM = "file://LICENSE.md;md5=b34277fe156508fd5a650609dc36d1fe" -XLNX_HDMI_VERSION = "5.10.0" +XLNX_HDMI_VERSION = "5.15.19" PV = "${XLNX_HDMI_VERSION}" S = "${WORKDIR}/git" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https" -SRCREV = "aeb9f2c9a50c5e8dd4245454116c47f841f78825" +SRCREV = "25b6fe7a26a975be15c002b48cfd4c291486491e" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb index acb9938f..197cb208 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb @@ -11,7 +11,7 @@ SRCREV ?= '${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/kernel", "linux-x # skip version sanity, because the version moves with AUTOREV KERNEL_VERSION_SANITY_SKIP = "1" -LINUX_VERSION ?= "4.9+" +LINUX_VERSION ?= "5.15+" LINUX_VERSION_EXTENSION ?= "-xilinx-dev" include linux-xlnx.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc index 4652154e..adefabea 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc @@ -4,16 +4,16 @@ LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" PV = "${LINUX_VERSION}+git${SRCPV}" # Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits -KBRANCH ?= "xlnx_rebase_v5.10" +KBRANCH ?= "xlnx_rebase_v5.15_LTS" SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}" FILESOVERRIDES:append = ":${XILINX_RELEASE_VERSION}" KERNELURI ?= "git://github.com/Xilinx/linux-xlnx.git;protocol=https;name=machine" -YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.10;destsuffix=yocto-kmeta" +YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.15;destsuffix=yocto-kmeta" SRC_URI = "${KERNELURI};${SRCBRANCHARG} ${YOCTO_META}" SRCREV_machine ?= "${SRCREV}" -SRCREV_meta ?= "20b185f6b5afbad309747a7901786e0231dc8195" +SRCREV_meta ?= "eeb5d0c9dd5e2928835c633644426ee357fbce12" SRCREV_FORMAT = "machine" require recipes-kernel/linux/linux-yocto.inc diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb deleted file mode 100644 index 660f6037..00000000 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb +++ /dev/null @@ -1,9 +0,0 @@ -LINUX_VERSION = "5.10" -KBRANCH="xlnx_rebase_v5.10" -SRCREV = "568989d44176ae0a38ea78c16d0590c726d3b60a" - -KCONF_AUDIT_LEVEL="0" - -include linux-xlnx.inc - -FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb new file mode 100644 index 00000000..60301f18 --- /dev/null +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2022.1.bb @@ -0,0 +1,9 @@ +LINUX_VERSION = "5.15.19" +KBRANCH="xlnx_rebase_v5.15_LTS" +SRCREV = "b0c1be301e78c320df8c4d93b18393bfd7fd4e9d" + +KCONF_AUDIT_LEVEL="0" + +include linux-xlnx.inc + +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb index 32a8e183..1114a49d 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb @@ -11,9 +11,9 @@ S = "${WORKDIR}/git" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -BRANCH = "xlnx_rel_v2021.2" +BRANCH = "xlnx_rel_v2022.1" REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" -SRCREV = "e208ae31f663af77b1b703b3c038ce7bf812fa83" +SRCREV = "9d2657550eccebccce08cacfcdd369367b9f6be4" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = " \ diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb index 7d37c66a..958183a0 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb @@ -6,9 +6,9 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" XILINX_VCU_VERSION = "1.0.0" PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" -SRCREV = "a9d452e772da6bc43f524230c79e6dc0f2442fd7" +SRCREV = "b3308c608be7ed9250b9c6732f6e0a02b1a2e985" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb index 0a5ab35e..5608e5a8 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb @@ -6,9 +6,9 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" XILINX_VCU_VERSION = "1.0.0" PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" -SRCREV = "372f702dc2983f42d219ce37000eae4b0515ec85" +SRCREV = "5bf158af204b181f00ac009c8745557642ecfe5f" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb index 2c4fc780..0013134d 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb @@ -8,9 +8,9 @@ PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" S = "${WORKDIR}/git" -BRANCH ?= "xlnx_rel_v2021.2" +BRANCH ?= "xlnx_rel_v2022.1" REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" -SRCREV = "17ef70e3a52b972f2c1f821f7b20d2f7af003711" +SRCREV = "569f980527fd58f43baf16bd0b294bf8c7cdf963" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 15ddd0ae..1c2b6819 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -9,7 +9,8 @@ ESW_BRANCH[2020.1] = "release-2020.1" ESW_BRANCH[2020.2] = "master-rel-2020.2" ESW_BRANCH[2021.1] = "xlnx_rel_v2021.1" ESW_BRANCH[2021.2] = "xlnx_rel_v2021.2" -ESW_BRANCH[git] = "xlnx_rel_v2021.2" +ESW_BRANCH[2022.1] = "xlnx_rel_v2022.1" +ESW_BRANCH[git] = "xlnx_rel_v2022.1" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[2019.1] = "26c14d9861010a0e3a55c73fb79efdb816eb42ca" @@ -18,7 +19,8 @@ ESW_REV[2020.1] = "338150ab3628a1ea6b06e964b16e712b131882dd" ESW_REV[2020.2] = "2516d5ed8161e16c2813b0e8e4ceac693f23de5c" ESW_REV[2021.1] = "d37a0e8824182597abf31ac3f1087a5321b33ad7" ESW_REV[2021.2] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" -ESW_REV[git] = "49c6694fc3cab6b87dd564da58a83bb8656a7c03" +ESW_REV[2022.1] = "b3d8b420b421730ea505da55b42174dc90f885c1" +ESW_REV[git] = "b3d8b420b421730ea505da55b42174dc90f885c1" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" @@ -31,7 +33,7 @@ LIC_FILES_CHKSUM[release-2020.1] = '8b565227e1264d677db8f841c2948cba' LIC_FILES_CHKSUM[master-rel-2020.2] = '3a6e22aebf6516f0f74a82e1183f74f8' LIC_FILES_CHKSUM[xlnx_rel_v2021.1] = "73e8997d53c2137fdeea4331a73f40fa" LIC_FILES_CHKSUM[xlnx_rel_v2021.2] = 'ba23909a4bcaf754a2e1ba996f1ca1b0' -LIC_FILES_CHKSUM[master] = '593ba3fb8be51271097ddaa4b9c65cde' +LIC_FILES_CHKSUM[xlnx_rel_v2022.1] = 'e62cb7a722c4430999e0a55a7234035d' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" diff --git a/meta-xilinx-standalone/conf/layer.conf b/meta-xilinx-standalone/conf/layer.conf index 31db64a0..f7ebaca4 100644 --- a/meta-xilinx-standalone/conf/layer.conf +++ b/meta-xilinx-standalone/conf/layer.conf @@ -16,4 +16,4 @@ LAYERDEPENDS_xilinx-standalone = "core xilinx" LAYERRECOMMENDS_xilinx-standalone = "xilinx-microblaze" LAYERSERIES_COMPAT_xilinx-standalone = "honister" -XILINX_RELEASE_VERSION = "v2021.2" +XILINX_RELEASE_VERSION = "v2022.1" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.1.bb new file mode 100644 index 00000000..3f9740a0 --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/fsbl-firmware_2022.1.bb @@ -0,0 +1,11 @@ +require fsbl-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://fsbl-fixups.patch \ + " + +# This version does not build for zynq +COMPATIBLE_MACHINE:zynq = "none" diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.1.bb new file mode 100644 index 00000000..cc810241 --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/plm-firmware_2022.1.bb @@ -0,0 +1,16 @@ +require plm-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-versal_fw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.1.bb new file mode 100644 index 00000000..2c554d6d --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/pmu-firmware_2022.1.bb @@ -0,0 +1,16 @@ +require pmu-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-zynqmp_pmufw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-ffunction-sections -fdata-sections -Wall -Wextra -Os -flto -ffat-lto-objects" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} diff --git a/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.1.bb b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.1.bb new file mode 100644 index 00000000..d861fb1c --- /dev/null +++ b/meta-xilinx-standalone/recipes-bsp/embeddedsw/psm-firmware_2022.1.bb @@ -0,0 +1,16 @@ +require psm-firmware.inc + +FILESPATH .= ":${FILE_DIRNAME}/embeddedsw" + +SRC_URI += " \ + file://makefile-skip-copy_bsp.sh.patch \ + file://0001-versal_fw-Fixup-core-makefiles.patch \ + " + +EXTRA_COMPILER_FLAGS = "-g -ffunction-sections -fdata-sections -Wall -Wextra" + +do_compile() { + oe_runmake + + ${MB_OBJCOPY} -O binary ${B}/${ESW_COMPONENT} ${B}/${ESW_COMPONENT}.bin +} -- cgit v1.2.3-54-g00ecf