From 504327c4434edbba831b00af1ec2bd9b96dc726b Mon Sep 17 00:00:00 2001 From: "Addepalli, Siva" Date: Thu, 3 Aug 2023 12:50:53 +0530 Subject: embeddedsw : Updated SRCREV for 2023.2_4127 sw_apps: zynqmp_fsbl: added SDT support dfeofdm: Antenna interleave delay reorder ipipsu: Update the target count sw_services:xilsecure:Fix HMAC security review comments scripts: linker_files: Add bootdata section to R5 linker scripts xilpm: versal_net: server: Fix incorrect PSM RAM size xilpm: versal: server: Fix incorrect PSM RAM size Export each of the memory_order enumerators Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 3a9e9141..871ea843 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" -ESW_REV[2023.2] = "1f847c1f77e107fe1c4ddf25c954f4f4a9207362" +ESW_REV[2023.2] = "45caafc34f34bd84b057cb51ae215a16fe9b88cd" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf