From 49fd83f73c5a2b4e01b0b84ad3f45645b04a0e90 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 2 Apr 2024 12:33:34 -1200 Subject: xen : Updated SRCREV for 2024.1_1391 OpenAMP passthrough to a domU --- meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc b/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc index 6e920348..a3d90596 100644 --- a/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc +++ b/meta-xilinx-virtualization/recipes-extended/xen/xen-xilinx_4.18.inc @@ -1,4 +1,4 @@ -SRCREV = "dbf966453f3f1f06bc8b7f59a5dc3adabdc8f89f" +SRCREV = "a4754372819eb69acb658fc013ad35c4d55bf9a5" XEN_URI = "git://github.com/Xilinx/xen.git;protocol=https" XEN_BRANCH = "xlnx_rebase_4.18" -- cgit v1.2.3-54-g00ecf From 09c83969db898f9833a6187da0e789f7587c50f8 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 3 Apr 2024 16:14:28 +0530 Subject: aie-rt : Updated SRCREV for 2024.1_8819 driver: src: Remove old resource manager code fal: src: rsc: Fix broadcast all bug for Linux backend fal: src: rsc: Add error logs for all resource types --- meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc index 0541a7a3..d6ca7942 100644 --- a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc +++ b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc @@ -3,7 +3,7 @@ SECTION = "libs" REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https" BRANCH ?= "main-aie" -SRCREV ?= "5621d74d5efa99fdddd9eca47de3294804c62c24" +SRCREV ?= "79a3171f7748b4cea2742495c22133f359b35cb5" LICENSE = "BSD-3-Clause" LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897" -- cgit v1.2.3-54-g00ecf From 00cb2c2d0d355c38a9a2a2184e9eb0cfbf689a3e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 3 Apr 2024 18:09:35 +0530 Subject: open-amp : Updated SRCREV for 2024.1_8471 apps: zynqmp_r5: zynqmp: Add default values in case they are missing in BSP --- .../openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb index 01df6033..b19531d8 100644 --- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb @@ -1,5 +1,5 @@ SRCBRANCH ?= "2024" -SRCREV = "f4a7bc0fca5b14bb8fd185918614bcc78ce93028" +SRCREV = "7d39410ad2172be9f339c4ce565ed765ddd8c5c8" BRANCH = "2024" LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505" PV = "${SRCBRANCH}+git${SRCPV}" -- cgit v1.2.3-54-g00ecf From 3b01ab9db664a65f9b065dbb3f9fc55bbf19a8d7 Mon Sep 17 00:00:00 2001 From: Gregory Williams Date: Mon, 1 Apr 2024 11:48:37 -0700 Subject: meta-xilinx-core: ai-engine: Add new FAL Linux compile flag FAL now has a compile switch when compiling for Linux platforms, this change will enable this flag when compiling FAL examples. Signed-off-by: Gregory Williams Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb index 6ac86a1b..e219e480 100644 --- a/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb +++ b/meta-xilinx-core/recipes-bsp/ai-engine/aiefal_1.6.bb @@ -23,7 +23,7 @@ DEPENDS = "libxaiengine" OECMAKE_SOURCEPATH = "${S}/${XAIEFAL_DIR}" -EXTRA_OECMAKE = "-DWITH_TESTS=OFF " +EXTRA_OECMAKE = "-DWITH_TESTS=OFF -DFAL_LINUX=ON " EXTRA_OECMAKE:append = "${@'-DWITH_EXAMPLES=ON' if d.getVar('WITH_EXAMPLES') == 'y' else '-DWITH_EXAMPLES=OFF'}" FILES:${PN}-demos = " \ -- cgit v1.2.3-54-g00ecf From 3b79a719d0e199380eb3756d22fd438f4e26b24e Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Tue, 2 Apr 2024 04:43:23 -0700 Subject: lopper: srcrev update missing one commit form latest d67410d openamp: xlnx: Update model parsing Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend index 6e31d1f0..4a7085bc 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend @@ -1,5 +1,5 @@ SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" -SRCREV = "9e880fa8bad815f01ca8ec4a3e141e5386f012fd" +SRCREV = "d67410d3b39847fb508f5a17e504a3242b2b33c1" FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" -- cgit v1.2.3-54-g00ecf From d59a688a54f219c3b5725a24375e3a39f5088ef7 Mon Sep 17 00:00:00 2001 From: John Toomey Date: Wed, 3 Apr 2024 15:36:31 +0100 Subject: xilinx-bootbin: Add optional data section to BIF Add optional data section to BIF file generation code to be used with version or other information Signed-off-by: John Toomey Signed-off-by: Mark Hatle (cherry picked from commit cdeb46c57358e579be9f1c1be95a544fd0e713e4) Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc | 3 +++ meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc index fff2c7a3..cd6adcef 100644 --- a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc +++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc @@ -4,6 +4,9 @@ BOOTGEN_EXTRA_ARGS += "-dump bh" # specify BIF common attribute for FSBL BIF_COMMON_ATTR ?= "" +# specify BIF optional attributes +BIF_OPTIONAL_DATA ?= "" + #specify BIF partition attributes required for BOOT.bin BIF_FSBL_ATTR ??= "base-pdi plmfw psmfw" BIF_ATF_ATTR ??= "arm-trusted-firmware" diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb index 4c8bfa0e..e0e1e506 100644 --- a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb +++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb @@ -125,6 +125,10 @@ python do_configure() { biffd.write("the_ROM_image:\n") biffd.write("{\n") + if d.getVar("BIF_OPTIONAL_DATA"): + opt_data = d.getVar("BIF_OPTIONAL_DATA") or "" + biffd.write("\toptionaldata { %s }\n" % opt_data) + arch = d.getVar("SOC_FAMILY") bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split() if bifattr: -- cgit v1.2.3-54-g00ecf From d52eb2c02f0f69b927066f70c30010374fdb7d0b Mon Sep 17 00:00:00 2001 From: John Toomey Date: Wed, 3 Apr 2024 15:36:32 +0100 Subject: bootbin-version-string: Add text version file Add a version header file in plain text format required for Versal machines using the optional data field in the BIF file for version information Signed-off-by: John Toomey Signed-off-by: Mark Hatle (cherry picked from commit c6ae24ee38a69e4bcd463337aed43276d70845df) Signed-off-by: Mark Hatle --- .../recipes-bsp/bootbin/bootbin-version-string.bb | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb diff --git a/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb new file mode 100644 index 00000000..af30a17d --- /dev/null +++ b/meta-xilinx-core/recipes-bsp/bootbin/bootbin-version-string.bb @@ -0,0 +1,32 @@ +DESCRIPTION = "Bootbin version file - text format" +SUMMARY = "The BIF file for bootbin requires a version file in a text format" +LICENSE = "MIT" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" + +COMPATIBLE_MACHINE = "^$" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +BOOTBIN_VER_MAIN ?= "" +BOOTBIN_VER_SUFFIX ?= "${@(d.getVar('XILINX_VER_BUILD') or '')[:8] if d.getVar('XILINX_VER_UPDATE') != 'release' and not d.getVar('XILINX_VER_UPDATE').startswith('update') else ''}" +BOOTBIN_VER_FILE = "bootbin-version-string.txt" + +#BOOTBIN_MANIFEST_FILE ?= "bootbin-version-header.manifest" + +inherit deploy image-artifact-names + +python do_configure() { + if d.getVar("BOOTBIN_VER_SUFFIX"): + version = version + "-" + d.getVar("BOOTBIN_VER_SUFFIX") + with open(d.expand("${B}/${BOOTBIN_VER_FILE}"), "w") as f: + f.write(version) +} + +do_deploy() { + install -m 0644 ${B}/${BOOTBIN_VER_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.txt + ln -s ${IMAGE_NAME}.txt ${DEPLOYDIR}/${IMAGE_LINK_NAME}.txt +# install -m 0644 ${B}/${BOOTBIN_MANIFEST_FILE} ${DEPLOYDIR}/${IMAGE_NAME}.manifest +# ln -s ${IMAGE_NAME}.manifest ${DEPLOYDIR}/${IMAGE_LINK_NAME}.manifest +} + +addtask deploy after do_compile -- cgit v1.2.3-54-g00ecf From ce8032d3494807793baf6f752a4de169b0ede0d0 Mon Sep 17 00:00:00 2001 From: saumya garg Date: Wed, 3 Apr 2024 10:17:54 +0530 Subject: xrt, zocl : Update commit id Changelog: Configure both channel IDs for aie_trace & aie_profile (#8038) Fix bug in Edge sw_emu flow (#8044) add cmake definition for linux builds (#8042) Improvements to AIE trace on clients (#8039) Fixing the map operator logic (#8040) Implementation of Hip stream apis (#8018) Hip test tidy up (#8029) Simplifying hip memory APIs interfaces. (#8037) CR-1192489: Memory Module Metric Event IDs are produced in tiles where no Mem Port kernel driver to Linux 6.8 (#8005) Fix on client to correct partition info device query request (#8033) VITIS-11112 HIP Binding: Memory Management. (#7983) Signed-off-by: saumya garg Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 7c2e932c..5c24ffa6 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG};name=xrt" BRANCH= "master" -SRCREV_xrt = "f23d53edd42fea0f0acd08c194b4750ed77127e2" +SRCREV_xrt = "34ceebc40b326aae408f8dc523c785db796e0483" PV = "202320.2.17.0" SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https" -- cgit v1.2.3-54-g00ecf From c09d6fbc6f6eb486498d81aa1f191b4be4767d7a Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 3 Apr 2024 13:56:33 -0600 Subject: dfx_user_dts.bbclass: Make bit or bin or pdi as required input 1. Make bit or bin or pdi as required input for firmware recipes. If bit or bin or pdi of respective soc_family is not included then raise bitbake parse skip recipe errors. 2. Check for absolute dtbo/bin/bit path if any of these files exits in SRC_URI. 3. Skip recipe if both dtbo and dts/dtsi found in SRC_URI. 4. Fix logic to convert from bit to bin for zynqmp or zynq soc family. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../classes-recipe/dfx_user_dts.bbclass | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass index 2b699d9d..188d594b 100644 --- a/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass +++ b/meta-xilinx-core/classes-recipe/dfx_user_dts.bbclass @@ -97,12 +97,15 @@ python() { # Check for valid combination of input files in SRC_URI # Skip recipe if any of the below conditions are not satisfied. - # 1. At least one bit or bin or pdi or dts or dtsi or dtbo should exists. + # 1. At least one bit or bin or pdi should exists. # 2. More than one dtbo. # 3. More than one bit or bin or pdi. # 4. More than one dts and zero dtsi. - # 5. More than one dtsi and zero dts. - if dtsi_found or dtbo_found or bit_found or bin_found or pdi_found: + # 5. More than one dtsi and zero dts + # 6. Both bit and bin exists. + # 7. Both bit or bin and pdi exits. + # 8. Both dts or dtsi and dtbo exists. + if bit_found or bin_found or pdi_found: bb.debug(2, "dtsi or dtbo or bitstream or pdi found in SRC_URI") if bit_found and pdi_found : raise bb.parse.SkipRecipe("Both '.bit' and '.pdi' file found in SRC_URI, this is invalid use case.") @@ -112,8 +115,11 @@ python() { if bit_found and bin_found: raise bb.parse.SkipRecipe("Both '.bit' and '.bin' file found in SRC_URI, either .bit or .bin file is supported but not both.") + + if dtsi_found and dtbo_found: + raise bb.parse.SkipRecipe("Both '.dts or dtsi' and '.dtbo' file found in SRC_URI, either .dts/dtsi or .dtbo file is supported but not both.") else: - raise bb.parse.SkipRecipe("Need one '.dtsi' or '.dtbo' or '.bit' or '.bin' or '.pdi' file added to SRC_URI ") + raise bb.parse.SkipRecipe("Need one '.bit' or '.bin' or '.pdi' file added to SRC_URI.") # Check for valid combination of dtsi and dts files in SRC_URI # Following file combinations are not supported use case. @@ -177,10 +183,11 @@ python devicetree_do_compile:append() { import glob, subprocess, shutil soc_family = d.getVar("SOC_FAMILY") - dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.dtbo'),recursive=True) if os.path.isfile(f)) - bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/*.bin'),recursive=True) if os.path.isfile(f)) + dtbo_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('DTSI_PATH') or '') + '/*.dtbo'),recursive=True) if os.path.isfile(f)) + bin_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIN_PATH') or '') + '/*.bin'),recursive=True) if os.path.isfile(f)) + bit_count = sum(1 for f in glob.iglob((d.getVar('S') + '/' + (d.getVar('BIT_PATH') or '') + '/*.bit'),recursive=True) if os.path.isfile(f)) # Skip devicetree do_compile task if input file is dtbo or bin in SRC_URI - if not dtbo_count and not bin_count: + if not dtbo_count and not bin_count and bit_count: # Convert .bit to .bin format only if dtsi is input. # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit # or .bin format and corresponding file name. Hence we are not doing .bin -- cgit v1.2.3-54-g00ecf From 882bfdfd774038cee740405f5d9a6f5b3a7592b5 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Wed, 3 Apr 2024 13:56:34 -0600 Subject: README.dfx.user.dts.md: Update versal dfx load instructions 1. Update versal dfx static and partial load instructions. 2. Add Versal segmented configuration load instructions. 3. Also update zynqmp logs. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- docs/README.dfx.user.dts.md | 498 ++++++++++++++++++++++++-------------------- 1 file changed, 271 insertions(+), 227 deletions(-) diff --git a/docs/README.dfx.user.dts.md b/docs/README.dfx.user.dts.md index 724c1692..9caf866e 100644 --- a/docs/README.dfx.user.dts.md +++ b/docs/README.dfx.user.dts.md @@ -345,58 +345,59 @@ IMAGE_INSTALL:append = " \ * ZynqMP ``` -yocto-zynqmp-generic:~$ sudo su -yocto-zynqmp-generic:/home/petalinux# cat /proc/interrupts +yocto-zynqmp-generic:~$ cd / +yocto-zynqmp-generic:/$ sudo su +yocto-zynqmp-generic:/# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 - 11: 5820 5482 14979 6981 GICv2 30 Level arch_timer + 11: 3399 4404 3273 3113 GICv2 30 Level arch_timer 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi - 15: 0 0 0 0 GICv2 175 Level arm-pmu - 16: 0 0 0 0 GICv2 176 Level arm-pmu - 17: 0 0 0 0 GICv2 177 Level arm-pmu - 18: 0 0 0 0 GICv2 178 Level arm-pmu - 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc - 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc - 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller - 22: 0 0 0 0 GICv2 88 Level ams-irq - 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon - 24: 366 0 0 0 GICv2 53 Level xuartps - 27: 0 0 0 0 GICv2 156 Level zynqmp-dma - 28: 0 0 0 0 GICv2 157 Level zynqmp-dma - 29: 0 0 0 0 GICv2 158 Level zynqmp-dma - 30: 0 0 0 0 GICv2 159 Level zynqmp-dma - 31: 0 0 0 0 GICv2 160 Level zynqmp-dma - 32: 0 0 0 0 GICv2 161 Level zynqmp-dma - 33: 0 0 0 0 GICv2 162 Level zynqmp-dma - 34: 0 0 0 0 GICv2 163 Level zynqmp-dma - 35: 0 0 0 0 GICv2 109 Level zynqmp-dma - 36: 0 0 0 0 GICv2 110 Level zynqmp-dma - 37: 0 0 0 0 GICv2 111 Level zynqmp-dma - 38: 0 0 0 0 GICv2 112 Level zynqmp-dma - 39: 0 0 0 0 GICv2 113 Level zynqmp-dma - 40: 0 0 0 0 GICv2 114 Level zynqmp-dma - 41: 0 0 0 0 GICv2 115 Level zynqmp-dma - 42: 0 0 0 0 GICv2 116 Level zynqmp-dma - 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller - 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi - 45: 325 0 0 0 GICv2 95 Level eth0, eth0 - 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon - 47: 2798 0 0 0 GICv2 49 Level cdns-i2c - 48: 326 0 0 0 GICv2 50 Level cdns-i2c - 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog - 51: 0 0 0 0 GICv2 151 Level fd4a0000.display - 52: 551 0 0 0 GICv2 81 Level mmc0 - 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] - 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 - 55: 0 0 0 0 zynq-gpio 22 Edge sw19 -IPI0: 51 94 136 48 Rescheduling interrupts -IPI1: 2295 6271 2952 873 Function call interrupts + 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc + 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc + 17: 0 0 0 0 GICv2 88 Level ams-irq + 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon + 19: 0 0 0 0 GICv2 175 Level arm-pmu + 20: 0 0 0 0 GICv2 176 Level arm-pmu + 21: 0 0 0 0 GICv2 177 Level arm-pmu + 22: 0 0 0 0 GICv2 178 Level arm-pmu + 23: 379 0 0 0 GICv2 53 Level xuartps + 26: 0 0 0 0 GICv2 156 Level zynqmp-dma + 27: 0 0 0 0 GICv2 157 Level zynqmp-dma + 28: 0 0 0 0 GICv2 158 Level zynqmp-dma + 29: 0 0 0 0 GICv2 159 Level zynqmp-dma + 30: 0 0 0 0 GICv2 160 Level zynqmp-dma + 31: 0 0 0 0 GICv2 161 Level zynqmp-dma + 32: 0 0 0 0 GICv2 162 Level zynqmp-dma + 33: 0 0 0 0 GICv2 163 Level zynqmp-dma + 34: 0 0 0 0 GICv2 109 Level zynqmp-dma + 35: 0 0 0 0 GICv2 110 Level zynqmp-dma + 36: 0 0 0 0 GICv2 111 Level zynqmp-dma + 37: 0 0 0 0 GICv2 112 Level zynqmp-dma + 38: 0 0 0 0 GICv2 113 Level zynqmp-dma + 39: 0 0 0 0 GICv2 114 Level zynqmp-dma + 40: 0 0 0 0 GICv2 115 Level zynqmp-dma + 41: 0 0 0 0 GICv2 116 Level zynqmp-dma + 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller + 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi + 44: 77 0 0 0 GICv2 95 Level eth0, eth0 + 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon + 46: 2365 0 0 0 GICv2 49 Level cdns-i2c + 47: 326 0 0 0 GICv2 50 Level cdns-i2c + 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog + 50: 0 0 0 0 GICv2 151 Level fd4a0000.display + 51: 551 0 0 0 GICv2 81 Level mmc0 + 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] + 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 + 54: 0 0 0 0 zynq-gpio 22 Edge sw19 +IPI0: 73 69 133 115 Rescheduling interrupts +IPI1: 2590 1426 1711 13134 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 0 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 CPU wake-up interrupts Err: 0 -yocto-zynqmp-generic:/home/petalinux# tree /lib/firmware/ +yocto-zynqmp-generic:/# +yocto-zynqmp-generic:/# tree /lib/firmware/ /lib/firmware/ `-- xilinx `-- zcu111-pl-demo-user-dts @@ -405,83 +406,127 @@ yocto-zynqmp-generic:/home/petalinux# tree /lib/firmware/ `-- zcu111-pl-demo-user-dts.dtbo 2 directories, 3 files -yocto-zynqmp-generic:/home/petalinux# fpgautil -b /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.bin -o /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.dtbo -[ 370.737539] fpga_manager fpga0: writing zcu111-pl-demo-user-dts.bin to Xilinx ZynqMP FPGA Manager -[ 370.960368] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name -[ 370.970508] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid -[ 370.979755] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets -[ 370.989244] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid -[ 370.998947] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0 -[ 371.008449] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0 -[ 371.018398] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_0 -[ 371.028420] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0 -[ 371.038442] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_1 -[ 371.048467] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_2 -[ 371.058487] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0 -[ 371.068852] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ddr4_0 -[ 371.096047] gpio gpiochip3: (a0000000.gpio): not an immutable chip, please consider fixing it! -[ 371.096223] gpio gpiochip4: (a0010000.gpio): not an immutable chip, please consider fixing it! -[ 371.115206] a0030000.serial: ttyUL0 at MMIO 0xa0030000 (irq = 58, base_baud = 0) is a uartlite -[ 371.124178] uartlite a0030000.serial: Runtime PM usage count underflow! -[ 371.133186] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1 -Time taken to load BIN is 409.000000 Milli Seconds +yocto-zynqmp-generic:/# +yocto-zynqmp-generic:/# fpgautil -b /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.bin -o /lib/firmware/xilinx/zcu111-pl-demo-user-dts/zcu111-pl-demo-user-dts.dtbo +[ 86.077583] fpga_manager fpga0: writing zcu111-pl-demo-user-dts.bin to Xilinx ZynqMP FPGA Manager +[ 86.300854] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name +[ 86.311158] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/pid +[ 86.320571] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/resets +[ 86.330230] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/uid +[ 86.340074] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0 +[ 86.349574] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0 +[ 86.359510] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_0 +[ 86.369526] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0 +[ 86.379544] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_1 +[ 86.389561] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_2 +[ 86.399588] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0 +[ 86.409951] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ddr4_0 +[ 86.439309] a0030000.serial: ttyUL0 at MMIO 0xa0030000 (irq = 57, base_baud = 0) is a uartlite +[ 86.456365] uartlite a0030000.serial: Runtime PM usage count underflow! +[ 86.466353] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1 +Time taken to load BIN is 402.000000 Milli Seconds BIN FILE loaded through FPGA manager successfully -yocto-zynqmp-generic:/home/petalinux# +yocto-zynqmp-generic:/# ``` * Versal (DFx Static) ``` -yocto-vck190-dfx-2023:~$ sudo su -root@yocto-vck190-dfx-2023:~# -root@yocto-vck190-dfx-2023:~# fpgautil -o /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.dtbo -[ 257.555571] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config -[ 257.565879] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid -[ 257.574670] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid -[ 257.583599] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0 -[ 257.593434] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR1 -[ 257.603268] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR2 -[ 257.613100] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_axi_bram_ctrl_0 -[ 257.624762] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp1 -[ 257.636589] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp2 -[ 257.648415] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp3 -[ 257.663234] of-fpga-region fpga:fpga-PR0: FPGA Region probed -[ 257.669135] of-fpga-region fpga:fpga-PR1: FPGA Region probed -[ 257.675022] of-fpga-region fpga:fpga-PR2: FPGA Region probed -root@yocto-vck190-dfx-2023:~# +yocto-vck190-versal:/$ sudo su +yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.pdi -o /lib/firmware/xilinx/vck190-dfx-static/vck190-dfx-static.dtbo +[ 110.575263] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config +[ 110.585557] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid +[ 110.594365] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid +[ 110.603307] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0 +[ 110.613152] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR1 +[ 110.623007] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR2 +[ 110.632849] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_axi_bram_ctrl_0 +[ 110.644516] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp1 +[ 110.656351] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp2 +[ 110.668188] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_region_dfx_decoupler_rp3 +[ 110.682762] of-fpga-region fpga:fpga-PR0: FPGA Region probed +[ 110.689956] of-fpga-region fpga:fpga-PR1: FPGA Region probed +[ 110.695890] of-fpga-region fpga:fpga-PR2: FPGA Region probed +Time taken to load BIN is 133.000000 Milli Seconds +BIN FILE loaded through FPGA manager successfully +yocto-vck190-versal:/# ``` * Versal (DFx RP) ``` -root@yocto-vck190-dfx-2023:~# fpgautil -b /lib/firmware/xilinx/vck190-dfx-static/rp1/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.pdi -o /lib/firmware/xilinx/vck190-dfx-static/rp1/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.dtbo -f Partial -n PR0 -[ 273.511455] fpga_manager fpga0: writing vck190-dfx-rp1rm1-dipsw.pdi to Xilinx Versal FPGA Manager -[284052.461]Loading PDI from DDR -[284052.566]Monolithic/Master Device -[284055.847]3.365 ms: PDI initialization time -[284059.809]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700002 -[284065.432]---Loading Partition#: 0x0, Id: 0x103 -[284069.829] 0.033 ms for Partition#: 0x0, Size: 1312 Bytes -[284074.973]---Loading Partition#: 0x1, Id: 0x105 -[284079.344] 0.007 ms for Partition#: 0x1, Size: 160 Bytes -[284084.430]---Loading Partition#: 0x2, Id: 0x205 -[284088.844] 0.049 ms for Partition#: 0x2, Size: 960 Bytes -[284093.887]---Loading Partition#: 0x3, Id: 0x203 -[284098.280] 0.030 ms for Partition#: 0x3, Size: 688 Bytes -[284103.342]---Loading Partition#: 0x4, Id: 0x303 -[284108.863] 1.156 ms for Partition#: 0x4, Size: 209440 Bytes -[284113.052]---Loading Partition#: 0x5, Id: 0x305 -[284117.712] 0.296 ms for Partition#: 0x5, Size: 3536 Bytes -[284122.594]---Loading Partition#: 0x6, Id: 0x403 -[284126.991] 0.034 ms for Partition#: 0x6, Size: 8096 Bytes -[284132.136]---Loading Partition#: 0x7, Id: 0x405 -[284136.507] 0.007 ms for Partition#: 0x7, Size: 160 Bytes -[284141.636]Subsystem PDI Load: Done -[ 273.615503] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/firmware-name -[ 273.627382] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/fpga-bridges -[ 273.636953] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/partial-fpga-config -[ 273.647241] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/rp1_axi_gpio_0 -[ 273.660826] gpio gpiochip1: (a4010000.gpio): not an immutable chip, please consider fixing it! -[ 273.670490] input: pl-gpio-keys as /devices/platform/pl-gpio-keys/input/input0 -Time taken to load BIN is 171.000000 Milli Seconds +yocto-vck190-versal:/$ sudo su +yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.pdi -o /lib/firmware/xilinx/vck190-dfx-rp1rm1-dipsw/vck190-dfx-rp1rm1-dipsw.dtbo -f Partial -n PR0 +[ 154.155127] fpga_manager fpga0: writing vck190-dfx-rp1rm1-dipsw.pdi to Xilinx Versal FPGA Manager +[173465.709]Loading PDI from DDR +[173465.800]Monolithic/Master Device +[173469.235]3.520 ms: PDI initialization time +[173473.045]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700002 +[173478.669]---Loading Partition#: 0x0, Id: 0x103 +[173483.052] 0.032 ms for Partition#: 0x0, Size: 1264 Bytes +[173488.219]---Loading Partition#: 0x1, Id: 0x203 +[173492.599] 0.030 ms for Partition#: 0x1, Size: 672 Bytes +[173497.682]---Loading Partition#: 0x2, Id: 0x303 +[173503.193] 1.159 ms for Partition#: 0x2, Size: 204960 Bytes +[173507.400]---Loading Partition#: 0x3, Id: 0x403 +[173511.805] 0.054 ms for Partition#: 0x3, Size: 8400 Bytes +[173516.979]Subsystem PDI Load: Done +[ 154.220425] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/rp1_axi_gpio_0 +[ 154.239592] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input1 +Time taken to load BIN is 99.000000 Milli Seconds BIN FILE loaded through FPGA manager successfully -root@yocto-vck190-dfx-2023:~# +yocto-vck190-versal:/# +``` +* Versal (Segmented Configuration) +``` +yocto-vck190-versal:/$ sudo su +yocto-vck190-versal:/# fpgautil -b /lib/firmware/xilinx/vck190-dfx-full/vck190-dfx-full.pdi -o /lib/firmware/xilinx/vck190-dfx-full/vck190-dfx-full.dtbo +[ 642.857986] fpga_manager fpga0: writing vck190-dfx-full.pdi to Xilinx Versal FPGA Manager +[653673.622]Loading PDI from DDR +[653673.713]Monolithic/Master Device +[653677.159]3.531 ms: PDI initialization time +[653680.973]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700001 +[653686.608]---Loading Partition#: 0x0, Id: 0x103 +[653705.058] 14.091 ms for Partition#: 0x0, Size: 22176 Bytes +[653707.626]---Loading Partition#: 0x1, Id: 0x105 +[653712.243] 0.264 ms for Partition#: 0x1, Size: 4784 Bytes +[653717.183]---Loading Partition#: 0x2, Id: 0x205 +[653725.148] 3.608 ms for Partition#: 0x2, Size: 64368 Bytes +[653727.632]---Loading Partition#: 0x3, Id: 0x203 +[653732.018] 0.030 ms for Partition#: 0x3, Size: 672 Bytes +[653737.107]---Loading Partition#: 0x4, Id: 0x303 +[653768.983] 27.516 ms for Partition#: 0x4, Size: 1115456 Bytes +[653771.723]---Loading Partition#: 0x5, Id: 0x305 +[653777.150] 1.068 ms for Partition#: 0x5, Size: 69056 Bytes +[653781.371]---Loading Partition#: 0x6, Id: 0x403 +[653785.892] 0.166 ms for Partition#: 0x6, Size: 242320 Bytes +[653791.103]---Loading Partition#: 0x7, Id: 0x405 +ERR PldMemCtrlrMap: 0x490E +ERR PldInitNode: 0xFFFF +ERR XPm_InitNode: 0xFFFF +ALERT XPm_ProcessCmd: Error 0x15 while processing command 0xC023E +ALERT XPm_ProcessCmd: Err Code: 0x15 +[653811.158]CMD: 0x000C023E execute failed, Processed Cdo Length 0x129C +[653817.390]CMD Payload START, Len:0x00000008 + 0x00000000F20012C0: 0x18700001 0x0000000A 0xF6110000 0x00000002 + 0x00000000F20012CC: 0x00000000 0x00000000 0x80000000 0x00000000 + 0x00000000F20012DC: +[653834.800]CMD Payload END +[653837.277]Error loading PL data: +CFU_ISR: 0x00000000, CFU_STATUS: 0x00002A8C +PMC ERR1: 0x00000000, PMC ERR2: 0x00000000 +[653848.127]PLM Error Status: 0x223E0015 +[65 851.704]XPlm _IpiDispatehHandl0:: Error:hIPI crmmand faileddfor tommanA ID: 0x1000701 +[653859.465]PLM Error Status: 0x27010015 +[ 643.063905] fpga_region region0: failed to load FPGA image +[ 643.069420] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/firmware-name +[ 643.079075] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/pid +[ 643.087857] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/uid +[ 643.096849] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_bram_ctrl_0 +[ 643.107288] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_dip_sw +[ 643.117729] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_led +[ 643.127906] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_gpio_pb +[ 643.137996] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_uartlite_0 +[ 643.178340] 20100000000.serial: ttyUL0 at MMIO 0x20100000000 (irq = 41, base_baud = 0) is a uartlite +[ 643.189536] uartlite 20100000000.serial: Runtime PM usage count underflow! +[ 643.198059] input: axi:pl-gpio-keys as /devices/platform/axi/axi:pl-gpio-keys/input/input0 +yocto-vck190-versal:/# ``` --- @@ -491,134 +536,133 @@ root@yocto-vck190-dfx-2023:~# * Verify PL GPIO DIP switches and Push buttons are registered. * Move the DIP Switches ON/OFF and verify the interrupt counts. ``` -yocto-zynqmp-generic:/home/petalinux# cat /proc/interrupts +yocto-zynqmp-generic:/# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 - 11: 7674 7136 20210 8226 GICv2 30 Level arch_timer + 11: 4254 6509 4214 4236 GICv2 30 Level arch_timer 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi - 15: 0 0 0 0 GICv2 175 Level arm-pmu - 16: 0 0 0 0 GICv2 176 Level arm-pmu - 17: 0 0 0 0 GICv2 177 Level arm-pmu - 18: 0 0 0 0 GICv2 178 Level arm-pmu - 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc - 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc - 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller - 22: 0 0 0 0 GICv2 88 Level ams-irq - 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon - 24: 1143 0 0 0 GICv2 53 Level xuartps - 27: 0 0 0 0 GICv2 156 Level zynqmp-dma - 28: 0 0 0 0 GICv2 157 Level zynqmp-dma - 29: 0 0 0 0 GICv2 158 Level zynqmp-dma - 30: 0 0 0 0 GICv2 159 Level zynqmp-dma - 31: 0 0 0 0 GICv2 160 Level zynqmp-dma - 32: 0 0 0 0 GICv2 161 Level zynqmp-dma - 33: 0 0 0 0 GICv2 162 Level zynqmp-dma - 34: 0 0 0 0 GICv2 163 Level zynqmp-dma - 35: 0 0 0 0 GICv2 109 Level zynqmp-dma - 36: 0 0 0 0 GICv2 110 Level zynqmp-dma - 37: 0 0 0 0 GICv2 111 Level zynqmp-dma - 38: 0 0 0 0 GICv2 112 Level zynqmp-dma - 39: 0 0 0 0 GICv2 113 Level zynqmp-dma - 40: 0 0 0 0 GICv2 114 Level zynqmp-dma - 41: 0 0 0 0 GICv2 115 Level zynqmp-dma - 42: 0 0 0 0 GICv2 116 Level zynqmp-dma - 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller - 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi - 45: 485 0 0 0 GICv2 95 Level eth0, eth0 - 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon - 47: 2798 0 0 0 GICv2 49 Level cdns-i2c - 48: 326 0 0 0 GICv2 50 Level cdns-i2c - 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog - 51: 0 0 0 0 GICv2 151 Level fd4a0000.display - 52: 551 0 0 0 GICv2 81 Level mmc0 - 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] - 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 - 55: 0 0 0 0 zynq-gpio 22 Edge sw19 - 59: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N - 60: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E - 61: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S - 62: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W - 63: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C - 64: 0 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 - 65: 0 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 - 66: 0 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 - 67: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 - 68: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 - 69: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 - 70: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 - 71: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 -IPI0: 64 106 160 56 Rescheduling interrupts -IPI1: 2712 6721 3259 998 Function call interrupts + 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc + 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc + 17: 0 0 0 0 GICv2 88 Level ams-irq + 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon + 19: 0 0 0 0 GICv2 175 Level arm-pmu + 20: 0 0 0 0 GICv2 176 Level arm-pmu + 21: 0 0 0 0 GICv2 177 Level arm-pmu + 22: 0 0 0 0 GICv2 178 Level arm-pmu + 23: 579 0 0 0 GICv2 53 Level xuartps + 26: 0 0 0 0 GICv2 156 Level zynqmp-dma + 27: 0 0 0 0 GICv2 157 Level zynqmp-dma + 28: 0 0 0 0 GICv2 158 Level zynqmp-dma + 29: 0 0 0 0 GICv2 159 Level zynqmp-dma + 30: 0 0 0 0 GICv2 160 Level zynqmp-dma + 31: 0 0 0 0 GICv2 161 Level zynqmp-dma + 32: 0 0 0 0 GICv2 162 Level zynqmp-dma + 33: 0 0 0 0 GICv2 163 Level zynqmp-dma + 34: 0 0 0 0 GICv2 109 Level zynqmp-dma + 35: 0 0 0 0 GICv2 110 Level zynqmp-dma + 36: 0 0 0 0 GICv2 111 Level zynqmp-dma + 37: 0 0 0 0 GICv2 112 Level zynqmp-dma + 38: 0 0 0 0 GICv2 113 Level zynqmp-dma + 39: 0 0 0 0 GICv2 114 Level zynqmp-dma + 40: 0 0 0 0 GICv2 115 Level zynqmp-dma + 41: 0 0 0 0 GICv2 116 Level zynqmp-dma + 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller + 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi + 44: 146 0 0 0 GICv2 95 Level eth0, eth0 + 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon + 46: 2365 0 0 0 GICv2 49 Level cdns-i2c + 47: 326 0 0 0 GICv2 50 Level cdns-i2c + 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog + 50: 0 0 0 0 GICv2 151 Level fd4a0000.display + 51: 551 0 0 0 GICv2 81 Level mmc0 + 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] + 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 + 54: 0 0 0 0 zynq-gpio 22 Edge sw19 + 58: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N + 59: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E + 60: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S + 61: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W + 62: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C + 63: 0 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 + 64: 0 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 + 65: 0 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 + 66: 0 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 + 67: 0 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 + 68: 0 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 + 69: 0 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 + 70: 0 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 +IPI0: 77 79 141 123 Rescheduling interrupts +IPI1: 2621 1536 1782 13236 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 0 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 CPU wake-up interrupts Err: 0 -yocto-zcu111-zynqmp:/home/petalinux# -yocto-zcu111-zynqmp:/home/petalinux# cat /proc/interrupts +yocto-zynqmp-generic:/# +yocto-zynqmp-generic:/# +yocto-zynqmp-generic:/# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 - 11: 8530 7717 22106 8626 GICv2 30 Level arch_timer + 11: 4972 7894 4568 4673 GICv2 30 Level arch_timer 14: 0 0 0 0 GICv2 67 Level zynqmp-ipi - 15: 0 0 0 0 GICv2 175 Level arm-pmu - 16: 0 0 0 0 GICv2 176 Level arm-pmu - 17: 0 0 0 0 GICv2 177 Level arm-pmu - 18: 0 0 0 0 GICv2 178 Level arm-pmu - 19: 0 0 0 0 GICv2 58 Level ffa60000.rtc - 20: 0 0 0 0 GICv2 59 Level ffa60000.rtc - 21: 0 0 0 0 GICv2 42 Level ff960000.memory-controller - 22: 0 0 0 0 GICv2 88 Level ams-irq - 23: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon - 24: 1234 0 0 0 GICv2 53 Level xuartps - 27: 0 0 0 0 GICv2 156 Level zynqmp-dma - 28: 0 0 0 0 GICv2 157 Level zynqmp-dma - 29: 0 0 0 0 GICv2 158 Level zynqmp-dma - 30: 0 0 0 0 GICv2 159 Level zynqmp-dma - 31: 0 0 0 0 GICv2 160 Level zynqmp-dma - 32: 0 0 0 0 GICv2 161 Level zynqmp-dma - 33: 0 0 0 0 GICv2 162 Level zynqmp-dma - 34: 0 0 0 0 GICv2 163 Level zynqmp-dma - 35: 0 0 0 0 GICv2 109 Level zynqmp-dma - 36: 0 0 0 0 GICv2 110 Level zynqmp-dma - 37: 0 0 0 0 GICv2 111 Level zynqmp-dma - 38: 0 0 0 0 GICv2 112 Level zynqmp-dma - 39: 0 0 0 0 GICv2 113 Level zynqmp-dma - 40: 0 0 0 0 GICv2 114 Level zynqmp-dma - 41: 0 0 0 0 GICv2 115 Level zynqmp-dma - 42: 0 0 0 0 GICv2 116 Level zynqmp-dma - 43: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller - 44: 5938 0 0 0 GICv2 47 Level ff0f0000.spi - 45: 527 0 0 0 GICv2 95 Level eth0, eth0 - 46: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon - 47: 2798 0 0 0 GICv2 49 Level cdns-i2c - 48: 326 0 0 0 GICv2 50 Level cdns-i2c - 50: 0 0 0 0 GICv2 84 Edge ff150000.watchdog - 51: 0 0 0 0 GICv2 151 Level fd4a0000.display - 52: 551 0 0 0 GICv2 81 Level mmc0 - 53: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] - 54: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 - 55: 0 0 0 0 zynq-gpio 22 Edge sw19 - 59: 2 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N - 60: 4 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E - 61: 6 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S - 62: 4 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W - 63: 2 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C - 64: 20 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 - 65: 20 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 - 66: 2 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 - 67: 8 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 - 68: 4 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 - 69: 2 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 - 70: 2 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 - 71: 2 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 -IPI0: 64 107 160 56 Rescheduling interrupts -IPI1: 2720 6763 3430 998 Function call interrupts + 15: 0 0 0 0 GICv2 58 Level ffa60000.rtc + 16: 0 0 0 0 GICv2 59 Level ffa60000.rtc + 17: 0 0 0 0 GICv2 88 Level ams-irq + 18: 0 0 0 0 GICv2 155 Level axi-pmon, axi-pmon + 19: 0 0 0 0 GICv2 175 Level arm-pmu + 20: 0 0 0 0 GICv2 176 Level arm-pmu + 21: 0 0 0 0 GICv2 177 Level arm-pmu + 22: 0 0 0 0 GICv2 178 Level arm-pmu + 23: 685 0 0 0 GICv2 53 Level xuartps + 26: 0 0 0 0 GICv2 156 Level zynqmp-dma + 27: 0 0 0 0 GICv2 157 Level zynqmp-dma + 28: 0 0 0 0 GICv2 158 Level zynqmp-dma + 29: 0 0 0 0 GICv2 159 Level zynqmp-dma + 30: 0 0 0 0 GICv2 160 Level zynqmp-dma + 31: 0 0 0 0 GICv2 161 Level zynqmp-dma + 32: 0 0 0 0 GICv2 162 Level zynqmp-dma + 33: 0 0 0 0 GICv2 163 Level zynqmp-dma + 34: 0 0 0 0 GICv2 109 Level zynqmp-dma + 35: 0 0 0 0 GICv2 110 Level zynqmp-dma + 36: 0 0 0 0 GICv2 111 Level zynqmp-dma + 37: 0 0 0 0 GICv2 112 Level zynqmp-dma + 38: 0 0 0 0 GICv2 113 Level zynqmp-dma + 39: 0 0 0 0 GICv2 114 Level zynqmp-dma + 40: 0 0 0 0 GICv2 115 Level zynqmp-dma + 41: 0 0 0 0 GICv2 116 Level zynqmp-dma + 42: 0 0 0 0 GICv2 154 Level fd4c0000.dma-controller + 43: 11183 0 0 0 GICv2 47 Level ff0f0000.spi + 44: 265 0 0 0 GICv2 95 Level eth0, eth0 + 45: 0 0 0 0 GICv2 57 Level axi-pmon, axi-pmon + 46: 2365 0 0 0 GICv2 49 Level cdns-i2c + 47: 326 0 0 0 GICv2 50 Level cdns-i2c + 49: 0 0 0 0 GICv2 84 Edge ff150000.watchdog + 50: 0 0 0 0 GICv2 151 Level fd4a0000.display + 51: 551 0 0 0 GICv2 81 Level mmc0 + 52: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci] + 53: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 + 54: 0 0 0 0 zynq-gpio 22 Edge sw19 + 58: 12 0 0 0 gpio-xilinx 4 Edge PL_GPIO_PB_SW9_N + 59: 8 0 0 0 gpio-xilinx 3 Edge PL_GPIO_PB_SW12_E + 60: 8 0 0 0 gpio-xilinx 2 Edge PL_GPIO_PB_SW13_S + 61: 8 0 0 0 gpio-xilinx 1 Edge PL_GPIO_PB_SW10_W + 62: 10 0 0 0 gpio-xilinx 0 Edge PL_GPIO_PB_SW11_C + 63: 2 0 0 0 gpio-xilinx 7 Edge PL_GPIO_DIP_SW7 + 64: 4 0 0 0 gpio-xilinx 6 Edge PL_GPIO_DIP_SW6 + 65: 2 0 0 0 gpio-xilinx 5 Edge PL_GPIO_DIP_SW5 + 66: 2 0 0 0 gpio-xilinx 4 Edge PL_GPIO_DIP_SW4 + 67: 2 0 0 0 gpio-xilinx 3 Edge PL_GPIO_DIP_SW3 + 68: 2 0 0 0 gpio-xilinx 2 Edge PL_GPIO_DIP_SW2 + 69: 2 0 0 0 gpio-xilinx 1 Edge PL_GPIO_DIP_SW1 + 70: 4 0 0 0 gpio-xilinx 0 Edge PL_GPIO_DIP_SW0 +IPI0: 77 79 142 123 Rescheduling interrupts +IPI1: 2641 1596 2011 13239 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts IPI3: 0 0 0 0 CPU stop (for crash dump) interrupts IPI4: 0 0 0 0 Timer broadcast interrupts IPI5: 0 0 0 0 IRQ work interrupts IPI6: 0 0 0 0 CPU wake-up interrupts Err: 0 -yocto-zynqmp-generic:/home/petalinux# +yocto-zynqmp-generic:/# ``` --- @@ -629,11 +673,11 @@ yocto-zynqmp-generic:/home/petalinux# fpgautil -R ``` * Versal (DFx RP) ``` -root@yocto-vck190-dfx-2023:~# fpgautil -R -n PR0 +yocto-vck190-versal:/# fpgautil -R -n PR0 ``` * Versal (DFx Static) ``` -root@yocto-vck190-dfx-2023:~# fpgautil -R -n Full +yocto-vck190-versal:/# fpgautil -R -n Full ``` --- -- cgit v1.2.3-54-g00ecf From d9b70b9917e95850f507cd72523b149ac526042a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 5 Apr 2024 06:02:04 +0530 Subject: dts : Updated SRCREV for 2024.1_6971 versal: Add support for the SE variant of xcvp1002 versal: Add support for the SE variant of xcvm2152 versal: Add support for xcvm2152 --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb index c4fc180e..8cded998 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "c54a1cfb7076aaf8abdfe50e89245b37cdb1c077" +SRCREV ?= "4aba28ff34f571185a4367d2a062d5453eba3159" -- cgit v1.2.3-54-g00ecf From ed1561113032960ef54387067cc7df8d40ae39e2 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Sun, 7 Apr 2024 06:02:07 +0530 Subject: dts : Updated SRCREV for 2024.1_2055 versal: Add support for xqvm1102, xqve2102, xqvp2502, xqvp1052 and xqve2302 versal: Add support for xave2602 and xave2802 versal: SE variants support --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb index 8cded998..0b9d14cb 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "4aba28ff34f571185a4367d2a062d5453eba3159" +SRCREV ?= "9d3ef6718542592cb677cbb625072e15290407f8" -- cgit v1.2.3-54-g00ecf From 3f2d2c64fb46492fe54b8f6bb7442dc462e5b069 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 8 Apr 2024 06:02:09 +0530 Subject: dts : Updated SRCREV for 2024.1_1751 vck190: Add 2g OSPI flash --- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb index 0b9d14cb..2907bbf1 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb @@ -2,5 +2,5 @@ require qemu-devicetrees.inc BRANCH ?= "master" -SRCREV ?= "9d3ef6718542592cb677cbb625072e15290407f8" +SRCREV ?= "b9c88cbfaaa0c8b8be70ea3c74f4cb69fb02a080" -- cgit v1.2.3-54-g00ecf From eae40b3fffd9cf75956405b7e16629dcee68b6f0 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 8 Apr 2024 06:01:40 +0530 Subject: qemu : Updated SRCREV for 2024.1_2095 m25p80: Consider 4byte address for octal ddr mode --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc index ffaf3cdf..2733e01b 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc @@ -1,3 +1,3 @@ XILINX_QEMU_VERSION = "v8.1.0" BRANCH = "master" -SRCREV = "aa05b83770c0cd5a4f7fcbcef7efc806ae2abe9f" +SRCREV = "d522393f8bc2fdb39db7e7563942f571e8aaea7a" -- cgit v1.2.3-54-g00ecf From d43240bc686eed964a88b06d973f188f3eef5b4a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 8 Apr 2024 06:18:13 +0530 Subject: u-boot-xlnx : Updated SRCREV for 2024.1_5819 arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts mtd: spi-nor: Remove SPI_NOR_OCTAL_READ flag soc: zynqmp: Add the IDcode for TEG variant zlib: Remove incorrect ZLIB_VERSION zlib: Port fix for CVE-2016-9841 to U-Boot zlib: Rename write variable to wnext (window write index) zlib: Rename this variable to here (current decoding table entry) configs: versal: Disable the config for spansion flash --- meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc index b919b230..b4ac7998 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2024.1.inc @@ -2,7 +2,7 @@ UBOOT_VERSION = "v2024.01" UBRANCH = "xlnx_rebase_v2024.01" -SRCREV = "12c2fe646e7e98ba98334c75e082cc10faf0413d" +SRCREV = "a64b554a4a7e0c540dd4fbb69bcf765a88d7359f" LICENSE = "GPL-2.0-or-later" LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" -- cgit v1.2.3-54-g00ecf From 48e92abd6e78b45edab34f5502d2c4e3916ff580 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 4 Apr 2024 16:46:28 -0600 Subject: versal-generic.conf: Update QEMU_HW_DTB_PMC Update QEMU_HW_DTB_PMC to use board-versal-pmc-virt.dtb instead of board-versal-pmc-vc-p-a2197-00.dtb as board-versal-pmc-vc-p-a2197-00.dtb dtb targets tenzing board. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-generic.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf index f87dc140..04e9702f 100644 --- a/meta-xilinx-core/conf/machine/versal-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-generic.conf @@ -84,7 +84,7 @@ QB_KERNEL_CMDLINE_APPEND ?= "" QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch" QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb" -QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb" +QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb" QEMU_HW_DTB_PS_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-ps-virt.dtb" QEMU_HW_DTB_PMC_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-pmc-virt.dtb" -- cgit v1.2.3-54-g00ecf From 7063fa8d7e099fa2e9dc277a1b1985c481c05dc3 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 4 Apr 2024 16:46:29 -0600 Subject: versal-prime-generic: Fix QEMU PLM boot issue QEMU PLM error code are observed as shown below. [13422.262]**************************************** [13422.490]Xilinx Versal Platform Loader and Manager [13422.508]Release 2024.1 Mar 30 2024 - 14:13:53 [13422.562]Platform Version: v0.0 PMC: v0.0, PS: v0.0 [13422.588]BOOTMODE: 0x5, MULTIBOOT: 0xF0000000 [13422.608]**************************************** [13427.899]Non Secure Boot [13441.028]PLM Initialization Time [13441.090]***********Boot PDI Load: Started*********** [13441.191]Loading PDI from SD1 [13441.218]Monolithic/Master Device [14850.660]1409.510 ms: PDI initialization time [14850.719]+++Loading Image#: 0x1, Name: lpd, Id: 0x04210002 [14850.755]---Loading Partition#: 0x1, Id: 0xC [14892.625] 41.831 ms for Partition#: 0x1, Size: 11360 Bytes [14893.706]---Loading Partition#: 0x2, Id: 0x0 [14902.163] 7.679 ms for Partition#: 0x2, Size: 65104 Bytes PSM Firmware version: 2024.1 [Build: Mar 30 2024 14:13:53 ] [15013.595]+++Loading Image#: 0x2, Name: pl_cfi, Id: 0x18700000 [15014.589]---Loading Partition#: 0x3, Id: 0x3 [21947.779]Polling 0xF11A0000 Mask: 0xFFFFFFFF ExpectedValue: 0x14CAA093 [21949.039]MaskPoll: Addr: 0x0F11A0000, Mask: 0xFFFFFFFF, ExpVal: 0x14CAA093, Timeout: 1000000, RegVal: 0x14CA8093 ...ERROR [21951.067]CMD: 0x00040101 execute failed, Processed Cdo Length 0x84 [21952.260]CMD Payload START, Len:0x00000004 0x00000000F20000A8: 0xF11A0000 0xFFFFFFFF 0x14CAA093 0x00000001 0x00000000F20000B4: [21954.516]CMD Payload END [21955.035]Error loading PL data: CFU_ISR: 0x00000000, CFU_STATUS: 0x0000080C PMC ERR1: 0x00000000, PMC ERR2: 0x00000000 [21957.810]PLM Error Status: 0x21010001 [21958.489]============Register Dump============ [21959.269]PMC_TAP_IDCODE: 0x14CA8093 [21959.887]EFUSE_CACHE_IP_DISABLE_0(EXTENDED IDCODE): 0x00004000 [21960.901]PMC_TAP_VERSION: 0x03000000 [21961.516]CRP_BOOT_MODE_USER: 0x00000005 [21962.179]CRP_BOOT_MODE_POR: 0x00000005 [21962.823]CRP_RESET_REASON: 0x00000202 [21963.462]PMC_GLOBAL_PMC_MULTI_BOOT: 0xF0000000 [21964.242]PMC_GLOBAL_PWR_STATUS: 0x00000000 [21964.946]PMC_GLOBAL_PMC_GSW_ERR: 0x00000000 [21965.666]PMC_GLOBAL_PLM_ERR: 0x00000000 [21966.342]PMC_GLOBAL_PMC_ERR1_STATUS: 0x00000000 [21967.136]PMC_GLOBAL_PMC_ERR2_STATUS: 0x00000000 [21967.917]PMC_GLOBAL_GICP0_IRQ_STATUS: 0x20000000 [21968.713]PMC_GLOBAL_GICP1_IRQ_STATUS: 0x00000000 [21969.507]PMC_GLOBAL_GICP2_IRQ_STATUS: 0x00000000 [21970.307]PMC_GLOBAL_GICP3_IRQ_STATUS: 0x00000000 [21971.113]PMC_GLOBAL_GICP4_IRQ_STATUS: 0x00000000 [21971.921]PMC_GLOBAL_GICP_PMC_IRQ_STATUS: 0x00000000 [21972.767]============Register Dump============ This is due to default QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for VMK180 machine conf file. Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to board-versal-ps-vmk180.dtb. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-prime-generic.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meta-xilinx-core/conf/machine/versal-prime-generic.conf b/meta-xilinx-core/conf/machine/versal-prime-generic.conf index 94e9b05e..206f0e2a 100644 --- a/meta-xilinx-core/conf/machine/versal-prime-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-prime-generic.conf @@ -6,6 +6,8 @@ require conf/machine/versal-generic.conf SOC_VARIANT = "prime" +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vmk180.dtb" + #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_prime_generic']['versal-prime-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From bc989ba4a8c21b7c60959335e47ed97fa3b1a9b3 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 4 Apr 2024 16:46:30 -0600 Subject: README.sdt.bsp.md: Add system device tree bsp README Add system device tree bsp README which provide BSP settings such as QEMU PMC/PMU DTB, QEMU PS DTB etc. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../README.sdt.bsp.md | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 meta-xilinx-standalone-experimental/README.sdt.bsp.md diff --git a/meta-xilinx-standalone-experimental/README.sdt.bsp.md b/meta-xilinx-standalone-experimental/README.sdt.bsp.md new file mode 100644 index 00000000..d87550d3 --- /dev/null +++ b/meta-xilinx-standalone-experimental/README.sdt.bsp.md @@ -0,0 +1,39 @@ +# SDT BSP + +This section describes the SDT BSP settings which must be added to the generated +machine configuration file, following [Build Instructions](README.md) step 4, in +order to use the runqemu command. + +## SDT BSP settings + +The following board settings need to be added in sdt machine configuration file +to define which QEMU device trees should be used. + +> **Variable usage examples:** +> +> QEMU Device tree deploy directory: `QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch"` +> +> QEMU PMU Device tree: `QEMU_HW_DTB_PMU = "${QEMU_HW_DTB_PATH}/zynqmp-pmu.dtb"` +> +> QEMU PMC Device tree: `QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"` +> +> QEMU PS Board Device tree: `QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"` + +| Devices | Evaluation Board | QEMU PMC or PMU DTB file | QEMU PS DTB file | +|------------|-------------------------------------------------------------------------------|-----------------------------|-------------------------------| +| ZynqMP | [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| | [ZCU670](https://www.xilinx.com/products/boards-and-kits/zcu670.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | +| Versal | [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vck190.dtb` | +| | [VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vmk180.dtb` | +| | [VPK120](https://www.xilinx.com/products/boards-and-kits/vpk120.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk120.dtb` | +| | [VPK180](https://www.xilinx.com/products/boards-and-kits/vpk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk180.dtb` | +| | [VEK280](https://www.xilinx.com/products/boards-and-kits/vek280.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vek280.dtb` | +| | [VHK158](https://www.xilinx.com/products/boards-and-kits/vhk158.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vhk158.dtb` | + +> **Note:** Additional information on Xilinx architectures can be found at: + https://www.xilinx.com/products/silicon-devices.html -- cgit v1.2.3-54-g00ecf From 5f12f5fde5a6f736182cc0cd4c1bc99d18107f42 Mon Sep 17 00:00:00 2001 From: Onkar Harsh Date: Sat, 6 Apr 2024 18:07:18 +0530 Subject: lopper: Update SRCREV for lopper The SRCREV update contains below commits: assists: generate_config_object: Enable user-driven customization of library options assists: generate_config_object: Addressed the scenario where, not all masters are reset masters lopper:assists:baremetallinker: Do not consider linear SPIs for memory tests lopper:assists:gen_domain_dts: Remove axi_noc and noc_ddr4 IPs from linux ignore list base: add expression to clock phandle description Signed-off-by: Onkar Harsh Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend index 4a7085bc..e9a1191d 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend @@ -1,5 +1,5 @@ SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" -SRCREV = "d67410d3b39847fb508f5a17e504a3242b2b33c1" +SRCREV = "326ea3bf2d689513ed0cf07a68a79a6845db057b" FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" -- cgit v1.2.3-54-g00ecf From 033b64ae5220a4dc50fc1464f6919ff936a47eb2 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 8 Apr 2024 13:44:29 -0600 Subject: versal-hbm-generic: Fix QEMU boot issue VHK158 SDT QEMU doesn't come up with PLM, this to default QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for VHK158 machine conf file. Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to board-versal-ps-vmk158.dtb and also adjust the QB_MEM to 32GB as versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM for QEMU boot. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-hbm-generic.conf | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf index 23fffcb9..3e72da60 100644 --- a/meta-xilinx-core/conf/machine/versal-hbm-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-hbm-generic.conf @@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf SOC_VARIANT = "hbm" +# VHK158 has 32GB memory only but default versal-generic has QB_MEM set to 8G, +# Since versal-vhk158-reva.dts has 32GB set, we need set same in QB_MEM +QB_MEM = "-m 32G" + +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vhk158.dtb" + #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_hbm_generic']['versal-hbm-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From 2d98ceee2b3b66220f77bf18b92c24fe73843569 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 8 Apr 2024 15:51:16 -0600 Subject: README.sdt.bsp.md: Update README with QB_MEM info Update README with QB_MEM info to boot QEMU using SDT builds. Also fix typo in README. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- .../README.sdt.bsp.md | 41 +++++++++++++--------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/meta-xilinx-standalone-experimental/README.sdt.bsp.md b/meta-xilinx-standalone-experimental/README.sdt.bsp.md index d87550d3..2b2ce4b0 100644 --- a/meta-xilinx-standalone-experimental/README.sdt.bsp.md +++ b/meta-xilinx-standalone-experimental/README.sdt.bsp.md @@ -15,25 +15,32 @@ to define which QEMU device trees should be used. > > QEMU PMU Device tree: `QEMU_HW_DTB_PMU = "${QEMU_HW_DTB_PATH}/zynqmp-pmu.dtb"` > -> QEMU PMC Device tree: `QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"` +> QEMU PS Device tree: `QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"` > -> QEMU PS Board Device tree: `QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"` +> QEMU PMC Board Device tree: `QEMU_HW_DTB_PMC = "${QEMU_HW_DTB_PATH}/board-versal-pmc-virt.dtb"` +> +> QEMU Memory: Some boards for example VEK280 and VH158 memory configurations are +> different, Hence we need to adjust the same in QB_MEM to match board dtsi files. +> Below are some examples. +> * ZynqMP `QB_MEM = "-m 4096"` +> * Versal VEK280 `QB_MEM = "-m 12G"` + -| Devices | Evaluation Board | QEMU PMC or PMU DTB file | QEMU PS DTB file | -|------------|-------------------------------------------------------------------------------|-----------------------------|-------------------------------| -| ZynqMP | [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| | [ZCU670](https://www.xilinx.com/products/boards-and-kits/zcu670.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | -| Versal | [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vck190.dtb` | -| | [VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vmk180.dtb` | -| | [VPK120](https://www.xilinx.com/products/boards-and-kits/vpk120.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk120.dtb` | -| | [VPK180](https://www.xilinx.com/products/boards-and-kits/vpk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk180.dtb` | -| | [VEK280](https://www.xilinx.com/products/boards-and-kits/vek280.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vek280.dtb` | -| | [VHK158](https://www.xilinx.com/products/boards-and-kits/vhk158.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vhk158.dtb` | +| Devices | Evaluation Board | QEMU PMC or PMU DTB file | QEMU PS DTB file | QB Mem | +|---------|-------------------------------------------------------------------------------|-----------------------------|-------------------------------|--------| +| ZynqMP | [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| | [ZCU670](https://www.xilinx.com/products/boards-and-kits/zcu670.html) | `zynqmp-pmu.dtb` | `zcu102-arm.dtb` | 4096 | +| Versal | [VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vck190.dtb` | 8G | +| | [VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vmk180.dtb` | 8G | +| | [VPK120](https://www.xilinx.com/products/boards-and-kits/vpk120.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk120.dtb` | 8G | +| | [VPK180](https://www.xilinx.com/products/boards-and-kits/vpk180.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vpk180.dtb` | 8G | +| | [VEK280](https://www.xilinx.com/products/boards-and-kits/vek280.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vek280.dtb` | 12G | +| | [VHK158](https://www.xilinx.com/products/boards-and-kits/vhk158.html) | `board-versal-pmc-virt.dtb` | `board-versal-ps-vhk158.dtb` | 32G | > **Note:** Additional information on Xilinx architectures can be found at: https://www.xilinx.com/products/silicon-devices.html -- cgit v1.2.3-54-g00ecf From 54a1ee1b26975e53ef406ec57daf6187abc5f496 Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Mon, 8 Apr 2024 13:44:31 -0600 Subject: versal-ai-edge-generic: Fix QEMU boot issue VEK280 SDT QEMU doesn't come up with PLM, this to default QEMU_HW_DTB_PS used from versal-generic.conf file doesn't work for VEK280 machine conf file. Fix QEMU PLM boot issue by setting the right QEMU_HW_DTB_PS to board-versal-ps-vek280.dtb and also adjust the QB_MEM to 12GB to match with board dtsi file, we need set same in QB_MEM for QEMU boot. Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf index bf5523ed..1028ac04 100644 --- a/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf +++ b/meta-xilinx-core/conf/machine/versal-ai-edge-generic.conf @@ -6,6 +6,12 @@ require conf/machine/versal-generic.conf SOC_VARIANT = "ai-edge" +# VEK280 board has 12GB memory only but default versal-generic has QB_MEM set to +# 8G, Hence we need set 12G in QB_MEM. +QB_MEM = "-m 12G" + +QEMU_HW_DTB_PS = "${QEMU_HW_DTB_PATH}/board-versal-ps-vek280.dtb" + #### No additional settings should be after the Postamble #### Postamble PACKAGE_EXTRA_ARCHS:append = "${@['', ' versal_ai_edge_generic']['versal-ai-edge-generic' != "${MACHINE}"]}" -- cgit v1.2.3-54-g00ecf From e93a9e6f7e731953c5c576d86010f4ec1b89ae07 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 10 Apr 2024 06:14:40 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_8591 Updated sysmonpsv to 4.2 Revert "sysmonpsv: Added SSIT Support" BSP: riscv: Fix FPU context handling in trap handler vphy: Added support for DP2.1 sw_services:xilocp:Fix review comments for XOcp_DmeXppuConfig sw_services:xilloader:Fixed doxygen comments format TPG: Addition of bool library in header file bsp: cortexr52: Use PMU as default timer for Cortex-R52 sw_services: xilplmi: Fix MISRA-C violation 8.6 sw_services: xilplmi: Fix MISRA-C violation 2.2 sw_services: xilplmi: Fix MISRA-C violation 17.8 sw_services: xilplmi: Fix MISRA-C violation 10.3 mipicsiss: example: update GPIO address. sw_apps: zynqmp_pmufw: Correct typo for SOM specific macro dp21: Fix linking issues in C++ dp14: Fix linking issues in C++ dp12: Fix linking issues in C++ rfdc: NCO Frequency xilplmi: added CDO debug prints intc: Fix xintc_low_level_example for HW designs with fast interrupts --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 17e26446..74de7ea6 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" -ESW_REV[2024.1] = "827c36863db8e94c1b46e1f40fbc636467913589" +ESW_REV[2024.1] = "18910bd57542d5b3cdc04e4442e565e065685e88" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf From c01790e541f5fa37c8053bafff08a1805358753b Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 10 Apr 2024 06:21:41 +0530 Subject: aie-rt : Updated SRCREV for 2024.1_2471 driver:src:Softpartition boundary Isolation fixed --- meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc index d6ca7942..a59ef469 100644 --- a/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc +++ b/meta-xilinx-core/recipes-bsp/ai-engine/aie-rt.inc @@ -3,7 +3,7 @@ SECTION = "libs" REPO ?= "git://github.com/Xilinx/aie-rt.git;protocol=https" BRANCH ?= "main-aie" -SRCREV ?= "79a3171f7748b4cea2742495c22133f359b35cb5" +SRCREV ?= "c41476c833034259eb760d2a2f7c7118a5be727d" LICENSE = "BSD-3-Clause" LIC_FILES_CHKSUM ?= "file://license.txt;md5=04a153cae61a8a606fc79dff49c2c897" -- cgit v1.2.3-54-g00ecf From 4ea7a9cf93c7345c316babfbbbedb5740bddea88 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 10 Apr 2024 06:17:56 +0530 Subject: linux-xlnx : Updated SRCREV for 2024.1_9495 net: axienet: Correct tx_buff size when DRE is not enabled clk: clocking-wizard: calculate dividers fractional parts v4l: xilinx: dprxss: Fix xhdcp1x_rx_init() function declaration v4l: xilinx: dprxss: Fix gcc warning staging: xilinx_hdcp: Fix gcc warning mtd: spi-nor: Use same bit mask macro in spi & spi-nor core Revert "drivers: clk: zynqmp: add hack to use old algorithm for divider round rate" fpga: Fix the reset handling remoteproc: zynqmp_r5: Clean up support for Versal NET CTCM mtd: spi-nor: Add support for BP3 at SR bit 5 mtd: spi-nor: Use params->size for flash size info mtd: spi-nor: Avoid writing EAR register for flashes less than 16MB mtd: spi-nor: Use nor->info->id[0] for manufacturer id --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb index 8f65469a..6042293b 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb @@ -1,7 +1,7 @@ LINUX_VERSION = "6.6.10" YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" KBRANCH="xlnx_rebase_v6.6_LTS" -SRCREV = "dcac89c7c78a556240e07ac3c6c568dd5be90ef3" +SRCREV = "847d102ca8f60e9f5cd17c685ecb525e6373ca6b" SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From ee20318ad55fcf09e17432160dfe3bc11ffd67f1 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Wed, 10 Apr 2024 15:53:35 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_3975 zynqmp_pmufw: Update FPGA config reg status to use local buf dp21txss: Add support for octa pixel mode dp21txss: Add support for OctaPixel Mode dp21rxss: Add support for OctaPixel Mode dp21: Add support for octa pixel mode dp21: Add support for OctaPixel Mode dp21: Fix C++ warnings dp14: Fix C++ warnings sw_services:xilocp:Fix issue for getting swpcr data sw_services:xilocp: Clear memory buffer after calculating PCR xilplmi: Correct configuration read format for VP1902 device. xilsem: Correct configuration read format for VP1902. i2s: Fix C++ compilation errors sw_services: xilcert: Fixed calculation of hash in serial field xilsecure: fixed header inclusion in SDT flow dfeofdm: Update hw version emacps: Fix HwTail check in XEmacPs_BdRingFromHwRX sw_services:xilnvm:Update validation check during additional PPK programming BSP: riscv: Fix instruction cache APIs dfeprach: Update device node name usbpsu: Add doxygen and editorial fixes sw_services: xilpm: Remove usage of GSW ERROR register in BISR code esw: In SDT flow for the Microblaze processor, include libgloss in the link libraries by default sw_services:xilskey:Add description for XILSKEY_PUF_KEK_REGEN_RDY_TIMEOUT xilpm: versal_common: server: Remove PGGS2 and PGGS3 related code --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 74de7ea6..f959b382 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" -ESW_REV[2024.1] = "18910bd57542d5b3cdc04e4442e565e065685e88" +ESW_REV[2024.1] = "22ca729a1838c0151454948fc99d200351639415" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf From 0e407c67d5138ba82c44b020704d2d17c663f03b Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Mon, 8 Apr 2024 15:45:22 -0700 Subject: lopper: srcrev update openamp: xlnx: versal: match model parsing same as VNET Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend index e9a1191d..9414650a 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend @@ -1,5 +1,5 @@ SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" -SRCREV = "326ea3bf2d689513ed0cf07a68a79a6845db057b" +SRCREV = "4672dd2c63660b327970cb6e0c3b20169e73e04b" FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" -- cgit v1.2.3-54-g00ecf From c9be64c685255f502438c2e134cb7377070935f6 Mon Sep 17 00:00:00 2001 From: saumya garg Date: Wed, 10 Apr 2024 15:00:44 +0530 Subject: xrt, zocl: Update commit id Changelog: Cleanup clangtidy warnings (#8057) Providing a work-around to allocate instruction buffer in HIP (#8047) SC warning fix on RAVE and xsabin extension warning fix on Versal (#8053) aie-status reports fix (#8051) VITIS-11503 - Dump instruction bo created from Elf so verification can be done (#8043) VITIS-11503 - change elf section name from mc_code to control-packet (#8054) Defining Mailbox Macro for QDMA to fix APU crash on RAVE (#8052) revert sdr changes (#8049) ML Timeline Plugin should read timestamp data before AIE Profile/Debug (#8045) Signed-off-by: saumya garg Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 5c24ffa6..f3313631 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG};name=xrt" BRANCH= "master" -SRCREV_xrt = "34ceebc40b326aae408f8dc523c785db796e0483" +SRCREV_xrt = "58cba71cf60f1de1f935a32f0b739d568390b95d" PV = "202320.2.17.0" SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https" -- cgit v1.2.3-54-g00ecf From 4781790929b112ee58bfd8506ac80b81ef479108 Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Wed, 10 Apr 2024 08:02:45 -0700 Subject: lopper: update SRCREV 30bed2b openamp: xlnx: Add vc-p and vn-p models Signed-off-by: Ben Levinsky Signed-off-by: Mark Hatle --- .../virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend index 9414650a..b8da828d 100644 --- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend +++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend @@ -1,5 +1,5 @@ SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=v0.2024.x;protocol=https" -SRCREV = "4672dd2c63660b327970cb6e0c3b20169e73e04b" +SRCREV = "30bed2bbebeae4c190a74a5d6f26f43a62135041" FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" -- cgit v1.2.3-54-g00ecf From 6bcadaed7bc65de94d2579379a7101723e43208f Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 10 Apr 2024 17:01:53 -0500 Subject: Switch from master to xlnx_rel_v2024.1 branch Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb | 2 +- meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb | 2 +- meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb | 2 +- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc | 2 +- meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb | 2 +- meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb | 2 +- meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb | 2 +- meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb index f7e18273..1f1d0606 100644 --- a/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb +++ b/meta-xilinx-core/recipes-apps/image-update/image-update_1.1.bb @@ -6,7 +6,7 @@ SUMMARY = "Image update is used to update alternate image on compatible firmware LICENSE = "MIT" LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSES/MIT;md5=2ac09a7a37dd6ee0ba23ce497d57d09b" -BRANCH = "master" +BRANCH = "xlnx_rel_v2024.1" SRC_URI = "git://github.com/Xilinx/linux-image_update.git;branch=${BRANCH};protocol=https" SRCREV = "a68308f329578d3585fd335071a9184aa7f46d2e" diff --git a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb index b0acf0ef..28f997f2 100644 --- a/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb +++ b/meta-xilinx-core/recipes-bsp/dfx-mgr/dfx-mgr_2024.1.bb @@ -8,7 +8,7 @@ REPO ?= "git://github.com/Xilinx/dfx-mgr.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" -BRANCH = "master" +BRANCH = "xlnx_rel_v2024.1" SRCREV = "ec70363a2a878737057995f922a9460d18aafa26" SOMAJOR = "1" SOMINOR = "0" diff --git a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb index 0cbcaac7..42e67ce6 100644 --- a/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb +++ b/meta-xilinx-core/recipes-bsp/libdfx/libdfx_2024.1.bb @@ -4,7 +4,7 @@ DESCRIPTION = "Xilinx libdfx Library and headers" LICENSE = "MIT & GPL-2.0-or-later" LIC_FILES_CHKSUM = "file://LICENSE.md;md5=94aba86aec117f003b958a52f019f1a7" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/libdfx.git;protocol=https" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" SRC_URI = "${REPO};${BRANCHARG}" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb index 2907bbf1..d10504d3 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2024.1.bb @@ -1,6 +1,6 @@ require qemu-devicetrees.inc -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" SRCREV ?= "b9c88cbfaaa0c8b8be70ea3c74f4cb69fb02a080" diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc index 2733e01b..306006f2 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc @@ -1,3 +1,3 @@ XILINX_QEMU_VERSION = "v8.1.0" -BRANCH = "master" +BRANCH = "xlnx_rel_v2024.1" SRCREV = "d522393f8bc2fdb39db7e7563942f571e8aaea7a" diff --git a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb index db99c4d7..82c411a2 100644 --- a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb +++ b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb @@ -13,7 +13,7 @@ PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https" -BRANCH ?= "xlnx_rel_v2023.2" +BRANCH ?= "xlnx_rel_v2024.1" SRCREV ?= "b3a772aad859cdadc8513b11c3e995546c20e75e" BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb index 17039abb..503cee02 100644 --- a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb +++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_2024.1.bb @@ -9,7 +9,7 @@ PV = "${XLNX_DP_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', Fal S = "${WORKDIR}/git" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/xilinx/dp-modules.git;protocol=https" SRCREV ?= "e20942b256e6fb18eaef919c7441f65ad8afcf43" diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb index 9757ae4b..73a22d30 100644 --- a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb +++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_2024.1.bb @@ -9,7 +9,7 @@ PV = "${XLNX_HDMI_VERSION}+xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', F S = "${WORKDIR}/git" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https" SRCREV = "edd297762e0bac3f4c5b64ef67244968e22020e2" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb index be8f6075..f474595c 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu_2024.1.bb @@ -11,7 +11,7 @@ S = "${WORKDIR}/git" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -BRANCH = "master" +BRANCH = "xlnx_rel_v2024.1" REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https" SRCREV = "91d19a16308a438596138d30d8174e148fc45584" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb index bff19a9c..14226aa7 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx_2024.1.bb @@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd" XILINX_VCU_VERSION = "1.0.0" PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https" SRCREV = "dc34204543b89997577bd2c9757b3c218e6caccc" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb index 8c3df7db..e3f656b0 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx_2024.1.bb @@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.md;md5=002a0a92906100955ea6ed02dcd2c2cd" XILINX_VCU_VERSION = "1.0.0" PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}+git${SRCPV}" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https" SRCREV = "940f9fa933402de6f959911c236f36add5dd3a40" diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb index 69c4d7ef..6ecdc4af 100644 --- a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware_2024.1.bb @@ -8,7 +8,7 @@ PV = "${XILINX_VCU_VERSION}-xilinx-v${@bb.parse.vars_from_file(d.getVar('FILE', S = "${WORKDIR}/git" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https" SRCREV = "6ee1998c53817ab0c137b8b99089337d5caba62c" diff --git a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb index ccbe77a8..84f9cc2a 100644 --- a/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vdu/kernel-module-vdu_2024.1.bb @@ -11,7 +11,7 @@ PV .= "+git${SRCPV}" S = "${WORKDIR}/git" FILESEXTRAPATHS:prepend := "${THISDIR}/files:" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vdu-modules.git;protocol=https" SRCREV ?= "25773344ce1e539e7136c5a30cdee98a6cf490a8" diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb index 5186d4fc..3acbf3ef 100644 --- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-ctrlsw_2024.1.bb @@ -11,7 +11,7 @@ inherit autotools features_check REQUIRED_MACHINE_FEATURES = "vdu" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vdu-ctrl-sw.git;protocol=https" SRCREV ?= "7af131e0780d52ebc7bd6173bf1b99fec4dc522f" diff --git a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb index 91b2a150..5ba604f8 100644 --- a/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vdu/libvdu-omxil_2024.1.bb @@ -7,7 +7,7 @@ XILINX_VDU_VERSION = "1.0.0" PV =. "${XILINX_VDU_VERSION}-xilinx-v" PV .= "+git${SRCPV}" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vdu-omx-il.git;protocol=https" SRCREV ?= "af9c6e8935799f4dcd579b0164dd05eb039b569d" diff --git a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb index 147a80b6..193ea3a5 100644 --- a/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb +++ b/meta-xilinx-core/recipes-multimedia/vdu/vdu-firmware_2024.1.bb @@ -13,7 +13,7 @@ inherit autotools features_check REQUIRED_MACHINE_FEATURES = "vdu" -BRANCH ?= "master" +BRANCH ?= "xlnx_rel_v2024.1" REPO ?= "git://github.com/Xilinx/vdu-firmware.git;protocol=https" SRCREV ?= "724de80630edcb87d865d69f1a6c0dc61c3f9f12" -- cgit v1.2.3-54-g00ecf From 5eb1dcbaa522632f40900972154f9afbb0c5b3d3 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 10 Apr 2024 17:28:36 -0500 Subject: openamp-layer: Move from 2024 to xlnx_rel_v2024.1 Signed-off-by: Mark Hatle --- .../openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb | 2 +- .../openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb index ca447615..b33d5064 100644 --- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/libmetal/libmetal-xlnx_v2024.1.bb @@ -1,6 +1,6 @@ SRCBRANCH ?= "2024" SRCREV = "e2fdb4fecbebe41b4cd1c0b4fbfa3496bcded485" -BRANCH = "2024" +BRANCH = "xlnx_rel_v2024.1" LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=f4d5df0f12dcea1b1a0124219c0dbab4" PV = "${SRCBRANCH}+git${SRCPV}" diff --git a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb index b19531d8..bf779ff5 100644 --- a/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb +++ b/meta-xilinx-core/dynamic-layers/openamp-layer/recipes-openamp/open-amp/open-amp-xlnx_v2024.1.bb @@ -1,6 +1,6 @@ SRCBRANCH ?= "2024" SRCREV = "7d39410ad2172be9f339c4ce565ed765ddd8c5c8" -BRANCH = "2024" +BRANCH = "xlnx_rel_v2024.1" LIC_FILES_CHKSUM ?= "file://LICENSE.md;md5=ab88daf995c0bd0071c2e1e55f3d3505" PV = "${SRCBRANCH}+git${SRCPV}" REPO = "git://github.com/Xilinx/open-amp.git;protocol=https" -- cgit v1.2.3-54-g00ecf From f49b919f82576e6460ffec92621705700bc9cec6 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 12 Apr 2024 06:01:42 +0530 Subject: qemu : Updated SRCREV for 2024.1_4679 fdt_generic_devices: Add phy aliases arm_generic_fdt: Create ethernet phy in postinit fdt_generic_util: Add a postinit call back --- meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc index 306006f2..d48350b2 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-2024.1.inc @@ -1,3 +1,3 @@ XILINX_QEMU_VERSION = "v8.1.0" BRANCH = "xlnx_rel_v2024.1" -SRCREV = "d522393f8bc2fdb39db7e7563942f571e8aaea7a" +SRCREV = "2319c870e754148ec3b9d40be0d3dbee959c3251" -- cgit v1.2.3-54-g00ecf From 6db7ce3f5fa5eac54a6ff563cd69b1293c701491 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Fri, 12 Apr 2024 18:29:00 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_8603 xilpm: versal_common: server: Add error message for PSM-PLM version conflict lib: sw_services: versal_common: Add check for the IPI permission access in feature check API lwip : Add lwip_dhcp_does_acd_check sw_services:xilnvm:versalnet:Fix for MISRA-C Rule 8.3 sw_services:xilnvm:versalnet:Fix for coverity warning sw_services:xilnvm:versalnet:Fix MISRA-C Rule 12.1 XilSkey: efuse status bits of ultrascale devices srec_bootloader: Fix compilation error on Microblaze RISC-V xilpm: versal: server: Skip NoC clock gating consideration during the boot uartns550: Fix compilation warning of interrupt example dp14txss:zcu102_pt_hdcp: Modified applicaiton to continue without hdcp incase of wrong password entered during fetching keys from EEPROM. --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index f959b382..388855cc 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" -ESW_REV[2024.1] = "22ca729a1838c0151454948fc99d200351639415" +ESW_REV[2024.1] = "21678feea6c535657988b9cede10270f8bdf3695" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf From 9451b262ab17ffd1a42260fe51ae4d38a62d7d6c Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 15 Apr 2024 06:18:29 +0530 Subject: linux-xlnx : Updated SRCREV for 2024.1_8411 microblaze: Change TLB mapping and free space allocation arm64: versal-net Add dcc node and dcc in aliases for versal-net-ipp-rev1.9.dts arm64: zynqmp: Disable Tri-state for SDIO arm64: dts: zynqmp: make hw-ecc as the default ecc mode mailbox: zynqmp: Enable Bufferless IPI usage on Versal-based SOCs mailbox: zynqmp: Move buffered IPI setup to of_match selected routine mailbox: zynqmp: Move of_match structure closer to usage phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate video/hdmi: Add support for version 3 AVI Infoframe phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode drm: xlnx: hdmi: Set wait event flag for TMDS mode drm: xlnx: hdmi: Fix TMDS clock calculation for RGB YUV422 YUV444 formats phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5 drm: xlnx: hdmi: Fix overwriting the max_frl_rate variable drm: xlnx: hdmi: Downgrade the FRL rate when sink requests drm: xlnx: hdmi: Fix lts2 state machine drm: xlnx: hdmi: Implement xlnx_hdmi_frl_config function drm: xlnx: hdmi: Implement streamdown callback function drm: xlnx: hdmi: Add support for all FRL line rates drm: xlnx: hdmi: Implement streamup callback function drm: xlnx: hdmi: Implement connect callback function drm: xlnx: hdmi: Set wait event flag in ltsp state drm: xlnx: hdmi: Fix FRL link and video clock values drm: xlnx: hdmi: Fix VTC macros as per the IP specification phy: xilinx-xhdmiphy: Fix MMCM parameter values for GTYE5/GTYP drm: xlnx: hdmi: Optimize phy configuration function calls firmware: xilinx: Dont send linux address to get fpga config get status --- meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb index 6042293b..3008a572 100644 --- a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb +++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2024.1.bb @@ -1,7 +1,7 @@ LINUX_VERSION = "6.6.10" YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.6;destsuffix=yocto-kmeta" KBRANCH="xlnx_rebase_v6.6_LTS" -SRCREV = "847d102ca8f60e9f5cd17c685ecb525e6373ca6b" +SRCREV = "73608e3d7f39dc2b44a1d3c135dec85bcb1b67f0" SRCREV_meta = "5d0809d0d939c7738cb6e5391126c73fd0e4e865" KCONF_AUDIT_LEVEL="0" -- cgit v1.2.3-54-g00ecf From 0b97d86d11f3defc08e23bfb09a9651bd5f25f76 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 15 Apr 2024 20:12:35 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_4703 update Embedded SW license 2024.1 release sw_services: xilfpga: Add doxygen fixes sysmonpsu: Add Xiltimer to CMakeLists scripts: pyesw: Enable user-driven customization of library options for xilpm trngpsv: Update trngpsv minor version trngpsx: Update trngpsx minor version sw_services: xilsecure: Update minor version number to 24.1 sw_services:xilocp: Fix DME failure sysmonpsv: Handle Secondary SLRs sw_services:xilsecure:Fix Branch Past initialization sw_services:xilsecure:Fix MISRA-C Rule 17.7 sw_services:xilsecure:Fix MISRA-C Rule 10.3 sw_services:xilsecure:Fix overrun issue sw_services: xilpm: Enable the capability to adjust bsp config flags in the Rigel flow freertos10_xilinx: Fix portPOINTER_SIZE_TYPE value for Cortex A78 scripts: pyesw: retarget_app: Add support for shared workspace use case xilpm: versal_common: server: Add a macro to exclude USB idle code bsp: Add macro to disable long values print support as needed dp12txss: examples: Fix IIC Baseaddress for new unified version dp12rxss: examples: Fix IIC Baseaddress for new unified version xilpm: versal: NoC ScanClear workaround for xcvm2152 --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 388855cc..9271bb5f 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" -ESW_REV[2024.1] = "21678feea6c535657988b9cede10270f8bdf3695" +ESW_REV[2024.1] = "86b2c5e38d51a98e6559799a2f25dc8c72535797" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" @@ -23,7 +23,7 @@ LICENSE = "MIT" LIC_FILES_CHKSUM[master] = '9fceecdbcad88698f265578f3d4cb26c' LIC_FILES_CHKSUM[xlnx_rel_v2023.1_update] = '3c310a3ee2197a4c92c6a0e2937c207c' LIC_FILES_CHKSUM[xlnx_rel_v2023.2_update] = '9fceecdbcad88698f265578f3d4cb26c' -LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '9fceecdbcad88698f265578f3d4cb26c' +LIC_FILES_CHKSUM[xlnx_rel_v2024.1-next] = '443113d5aa8fd5facf31e9c5d25dc114' LIC_FILES_CHKSUM ??= "file://license.txt;md5=${@d.getVarFlag('LIC_FILES_CHKSUM', d.getVar('BRANCH')) or '0'}" SRC_URI = "${EMBEDDEDSW_SRCURI}" -- cgit v1.2.3-54-g00ecf From 54d17cdc88be2820e99081d036c09b20240c1733 Mon Sep 17 00:00:00 2001 From: saumya garg Date: Fri, 12 Apr 2024 13:44:04 +0530 Subject: xrt, zocl: change commit id Changelog: Fix to handle input_ports_details and output_ports_details Interface tiles metric for PLIO designs (#8064) Changing a copy to a move for when profiling samples are written (#8065) VITIS-11806 Command-chaining: XRT C++ Command List (#8063) VITIS-11832 - Support transaction buffer patching in XRT (#8059) fix printing logs on windows (#8062) using the correct workspace path for windows (#8061) Signed-off-by: saumya garg Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index f3313631..b301830f 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,8 +3,8 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG};name=xrt" BRANCH= "master" -SRCREV_xrt = "58cba71cf60f1de1f935a32f0b739d568390b95d" -PV = "202320.2.17.0" +SRCREV_xrt = "baf88820fb3fc24dda4dc08c91ecbca2c76c7b0f" +PV = "202410.2.17.0" SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https" SRCREV_dma_ip_drivers = "9f02769a2eddde008158c96efa39d7edb6512578" -- cgit v1.2.3-54-g00ecf From 1bb654f7de3d7a5cb061698d74ffd97b715dc1c5 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Tue, 16 Apr 2024 13:17:23 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_7987 v_hdmitxss: TxOnly: Fix compilation error with Txonly design v_hdmirxss: RxOnly: Fix compilation error with Rxonly design --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 9271bb5f..5515c117 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -13,7 +13,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" -ESW_REV[2024.1] = "86b2c5e38d51a98e6559799a2f25dc8c72535797" +ESW_REV[2024.1] = "7a83d27befe888ee4efc1ad90fb22a884eef6700" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf