From 981066be2074edeb8bcfcd35dd9c490df22d27b0 Mon Sep 17 00:00:00 2001 From: saumya garg Date: Tue, 11 Jul 2023 23:59:19 +0530 Subject: Update xrt, zocl commit id Changelog: fixed MEM tile edge events (#7621) VITIS-8730: documentation of read, write device memory directly (#7616) AIE trace improvements and new features (#7591) fixing aarch64 compilation issue (#7614) VITIS-8985 Refactor hw context metadata field in query requests (#7610) CR-1167065 Reset command header prior to starting command (#7608) Add xrt::ext::bo support for specifying read/write direction (#7607) Vitis 6327 Add PS kernel xclbins into APU Package (#7594) VITIS-9144 xbutil report for AIE column topology (#7605) Adding a precondition to the CU utilization table to make sure it is not printed when there is no data (#7601) Fix bug in CMake function (#7604) XRT OS Support for RHEl 8.8 and 9.2 (#7603) VITIS-8127 Refactor SubCmdConfigure (#7571) throwing an exception if alloc_bo/alloc_userptrbo is failed (#7602) Signed-off-by: saumya garg Signed-off-by: Mark Hatle --- meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 51da5562..eda20f1d 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc @@ -3,6 +3,6 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' SRC_URI = "${REPO};${BRANCHARG}" BRANCH= "master" -SRCREV= "b1e154bed787183eb677d1546fc632d6799895b9" +SRCREV= "ba5d5fffa4bc5e9d7a1f478998cf730360125a60" PV = "202320.2.16.0" -- cgit v1.2.3-54-g00ecf