From c933f83a698d0cac9ce0c9a712b6cbbac227893f Mon Sep 17 00:00:00 2001 From: Sandeep Gundlupet Raju Date: Thu, 5 May 2022 18:50:43 -0600 Subject: meta-xilinx: Clean up vendor specific machine configuration files 1. Add new metal-xilinx-vendor layer which supports vendor specific machine configuration files, device-tree, kernel, platform-init etc. 2. Moved below vendor machine conf files, dt and related configs from meta-xilinx-bsp and meta-xilinx-contrib to meta-xilinx-vendor layer. - microzed-zynq7.conf - minized-zynq7.conf - picozed-zynq7.conf - zedboard-zynq7.conf - zybo-zynq7.conf - zybo-linux-bd-zynq7.conf - ultra96-zynqmp.conf 3. Obsolete qemu-zynq7, s3adsp1800-qemu-microblazeeb, v350-versal and vc-p-a2197-00-versal from meta-xilinx-bsp layer. Users should use zynq-generic.conf for zynq7000 qemu boot should be functionally equivalent to qemu-zynq7. 4. Add new MAINTAINERS.md file and move maintainers, Mailing list and Patches content from meta-xilinx-* README.md to MAINTAINERS.md file. 5. Updated README.md file for supported board machines files in meta-xilinx-bsp, meta-xilinx-contrib and meta-xilinx-vendor layers. 6. Disabled old drm kernel patches for zybo-linux-bd-zynq mahcine in meta-xilinx-contrib layer as these patches doesn't apply on 5.x kernel, if we don't hear from patch submitter we will remove these patches from meta-xilinx-contrib layer. 7. Removed drm kernel cache metadate for zybo-linux-bd-zynq7 machine as these configs are already available in xilinx_zynq_defconfig. 8. Fixed build issue for u-boot by changing PREFERRED_PROVIDER_virtual/bootloader from u-boot to u-boot-xlnx. 9. Add meta-xilinx-vendor to bblayers.conf.sample Signed-off-by: Sandeep Gundlupet Raju Signed-off-by: Mark Hatle --- MAINTAINERS.md | 34 + meta-microblaze/README.md | 25 +- meta-xilinx-bsp/README.md | 102 +- .../conf/machine/include/board/ultra96.inc | 12 - meta-xilinx-bsp/conf/machine/microzed-zynq7.conf | 26 - .../conf/machine/ml605-qemu-microblazeel.conf | 20 - meta-xilinx-bsp/conf/machine/picozed-zynq7.conf | 28 - meta-xilinx-bsp/conf/machine/qemu-zynq7.conf | 9 - .../conf/machine/s3adsp1800-qemu-microblazeeb.conf | 21 - meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf | 23 - meta-xilinx-bsp/conf/machine/v350-versal.conf | 19 - .../conf/machine/vc-p-a2197-00-versal.conf | 10 - meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf | 24 - .../conf/machine/zybo-linux-bd-zynq7.conf | 27 - meta-xilinx-bsp/conf/machine/zybo-zynq7.conf | 29 - .../recipes-bsp/device-tree/device-tree.bbappend | 5 - .../recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 3 - .../recipes-bsp/device-tree/device-tree.bbappend | 10 - .../device-tree/files/picozed-zynq7.dts | 98 - .../device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi | 63 - .../device-tree/files/zybo-linux-bd-zynq7/pl.dtsi | 215 - .../zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts | 184 - .../platform-init/platform-init.bbappend | 4 - .../platform-init/picozed-zynq7/ps7_init_gpl.c | 13191 ------------------- .../platform-init/picozed-zynq7/ps7_init_gpl.h | 130 - meta-xilinx-contrib/README.md | 42 +- .../conf/machine/minized-zynq7.conf | 27 - .../conf/machine/ml605-qemu-microblazeel.conf | 20 + .../linux/linux-xlnx_2022.2.bbappend | 13 +- meta-xilinx-core/README.md | 30 +- meta-xilinx-core/conf/bblayers.conf.sample | 1 + meta-xilinx-pynq/README.md | 27 +- meta-xilinx-standalone-experimental/README.md | 37 +- meta-xilinx-standalone/README.md | 39 +- meta-xilinx-vendor/COPYING.MIT | 17 + meta-xilinx-vendor/README.md | 37 + meta-xilinx-vendor/conf/layer.conf | 13 + .../conf/machine/include/board/ultra96.inc | 12 + .../conf/machine/microzed-zynq7.conf | 23 + meta-xilinx-vendor/conf/machine/minized-zynq7.conf | 24 + meta-xilinx-vendor/conf/machine/picozed-zynq7.conf | 25 + .../conf/machine/ultra96-zynqmp.conf | 23 + .../conf/machine/zedboard-zynq7.conf | 24 + .../conf/machine/zybo-linux-bd-zynq7.conf | 24 + meta-xilinx-vendor/conf/machine/zybo-zynq7.conf | 27 + .../recipes-bsp/device-tree/device-tree.bbappend | 7 + .../recipes-bsp/embeddedsw/pmu-firmware_%.bbappend | 3 + .../recipes-bsp/device-tree/device-tree.bbappend | 13 + .../device-tree/files/picozed-zynq7.dts | 98 + .../device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi | 63 + .../device-tree/files/zybo-linux-bd-zynq7/pl.dtsi | 215 + .../zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts | 184 + .../platform-init/platform-init.bbappend | 4 + .../platform-init/picozed-zynq7/ps7_init_gpl.c | 13191 +++++++++++++++++++ .../platform-init/picozed-zynq7/ps7_init_gpl.h | 130 + 55 files changed, 14318 insertions(+), 14387 deletions(-) create mode 100644 MAINTAINERS.md delete mode 100644 meta-xilinx-bsp/conf/machine/include/board/ultra96.inc delete mode 100644 meta-xilinx-bsp/conf/machine/microzed-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf delete mode 100644 meta-xilinx-bsp/conf/machine/picozed-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/qemu-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf delete mode 100644 meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf delete mode 100644 meta-xilinx-bsp/conf/machine/v350-versal.conf delete mode 100644 meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf delete mode 100644 meta-xilinx-bsp/conf/machine/zybo-zynq7.conf delete mode 100644 meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi delete mode 100644 meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c delete mode 100644 meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h delete mode 100644 meta-xilinx-contrib/conf/machine/minized-zynq7.conf create mode 100644 meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf create mode 100644 meta-xilinx-vendor/COPYING.MIT create mode 100644 meta-xilinx-vendor/README.md create mode 100644 meta-xilinx-vendor/conf/layer.conf create mode 100644 meta-xilinx-vendor/conf/machine/include/board/ultra96.inc create mode 100644 meta-xilinx-vendor/conf/machine/microzed-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/minized-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/picozed-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf create mode 100644 meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf create mode 100644 meta-xilinx-vendor/conf/machine/zybo-zynq7.conf create mode 100644 meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend create mode 100644 meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi create mode 100644 meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c create mode 100644 meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h diff --git a/MAINTAINERS.md b/MAINTAINERS.md new file mode 100644 index 00000000..d14b73e5 --- /dev/null +++ b/MAINTAINERS.md @@ -0,0 +1,34 @@ +# Maintainers, Mailing list, Patches + +Please send any patches, pull requests, comments or questions for this layer to +the [meta-xilinx mailing list](https://lists.yoctoproject.org/g/meta-xilinx): + + meta-xilinx@lists.yoctoproject.org + +When sending patches, please make sure the email subject line includes +"[meta-xilinx][PATCH]" and cc'ing the maintainers. + +For more details follow the OE community patch submission guidelines, as described in: + +https://www.openembedded.org/wiki/Commit_Patch_Message_Guidelines +https://www.openembedded.org/wiki/How_to_submit_a_patch_to_OpenEmbedded + +`git send-email --subject-prefix 'meta-xilinx][PATCH' --to meta-xilinx@yoctoproject.org` + +**Maintainers:** + + Mark Hatle + Sandeep Gundlupet Raju + John Toomey + +> **Note:** + +* meta-xilinx-contrib layer: + * We don't have any maintainers when user submit a patch to this layer + email meta-xilinx@yoctoproject.org and cc'ing below reviewers. + +**Reviewers:** + + Mark Hatle + Sandeep Gundlupet Raju + John Toomey diff --git a/meta-microblaze/README.md b/meta-microblaze/README.md index 9e7ea2c6..acf6c253 100644 --- a/meta-microblaze/README.md +++ b/meta-microblaze/README.md @@ -1,24 +1,8 @@ -meta-microblaze -=============== +# meta-microblaze This layer provides support specific to the MicroBlaze architecture - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -26,3 +10,8 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) + + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-bsp/README.md b/meta-xilinx-bsp/README.md index e4142861..f41f6d4a 100644 --- a/meta-xilinx-bsp/README.md +++ b/meta-xilinx-bsp/README.md @@ -1,56 +1,38 @@ -meta-xilinx -=========== +# meta-xilinx -This layer provides support for MicroBlaze, Zynq and ZynqMP. +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures Xilinx evaluation boards. -Additional documentation: +## Additional documentation: -* [Building](README.building.md) -* [Booting](README.booting.md) +* [Building](../README.building.md) +* [Booting](../README.booting.md) -Supported Boards/Machines -========================= +## Supported Boards/Machines -Boards/Machines supported by this layer: +**Boards/Machines supported by this layer:** -* MicroBlaze: - * [Xilinx ML605 (QEMU)](conf/machine/ml605-qemu-microblazeel.conf) - `ml605-qemu-microblazeel` (QEMU support) - * [Xilinx S3A DSP 1800 (QEMU)](conf/machine/s3adsp1800-qemu-microblazeeb.conf) - `s3adsp1800-qemu-microblazeeb` (QEMU support) - * [Xilinx KC705](conf/machine/kc705-microblazeel.conf) - `kc705-microblazeel` -* Zynq: - * [Zynq (QEMU)](conf/machine/qemu-zynq7.conf) - `qemu-zynq7` (QEMU Support) - * [Xilinx ZC702](conf/machine/zc702-zynq7.conf) - `zc702-zynq7` (with QEMU support) - * [Xilinx ZC706](conf/machine/zc706-zynq7.conf) - `zc706-zynq7` (with QEMU support) - * [Avnet MicroZed](conf/machine/microzed-zynq7.conf) - `microzed-zynq7` - * [Avnet PicoZed](conf/machine/picozed-zynq7.conf) - `picozed-zynq7` - * [Avnet/Digilent ZedBoard](conf/machine/zedboard-zynq7.conf) - `zedboard-zynq7` - * [Digilent Zybo](conf/machine/zybo-zynq7.conf) - `zybo-zynq7` - * [Digilent Zybo Linux BD](conf/machine/zybo-linux-bd-zynq7.conf) - `zybo-linux-bd-zynq7` -* ZynqMP: - * [Xilinx ZCU102](conf/machine/zcu102-zynqmp.conf) - `zcu102-zynqmp` (QEMU support) - * [Xilinx ZCU106](conf/machine/zcu106-zynqmp.conf) - `zcu106-zynqmp` - * [Xilinx ZCU104](conf/machine/zcu104-zynqmp.conf) - `zcu104-zynqmp` +| Platform | Xilinx Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx KC705](https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html)|[kc705-microblazeel](conf/machine/kc705-microblazeel.conf)|`kc705-full`| +|Zynq-7000|Zynq (QEMU)|[qemu-zynq7](conf/machine/qemu-zynq7.conf)|NA| +||[Xilinx ZC702](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html)|[zc702-zynq7](conf/machine/zc702-zynq7.conf)|`zc702`| +||[Xilinx ZC706](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html)|[zc706-zynq7](conf/machine/zc706-zynq7.conf)|`zc706`| +|ZynqMP|[Xilinx ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html)|[zcu102-zynqmp](conf/machine/zcu102-zynqmp.conf)|`zcu102-rev1.0`| +||[Xilinx ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html)|[zcu104-zynqmp](conf/machine/zcu104-zynqmp.conf)|`zcu104-revc`| +||[Xilinx ZCU106](https://www.xilinx.com/products/boards-and-kits/zcu106.html)|[zcu106-zynqmp](conf/machine/zcu106-zynqmp.conf)|`zcu106-reva`| +||[Xilinx ZCU111](https://www.xilinx.com/products/boards-and-kits/zcu111.html)|[zcu111-zynqmp](conf/machine/zcu111-zynqmp.conf)|`zcu111-reva`| +||[Xilinx ZCU1275](https://www.xilinx.com/products/boards-and-kits/zcu1275.html)|[zcu1275-zynqmp](conf/machine/zcu1275-zynqmp.conf)|`zcu1275-revb`| +||[Xilinx ZCU1285](https://www.xilinx.com/products/boards-and-kits/zcu1285.html)|[zcu1285-zynqmp](conf/machine/zcu1285-zynqmp.conf)|`zcu1285-reva`| +||[Xilinx ZCU208](https://www.xilinx.com/products/boards-and-kits/zcu208.html)|[zcu208-zynqmp](conf/machine/zcu208-zynqmp.conf)|`zcu208-reva`| +||[Xilinx ZCU216](https://www.xilinx.com/products/boards-and-kits/zcu216.html)|[zcu216-zynqmp](conf/machine/zcu216-zynqmp.conf)|`zcu216-reva`| +|Versal|[Xilinx VCK190](https://www.xilinx.com/products/boards-and-kits/vck190.html)|[vck190-versal](conf/machine/vck190-versal.conf)|`versal-vck190-reva-x-ebm-01-reva`| +||[Xilinx VMK180](https://www.xilinx.com/products/boards-and-kits/vmk180.html)|[vmk180-versal](conf/machine/vmk180-versal.conf)|`versal-vmk180-reva-x-ebm-01-reva`| +||[Xilinx VCK5000](https://www.xilinx.com/products/boards-and-kits/vck5000.html)|[vck5000-versal](conf/machine/vck5000-versal.conf)|`versal-vck5000-reva-x-ebm-01-reva`| -Additional information on Xilinx architectures can be found at: - http://www.xilinx.com/support/index.htm +> **Note:** Additional information on Xilinx architectures can be found at: + https://www.xilinx.com/products/silicon-devices.html -For Zybo Linux BD reference design, please see meta-xilinx-contrib layer - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -58,31 +40,9 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) -Recipe Licenses -=============== - -Due to licensing restrictions some recipes in this layer rely on closed source -or restricted content provided by Xilinx. In order to use these recipes you must -accept or agree to the licensing terms (e.g. EULA, Export Compliance, NDA, -Redistribution, etc). This layer **does not enforce** any legal requirement, it -is the **responsibility of the user** the ensure that they are in compliance -with any licenses or legal requirements for content used. - -In order to use recipes that rely on restricted content the `xilinx` license -flag must be white-listed in the build configuration (e.g. `local.conf`). This -can be done on a per package basis: - - LICENSE_FLAGS_WHITELIST += "xilinx_pmu-rom" - -or generally: - - LICENSE_FLAGS_WHITELIST += "xilinx" - -Generally speaking Xilinx content that is provided as a restricted download -cannot be obtained without a Xilinx account, in order to use this content you -must first download it with your Xilinx account and place the downloaded content -in the `downloads/` directory of your build or on a `PREMIRROR`. Attempting to -fetch the content using bitbake will fail, indicating the URL from which to -acquire the content. + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc b/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc deleted file mode 100644 index bfb57e00..00000000 --- a/meta-xilinx-bsp/conf/machine/include/board/ultra96.inc +++ /dev/null @@ -1,12 +0,0 @@ -# Ultra96 items that need to be configured from zynqmp-generic -KERNEL_DEVICETREE:ultra96 = "xilinx/zynqmp-zcu100-revC.dtb" - -# Affects meta-xilinx-tools xsctyaml.bbclass related items -YAML_SERIAL_CONSOLE_STDIN:ultra96 ?= "psu_uart_1" -YAML_SERIAL_CONSOLE_STDOUT:ultra96 ?= "psu_uart_1" - -YAML_COMPILER_FLAGS:append:ultra96 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " - -# Enable bluetooth and wifi module -MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append:ultra96 = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" - diff --git a/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf b/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf deleted file mode 100644 index c0e8e6dd..00000000 --- a/meta-xilinx-bsp/conf/machine/microzed-zynq7.conf +++ /dev/null @@ -1,26 +0,0 @@ -#@TYPE: Machine -#@NAME: microzed-zynq7 -#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/) - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" - -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -KERNEL_DEVICETREE = "zynq-microzed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf deleted file mode 100644 index 157a75c2..00000000 --- a/meta-xilinx-bsp/conf/machine/ml605-qemu-microblazeel.conf +++ /dev/null @@ -1,20 +0,0 @@ -#@TYPE: Machine -#@NAME: ml605-qemu-microblazeel -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model) - -TUNE_FEATURES:tune-microblaze ?= "microblaze v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard" - -require conf/machine/microblaze-generic.conf - -USE_VT = "" - -# Use the networking setup from qemuarm -MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" -FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-ml605" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf b/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf deleted file mode 100644 index d4f63f95..00000000 --- a/meta-xilinx-bsp/conf/machine/picozed-zynq7.conf +++ /dev/null @@ -1,28 +0,0 @@ -#@TYPE: Machine -#@NAME: picozed-zynq7 -#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/) -# -# Note: This machine configuration is intended as a generic config for -# the picozed SOM. It also covers the multiple SKUs for the picoZed -# including 7010, 7020, 7015 and 7030. - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" - -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf b/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf deleted file mode 100644 index f28e3d4a..00000000 --- a/meta-xilinx-bsp/conf/machine/qemu-zynq7.conf +++ /dev/null @@ -1,9 +0,0 @@ -#@TYPE: Machine -#@NAME: qemu-zynq7 -#@DESCRIPTION: Zynq QEMU machine support ('xilinx-zynq-a9' model) - -require conf/machine/zynq-generic.conf - -# Use the networking setup from qemuarm -MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" -FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" diff --git a/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf b/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf deleted file mode 100644 index 12621357..00000000 --- a/meta-xilinx-bsp/conf/machine/s3adsp1800-qemu-microblazeeb.conf +++ /dev/null @@ -1,21 +0,0 @@ -#@TYPE: Machine -#@NAME: s3adsp1800-qemu-microblazeeb -#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-s3adsp1800' model) - -TUNE_FEATURES:tune-microblaze ?= "microblaze v8.00 bigendian barrel-shift pattern-compare multiply-low" - -require conf/machine/microblaze-generic.conf - -MACHINE_FEATURES = "" - -USE_VT = "" -SERIAL_CONSOLES ?= "115200;ttyUL0" - -KERNEL_IMAGETYPE ?= "linux.bin.ub" - -# This machine is a targeting a QEMU model, runqemu setup: -QB_MEM = "-m 256" -QB_MACHINE = "-machine petalogix-s3adsp1800" -QB_OPT_APPEND = "-nographic -serial mon:stdio" -QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" - diff --git a/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf b/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf deleted file mode 100644 index ff74ac3d..00000000 --- a/meta-xilinx-bsp/conf/machine/ultra96-zynqmp.conf +++ /dev/null @@ -1,23 +0,0 @@ -#@TYPE: Machine -#@NAME: ultra96-zynqmp -#@DESCRIPTION: Machine support for Ultra96 Evaluation Board. -# - -SOC_VARIANT = 'eg' - -require conf/machine/zynqmp-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":ultra96" - -KERNEL_DEVICETREE = "xilinx/zynqmp-zcu100-revC.dtb" - -# Affects meta-xilinx-tools xsctyaml.bbclass related items -YAML_SERIAL_CONSOLE_STDIN ?= "psu_uart_1" -YAML_SERIAL_CONSOLE_STDOUT ?= "psu_uart_1" - -YAML_COMPILER_FLAGS:append = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " - -# Enable bluetooth and wifi module -MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" - diff --git a/meta-xilinx-bsp/conf/machine/v350-versal.conf b/meta-xilinx-bsp/conf/machine/v350-versal.conf deleted file mode 100644 index d865dc5a..00000000 --- a/meta-xilinx-bsp/conf/machine/v350-versal.conf +++ /dev/null @@ -1,19 +0,0 @@ -#@TYPE: Machine -#@NAME: v350-versal -##@DESCRIPTION: Machine support for v350 versal. - -SOC_VARIANT = "ai-core" - -require conf/machine/versal-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":v350" - -EXTRA_IMAGEDEPENDS += " \ - arm-trusted-firmware \ - virtual/boot-bin \ - virtual/bootloader \ - virtual/psm-firmware \ - virtual/plm \ - u-boot-zynq-scr \ -" diff --git a/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf b/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf deleted file mode 100644 index c20166e3..00000000 --- a/meta-xilinx-bsp/conf/machine/vc-p-a2197-00-versal.conf +++ /dev/null @@ -1,10 +0,0 @@ -#@TYPE: Machine -#@NAME: vc-p-a2197-versal -##@DESCRIPTION: Machine support for vc-p-a2197 versal . - -SOC_VARIANT = "ai-core" - -require conf/machine/versal-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":vc-p-a2197-00" diff --git a/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf b/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf deleted file mode 100644 index 4da6bb4e..00000000 --- a/meta-xilinx-bsp/conf/machine/zedboard-zynq7.conf +++ /dev/null @@ -1,24 +0,0 @@ -#@TYPE: Machine -#@NAME: zedboard-zynq7 -#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/) -# -# For details on the Evaluation board: -# http://www.zedboard.org/content/overview -# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard: -# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard -# - -require conf/machine/zynq-generic.conf - -# Add board compatibility override -MACHINEOVERRIDES .= ":zedboard" - -SPL_BINARY ?= "spl/boot.bin" - -KERNEL_DEVICETREE = "zynq-zed.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - boot.scr \ - " diff --git a/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf deleted file mode 100644 index df26ea0d..00000000 --- a/meta-xilinx-bsp/conf/machine/zybo-linux-bd-zynq7.conf +++ /dev/null @@ -1,27 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-linux-bd-zynq7 -#@DESCRIPTION: Machine support for zybo-linux-bd project. -# -# generated base on ZYBO linux-bd project -# - -require conf/machine/zynq-generic.conf - -PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot" - -MACHINE_FEATURES += "keyboard screen alsa sdio" - -SPL_BINARY ?= "spl/boot.bin" -FORCE_PLATFORM_INIT = "1" -UBOOT_ELF = "u-boot" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - bitstream \ - uEnv.txt \ - " - -KERNEL_FEATURES += " \ - bsp/xilinx/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.scc \ - features/xilinx/v4l2/v4l2.scc \ - " diff --git a/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf b/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf deleted file mode 100644 index aa1eafe4..00000000 --- a/meta-xilinx-bsp/conf/machine/zybo-zynq7.conf +++ /dev/null @@ -1,29 +0,0 @@ -#@TYPE: Machine -#@NAME: zybo-zynq7 -#@DESCRIPTION: Machine support for ZYBO. -# -# For details on the ZYBO board: -# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO -# - -require conf/machine/zynq-generic.conf - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -SPL_BINARY ?= "spl/boot.bin" -UBOOT_ELF = "u-boot" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/boot-bin \ - virtual/bootloader \ - u-boot-zynq-scr \ - " - -KERNEL_DEVICETREE = "zynq-zybo.dtb" - -IMAGE_BOOT_FILES += " \ - boot.bin \ - uEnv.txt \ - " - diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend index f3c932db..2640c2c2 100644 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -1,7 +1,3 @@ -YAML_MAIN_MEMORY_CONFIG:ultra96 ?= "psu_ddr_0" -YAML_CONSOLE_DEVICE_CONFIG:ultra96 ?= "psu_uart_1" -YAML_DT_BOARD_FLAGS:ultra96 ?= "{BOARD avnet-ultra96-rev1}" - YAML_MAIN_MEMORY_CONFIG:kc705 ?= "mig_7series_0" YAML_CONSOLE_DEVICE_CONFIG:kc705 ?= "axi_uartlite_0" YAML_DT_BOARD_FLAGS:kc705 ?= "{BOARD kc705-full}" @@ -10,7 +6,6 @@ YAML_DT_BOARD_FLAGS:zcu102 ?= "{BOARD zcu102-rev1.0}" YAML_DT_BOARD_FLAGS:zcu106 ?= "{BOARD zcu106-reva}" YAML_DT_BOARD_FLAGS:zc702 ?= "{BOARD zc702}" YAML_DT_BOARD_FLAGS:zc706 ?= "{BOARD zc706}" -YAML_DT_BOARD_FLAGS:zedboard ?= "{BOARD zedboard}" YAML_DT_BOARD_FLAGS:zc1254 ?= "{BOARD zc1254-reva}" YAML_DT_BOARD_FLAGS:zcu104 ?= "{BOARD zcu104-revc}" YAML_DT_BOARD_FLAGS:zcu111 ?= "{BOARD zcu111-reva}" diff --git a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend deleted file mode 100644 index e925d608..00000000 --- a/meta-xilinx-bsp/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend +++ /dev/null @@ -1,3 +0,0 @@ -ULTRA96_VERSION ?= "1" -YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" - diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend index 94020f25..83f8c57b 100644 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend +++ b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bbappend @@ -1,19 +1,9 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files:" # device tree sources for the various machines -COMPATIBLE_MACHINE:picozed-zynq7 = ".*" -SRC_URI:append:picozed-zynq7 = " file://picozed-zynq7.dts" - COMPATIBLE_MACHINE:qemu-zynq7 = ".*" SRC_URI:append:qemu-zynq7 = " file://qemu-zynq7.dts" -COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = ".*" -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://zybo-linux-bd-zynq7.dts \ - file://pcw.dtsi \ - file://pl.dtsi \ - " - COMPATIBLE_MACHINE:kc705-microblazeel = ".*" SRC_URI:append:kc705-microblazeel = " \ file://kc705-microblazeel.dts \ diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts deleted file mode 100644 index 6f9b653a..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts +++ /dev/null @@ -1,98 +0,0 @@ -/dts-v1/; -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" - -/ { - model = "Avnet picoZed"; - compatible = "avnet,picozed", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - usb_phy0: phy0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ - }; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - compatible = "marvell,88e1512", "marvell,88e1510"; - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&sdhci1 { - status = "okay"; - /* SD1 is onnected to a non-removable eMMC flash device */ - non-removable; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; - usb-phy = <&usb_phy0>; -}; - -&qspi { - status = "okay"; - primary_flash: ps7-qspi@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <50000000>; - /* Example 16M partition table using U-Boot + U-Boot SPL */ - partition@0x0 { - label = "boot"; - reg = <0x0 0xe0000>; - }; - partition@0xe0000 { - label = "ubootenv"; - reg = <0xe0000 0x20000>; - }; - partition@0x100000 { - label = "uboot"; - reg = <0x100000 0x100000>; - }; - partition@0x200000 { - label = "kernel"; - reg = <0x200000 0x4f0000>; - }; - partition@0x6f0000 { - label = "devicetree"; - reg = <0x6f0000 0x10000>; - }; - partition@0x700000 { - label = "rootfs"; - reg = <0x700000 0x400000>; - }; - partition@0xb00000 { - label = "spare"; - reg = <0xb00000 0x500000>; - }; - }; -}; - diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi deleted file mode 100644 index 0f678d39..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - cpus { - cpu@0 { - operating-points = <650000 1000000 325000 1000000>; - }; - }; -}; -&gem0 { - phy-mode = "rgmii-id"; - status = "okay"; - xlnx,ptp-enet-clock = <0x6750918>; -}; -&gpio0 { - emio-gpio-width = <64>; - gpio-mask-high = <0x0>; - gpio-mask-low = <0x5600>; -}; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; -&intc { - num_cpus = <2>; - num_interrupts = <96>; -}; -&qspi { - is-dual = <0>; - num-cs = <1>; - status = "okay"; -}; -&sdhci0 { - status = "okay"; - xlnx,has-cd = <0x1>; - xlnx,has-power = <0x0>; - xlnx,has-wp = <0x1>; -}; -&uart1 { - current-speed = <115200>; - device_type = "serial"; - port-number = <0>; - status = "okay"; -}; -&usb0 { - dr_mode = "host"; - phy_type = "ulpi"; - status = "okay"; - usb-reset = <&gpio0 46 0>; -}; -&clkc { - fclk-enable = <0x3>; - ps-clk-frequency = <50000000>; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi deleted file mode 100644 index 32bc7688..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -/* - * CAUTION: This file is automatically generated by Xilinx. - * Version: HSI 2015.4 - * Today is: Fri Mar 4 15:40:49 2016 -*/ - - -/ { - amba_pl: amba_pl { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges ; - axi_dynclk_0: axi_dynclk@43c10000 { - compatible = "xlnx,axi-dynclk-1.0"; - reg = <0x43c10000 0x10000>; - xlnx,s00-axi-addr-width = <0x5>; - xlnx,s00-axi-data-width = <0x20>; - }; - axi_gpio_btn: gpio@41210000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41210000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_hdmi: gpio@41230000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - interrupt-parent = <&intc>; - interrupts = <0 29 4>; - reg = <0x41230000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x1>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_led: gpio@41200000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41200000 0x10000>; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x1>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_gpio_sw: gpio@41220000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x41220000 0x10000>; - xlnx,all-inputs = <0x1>; - xlnx,all-inputs-2 = <0x0>; - xlnx,all-outputs = <0x0>; - xlnx,all-outputs-2 = <0x0>; - xlnx,dout-default = <0x00000000>; - xlnx,dout-default-2 = <0x00000000>; - xlnx,gpio-width = <0x4>; - xlnx,gpio2-width = <0x20>; - xlnx,interrupt-present = <0x0>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xFFFFFFFF>; - xlnx,tri-default-2 = <0xFFFFFFFF>; - }; - axi_i2s_adi_0: axi_i2s_adi@43c20000 { - compatible = "xlnx,axi-i2s-adi-1.0"; - reg = <0x43c20000 0x10000>; - xlnx,bclk-pol = <0x0>; - xlnx,dma-type = <0x1>; - xlnx,has-rx = <0x1>; - xlnx,has-tx = <0x1>; - xlnx,lrclk-pol = <0x0>; - xlnx,num-ch = <0x1>; - xlnx,s-axi-min-size = <0x000001FF>; - xlnx,slot-width = <0x18>; - }; - axi_vdma_0: dma@43000000 { - #dma-cells = <1>; - compatible = "xlnx,axi-vdma-1.00.a"; - clocks = <&clkc 15>; - clock-names = "s_axi_lite_aclk"; - interrupt-parent = <&intc>; - interrupts = <0 30 4>; - reg = <0x43000000 0x10000>; - xlnx,flush-fsync = <0x1>; - xlnx,num-fstores = <0x1>; - dma-channel@43000000 { - compatible = "xlnx,axi-vdma-mm2s-channel"; - interrupts = <0 30 4>; - xlnx,datawidth = <0x20>; - xlnx,device-id = <0x0>; - }; - }; - v_tc_0: v_tc@43c00000 { - compatible = "xlnx,v-tc-6.1"; - interrupt-parent = <&intc>; - interrupts = <0 31 4>; - reg = <0x43c00000 0x10000>; - xlnx,det-achroma-en = <0x0>; - xlnx,det-avideo-en = <0x1>; - xlnx,det-fieldid-en = <0x0>; - xlnx,det-hblank-en = <0x1>; - xlnx,det-hsync-en = <0x1>; - xlnx,det-vblank-en = <0x1>; - xlnx,det-vsync-en = <0x1>; - xlnx,detect-en = <0x0>; - xlnx,fsync-hstart0 = <0x0>; - xlnx,fsync-hstart1 = <0x0>; - xlnx,fsync-hstart10 = <0x0>; - xlnx,fsync-hstart11 = <0x0>; - xlnx,fsync-hstart12 = <0x0>; - xlnx,fsync-hstart13 = <0x0>; - xlnx,fsync-hstart14 = <0x0>; - xlnx,fsync-hstart15 = <0x0>; - xlnx,fsync-hstart2 = <0x0>; - xlnx,fsync-hstart3 = <0x0>; - xlnx,fsync-hstart4 = <0x0>; - xlnx,fsync-hstart5 = <0x0>; - xlnx,fsync-hstart6 = <0x0>; - xlnx,fsync-hstart7 = <0x0>; - xlnx,fsync-hstart8 = <0x0>; - xlnx,fsync-hstart9 = <0x0>; - xlnx,fsync-vstart0 = <0x0>; - xlnx,fsync-vstart1 = <0x0>; - xlnx,fsync-vstart10 = <0x0>; - xlnx,fsync-vstart11 = <0x0>; - xlnx,fsync-vstart12 = <0x0>; - xlnx,fsync-vstart13 = <0x0>; - xlnx,fsync-vstart14 = <0x0>; - xlnx,fsync-vstart15 = <0x0>; - xlnx,fsync-vstart2 = <0x0>; - xlnx,fsync-vstart3 = <0x0>; - xlnx,fsync-vstart4 = <0x0>; - xlnx,fsync-vstart5 = <0x0>; - xlnx,fsync-vstart6 = <0x0>; - xlnx,fsync-vstart7 = <0x0>; - xlnx,fsync-vstart8 = <0x0>; - xlnx,fsync-vstart9 = <0x0>; - xlnx,gen-achroma-en = <0x0>; - xlnx,gen-achroma-polarity = <0x1>; - xlnx,gen-auto-switch = <0x0>; - xlnx,gen-avideo-en = <0x1>; - xlnx,gen-avideo-polarity = <0x1>; - xlnx,gen-cparity = <0x0>; - xlnx,gen-f0-vblank-hend = <0x500>; - xlnx,gen-f0-vblank-hstart = <0x500>; - xlnx,gen-f0-vframe-size = <0x2ee>; - xlnx,gen-f0-vsync-hend = <0x500>; - xlnx,gen-f0-vsync-hstart = <0x500>; - xlnx,gen-f0-vsync-vend = <0x2d9>; - xlnx,gen-f0-vsync-vstart = <0x2d4>; - xlnx,gen-f1-vblank-hend = <0x500>; - xlnx,gen-f1-vblank-hstart = <0x500>; - xlnx,gen-f1-vframe-size = <0x2ee>; - xlnx,gen-f1-vsync-hend = <0x500>; - xlnx,gen-f1-vsync-hstart = <0x500>; - xlnx,gen-f1-vsync-vend = <0x2d9>; - xlnx,gen-f1-vsync-vstart = <0x2d4>; - xlnx,gen-fieldid-en = <0x0>; - xlnx,gen-fieldid-polarity = <0x1>; - xlnx,gen-hactive-size = <0x500>; - xlnx,gen-hblank-en = <0x1>; - xlnx,gen-hblank-polarity = <0x1>; - xlnx,gen-hframe-size = <0x672>; - xlnx,gen-hsync-en = <0x1>; - xlnx,gen-hsync-end = <0x596>; - xlnx,gen-hsync-polarity = <0x1>; - xlnx,gen-hsync-start = <0x56e>; - xlnx,gen-interlaced = <0x0>; - xlnx,gen-vactive-size = <0x2d0>; - xlnx,gen-vblank-en = <0x1>; - xlnx,gen-vblank-polarity = <0x1>; - xlnx,gen-video-format = <0x2>; - xlnx,gen-vsync-en = <0x1>; - xlnx,gen-vsync-polarity = <0x1>; - xlnx,generate-en = <0x1>; - xlnx,has-axi4-lite = <0x1>; - xlnx,has-intc-if = <0x0>; - xlnx,interlace-en = <0x0>; - xlnx,max-lines = <0x1000>; - xlnx,max-pixels = <0x1000>; - xlnx,num-fsyncs = <0x1>; - xlnx,sync-en = <0x0>; - }; - }; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts deleted file mode 100644 index 19654392..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; -/include/ "skeleton.dtsi" -/include/ "zynq-7000.dtsi" -/include/ "zynq-7000-qspi-dummy.dtsi" -/include/ "pcw.dtsi" -/include/ "pl.dtsi" - -/ { - model = "Digilent-Zybo-Linux-BD-v2015.4"; - aliases { - serial0 = &uart1; - ethernet0 = &gem0; - spi0 = &qspi; - }; - chosen { - bootargs = ""; - stdout-path = "serial0:115200n8"; - }; - memory { - device_type = "memory"; - reg = <0x0 0x20000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - btn4 { - label = "btn4"; - gpios = <&gpio0 50 0>; - linux,code = <108>; /* down */ - gpio-key,wakeup; - autorepeat; - }; - btn5 { - label = "btn5"; - gpios = <&gpio0 51 0>; - linux,code = <103>; /* up */ - gpio-key,wakeup; - autorepeat; - }; - }; - - usb_phy0: usb_phy@0 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - reset-gpios = <&gpio0 46 1>; - }; -}; - -&amba { - u-boot,dm-pre-reloc; -}; - -&amba_pl { - encoder_0: digilent_encoder { - compatible = "digilent,drm-encoder"; - dglnt,edid-i2c = <&i2c1>; - }; - - xilinx_drm { - compatible = "xlnx,drm"; - xlnx,vtc = <&v_tc_0>; - xlnx,connector-type = "HDMIA"; - xlnx,encoder-slave = <&encoder_0>; - clocks = <&axi_dynclk_0>; - planes { - xlnx,pixel-format = "xrgb8888"; - plane0 { - dmas = <&axi_vdma_0 0>; - dma-names = "dma0"; - }; - }; - }; - - i2s_clk: i2s_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <12288000>; - clock-output-names = "i2s_clk"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "ZYBO-Sound-Card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MICIN", "Microphone Jack", - "Headphone Jack", "LHPOUT", - "Headphone Jack", "RHPOUT", - "LLINEIN", "Line In Jack", - "RLINEIN", "Line In Jack"; - dailink0_master: simple-audio-card,cpu { - clocks = <&i2s_clk>; - sound-dai = <&axi_i2s_adi_0>; - }; - simple-audio-card,codec { - clocks = <&i2s_clk>; - sound-dai = <&ssm2603>; - }; - }; -}; - -&axi_dynclk_0 { - compatible = "digilent,axi-dynclk"; - #clock-cells = <0>; - clocks = <&clkc 15>; -}; - -&axi_i2s_adi_0 { - #sound-dai-cells = <0>; - compatible = "adi,axi-i2s-1.00.a"; - clocks = <&clkc 15>, <&i2s_clk>; - clock-names = "axi", "ref"; - dmas = <&dmac_s 0 &dmac_s 1>; - dma-names = "tx", "rx"; -}; - -&gem0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - local-mac-address = []; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <0>; - }; -}; - -&i2c0 { - eeprom@50 { - /* Microchip 24AA02E48 */ - compatible = "microchip,24c02"; - reg = <0x50>; - }; - - ssm2603: ssm2603@1a{ - #sound-dai-cells = <0>; - compatible = "adi,ssm2603"; - reg = <0x1a>; - }; -}; - -&qspi { - #address-cells = <1>; - #size-cells = <0>; - flash0: flash@0 { - compatible = "micron,m25p80", "s25fl128s"; - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - partition@0x00000000 { - label = "boot"; - reg = <0x00000000 0x00300000>; - }; - partition@0x00300000 { - label = "bootenv"; - reg = <0x00300000 0x00020000>; - }; - partition@0x00320000 { - label = "kernel"; - reg = <0x00320000 0x00a80000>; - }; - partition@0x00da0000 { - label = "spare"; - reg = <0x00da0000 0x00000000>; - }; - }; -}; - -&usb0 { - usb-phy = <&usb_phy0>; -}; - -&v_tc_0 { - compatible = "xlnx,v-tc-5.01.a"; -}; diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend deleted file mode 100644 index fbe42821..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bbappend +++ /dev/null @@ -1,4 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/platform-init:" - -COMPATIBLE_MACHINE:picozed-zynq7 = "picozed-zynq7" - diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c deleted file mode 100644 index 5587ab25..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c +++ /dev/null @@ -1,13191 +0,0 @@ -/****************************************************************************** -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see -* -* -******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init_gpl.c -* -* This file is automatically generated -* -*****************************************************************************/ - -#include "ps7_init_gpl.h" - -unsigned long ps7_pll_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_3_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reserved_reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCI_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. reserved_INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE_B = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCI_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. reserved_SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. reserved_DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. reserved_DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. reserved_SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. reserved_SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. reserved_GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. reserved_RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. reserved_VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. reserved_REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. reserved_REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reserved_VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reserved_VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reserved_VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reserved_VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[15:14] = 0x00000000U - // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reserved_INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reserved_TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reserved_TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reserved_TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. reserved_TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reserved_INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_3_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_LVL_INP_EN_0 = 1 - // .. ==> 0XF8000900[3:3] = 0x00000001U - // .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. USER_LVL_OUT_EN_0 = 1 - // .. ==> 0XF8000900[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. USER_LVL_INP_EN_1 = 1 - // .. ==> 0XF8000900[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. USER_LVL_OUT_EN_1 = 1 - // .. ==> 0XF8000900[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. reserved_FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. reserved_FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. reserved_FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. reserved_FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. reserved_FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. reserved_FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. reserved_FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. reserved_FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. reserved_FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_2_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 - // .. .. ==> 0XF8006078[3:0] = 0x00000001U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U - // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 - // .. .. ==> 0XF8006078[7:4] = 0x00000001U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U - // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 - // .. .. ==> 0XF8006078[11:8] = 0x00000001U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U - // .. .. reg_ddrc_t_cksre = 0x6 - // .. .. ==> 0XF8006078[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_t_cksrx = 0x6 - // .. .. ==> 0XF8006078[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_t_ckesr = 0x4 - // .. .. ==> 0XF8006078[25:20] = 0x00000004U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U - // .. .. - EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), - // .. .. reg_ddrc_t_ckpde = 0x2 - // .. .. ==> 0XF800607C[3:0] = 0x00000002U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U - // .. .. reg_ddrc_t_ckpdx = 0x2 - // .. .. ==> 0XF800607C[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. reg_ddrc_t_ckdpde = 0x2 - // .. .. ==> 0XF800607C[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_ckdpdx = 0x2 - // .. .. ==> 0XF800607C[15:12] = 0x00000002U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U - // .. .. reg_ddrc_t_ckcsx = 0x3 - // .. .. ==> 0XF800607C[19:16] = 0x00000003U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U - // .. .. - EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_TEST = 0x0 - // .. ==> 0XF8000B6C[11:10] = 0x00000000U - // .. ==> MASK : 0x00000C00U VAL : 0x00000000U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_2_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_pll_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: PLL SLCR REGISTERS - // .. .. START: ARM PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000110[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000110[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000110[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. ARM_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000001U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. SRCSEL = 0x0 - // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. .. DIVISOR = 0x3 - // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U - // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U - // .. .. .. CPU_6OR4XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U - // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. .. CPU_3OR2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U - // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U - // .. .. .. CPU_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U - // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. .. CPU_1XCLKACT = 0x1 - // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U - // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. .. CPU_PERI_CLKACT = 0x1 - // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U - // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), - // .. .. FINISH: ARM PLL INIT - // .. .. START: DDR PLL INIT - // .. .. PLL_RES = 0x2 - // .. .. ==> 0XF8000114[7:4] = 0x00000002U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000114[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0x12c - // .. .. ==> 0XF8000114[21:12] = 0x0000012CU - // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U - // .. .. - EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x20 - // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. DDR_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000002U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. .. DDR_3XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. DDR_2XCLKACT = 0x1 - // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U - // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. .. DDR_3XCLK_DIVISOR = 0x2 - // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U - // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U - // .. .. .. DDR_2XCLK_DIVISOR = 0x3 - // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U - // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), - // .. .. FINISH: DDR PLL INIT - // .. .. START: IO PLL INIT - // .. .. PLL_RES = 0x4 - // .. .. ==> 0XF8000118[7:4] = 0x00000004U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U - // .. .. PLL_CP = 0x2 - // .. .. ==> 0XF8000118[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. LOCK_CNT = 0xfa - // .. .. ==> 0XF8000118[21:12] = 0x000000FAU - // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U - // .. .. - EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), - // .. .. .. START: UPDATE FB_DIV - // .. .. .. PLL_FDIV = 0x3c - // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU - // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), - // .. .. .. FINISH: UPDATE FB_DIV - // .. .. .. START: BY PASS PLL - // .. .. .. PLL_BYPASS_FORCE = 1 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), - // .. .. .. FINISH: BY PASS PLL - // .. .. .. START: ASSERT RESET - // .. .. .. PLL_RESET = 1 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), - // .. .. .. FINISH: ASSERT RESET - // .. .. .. START: DEASSERT RESET - // .. .. .. PLL_RESET = 0 - // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U - // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), - // .. .. .. FINISH: DEASSERT RESET - // .. .. .. START: CHECK PLL STATUS - // .. .. .. IO_PLL_LOCK = 1 - // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U - // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. .. - EMIT_MASKPOLL(0XF800010C, 0x00000004U), - // .. .. .. FINISH: CHECK PLL STATUS - // .. .. .. START: REMOVE PLL BY PASS - // .. .. .. PLL_BYPASS_FORCE = 0 - // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U - // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. .. - EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), - // .. .. .. FINISH: REMOVE PLL BY PASS - // .. .. FINISH: IO PLL INIT - // .. FINISH: PLL SLCR REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_clock_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: CLOCK CONTROL SLCR REGISTERS - // .. CLKACT = 0x1 - // .. ==> 0XF8000128[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. DIVISOR0 = 0x23 - // .. ==> 0XF8000128[13:8] = 0x00000023U - // .. ==> MASK : 0x00003F00U VAL : 0x00002300U - // .. DIVISOR1 = 0x3 - // .. ==> 0XF8000128[25:20] = 0x00000003U - // .. ==> MASK : 0x03F00000U VAL : 0x00300000U - // .. - EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000138[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000138[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), - // .. CLKACT = 0x1 - // .. ==> 0XF8000140[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000140[6:4] = 0x00000000U - // .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. DIVISOR = 0x10 - // .. ==> 0XF8000140[13:8] = 0x00000010U - // .. ==> MASK : 0x00003F00U VAL : 0x00001000U - // .. DIVISOR1 = 0x1 - // .. ==> 0XF8000140[25:20] = 0x00000001U - // .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. - EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), - // .. CLKACT = 0x1 - // .. ==> 0XF800014C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. SRCSEL = 0x0 - // .. ==> 0XF800014C[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0xa - // .. ==> 0XF800014C[13:8] = 0x0000000AU - // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. - EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000150[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000150[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000150[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000150[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), - // .. CLKACT0 = 0x0 - // .. ==> 0XF8000154[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. CLKACT1 = 0x1 - // .. ==> 0XF8000154[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. SRCSEL = 0x0 - // .. ==> 0XF8000154[5:4] = 0x00000000U - // .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. DIVISOR = 0x28 - // .. ==> 0XF8000154[13:8] = 0x00000028U - // .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. - EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), - // .. .. START: TRACE CLOCK - // .. .. FINISH: TRACE CLOCK - // .. .. CLKACT = 0x1 - // .. .. ==> 0XF8000168[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000168[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR = 0xa - // .. .. ==> 0XF8000168[13:8] = 0x0000000AU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U - // .. .. - EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000170[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000170[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000170[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x14 - // .. .. ==> 0XF8000180[13:8] = 0x00000014U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x3c - // .. .. ==> 0XF8000190[13:8] = 0x0000003CU - // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x28 - // .. .. ==> 0XF80001A0[13:8] = 0x00000028U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), - // .. .. CLK_621_TRUE = 0x1 - // .. .. ==> 0XF80001C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. - EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), - // .. .. DMA_CPU_2XCLKACT = 0x1 - // .. .. ==> 0XF800012C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. USB0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[2:2] = 0x00000001U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. .. USB1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. GEM0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[6:6] = 0x00000001U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U - // .. .. GEM1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. SDI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. SDI1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[11:11] = 0x00000001U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U - // .. .. SPI0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. CAN0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. CAN1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. I2C0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[18:18] = 0x00000001U - // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U - // .. .. I2C1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. UART0_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. UART1_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. GPIO_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[22:22] = 0x00000001U - // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U - // .. .. LQSPI_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[23:23] = 0x00000001U - // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U - // .. .. SMC_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[24:24] = 0x00000001U - // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U - // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), - // .. FINISH: CLOCK CONTROL SLCR REGISTERS - // .. START: THIS SHOULD BE BLANK - // .. FINISH: THIS SHOULD BE BLANK - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_ddr_init_data_1_0[] = { - // START: top - // .. START: DDR INITIALIZATION - // .. .. START: LOCK DDR - // .. .. reg_ddrc_soft_rstb = 0 - // .. .. ==> 0XF8006000[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 0x1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), - // .. .. FINISH: LOCK DDR - // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 - // .. .. ==> 0XF8006004[11:0] = 0x00000081U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U - // .. .. reg_ddrc_active_ranks = 0x1 - // .. .. ==> 0XF8006004[13:12] = 0x00000001U - // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U - // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 - // .. .. ==> 0XF8006004[18:14] = 0x00000000U - // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_block = 0x1 - // .. .. ==> 0XF8006004[20:19] = 0x00000001U - // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U - // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 - // .. .. ==> 0XF8006004[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 - // .. .. ==> 0XF8006004[26:22] = 0x00000000U - // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_open_bank = 0x0 - // .. .. ==> 0XF8006004[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 - // .. .. ==> 0XF8006004[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), - // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf - // .. .. ==> 0XF8006008[10:0] = 0x0000000FU - // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU - // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf - // .. .. ==> 0XF8006008[21:11] = 0x0000000FU - // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U - // .. .. reg_ddrc_hpr_xact_run_length = 0xf - // .. .. ==> 0XF8006008[25:22] = 0x0000000FU - // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U - // .. .. - EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), - // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF800600C[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 - // .. .. ==> 0XF800600C[21:11] = 0x00000002U - // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U - // .. .. reg_ddrc_lpr_xact_run_length = 0x8 - // .. .. ==> 0XF800600C[25:22] = 0x00000008U - // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U - // .. .. - EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), - // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 - // .. .. ==> 0XF8006010[10:0] = 0x00000001U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U - // .. .. reg_ddrc_w_xact_run_length = 0x8 - // .. .. ==> 0XF8006010[14:11] = 0x00000008U - // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U - // .. .. reg_ddrc_w_max_starve_x32 = 0x2 - // .. .. ==> 0XF8006010[25:15] = 0x00000002U - // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U - // .. .. - EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), - // .. .. reg_ddrc_t_rc = 0x1a - // .. .. ==> 0XF8006014[5:0] = 0x0000001AU - // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU - // .. .. reg_ddrc_t_rfc_min = 0xa0 - // .. .. ==> 0XF8006014[13:6] = 0x000000A0U - // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U - // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 - // .. .. ==> 0XF8006014[20:14] = 0x00000010U - // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), - // .. .. reg_ddrc_wr2pre = 0x12 - // .. .. ==> 0XF8006018[4:0] = 0x00000012U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U - // .. .. reg_ddrc_powerdown_to_x32 = 0x6 - // .. .. ==> 0XF8006018[9:5] = 0x00000006U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U - // .. .. reg_ddrc_t_faw = 0x16 - // .. .. ==> 0XF8006018[15:10] = 0x00000016U - // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U - // .. .. reg_ddrc_t_ras_max = 0x24 - // .. .. ==> 0XF8006018[21:16] = 0x00000024U - // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U - // .. .. reg_ddrc_t_ras_min = 0x13 - // .. .. ==> 0XF8006018[26:22] = 0x00000013U - // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U - // .. .. reg_ddrc_t_cke = 0x4 - // .. .. ==> 0XF8006018[31:28] = 0x00000004U - // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), - // .. .. reg_ddrc_write_latency = 0x5 - // .. .. ==> 0XF800601C[4:0] = 0x00000005U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U - // .. .. reg_ddrc_rd2wr = 0x7 - // .. .. ==> 0XF800601C[9:5] = 0x00000007U - // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U - // .. .. reg_ddrc_wr2rd = 0xe - // .. .. ==> 0XF800601C[14:10] = 0x0000000EU - // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U - // .. .. reg_ddrc_t_xp = 0x4 - // .. .. ==> 0XF800601C[19:15] = 0x00000004U - // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U - // .. .. reg_ddrc_pad_pd = 0x0 - // .. .. ==> 0XF800601C[22:20] = 0x00000000U - // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U - // .. .. reg_ddrc_rd2pre = 0x4 - // .. .. ==> 0XF800601C[27:23] = 0x00000004U - // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U - // .. .. reg_ddrc_t_rcd = 0x7 - // .. .. ==> 0XF800601C[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), - // .. .. reg_ddrc_t_ccd = 0x4 - // .. .. ==> 0XF8006020[4:2] = 0x00000004U - // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U - // .. .. reg_ddrc_t_rrd = 0x6 - // .. .. ==> 0XF8006020[7:5] = 0x00000006U - // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U - // .. .. reg_ddrc_refresh_margin = 0x2 - // .. .. ==> 0XF8006020[11:8] = 0x00000002U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U - // .. .. reg_ddrc_t_rp = 0x7 - // .. .. ==> 0XF8006020[15:12] = 0x00000007U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U - // .. .. reg_ddrc_refresh_to_x32 = 0x8 - // .. .. ==> 0XF8006020[20:16] = 0x00000008U - // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U - // .. .. reg_ddrc_sdram = 0x1 - // .. .. ==> 0XF8006020[21:21] = 0x00000001U - // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U - // .. .. reg_ddrc_mobile = 0x0 - // .. .. ==> 0XF8006020[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. reg_ddrc_clock_stop_en = 0x0 - // .. .. ==> 0XF8006020[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. reg_ddrc_read_latency = 0x7 - // .. .. ==> 0XF8006020[28:24] = 0x00000007U - // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U - // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 - // .. .. ==> 0XF8006020[29:29] = 0x00000001U - // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U - // .. .. reg_ddrc_dis_pad_pd = 0x0 - // .. .. ==> 0XF8006020[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_ddrc_loopback = 0x0 - // .. .. ==> 0XF8006020[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), - // .. .. reg_ddrc_en_2t_timing_mode = 0x0 - // .. .. ==> 0XF8006024[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_prefer_write = 0x0 - // .. .. ==> 0XF8006024[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_max_rank_rd = 0xf - // .. .. ==> 0XF8006024[5:2] = 0x0000000FU - // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU - // .. .. reg_ddrc_mr_wr = 0x0 - // .. .. ==> 0XF8006024[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_ddrc_mr_addr = 0x0 - // .. .. ==> 0XF8006024[8:7] = 0x00000000U - // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. .. reg_ddrc_mr_data = 0x0 - // .. .. ==> 0XF8006024[24:9] = 0x00000000U - // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U - // .. .. ddrc_reg_mr_wr_busy = 0x0 - // .. .. ==> 0XF8006024[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_type = 0x0 - // .. .. ==> 0XF8006024[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. reg_ddrc_mr_rdata_valid = 0x0 - // .. .. ==> 0XF8006024[27:27] = 0x00000000U - // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), - // .. .. reg_ddrc_final_wait_x32 = 0x7 - // .. .. ==> 0XF8006028[6:0] = 0x00000007U - // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U - // .. .. reg_ddrc_pre_ocd_x32 = 0x0 - // .. .. ==> 0XF8006028[10:7] = 0x00000000U - // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U - // .. .. reg_ddrc_t_mrd = 0x4 - // .. .. ==> 0XF8006028[13:11] = 0x00000004U - // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U - // .. .. - EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), - // .. .. reg_ddrc_emr2 = 0x8 - // .. .. ==> 0XF800602C[15:0] = 0x00000008U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U - // .. .. reg_ddrc_emr3 = 0x0 - // .. .. ==> 0XF800602C[31:16] = 0x00000000U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), - // .. .. reg_ddrc_mr = 0x930 - // .. .. ==> 0XF8006030[15:0] = 0x00000930U - // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U - // .. .. reg_ddrc_emr = 0x4 - // .. .. ==> 0XF8006030[31:16] = 0x00000004U - // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U - // .. .. - EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), - // .. .. reg_ddrc_burst_rdwr = 0x4 - // .. .. ==> 0XF8006034[3:0] = 0x00000004U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U - // .. .. reg_ddrc_pre_cke_x1024 = 0x105 - // .. .. ==> 0XF8006034[13:4] = 0x00000105U - // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U - // .. .. reg_ddrc_post_cke_x1024 = 0x1 - // .. .. ==> 0XF8006034[25:16] = 0x00000001U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U - // .. .. reg_ddrc_burstchop = 0x0 - // .. .. ==> 0XF8006034[28:28] = 0x00000000U - // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), - // .. .. reg_ddrc_force_low_pri_n = 0x0 - // .. .. ==> 0XF8006038[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_dis_dq = 0x0 - // .. .. ==> 0XF8006038[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_debug_mode = 0x0 - // .. .. ==> 0XF8006038[6:6] = 0x00000000U - // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. .. reg_phy_wr_level_start = 0x0 - // .. .. ==> 0XF8006038[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_phy_rd_level_start = 0x0 - // .. .. ==> 0XF8006038[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_dq0_wait_t = 0x0 - // .. .. ==> 0XF8006038[12:9] = 0x00000000U - // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), - // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 - // .. .. ==> 0XF800603C[3:0] = 0x00000007U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U - // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 - // .. .. ==> 0XF800603C[7:4] = 0x00000007U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U - // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 - // .. .. ==> 0XF800603C[11:8] = 0x00000007U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U - // .. .. reg_ddrc_addrmap_col_b5 = 0x0 - // .. .. ==> 0XF800603C[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b6 = 0x0 - // .. .. ==> 0XF800603C[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), - // .. .. reg_ddrc_addrmap_col_b2 = 0x0 - // .. .. ==> 0XF8006040[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b3 = 0x0 - // .. .. ==> 0XF8006040[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b4 = 0x0 - // .. .. ==> 0XF8006040[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b7 = 0x0 - // .. .. ==> 0XF8006040[15:12] = 0x00000000U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b8 = 0x0 - // .. .. ==> 0XF8006040[19:16] = 0x00000000U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U - // .. .. reg_ddrc_addrmap_col_b9 = 0xf - // .. .. ==> 0XF8006040[23:20] = 0x0000000FU - // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U - // .. .. reg_ddrc_addrmap_col_b10 = 0xf - // .. .. ==> 0XF8006040[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. reg_ddrc_addrmap_col_b11 = 0xf - // .. .. ==> 0XF8006040[31:28] = 0x0000000FU - // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U - // .. .. - EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), - // .. .. reg_ddrc_addrmap_row_b0 = 0x6 - // .. .. ==> 0XF8006044[3:0] = 0x00000006U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U - // .. .. reg_ddrc_addrmap_row_b1 = 0x6 - // .. .. ==> 0XF8006044[7:4] = 0x00000006U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U - // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 - // .. .. ==> 0XF8006044[11:8] = 0x00000006U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U - // .. .. reg_ddrc_addrmap_row_b12 = 0x6 - // .. .. ==> 0XF8006044[15:12] = 0x00000006U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U - // .. .. reg_ddrc_addrmap_row_b13 = 0x6 - // .. .. ==> 0XF8006044[19:16] = 0x00000006U - // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U - // .. .. reg_ddrc_addrmap_row_b14 = 0x6 - // .. .. ==> 0XF8006044[23:20] = 0x00000006U - // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U - // .. .. reg_ddrc_addrmap_row_b15 = 0xf - // .. .. ==> 0XF8006044[27:24] = 0x0000000FU - // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U - // .. .. - EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), - // .. .. reg_ddrc_rank0_rd_odt = 0x0 - // .. .. ==> 0XF8006048[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_rank0_wr_odt = 0x1 - // .. .. ==> 0XF8006048[5:3] = 0x00000001U - // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U - // .. .. reg_ddrc_rank1_rd_odt = 0x1 - // .. .. ==> 0XF8006048[8:6] = 0x00000001U - // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U - // .. .. reg_ddrc_rank1_wr_odt = 0x1 - // .. .. ==> 0XF8006048[11:9] = 0x00000001U - // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. .. reg_phy_rd_local_odt = 0x0 - // .. .. ==> 0XF8006048[13:12] = 0x00000000U - // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U - // .. .. reg_phy_wr_local_odt = 0x3 - // .. .. ==> 0XF8006048[15:14] = 0x00000003U - // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U - // .. .. reg_phy_idle_local_odt = 0x3 - // .. .. ==> 0XF8006048[17:16] = 0x00000003U - // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U - // .. .. reg_ddrc_rank2_rd_odt = 0x0 - // .. .. ==> 0XF8006048[20:18] = 0x00000000U - // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U - // .. .. reg_ddrc_rank2_wr_odt = 0x0 - // .. .. ==> 0XF8006048[23:21] = 0x00000000U - // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_rd_odt = 0x0 - // .. .. ==> 0XF8006048[26:24] = 0x00000000U - // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. .. reg_ddrc_rank3_wr_odt = 0x0 - // .. .. ==> 0XF8006048[29:27] = 0x00000000U - // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), - // .. .. reg_phy_rd_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_wr_cmd_to_data = 0x0 - // .. .. ==> 0XF8006050[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_phy_rdc_we_to_re_delay = 0x8 - // .. .. ==> 0XF8006050[11:8] = 0x00000008U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U - // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 - // .. .. ==> 0XF8006050[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_phy_use_fixed_re = 0x1 - // .. .. ==> 0XF8006050[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 - // .. .. ==> 0XF8006050[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 - // .. .. ==> 0XF8006050[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_phy_clk_stall_level = 0x0 - // .. .. ==> 0XF8006050[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[27:24] = 0x00000007U - // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U - // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 - // .. .. ==> 0XF8006050[31:28] = 0x00000007U - // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U - // .. .. - EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), - // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 - // .. .. ==> 0XF8006058[7:0] = 0x00000001U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U - // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 - // .. .. ==> 0XF8006058[15:8] = 0x00000001U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U - // .. .. reg_ddrc_dis_dll_calib = 0x0 - // .. .. ==> 0XF8006058[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), - // .. .. reg_ddrc_rd_odt_delay = 0x3 - // .. .. ==> 0XF800605C[3:0] = 0x00000003U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U - // .. .. reg_ddrc_wr_odt_delay = 0x0 - // .. .. ==> 0XF800605C[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. reg_ddrc_rd_odt_hold = 0x0 - // .. .. ==> 0XF800605C[11:8] = 0x00000000U - // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U - // .. .. reg_ddrc_wr_odt_hold = 0x5 - // .. .. ==> 0XF800605C[15:12] = 0x00000005U - // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), - // .. .. reg_ddrc_pageclose = 0x0 - // .. .. ==> 0XF8006060[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_lpr_num_entries = 0x1f - // .. .. ==> 0XF8006060[6:1] = 0x0000001FU - // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU - // .. .. reg_ddrc_auto_pre_en = 0x0 - // .. .. ==> 0XF8006060[7:7] = 0x00000000U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. .. reg_ddrc_refresh_update_level = 0x0 - // .. .. ==> 0XF8006060[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_ddrc_dis_wc = 0x0 - // .. .. ==> 0XF8006060[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_ddrc_dis_collision_page_opt = 0x0 - // .. .. ==> 0XF8006060[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_ddrc_selfref_en = 0x0 - // .. .. ==> 0XF8006060[12:12] = 0x00000000U - // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), - // .. .. reg_ddrc_go2critical_hysteresis = 0x0 - // .. .. ==> 0XF8006064[12:5] = 0x00000000U - // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U - // .. .. reg_arb_go2critical_en = 0x1 - // .. .. ==> 0XF8006064[17:17] = 0x00000001U - // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U - // .. .. - EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), - // .. .. reg_ddrc_wrlvl_ww = 0x41 - // .. .. ==> 0XF8006068[7:0] = 0x00000041U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U - // .. .. reg_ddrc_rdlvl_rr = 0x41 - // .. .. ==> 0XF8006068[15:8] = 0x00000041U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U - // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 - // .. .. ==> 0XF8006068[25:16] = 0x00000028U - // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U - // .. .. - EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), - // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 - // .. .. ==> 0XF800606C[7:0] = 0x00000010U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U - // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 - // .. .. ==> 0XF800606C[15:8] = 0x00000016U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U - // .. .. - EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), - // .. .. refresh_timer0_start_value_x32 = 0x0 - // .. .. ==> 0XF80060A0[11:0] = 0x00000000U - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U - // .. .. refresh_timer1_start_value_x32 = 0x8 - // .. .. ==> 0XF80060A0[23:12] = 0x00000008U - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U - // .. .. - EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), - // .. .. reg_ddrc_dis_auto_zq = 0x0 - // .. .. ==> 0XF80060A4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_ddr3 = 0x1 - // .. .. ==> 0XF80060A4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. reg_ddrc_t_mod = 0x200 - // .. .. ==> 0XF80060A4[11:2] = 0x00000200U - // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U - // .. .. reg_ddrc_t_zq_long_nop = 0x200 - // .. .. ==> 0XF80060A4[21:12] = 0x00000200U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U - // .. .. reg_ddrc_t_zq_short_nop = 0x40 - // .. .. ==> 0XF80060A4[31:22] = 0x00000040U - // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), - // .. .. t_zq_short_interval_x1024 = 0xcb73 - // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U - // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U - // .. .. dram_rstn_x1024 = 0x69 - // .. .. ==> 0XF80060A8[27:20] = 0x00000069U - // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U - // .. .. - EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), - // .. .. deeppowerdown_en = 0x0 - // .. .. ==> 0XF80060AC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. deeppowerdown_to_x1024 = 0xff - // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU - // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU - // .. .. - EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), - // .. .. dfi_wrlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU - // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU - // .. .. dfi_rdlvl_max_x1024 = 0xfff - // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU - // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U - // .. .. ddrc_reg_twrlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. ddrc_reg_trdlvl_max_error = 0x0 - // .. .. ==> 0XF80060B0[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. reg_ddrc_dfi_wr_level_en = 0x1 - // .. .. ==> 0XF80060B0[26:26] = 0x00000001U - // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U - // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF80060B0[27:27] = 0x00000001U - // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U - // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 - // .. .. ==> 0XF80060B0[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. - EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), - // .. .. reg_ddrc_2t_delay = 0x0 - // .. .. ==> 0XF80060B4[8:0] = 0x00000000U - // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U - // .. .. reg_ddrc_skip_ocd = 0x1 - // .. .. ==> 0XF80060B4[9:9] = 0x00000001U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. .. reg_ddrc_dis_pre_bypass = 0x0 - // .. .. ==> 0XF80060B4[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), - // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 - // .. .. ==> 0XF80060B8[4:0] = 0x00000006U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U - // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 - // .. .. ==> 0XF80060B8[14:5] = 0x00000003U - // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U - // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 - // .. .. ==> 0XF80060B8[24:15] = 0x00000040U - // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U - // .. .. - EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 - // .. .. ==> 0XF80060C4[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), - // .. .. CORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060C8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. ECC_CORRECTED_BIT_NUM = 0x0 - // .. .. ==> 0XF80060C8[7:1] = 0x00000000U - // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), - // .. .. UNCORR_ECC_LOG_VALID = 0x0 - // .. .. ==> 0XF80060DC[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), - // .. .. STAT_NUM_CORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[15:8] = 0x00000000U - // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U - // .. .. STAT_NUM_UNCORR_ERR = 0x0 - // .. .. ==> 0XF80060F0[7:0] = 0x00000000U - // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), - // .. .. reg_ddrc_ecc_mode = 0x0 - // .. .. ==> 0XF80060F4[2:0] = 0x00000000U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U - // .. .. reg_ddrc_dis_scrub = 0x1 - // .. .. ==> 0XF80060F4[3:3] = 0x00000001U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U - // .. .. - EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), - // .. .. reg_phy_dif_on = 0x0 - // .. .. ==> 0XF8006114[3:0] = 0x00000000U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U - // .. .. reg_phy_dif_off = 0x0 - // .. .. ==> 0XF8006114[7:4] = 0x00000000U - // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006118[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006118[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006118[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006118[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006118[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006118[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006118[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF800611C[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF800611C[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF800611C[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF800611C[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF800611C[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF800611C[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF800611C[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006120[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006120[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006120[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006120[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006120[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006120[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006120[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_data_slice_in_use = 0x1 - // .. .. ==> 0XF8006124[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_phy_rdlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_gatelvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_wrlvl_inc_mode = 0x0 - // .. .. ==> 0XF8006124[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_tx = 0x0 - // .. .. ==> 0XF8006124[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_board_lpbk_rx = 0x0 - // .. .. ==> 0XF8006124[5:5] = 0x00000000U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. .. reg_phy_bist_shift_dq = 0x0 - // .. .. ==> 0XF8006124[14:6] = 0x00000000U - // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U - // .. .. reg_phy_bist_err_clr = 0x0 - // .. .. ==> 0XF8006124[23:15] = 0x00000000U - // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U - // .. .. reg_phy_dq_offset = 0x40 - // .. .. ==> 0XF8006124[30:24] = 0x00000040U - // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U - // .. .. - EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF800612C[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa1 - // .. .. ==> 0XF800612C[19:10] = 0x000000A1U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U - // .. .. - EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), - // .. .. reg_phy_wrlvl_init_ratio = 0x0 - // .. .. ==> 0XF8006130[9:0] = 0x00000000U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U - // .. .. reg_phy_gatelvl_init_ratio = 0xa0 - // .. .. ==> 0XF8006130[19:10] = 0x000000A0U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U - // .. .. - EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006134[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006134[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_wrlvl_init_ratio = 0x7 - // .. .. ==> 0XF8006138[9:0] = 0x00000007U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U - // .. .. reg_phy_gatelvl_init_ratio = 0xad - // .. .. ==> 0XF8006138[19:10] = 0x000000ADU - // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U - // .. .. - EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006140[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006140[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006140[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006144[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006144[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006144[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF8006148[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006148[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006148[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 - // .. .. ==> 0XF800614C[9:0] = 0x00000035U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U - // .. .. reg_phy_rd_dqs_slave_force = 0x0 - // .. .. ==> 0XF800614C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_rd_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800614C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006154[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006154[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006154[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c - // .. .. ==> 0XF8006158[9:0] = 0x0000007CU - // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006158[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006158[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF800615C[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF800615C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF800615C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 - // .. .. ==> 0XF8006160[9:0] = 0x00000087U - // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U - // .. .. reg_phy_wr_dqs_slave_force = 0x0 - // .. .. ==> 0XF8006160[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_dqs_slave_delay = 0x0 - // .. .. ==> 0XF8006160[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 - // .. .. ==> 0XF8006168[10:0] = 0x000000F6U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006168[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006168[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), - // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 - // .. .. ==> 0XF800616C[10:0] = 0x000000F5U - // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF800616C[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF800616C[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006170[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006170[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006170[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_fifo_we_slave_ratio = 0x102 - // .. .. ==> 0XF8006174[10:0] = 0x00000102U - // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U - // .. .. reg_phy_fifo_we_in_force = 0x0 - // .. .. ==> 0XF8006174[11:11] = 0x00000000U - // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. reg_phy_fifo_we_in_delay = 0x0 - // .. .. ==> 0XF8006174[20:12] = 0x00000000U - // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF800617C[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF800617C[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF800617C[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xbc - // .. .. ==> 0XF8006180[9:0] = 0x000000BCU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006180[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006180[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006184[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006184[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006184[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_wr_data_slave_ratio = 0xc7 - // .. .. ==> 0XF8006188[9:0] = 0x000000C7U - // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U - // .. .. reg_phy_wr_data_slave_force = 0x0 - // .. .. ==> 0XF8006188[10:10] = 0x00000000U - // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. .. reg_phy_wr_data_slave_delay = 0x0 - // .. .. ==> 0XF8006188[19:11] = 0x00000000U - // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), - // .. .. reg_phy_loopback = 0x0 - // .. .. ==> 0XF8006190[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_phy_bl2 = 0x0 - // .. .. ==> 0XF8006190[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_phy_at_spd_atpg = 0x0 - // .. .. ==> 0XF8006190[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_phy_bist_enable = 0x0 - // .. .. ==> 0XF8006190[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. reg_phy_bist_force_err = 0x0 - // .. .. ==> 0XF8006190[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. reg_phy_bist_mode = 0x0 - // .. .. ==> 0XF8006190[6:5] = 0x00000000U - // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. .. reg_phy_invert_clkout = 0x1 - // .. .. ==> 0XF8006190[7:7] = 0x00000001U - // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 - // .. .. ==> 0XF8006190[8:8] = 0x00000000U - // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. .. reg_phy_sel_logic = 0x0 - // .. .. ==> 0XF8006190[9:9] = 0x00000000U - // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_ratio = 0x100 - // .. .. ==> 0XF8006190[19:10] = 0x00000100U - // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U - // .. .. reg_phy_ctrl_slave_force = 0x0 - // .. .. ==> 0XF8006190[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006190[27:21] = 0x00000000U - // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U - // .. .. reg_phy_use_rank0_delays = 0x1 - // .. .. ==> 0XF8006190[28:28] = 0x00000001U - // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U - // .. .. reg_phy_lpddr = 0x0 - // .. .. ==> 0XF8006190[29:29] = 0x00000000U - // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. .. reg_phy_cmd_latency = 0x0 - // .. .. ==> 0XF8006190[30:30] = 0x00000000U - // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U - // .. .. reg_phy_int_lpbk = 0x0 - // .. .. ==> 0XF8006190[31:31] = 0x00000000U - // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), - // .. .. reg_phy_wr_rl_delay = 0x2 - // .. .. ==> 0XF8006194[4:0] = 0x00000002U - // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U - // .. .. reg_phy_rd_rl_delay = 0x4 - // .. .. ==> 0XF8006194[9:5] = 0x00000004U - // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U - // .. .. reg_phy_dll_lock_diff = 0xf - // .. .. ==> 0XF8006194[13:10] = 0x0000000FU - // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U - // .. .. reg_phy_use_wr_level = 0x1 - // .. .. ==> 0XF8006194[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 - // .. .. ==> 0XF8006194[15:15] = 0x00000001U - // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U - // .. .. reg_phy_use_rd_data_eye_level = 0x1 - // .. .. ==> 0XF8006194[16:16] = 0x00000001U - // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U - // .. .. reg_phy_dis_calib_rst = 0x0 - // .. .. ==> 0XF8006194[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_phy_ctrl_slave_delay = 0x0 - // .. .. ==> 0XF8006194[19:18] = 0x00000000U - // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), - // .. .. reg_arb_page_addr_mask = 0x0 - // .. .. ==> 0XF8006204[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006208[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006208[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006208[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006208[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006208[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF800620C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF800620C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF800620C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF800620C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF800620C[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006210[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006210[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006210[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006210[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006210[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_wr_portn = 0x3ff - // .. .. ==> 0XF8006214[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_wr_portn = 0x0 - // .. .. ==> 0XF8006214[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_wr_portn = 0x0 - // .. .. ==> 0XF8006214[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_wr_portn = 0x0 - // .. .. ==> 0XF8006214[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_dis_rmw_portn = 0x1 - // .. .. ==> 0XF8006214[19:19] = 0x00000001U - // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. .. - EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006218[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006218[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006218[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006218[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006218[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF800621C[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF800621C[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF800621C[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF800621C[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF800621C[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006220[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006220[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006220[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006220[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006220[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), - // .. .. reg_arb_pri_rd_portn = 0x3ff - // .. .. ==> 0XF8006224[9:0] = 0x000003FFU - // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU - // .. .. reg_arb_disable_aging_rd_portn = 0x0 - // .. .. ==> 0XF8006224[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. reg_arb_disable_urgent_rd_portn = 0x0 - // .. .. ==> 0XF8006224[17:17] = 0x00000000U - // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. .. reg_arb_dis_page_match_rd_portn = 0x0 - // .. .. ==> 0XF8006224[18:18] = 0x00000000U - // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U - // .. .. reg_arb_set_hpr_rd_portn = 0x0 - // .. .. ==> 0XF8006224[19:19] = 0x00000000U - // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), - // .. .. reg_ddrc_lpddr2 = 0x0 - // .. .. ==> 0XF80062A8[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. reg_ddrc_per_bank_refresh = 0x0 - // .. .. ==> 0XF80062A8[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_derate_enable = 0x0 - // .. .. ==> 0XF80062A8[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. reg_ddrc_mr4_margin = 0x0 - // .. .. ==> 0XF80062A8[11:4] = 0x00000000U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), - // .. .. reg_ddrc_mr4_read_interval = 0x0 - // .. .. ==> 0XF80062AC[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), - // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 - // .. .. ==> 0XF80062B0[3:0] = 0x00000005U - // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U - // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 - // .. .. ==> 0XF80062B0[11:4] = 0x00000012U - // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U - // .. .. reg_ddrc_t_mrw = 0x5 - // .. .. ==> 0XF80062B0[21:12] = 0x00000005U - // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U - // .. .. - EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), - // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 - // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U - // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U - // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 - // .. .. ==> 0XF80062B4[17:8] = 0x00000012U - // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U - // .. .. - EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), - // .. .. START: POLL ON DCI STATUS - // .. .. DONE = 1 - // .. .. ==> 0XF8000B74[13:13] = 0x00000001U - // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U - // .. .. - EMIT_MASKPOLL(0XF8000B74, 0x00002000U), - // .. .. FINISH: POLL ON DCI STATUS - // .. .. START: UNLOCK DDR - // .. .. reg_ddrc_soft_rstb = 0x1 - // .. .. ==> 0XF8006000[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. reg_ddrc_powerdown_en = 0x0 - // .. .. ==> 0XF8006000[1:1] = 0x00000000U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. .. reg_ddrc_data_bus_width = 0x0 - // .. .. ==> 0XF8006000[3:2] = 0x00000000U - // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U - // .. .. reg_ddrc_burst8_refresh = 0x0 - // .. .. ==> 0XF8006000[6:4] = 0x00000000U - // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U - // .. .. reg_ddrc_rdwr_idle_gap = 1 - // .. .. ==> 0XF8006000[13:7] = 0x00000001U - // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U - // .. .. reg_ddrc_dis_rd_bypass = 0x0 - // .. .. ==> 0XF8006000[14:14] = 0x00000000U - // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_act_bypass = 0x0 - // .. .. ==> 0XF8006000[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U - // .. .. reg_ddrc_dis_auto_refresh = 0x0 - // .. .. ==> 0XF8006000[16:16] = 0x00000000U - // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), - // .. .. FINISH: UNLOCK DDR - // .. .. START: CHECK DDR STATUS - // .. .. ddrc_reg_operating_mode = 1 - // .. .. ==> 0XF8006054[2:0] = 0x00000001U - // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U - // .. .. - EMIT_MASKPOLL(0XF8006054, 0x00000007U), - // .. .. FINISH: CHECK DDR STATUS - // .. FINISH: DDR INITIALIZATION - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_mio_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: OCM REMAPPING - // .. FINISH: OCM REMAPPING - // .. START: DDRIOB SETTINGS - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B40[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B40[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B40[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B40[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B40[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B40[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B40[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B40[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B44[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B44[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B44[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B44[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B44[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B44[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B44[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B44[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B48[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B48[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B48[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B48[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B48[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B48[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B48[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B48[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B4C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x1 - // .. ==> 0XF8000B4C[2:1] = 0x00000001U - // .. ==> MASK : 0x00000006U VAL : 0x00000002U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B4C[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B4C[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B4C[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B4C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B4C[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B4C[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B50[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B50[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B50[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B50[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B50[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B50[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B50[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B50[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B54[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x2 - // .. ==> 0XF8000B54[2:1] = 0x00000002U - // .. ==> MASK : 0x00000006U VAL : 0x00000004U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B54[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x1 - // .. ==> 0XF8000B54[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. DCR_TYPE = 0x3 - // .. ==> 0XF8000B54[6:5] = 0x00000003U - // .. ==> MASK : 0x00000060U VAL : 0x00000060U - // .. IBUF_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0 - // .. ==> 0XF8000B54[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B54[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B54[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), - // .. INP_POWER = 0x0 - // .. ==> 0XF8000B58[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. INP_TYPE = 0x0 - // .. ==> 0XF8000B58[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. DCI_UPDATE = 0x0 - // .. ==> 0XF8000B58[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. TERM_EN = 0x0 - // .. ==> 0XF8000B58[4:4] = 0x00000000U - // .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. DCR_TYPE = 0x0 - // .. ==> 0XF8000B58[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. IBUF_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. TERM_DISABLE_MODE = 0x0 - // .. ==> 0XF8000B58[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. OUTPUT_EN = 0x3 - // .. ==> 0XF8000B58[10:9] = 0x00000003U - // .. ==> MASK : 0x00000600U VAL : 0x00000600U - // .. PULLUP_EN = 0x0 - // .. ==> 0XF8000B58[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B5C[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B5C[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x3 - // .. ==> 0XF8000B5C[18:14] = 0x00000003U - // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U - // .. SLEW_N = 0x3 - // .. ==> 0XF8000B5C[23:19] = 0x00000003U - // .. ==> MASK : 0x00F80000U VAL : 0x00180000U - // .. GTL = 0x0 - // .. ==> 0XF8000B5C[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B5C[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B60[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B60[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B60[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B60[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B60[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B60[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B64[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B64[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B64[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B64[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B64[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B64[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), - // .. DRIVE_P = 0x1c - // .. ==> 0XF8000B68[6:0] = 0x0000001CU - // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU - // .. DRIVE_N = 0xc - // .. ==> 0XF8000B68[13:7] = 0x0000000CU - // .. ==> MASK : 0x00003F80U VAL : 0x00000600U - // .. SLEW_P = 0x6 - // .. ==> 0XF8000B68[18:14] = 0x00000006U - // .. ==> MASK : 0x0007C000U VAL : 0x00018000U - // .. SLEW_N = 0x1f - // .. ==> 0XF8000B68[23:19] = 0x0000001FU - // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U - // .. GTL = 0x0 - // .. ==> 0XF8000B68[26:24] = 0x00000000U - // .. ==> MASK : 0x07000000U VAL : 0x00000000U - // .. RTERM = 0x0 - // .. ==> 0XF8000B68[31:27] = 0x00000000U - // .. ==> MASK : 0xF8000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), - // .. VREF_INT_EN = 0x1 - // .. ==> 0XF8000B6C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. VREF_SEL = 0x4 - // .. ==> 0XF8000B6C[4:1] = 0x00000004U - // .. ==> MASK : 0x0000001EU VAL : 0x00000008U - // .. VREF_EXT_EN = 0x0 - // .. ==> 0XF8000B6C[6:5] = 0x00000000U - // .. ==> MASK : 0x00000060U VAL : 0x00000000U - // .. VREF_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[8:7] = 0x00000000U - // .. ==> MASK : 0x00000180U VAL : 0x00000000U - // .. REFIO_EN = 0x1 - // .. ==> 0XF8000B6C[9:9] = 0x00000001U - // .. ==> MASK : 0x00000200U VAL : 0x00000200U - // .. REFIO_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DRST_B_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. CKE_PULLUP_EN = 0x0 - // .. ==> 0XF8000B6C[14:14] = 0x00000000U - // .. ==> MASK : 0x00004000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), - // .. .. START: ASSERT RESET - // .. .. RESET = 1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), - // .. .. FINISH: ASSERT RESET - // .. .. START: DEASSERT RESET - // .. .. RESET = 0 - // .. .. ==> 0XF8000B70[0:0] = 0x00000000U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), - // .. .. FINISH: DEASSERT RESET - // .. .. RESET = 0x1 - // .. .. ==> 0XF8000B70[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. ENABLE = 0x1 - // .. .. ==> 0XF8000B70[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. VRP_TRI = 0x0 - // .. .. ==> 0XF8000B70[2:2] = 0x00000000U - // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. .. VRN_TRI = 0x0 - // .. .. ==> 0XF8000B70[3:3] = 0x00000000U - // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. .. VRP_OUT = 0x0 - // .. .. ==> 0XF8000B70[4:4] = 0x00000000U - // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U - // .. .. VRN_OUT = 0x1 - // .. .. ==> 0XF8000B70[5:5] = 0x00000001U - // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U - // .. .. NREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[7:6] = 0x00000000U - // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. .. NREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[10:8] = 0x00000000U - // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U - // .. .. NREF_OPT4 = 0x1 - // .. .. ==> 0XF8000B70[13:11] = 0x00000001U - // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U - // .. .. PREF_OPT1 = 0x0 - // .. .. ==> 0XF8000B70[16:14] = 0x00000000U - // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U - // .. .. PREF_OPT2 = 0x0 - // .. .. ==> 0XF8000B70[19:17] = 0x00000000U - // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U - // .. .. UPDATE_CONTROL = 0x0 - // .. .. ==> 0XF8000B70[20:20] = 0x00000000U - // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. .. INIT_COMPLETE = 0x0 - // .. .. ==> 0XF8000B70[21:21] = 0x00000000U - // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. .. TST_CLK = 0x0 - // .. .. ==> 0XF8000B70[22:22] = 0x00000000U - // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. .. TST_HLN = 0x0 - // .. .. ==> 0XF8000B70[23:23] = 0x00000000U - // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. .. TST_HLP = 0x0 - // .. .. ==> 0XF8000B70[24:24] = 0x00000000U - // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. .. TST_RST = 0x0 - // .. .. ==> 0XF8000B70[25:25] = 0x00000000U - // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U - // .. .. INT_DCI_EN = 0x0 - // .. .. ==> 0XF8000B70[26:26] = 0x00000000U - // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), - // .. FINISH: DDRIOB SETTINGS - // .. START: MIO PROGRAMMING - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000700[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000700[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000700[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000700[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000700[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000700[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000700[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000700[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000700[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000704[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000704[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000704[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000704[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000704[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000704[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000704[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000704[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000704[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000708[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000708[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000708[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000708[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000708[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000708[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000708[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000708[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000708[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800070C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800070C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800070C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800070C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800070C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800070C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800070C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800070C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800070C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000710[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000710[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000710[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000710[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000710[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000710[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000710[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000710[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000710[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000714[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000714[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000714[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000714[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000714[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000714[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000714[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000714[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000714[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000718[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000718[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000718[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000718[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000718[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000718[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000718[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000718[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000718[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800071C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800071C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800071C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800071C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800071C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800071C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800071C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800071C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800071C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000720[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000720[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000720[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000720[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000720[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000720[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000720[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000720[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000720[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000724[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000724[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000724[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000724[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000724[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000724[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000724[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000724[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000724[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000728[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000728[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000728[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000728[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000728[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000728[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000728[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000728[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000728[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800072C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800072C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800072C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800072C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800072C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800072C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800072C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800072C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800072C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000730[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000730[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000730[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000730[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000730[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000730[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000730[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000730[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000730[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000734[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000734[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000734[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000734[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000734[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000734[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000734[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000734[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000734[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000738[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000738[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF8000738[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000738[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF8000738[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF8000738[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF8000738[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF8000738[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000738[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800073C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800073C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF800073C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800073C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF800073C[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF800073C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 3 - // .. ==> 0XF800073C[11:9] = 0x00000003U - // .. ==> MASK : 0x00000E00U VAL : 0x00000600U - // .. PULLUP = 0 - // .. ==> 0XF800073C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800073C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000740[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000740[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000740[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000740[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000740[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000740[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000740[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000740[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000740[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000744[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000744[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000744[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000744[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000744[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000744[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000744[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000744[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000744[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000748[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000748[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000748[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000748[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000748[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000748[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000748[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000748[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000748[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800074C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF800074C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800074C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800074C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800074C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800074C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800074C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800074C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800074C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000750[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000750[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000750[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000750[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000750[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000750[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000750[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000750[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000750[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000754[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 1 - // .. ==> 0XF8000754[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000754[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000754[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000754[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000754[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000754[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000754[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000754[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000758[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000758[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000758[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000758[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000758[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000758[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000758[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000758[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000758[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800075C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800075C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800075C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800075C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800075C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800075C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800075C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800075C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800075C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000760[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000760[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000760[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000760[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000760[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000760[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000760[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000760[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000760[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000764[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000764[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000764[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000764[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000764[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000764[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000764[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000764[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000764[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000768[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF8000768[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF8000768[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF8000768[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000768[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000768[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000768[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000768[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000768[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800076C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 1 - // .. ==> 0XF800076C[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. L1_SEL = 0 - // .. ==> 0XF800076C[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF800076C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800076C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800076C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800076C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800076C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800076C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000770[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000770[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000770[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000770[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000770[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000770[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000770[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000770[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000770[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000774[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000774[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000774[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000774[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000774[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000774[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000774[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000774[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000774[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000778[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000778[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000778[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000778[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000778[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000778[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000778[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000778[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000778[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF800077C[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF800077C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800077C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800077C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800077C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800077C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800077C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800077C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800077C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000780[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000780[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000780[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000780[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000780[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000780[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000780[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000780[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000780[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000784[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000784[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000784[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000784[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000784[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000784[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000784[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000784[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000784[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000788[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000788[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000788[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000788[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000788[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000788[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000788[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000788[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000788[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800078C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800078C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800078C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800078C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800078C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800078C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800078C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800078C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800078C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF8000790[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF8000790[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000790[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000790[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000790[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000790[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000790[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000790[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000790[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000794[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000794[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000794[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000794[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000794[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000794[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000794[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000794[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000794[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF8000798[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF8000798[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF8000798[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF8000798[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF8000798[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF8000798[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF8000798[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF8000798[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF8000798[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF800079C[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF800079C[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 1 - // .. ==> 0XF800079C[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. L2_SEL = 0 - // .. ==> 0XF800079C[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF800079C[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF800079C[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF800079C[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF800079C[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF800079C[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007A8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007A8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007A8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007A8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007A8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007A8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007A8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007A8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007A8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007AC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007AC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007AC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007AC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007AC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007AC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007AC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007AC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007AC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B0[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B4[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007B8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007B8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007B8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007B8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007B8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007B8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007B8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007B8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007B8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007BC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007BC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007BC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007BC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007BC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007BC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007BC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007BC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007BC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C0[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), - // .. TRI_ENABLE = 1 - // .. ==> 0XF80007C4[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. L0_SEL = 0 - // .. ==> 0XF80007C4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 7 - // .. ==> 0XF80007C4[7:5] = 0x00000007U - // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U - // .. Speed = 0 - // .. ==> 0XF80007C4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007C8[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007C8[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007C8[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007C8[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007C8[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007C8[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007C8[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007C8[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007C8[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007CC[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007CC[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007CC[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007CC[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 0 - // .. ==> 0XF80007CC[7:5] = 0x00000000U - // .. ==> MASK : 0x000000E0U VAL : 0x00000000U - // .. Speed = 0 - // .. ==> 0XF80007CC[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007CC[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007CC[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007CC[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D0[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D0[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D0[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D0[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D0[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D0[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D0[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D0[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D0[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), - // .. TRI_ENABLE = 0 - // .. ==> 0XF80007D4[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. L0_SEL = 0 - // .. ==> 0XF80007D4[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. L1_SEL = 0 - // .. ==> 0XF80007D4[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. L2_SEL = 0 - // .. ==> 0XF80007D4[4:3] = 0x00000000U - // .. ==> MASK : 0x00000018U VAL : 0x00000000U - // .. L3_SEL = 4 - // .. ==> 0XF80007D4[7:5] = 0x00000004U - // .. ==> MASK : 0x000000E0U VAL : 0x00000080U - // .. Speed = 0 - // .. ==> 0XF80007D4[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. IO_Type = 1 - // .. ==> 0XF80007D4[11:9] = 0x00000001U - // .. ==> MASK : 0x00000E00U VAL : 0x00000200U - // .. PULLUP = 0 - // .. ==> 0XF80007D4[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. DisableRcvr = 0 - // .. ==> 0XF80007D4[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), - // .. SDIO1_CD_SEL = 58 - // .. ==> 0XF8000834[21:16] = 0x0000003AU - // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U - // .. - EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), - // .. FINISH: MIO PROGRAMMING - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_peripherals_init_data_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B48[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B4C[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B50[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), - // .. IBUF_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[7:7] = 0x00000001U - // .. ==> MASK : 0x00000080U VAL : 0x00000080U - // .. TERM_DISABLE_MODE = 0x1 - // .. ==> 0XF8000B54[8:8] = 0x00000001U - // .. ==> MASK : 0x00000100U VAL : 0x00000100U - // .. - EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), - // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // .. START: SRAM/NOR SET OPMODE - // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: QSPI REGISTERS - // .. Holdb_dr = 1 - // .. ==> 0XE000D000[19:19] = 0x00000001U - // .. ==> MASK : 0x00080000U VAL : 0x00080000U - // .. - EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), - // .. FINISH: QSPI REGISTERS - // .. START: PL POWER ON RESET REGISTERS - // .. PCFG_POR_CNT_4K = 0 - // .. ==> 0XF8007000[29:29] = 0x00000000U - // .. ==> MASK : 0x20000000U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), - // .. FINISH: PL POWER ON RESET REGISTERS - // .. START: SMC TIMING CALCULATION REGISTER UPDATE - // .. .. START: NAND SET CYCLE - // .. .. FINISH: NAND SET CYCLE - // .. .. START: OPMODE - // .. .. FINISH: OPMODE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: SRAM/NOR CS0 SET CYCLE - // .. .. FINISH: SRAM/NOR CS0 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS0 BASE ADDRESS - // .. .. FINISH: NOR CS0 BASE ADDRESS - // .. .. START: SRAM/NOR CS1 SET CYCLE - // .. .. FINISH: SRAM/NOR CS1 SET CYCLE - // .. .. START: DIRECT COMMAND - // .. .. FINISH: DIRECT COMMAND - // .. .. START: NOR CS1 BASE ADDRESS - // .. .. FINISH: NOR CS1 BASE ADDRESS - // .. .. START: USB RESET - // .. .. .. START: USB0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. DIRECTION_0 = 0x80 - // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. OP_ENABLE_0 = 0x80 - // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x0 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. MASK_0_LSW = 0xff7f - // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU - // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U - // .. .. .. .. DATA_0_LSW = 0x80 - // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U - // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U - // .. .. .. .. - EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB0 RESET - // .. .. .. START: USB1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: USB1 RESET - // .. .. FINISH: USB RESET - // .. .. START: ENET RESET - // .. .. .. START: ENET0 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET0 RESET - // .. .. .. START: ENET1 RESET - // .. .. .. .. START: DIR MODE BANK 0 - // .. .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. .. START: DIR MODE BANK 1 - // .. .. .. .. FINISH: DIR MODE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. .. .. START: OUTPUT ENABLE BANK 1 - // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: ENET1 RESET - // .. .. FINISH: ENET RESET - // .. .. START: I2C RESET - // .. .. .. START: I2C0 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C0 RESET - // .. .. .. START: I2C1 RESET - // .. .. .. .. START: DIR MODE GPIO BANK0 - // .. .. .. .. FINISH: DIR MODE GPIO BANK0 - // .. .. .. .. START: DIR MODE GPIO BANK1 - // .. .. .. .. FINISH: DIR MODE GPIO BANK1 - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: OUTPUT ENABLE - // .. .. .. .. FINISH: OUTPUT ENABLE - // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] - // .. .. .. .. START: ADD 1 MS DELAY - // .. .. .. .. - EMIT_MASKDELAY(0XF8F00200, 1), - // .. .. .. .. FINISH: ADD 1 MS DELAY - // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] - // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] - // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] - // .. .. .. FINISH: I2C1 RESET - // .. .. FINISH: I2C RESET - // .. .. START: NOR CHIP SELECT - // .. .. .. START: DIR MODE BANK 0 - // .. .. .. FINISH: DIR MODE BANK 0 - // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] - // .. .. .. START: OUTPUT ENABLE BANK 0 - // .. .. .. FINISH: OUTPUT ENABLE BANK 0 - // .. .. FINISH: NOR CHIP SELECT - // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_post_config_1_0[] = { - // START: top - // .. START: SLCR SETTINGS - // .. UNLOCK_KEY = 0XDF0D - // .. ==> 0XF8000008[15:0] = 0x0000DF0DU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU - // .. - EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), - // .. FINISH: SLCR SETTINGS - // .. START: ENABLING LEVEL SHIFTER - // .. USER_INP_ICT_EN_0 = 3 - // .. ==> 0XF8000900[1:0] = 0x00000003U - // .. ==> MASK : 0x00000003U VAL : 0x00000003U - // .. USER_INP_ICT_EN_1 = 3 - // .. ==> 0XF8000900[3:2] = 0x00000003U - // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU - // .. - EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), - // .. FINISH: ENABLING LEVEL SHIFTER - // .. START: TPIU WIDTH IN CASE OF EMIO - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0XC5ACCE55 - // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. .. START: TRACE CURRENT PORT SIZE - // .. .. a = 2 - // .. .. ==> 0XF8803004[31:0] = 0x00000002U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), - // .. .. FINISH: TRACE CURRENT PORT SIZE - // .. .. START: TRACE LOCK ACCESS REGISTER - // .. .. a = 0X0 - // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U - // .. .. - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), - // .. .. FINISH: TRACE LOCK ACCESS REGISTER - // .. FINISH: TPIU WIDTH IN CASE OF EMIO - // .. START: FPGA RESETS TO 0 - // .. reserved_3 = 0 - // .. ==> 0XF8000240[31:25] = 0x00000000U - // .. ==> MASK : 0xFE000000U VAL : 0x00000000U - // .. FPGA_ACP_RST = 0 - // .. ==> 0XF8000240[24:24] = 0x00000000U - // .. ==> MASK : 0x01000000U VAL : 0x00000000U - // .. FPGA_AXDS3_RST = 0 - // .. ==> 0XF8000240[23:23] = 0x00000000U - // .. ==> MASK : 0x00800000U VAL : 0x00000000U - // .. FPGA_AXDS2_RST = 0 - // .. ==> 0XF8000240[22:22] = 0x00000000U - // .. ==> MASK : 0x00400000U VAL : 0x00000000U - // .. FPGA_AXDS1_RST = 0 - // .. ==> 0XF8000240[21:21] = 0x00000000U - // .. ==> MASK : 0x00200000U VAL : 0x00000000U - // .. FPGA_AXDS0_RST = 0 - // .. ==> 0XF8000240[20:20] = 0x00000000U - // .. ==> MASK : 0x00100000U VAL : 0x00000000U - // .. reserved_2 = 0 - // .. ==> 0XF8000240[19:18] = 0x00000000U - // .. ==> MASK : 0x000C0000U VAL : 0x00000000U - // .. FSSW1_FPGA_RST = 0 - // .. ==> 0XF8000240[17:17] = 0x00000000U - // .. ==> MASK : 0x00020000U VAL : 0x00000000U - // .. FSSW0_FPGA_RST = 0 - // .. ==> 0XF8000240[16:16] = 0x00000000U - // .. ==> MASK : 0x00010000U VAL : 0x00000000U - // .. reserved_1 = 0 - // .. ==> 0XF8000240[15:14] = 0x00000000U - // .. ==> MASK : 0x0000C000U VAL : 0x00000000U - // .. FPGA_FMSW1_RST = 0 - // .. ==> 0XF8000240[13:13] = 0x00000000U - // .. ==> MASK : 0x00002000U VAL : 0x00000000U - // .. FPGA_FMSW0_RST = 0 - // .. ==> 0XF8000240[12:12] = 0x00000000U - // .. ==> MASK : 0x00001000U VAL : 0x00000000U - // .. FPGA_DMA3_RST = 0 - // .. ==> 0XF8000240[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. FPGA_DMA2_RST = 0 - // .. ==> 0XF8000240[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. FPGA_DMA1_RST = 0 - // .. ==> 0XF8000240[9:9] = 0x00000000U - // .. ==> MASK : 0x00000200U VAL : 0x00000000U - // .. FPGA_DMA0_RST = 0 - // .. ==> 0XF8000240[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. reserved = 0 - // .. ==> 0XF8000240[7:4] = 0x00000000U - // .. ==> MASK : 0x000000F0U VAL : 0x00000000U - // .. FPGA3_OUT_RST = 0 - // .. ==> 0XF8000240[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. FPGA2_OUT_RST = 0 - // .. ==> 0XF8000240[2:2] = 0x00000000U - // .. ==> MASK : 0x00000004U VAL : 0x00000000U - // .. FPGA1_OUT_RST = 0 - // .. ==> 0XF8000240[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U - // .. FPGA0_OUT_RST = 0 - // .. ==> 0XF8000240[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), - // .. FINISH: FPGA RESETS TO 0 - // .. START: AFI REGISTERS - // .. .. START: AFI0 REGISTERS - // .. .. FINISH: AFI0 REGISTERS - // .. .. START: AFI1 REGISTERS - // .. .. FINISH: AFI1 REGISTERS - // .. .. START: AFI2 REGISTERS - // .. .. FINISH: AFI2 REGISTERS - // .. .. START: AFI3 REGISTERS - // .. .. FINISH: AFI3 REGISTERS - // .. FINISH: AFI REGISTERS - // .. START: LOCK IT BACK - // .. LOCK_KEY = 0X767B - // .. ==> 0XF8000004[15:0] = 0x0000767BU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU - // .. - EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), - // .. FINISH: LOCK IT BACK - // FINISH: top - // - EMIT_EXIT(), - - // -}; - -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; - - -#include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} - -unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; -unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; -unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; -unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; -unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - -int -ps7_post_config() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_post_config_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_post_config_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_post_config_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int -ps7_init() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret; - //int pcw_ver = 0; - - if (si_ver == PCW_SILICON_VERSION_1) { - ps7_mio_init_data = ps7_mio_init_data_1_0; - ps7_pll_init_data = ps7_pll_init_data_1_0; - ps7_clock_init_data = ps7_clock_init_data_1_0; - ps7_ddr_init_data = ps7_ddr_init_data_1_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; - //pcw_ver = 1; - - } else if (si_ver == PCW_SILICON_VERSION_2) { - ps7_mio_init_data = ps7_mio_init_data_2_0; - ps7_pll_init_data = ps7_pll_init_data_2_0; - ps7_clock_init_data = ps7_clock_init_data_2_0; - ps7_ddr_init_data = ps7_ddr_init_data_2_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; - //pcw_ver = 2; - - } else { - ps7_mio_init_data = ps7_mio_init_data_3_0; - ps7_pll_init_data = ps7_pll_init_data_3_0; - ps7_clock_init_data = ps7_clock_init_data_3_0; - ps7_ddr_init_data = ps7_ddr_init_data_3_0; - ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; - //pcw_ver = 3; - } - - // MIO init - ret = ps7_config (ps7_mio_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // PLL init - ret = ps7_config (ps7_pll_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // Clock init - ret = ps7_config (ps7_clock_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - // DDR init - ret = ps7_config (ps7_ddr_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - - - - // Peripherals init - ret = ps7_config (ps7_peripherals_init_data); - if (ret != PS7_INIT_SUCCESS) return ret; - //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); - return PS7_INIT_SUCCESS; -} - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} - - - - diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h deleted file mode 100644 index df5205e8..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h +++ /dev/null @@ -1,130 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License along -* with this program; if not, see -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 100000000 -#define FPGA2_FREQ 33333336 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -int ps7_debug(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif - - diff --git a/meta-xilinx-contrib/README.md b/meta-xilinx-contrib/README.md index 952392af..1b11d347 100644 --- a/meta-xilinx-contrib/README.md +++ b/meta-xilinx-contrib/README.md @@ -1,35 +1,21 @@ -meta-xilinx-contrib -=================== +# meta-xilinx-contrib This layer is a contribution layer to support for MicroBlaze, Zynq and ZynqMP architectures. -This layer depends on meta-xilinx-bsp layer. +Any patches from open source contributors for vendor board can be added here. -Supported Boards/Machines -========================= +## Supported Boards/Machines -* Zynq: - * Digilent Zybo Linux BD Reference design - * [Avnet MiniZed](conf/machine/minized-zynq7.conf) - `minized-zynq7` +**Boards/Machines supported by this layer:** -Maintainers, Mailing list, Patches -================================== -Please send any patches, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): +| Platform | Vendor Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx ML605 (QEMU)](https://www.digikey.com/en/products/detail/amd-xilinx/EK-V6-ML605-G/2175174)|[ml605-qemu-microblazeel](conf/machine/ml605-qemu-microblazeel.conf)|NA| +|Zynq-7000|NA|NA|NA| +|ZynqMP|NA|NA|NA| +|Versal|NA|NA|NA| - meta-xilinx@lists.yoctoproject.org with '[meta-xilinx-contrib]' in the subject. - - -Subscribe to mailing list at -https://lists.yoctoproject.org/listinfo/meta-xilinx - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -37,7 +23,9 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.openembedded.org/meta-xilinx - + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core, meta-xilinx-vendor + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-contrib/conf/machine/minized-zynq7.conf b/meta-xilinx-contrib/conf/machine/minized-zynq7.conf deleted file mode 100644 index a7c549cc..00000000 --- a/meta-xilinx-contrib/conf/machine/minized-zynq7.conf +++ /dev/null @@ -1,27 +0,0 @@ -#@TYPE: Machine -#@NAME: minized-zynq7 -#@DESCRIPTION: Machine support for MiniZed. (http://www.minized.org/) - -require conf/machine/include/tune-zynq.inc -require conf/machine/include/machine-xilinx-default.inc - -MACHINE_FEATURES = "ext2 vfat usbhost wifi bluetooth" - -# u-boot configuration -PREFERRED_PROVIDER_virtual/bootloader = "u-boot" -UBOOT_MACHINE ?= "zynq_minized_config" - -EXTRA_IMAGEDEPENDS += " \ - u-boot-zynq-uenv \ - virtual/bootloader \ - " - -SERIAL_CONSOLES ?= "115200;ttyPS0" - -MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" - -MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "linux-firmware-bcm43430" - -IMAGE_BOOT_FILES += " \ - uEnv.txt \ - " diff --git a/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf b/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf new file mode 100644 index 00000000..157a75c2 --- /dev/null +++ b/meta-xilinx-contrib/conf/machine/ml605-qemu-microblazeel.conf @@ -0,0 +1,20 @@ +#@TYPE: Machine +#@NAME: ml605-qemu-microblazeel +#@DESCRIPTION: MicroBlaze QEMU machine support ('petalogix-ml605' model) + +TUNE_FEATURES:tune-microblaze ?= "microblaze v8.50 barrel-shift reorder pattern-compare divide-hard multiply-high fpu-hard" + +require conf/machine/microblaze-generic.conf + +USE_VT = "" + +# Use the networking setup from qemuarm +MACHINEOVERRIDES:prepend:pn-init-ifupdown = "qemuall:" +FILESOVERRIDES:append:pn-init-ifupdown = ":qemuarm" + +# This machine is a targeting a QEMU model, runqemu setup: +QB_MEM = "-m 256" +QB_MACHINE = "-machine petalogix-ml605" +QB_OPT_APPEND = "-nographic -serial mon:stdio" +QB_NETWORK_DEVICE = "-net nic,netdev=net0,macaddr=@MAC@" + diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend index 2ce919ac..8ba7a490 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2022.2.bbappend @@ -1,9 +1,12 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:" -SRC_URI:append:zybo-linux-bd-zynq7 = " \ - file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ - file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ - file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ - " +# Note: These patches are very old and doesn't apply on top of 5.x +# kernel. For more details refer README.md file. + +#SRC_URI:append:zybo-linux-bd-zynq7 = " \ +# file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \ +# file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \ +# file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \ +# " SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg" diff --git a/meta-xilinx-core/README.md b/meta-xilinx-core/README.md index 8997760c..d450c4b3 100644 --- a/meta-xilinx-core/README.md +++ b/meta-xilinx-core/README.md @@ -1,24 +1,8 @@ -meta-xilinx-core -================ +# meta-xilinx-core -This layer provides support for MicroBlaze, Zynq and ZynqMP. +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures. - -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this layer to -the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org - -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: @@ -26,9 +10,10 @@ This layer depends on: URI: git://git.openembedded.org/openembedded-core layers: meta + branch: master or xilinx current release version (e.g. hosister) + -Configuring Machines -==================== +## Configuring Machines All machines that use meta-xilinx-tools should be derived from one of the following: microblaze-generic, zynq-generic, zynqmp-generic, or @@ -58,8 +43,7 @@ require you to specify the path to a PDI file using PDI_PATH. The XSCT version will extract the PDI automatically. -Recipe Licenses -=============== +## Recipe Licenses Due to licensing restrictions some recipes in this layer rely on closed source or restricted content provided by Xilinx. In order to use these recipes you must diff --git a/meta-xilinx-core/conf/bblayers.conf.sample b/meta-xilinx-core/conf/bblayers.conf.sample index 890ef3b6..a98e8936 100644 --- a/meta-xilinx-core/conf/bblayers.conf.sample +++ b/meta-xilinx-core/conf/bblayers.conf.sample @@ -23,6 +23,7 @@ BBLAYERS ?= " \ ##OEROOT##/../meta-xilinx/meta-xilinx-pynq \ ##OEROOT##/../meta-xilinx/meta-xilinx-standalone \ ##OEROOT##/../meta-xilinx/meta-xilinx-contrib \ + ##OEROOT##/../meta-xilinx/meta-xilinx-vendor \ ##OEROOT##/../meta-xilinx-tools \ ##OEROOT##/../meta-petalinux \ ##OEROOT##/../meta-virtualization \ diff --git a/meta-xilinx-pynq/README.md b/meta-xilinx-pynq/README.md index a40ff96b..7f8163f2 100644 --- a/meta-xilinx-pynq/README.md +++ b/meta-xilinx-pynq/README.md @@ -1,26 +1,19 @@ # meta-xilinx-pynq -================================ - -Introduction -------------------------- +## Introduction This layer collects recipes required to build and run PYNQ based examples using jupyter-notebooks on yocto -Maintainers, Patches/Submissions, Community -=========================================== -Please open pull requests for any changes. - -Maintainers: - - Sai Hari Chandana Kalluri (chandana.kalluri@xilinx.com) - Peter Ogden (ogden@xilinx.com) +## Dependencies -Layer dependencies -===================== +This layer depends on: -URI: git://git.openembedded.org/bitbake + URI: git://git.openembedded.org/bitbake -URI: git://git.openembedded.org/openembedded-core + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) -URI: git://git.openembedded.org/meta-openembedded + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-standalone-experimental/README.md b/meta-xilinx-standalone-experimental/README.md index e49b01f2..99675b0a 100644 --- a/meta-xilinx-standalone-experimental/README.md +++ b/meta-xilinx-standalone-experimental/README.md @@ -1,5 +1,5 @@ -meta-xilinx-standalone-experimental -=================================== +# meta-xilinx-standalone-experimental + This layer contains experimental items that may eventually be added to the meta-xilinx-standalone layer. The components in this layer may or may not be buildable as they may require unreleased code. @@ -9,9 +9,9 @@ this should be considered to be a preview release only. For instance, some components may not be buildable, expect APIs to change on various parts and pieces. -Build Instructions ------------------- -Note: to use this layer you must REMOVE meta-xilinx-tools from your +## Build Instructions + +**Note:** to use this layer you must REMOVE meta-xilinx-tools from your project. meta-xilinx-tools is not compatible with this experimental approach. You may also have to remove other layers that depend on meta-xilinx-tools, such as meta-som. @@ -32,27 +32,18 @@ To install the setup SDK: Then follow the instructions in the 'prestep/README-setup' file. -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this -layer to the [meta-xilinx mailing list] -(https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle - -Dependencies -============ +## Dependencies This layer depends on: - URI: git://git.yoctoproject.org/poky + URI: git://git.openembedded.org/bitbake + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-standalone + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-core, meta-xilinx-bsp, meta-xilinx-standalone + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-bsp diff --git a/meta-xilinx-standalone/README.md b/meta-xilinx-standalone/README.md index a3514230..ea9fdbc4 100644 --- a/meta-xilinx-standalone/README.md +++ b/meta-xilinx-standalone/README.md @@ -1,5 +1,4 @@ -meta-xilinx-standalone -====================== +# meta-xilinx-standalone This layer is meant to augment Yocto/OE functionality to provide a Baremetal/Standalone Toolchain as well as a generic version of various @@ -8,15 +7,14 @@ firmware that is required to boot a ZynqMP or Versal system. For optimized versions of the firmware and additional components you must use the meta-xilinx-tools layer. -Building --------- +## Building + The software in this layer may be used in either a standard single configuration build, or a multiconfig build. A multiconfig build, along with the MACHINES defined in meta-xilinx-bsps will automate the generation of certain firmwares. -Toolchains ----------- +## Toolchains To build standalone toolchains similar to those embedded with the Xilinx xsct tooling: @@ -29,8 +27,7 @@ Use one of the custom machines: MACHINE= DISTRO=xilinx-standalone bitbake meta-toolchain -Standalone Firmware -------------------- +## Standalone Firmware The standalone firmware is a genericly configured firmware, it can be build either in a single standalong configuration, or via an automated @@ -89,25 +86,17 @@ MACHINE=zynqmp-generic bitbake fsbl pmufw MACHINE=versal-generic bitbake plmfw psmfw -Maintainers, Mailing list, Patches -================================== - -Please send any patches, pull requests, comments or questions for this -layer to the [meta-xilinx mailing list] -(https://lists.yoctoproject.org/listinfo/meta-xilinx): - - meta-xilinx@lists.yoctoproject.org +## Dependencies -Maintainers: - - Sai Hari Chandana Kalluri - Mark Hatle +This layer depends on: -Dependencies -============ + URI: git://git.openembedded.org/bitbake -This layer depends on: + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/poky + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core, meta-xilinx-bsp + branch: master or xilinx current release version (e.g. hosister) - URI: git://git.yoctoproject.org/meta-xilinx/meta-xilinx-bsp diff --git a/meta-xilinx-vendor/COPYING.MIT b/meta-xilinx-vendor/COPYING.MIT new file mode 100644 index 00000000..fb950dc6 --- /dev/null +++ b/meta-xilinx-vendor/COPYING.MIT @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/meta-xilinx-vendor/README.md b/meta-xilinx-vendor/README.md new file mode 100644 index 00000000..51ff84e1 --- /dev/null +++ b/meta-xilinx-vendor/README.md @@ -0,0 +1,37 @@ +# meta-xilinx-vendor + +This layer provides support for MicroBlaze, Zynq, ZynqMP and Versal architectures vendor boards. + +## Supported Boards/Machines + +**Boards/Machines supported by this layer:** + + +| Platform | Vendor Board Variant | Machine Configuration file | Board Device tree | +| ---| --- | ---| ---------- | +|MicroBlaze|[Xilinx S3A DSP 1800](https://shop.trenz-electronic.de/en/TE0320-00-EV02I-FPGA-Module-with-Spartan-3A-DSP-1800K-EV02I-1-Gbit-DDR-RAM)|[s3adsp1800-qemu-microblazeeb](conf/machine/s3adsp1800-qemu-microblazeeb.conf)|NA| +|Zynq-7000|[Avent Microzed](https://www.xilinx.com/products/boards-and-kits/1-5lakcu.html)|[microzed-zynq7](conf/machine/microzed-zynq7.conf)|`zynq-microzed.dtb`| +||[Avnet Picozed](https://www.xilinx.com/products/boards-and-kits/1-58nuel.html)|[picozed-zynq7](conf/machine/picozed-zynq7.conf)|NA| +||[Avnet Minized](https://www.xilinx.com/products/boards-and-kits/1-odbhjd.html)|[minized-zynq7](conf/machine/minized-zynq7.conf)|NA| +||[Avnet/Digilent ZedBoard](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html)|[zedboard-zynq7](conf/machine/zedboard-zynq7.conf)|NA| +||[Digilent Zybo](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-zynq7](conf/machine/zybo-zynq7.conf)|`zynq-zybo.dtb`| +||[Digilent Zybo Linux BD](https://www.xilinx.com/support/university/boards-portfolio/xup-boards/DigilentZYBO.html)|[zybo-linux-bd-zynq7](conf/machine/zybo-linux-bd-zynq7.conf)|NA| +|ZynqMP|[Avent Ultra96](https://www.xilinx.com/products/boards-and-kits/1-vad4rl.html)|[ultra96-zynqmp](conf/machine/ultra96-zynqmp.conf)|`avnet-ultra96-rev1`| +|Versal|NA|NA|NA| + +> **Note:** +`For Zybo Linux BD reference design, please see meta-xilinx-contrib layer` + +## Dependencies + +This layer depends on: + + URI: git://git.openembedded.org/bitbake + + URI: git://git.openembedded.org/openembedded-core + layers: meta + branch: master or xilinx current release version (e.g. hosister) + + URI: git://git.yoctoproject.org/meta-xilinx.git + layers: meta-xilinx-microblaze, meta-xilinx-core + branch: master or xilinx current release version (e.g. hosister) diff --git a/meta-xilinx-vendor/conf/layer.conf b/meta-xilinx-vendor/conf/layer.conf new file mode 100644 index 00000000..b3e81efc --- /dev/null +++ b/meta-xilinx-vendor/conf/layer.conf @@ -0,0 +1,13 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have a packages directory, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +BBFILE_COLLECTIONS += "xilinx-vendor" +BBFILE_PATTERN_xilinx-vendor = "^${LAYERDIR}/" +BBFILE_PRIORITY_xilinx-vendor = "5" + +LAYERDEPENDS_xilinx-vendor = "xilinx" +LAYERSERIES_COMPAT_xilinx-vendor = "honister" diff --git a/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc b/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc new file mode 100644 index 00000000..bfb57e00 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/include/board/ultra96.inc @@ -0,0 +1,12 @@ +# Ultra96 items that need to be configured from zynqmp-generic +KERNEL_DEVICETREE:ultra96 = "xilinx/zynqmp-zcu100-revC.dtb" + +# Affects meta-xilinx-tools xsctyaml.bbclass related items +YAML_SERIAL_CONSOLE_STDIN:ultra96 ?= "psu_uart_1" +YAML_SERIAL_CONSOLE_STDOUT:ultra96 ?= "psu_uart_1" + +YAML_COMPILER_FLAGS:append:ultra96 = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " + +# Enable bluetooth and wifi module +MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append:ultra96 = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" + diff --git a/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf b/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf new file mode 100644 index 00000000..ce8058e4 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/microzed-zynq7.conf @@ -0,0 +1,23 @@ +#@TYPE: Machine +#@NAME: microzed-zynq7 +#@DESCRIPTION: Machine support for microZed. (http://www.microzed.org/) + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +KERNEL_DEVICETREE = "zynq-microzed.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/conf/machine/minized-zynq7.conf b/meta-xilinx-vendor/conf/machine/minized-zynq7.conf new file mode 100644 index 00000000..af9d982d --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/minized-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: minized-zynq7 +#@DESCRIPTION: Machine support for MiniZed. (http://www.minized.org/) + +require conf/machine/zynq-generic.conf + +MACHINE_FEATURES = "ext2 vfat usbhost wifi bluetooth" + +UBOOT_MACHINE ?= "zynq_minized_config" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/bootloader \ + " + +SERIAL_CONSOLES ?= "115200;ttyPS0" + +MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree" + +MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS += "linux-firmware-bcm43430" + +IMAGE_BOOT_FILES += " \ + uEnv.txt \ + " diff --git a/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf b/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf new file mode 100644 index 00000000..31f5e220 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/picozed-zynq7.conf @@ -0,0 +1,25 @@ +#@TYPE: Machine +#@NAME: picozed-zynq7 +#@DESCRIPTION: Machine support for picoZed. (http://www.picozed.org/) +# +# Note: This machine configuration is intended as a generic config for +# the picozed SOM. It also covers the multiple SKUs for the picoZed +# including 7010, 7020, 7015 and 7030. + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf b/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf new file mode 100644 index 00000000..ff74ac3d --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/ultra96-zynqmp.conf @@ -0,0 +1,23 @@ +#@TYPE: Machine +#@NAME: ultra96-zynqmp +#@DESCRIPTION: Machine support for Ultra96 Evaluation Board. +# + +SOC_VARIANT = 'eg' + +require conf/machine/zynqmp-generic.conf + +# Add board compatibility override +MACHINEOVERRIDES .= ":ultra96" + +KERNEL_DEVICETREE = "xilinx/zynqmp-zcu100-revC.dtb" + +# Affects meta-xilinx-tools xsctyaml.bbclass related items +YAML_SERIAL_CONSOLE_STDIN ?= "psu_uart_1" +YAML_SERIAL_CONSOLE_STDOUT ?= "psu_uart_1" + +YAML_COMPILER_FLAGS:append = " -DBOARD_SHUTDOWN_PIN=2 -DBOARD_SHUTDOWN_PIN_STATE=0 " + +# Enable bluetooth and wifi module +MACHINE_ESSENTIAL_EXTRA_RDEPENDS:append = " linux-firmware-wl18xx linux-firmware-ti-bt-wl180x" + diff --git a/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf b/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf new file mode 100644 index 00000000..4da6bb4e --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zedboard-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: zedboard-zynq7 +#@DESCRIPTION: Machine support for ZedBoard. (http://www.zedboard.org/) +# +# For details on the Evaluation board: +# http://www.zedboard.org/content/overview +# For design files (including 'zynq_fsbl_0.elf') for the ZedBoard: +# http://www.zedboard.org/reference-designs-categories/zynq-concepts-tools-and-techniques-zedboard +# + +require conf/machine/zynq-generic.conf + +# Add board compatibility override +MACHINEOVERRIDES .= ":zedboard" + +SPL_BINARY ?= "spl/boot.bin" + +KERNEL_DEVICETREE = "zynq-zed.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + boot.scr \ + " diff --git a/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf b/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf new file mode 100644 index 00000000..98718ae3 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zybo-linux-bd-zynq7.conf @@ -0,0 +1,24 @@ +#@TYPE: Machine +#@NAME: zybo-linux-bd-zynq7 +#@DESCRIPTION: Machine support for zybo-linux-bd project. +# +# generated base on ZYBO linux-bd project +# + +require conf/machine/zynq-generic.conf + +MACHINE_FEATURES += "keyboard screen alsa sdio" + +SPL_BINARY ?= "spl/boot.bin" +FORCE_PLATFORM_INIT = "1" +UBOOT_ELF = "u-boot" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + bitstream \ + uEnv.txt \ + " + +KERNEL_FEATURES += " \ + features/xilinx/v4l2/v4l2.scc \ + " diff --git a/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf b/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf new file mode 100644 index 00000000..74d117c0 --- /dev/null +++ b/meta-xilinx-vendor/conf/machine/zybo-zynq7.conf @@ -0,0 +1,27 @@ +#@TYPE: Machine +#@NAME: zybo-zynq7 +#@DESCRIPTION: Machine support for ZYBO. +# +# For details on the ZYBO board: +# https://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO +# + +require conf/machine/zynq-generic.conf + +SPL_BINARY ?= "spl/boot.bin" +UBOOT_ELF = "u-boot" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + virtual/boot-bin \ + virtual/bootloader \ + u-boot-zynq-scr \ + " + +KERNEL_DEVICETREE = "zynq-zybo.dtb" + +IMAGE_BOOT_FILES += " \ + boot.bin \ + uEnv.txt \ + " + diff --git a/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..963940f5 --- /dev/null +++ b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,7 @@ +# Ultra96 device tree configuration +YAML_MAIN_MEMORY_CONFIG:ultra96 ?= "psu_ddr_0" +YAML_CONSOLE_DEVICE_CONFIG:ultra96 ?= "psu_uart_1" +YAML_DT_BOARD_FLAGS:ultra96 ?= "{BOARD avnet-ultra96-rev1}" + +# ZedBoard device tree configuration +YAML_DT_BOARD_FLAGS:zedboard ?= "{BOARD zedboard}" diff --git a/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend new file mode 100644 index 00000000..e925d608 --- /dev/null +++ b/meta-xilinx-vendor/dynamic-layers/meta-xilinx-tools/recipes-bsp/embeddedsw/pmu-firmware_%.bbappend @@ -0,0 +1,3 @@ +ULTRA96_VERSION ?= "1" +YAML_COMPILER_FLAGS:append:ultra96 = " -DENABLE_MOD_ULTRA96 ${@bb.utils.contains('ULTRA96_VERSION', '2', ' -DULTRA96_VERSION=2 ', ' -DULTRA96_VERSION=1 ', d)}" + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 00000000..341e69dc --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,13 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +# device tree sources for the various machines +COMPATIBLE_MACHINE:picozed-zynq7 = ".*" +SRC_URI:append:picozed-zynq7 = " file://picozed-zynq7.dts" + +COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = ".*" +SRC_URI:append:zybo-linux-bd-zynq7 = " \ + file://zybo-linux-bd-zynq7.dts \ + file://pcw.dtsi \ + file://pl.dtsi \ + " + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts new file mode 100644 index 00000000..6f9b653a --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/picozed-zynq7.dts @@ -0,0 +1,98 @@ +/dts-v1/; +/include/ "zynq-7000.dtsi" +/include/ "zynq-7000-qspi-dummy.dtsi" + +/ { + model = "Avnet picoZed"; + compatible = "avnet,picozed", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + compatible = "marvell,88e1512", "marvell,88e1510"; + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +&sdhci1 { + status = "okay"; + /* SD1 is onnected to a non-removable eMMC flash device */ + non-removable; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&qspi { + status = "okay"; + primary_flash: ps7-qspi@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + /* Example 16M partition table using U-Boot + U-Boot SPL */ + partition@0x0 { + label = "boot"; + reg = <0x0 0xe0000>; + }; + partition@0xe0000 { + label = "ubootenv"; + reg = <0xe0000 0x20000>; + }; + partition@0x100000 { + label = "uboot"; + reg = <0x100000 0x100000>; + }; + partition@0x200000 { + label = "kernel"; + reg = <0x200000 0x4f0000>; + }; + partition@0x6f0000 { + label = "devicetree"; + reg = <0x6f0000 0x10000>; + }; + partition@0x700000 { + label = "rootfs"; + reg = <0x700000 0x400000>; + }; + partition@0xb00000 { + label = "spare"; + reg = <0xb00000 0x500000>; + }; + }; +}; + diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi new file mode 100644 index 00000000..0f678d39 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi @@ -0,0 +1,63 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Fri Mar 4 15:40:49 2016 +*/ + + +/ { + cpus { + cpu@0 { + operating-points = <650000 1000000 325000 1000000>; + }; + }; +}; +&gem0 { + phy-mode = "rgmii-id"; + status = "okay"; + xlnx,ptp-enet-clock = <0x6750918>; +}; +&gpio0 { + emio-gpio-width = <64>; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; +}; +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; +&intc { + num_cpus = <2>; + num_interrupts = <96>; +}; +&qspi { + is-dual = <0>; + num-cs = <1>; + status = "okay"; +}; +&sdhci0 { + status = "okay"; + xlnx,has-cd = <0x1>; + xlnx,has-power = <0x0>; + xlnx,has-wp = <0x1>; +}; +&uart1 { + current-speed = <115200>; + device_type = "serial"; + port-number = <0>; + status = "okay"; +}; +&usb0 { + dr_mode = "host"; + phy_type = "ulpi"; + status = "okay"; + usb-reset = <&gpio0 46 0>; +}; +&clkc { + fclk-enable = <0x3>; + ps-clk-frequency = <50000000>; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi new file mode 100644 index 00000000..32bc7688 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi @@ -0,0 +1,215 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Fri Mar 4 15:40:49 2016 +*/ + + +/ { + amba_pl: amba_pl { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges ; + axi_dynclk_0: axi_dynclk@43c10000 { + compatible = "xlnx,axi-dynclk-1.0"; + reg = <0x43c10000 0x10000>; + xlnx,s00-axi-addr-width = <0x5>; + xlnx,s00-axi-data-width = <0x20>; + }; + axi_gpio_btn: gpio@41210000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41210000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_hdmi: gpio@41230000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + interrupt-parent = <&intc>; + interrupts = <0 29 4>; + reg = <0x41230000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x1>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_led: gpio@41200000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41200000 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x1>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_gpio_sw: gpio@41220000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x41220000 0x10000>; + xlnx,all-inputs = <0x1>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x4>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x0>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + axi_i2s_adi_0: axi_i2s_adi@43c20000 { + compatible = "xlnx,axi-i2s-adi-1.0"; + reg = <0x43c20000 0x10000>; + xlnx,bclk-pol = <0x0>; + xlnx,dma-type = <0x1>; + xlnx,has-rx = <0x1>; + xlnx,has-tx = <0x1>; + xlnx,lrclk-pol = <0x0>; + xlnx,num-ch = <0x1>; + xlnx,s-axi-min-size = <0x000001FF>; + xlnx,slot-width = <0x18>; + }; + axi_vdma_0: dma@43000000 { + #dma-cells = <1>; + compatible = "xlnx,axi-vdma-1.00.a"; + clocks = <&clkc 15>; + clock-names = "s_axi_lite_aclk"; + interrupt-parent = <&intc>; + interrupts = <0 30 4>; + reg = <0x43000000 0x10000>; + xlnx,flush-fsync = <0x1>; + xlnx,num-fstores = <0x1>; + dma-channel@43000000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupts = <0 30 4>; + xlnx,datawidth = <0x20>; + xlnx,device-id = <0x0>; + }; + }; + v_tc_0: v_tc@43c00000 { + compatible = "xlnx,v-tc-6.1"; + interrupt-parent = <&intc>; + interrupts = <0 31 4>; + reg = <0x43c00000 0x10000>; + xlnx,det-achroma-en = <0x0>; + xlnx,det-avideo-en = <0x1>; + xlnx,det-fieldid-en = <0x0>; + xlnx,det-hblank-en = <0x1>; + xlnx,det-hsync-en = <0x1>; + xlnx,det-vblank-en = <0x1>; + xlnx,det-vsync-en = <0x1>; + xlnx,detect-en = <0x0>; + xlnx,fsync-hstart0 = <0x0>; + xlnx,fsync-hstart1 = <0x0>; + xlnx,fsync-hstart10 = <0x0>; + xlnx,fsync-hstart11 = <0x0>; + xlnx,fsync-hstart12 = <0x0>; + xlnx,fsync-hstart13 = <0x0>; + xlnx,fsync-hstart14 = <0x0>; + xlnx,fsync-hstart15 = <0x0>; + xlnx,fsync-hstart2 = <0x0>; + xlnx,fsync-hstart3 = <0x0>; + xlnx,fsync-hstart4 = <0x0>; + xlnx,fsync-hstart5 = <0x0>; + xlnx,fsync-hstart6 = <0x0>; + xlnx,fsync-hstart7 = <0x0>; + xlnx,fsync-hstart8 = <0x0>; + xlnx,fsync-hstart9 = <0x0>; + xlnx,fsync-vstart0 = <0x0>; + xlnx,fsync-vstart1 = <0x0>; + xlnx,fsync-vstart10 = <0x0>; + xlnx,fsync-vstart11 = <0x0>; + xlnx,fsync-vstart12 = <0x0>; + xlnx,fsync-vstart13 = <0x0>; + xlnx,fsync-vstart14 = <0x0>; + xlnx,fsync-vstart15 = <0x0>; + xlnx,fsync-vstart2 = <0x0>; + xlnx,fsync-vstart3 = <0x0>; + xlnx,fsync-vstart4 = <0x0>; + xlnx,fsync-vstart5 = <0x0>; + xlnx,fsync-vstart6 = <0x0>; + xlnx,fsync-vstart7 = <0x0>; + xlnx,fsync-vstart8 = <0x0>; + xlnx,fsync-vstart9 = <0x0>; + xlnx,gen-achroma-en = <0x0>; + xlnx,gen-achroma-polarity = <0x1>; + xlnx,gen-auto-switch = <0x0>; + xlnx,gen-avideo-en = <0x1>; + xlnx,gen-avideo-polarity = <0x1>; + xlnx,gen-cparity = <0x0>; + xlnx,gen-f0-vblank-hend = <0x500>; + xlnx,gen-f0-vblank-hstart = <0x500>; + xlnx,gen-f0-vframe-size = <0x2ee>; + xlnx,gen-f0-vsync-hend = <0x500>; + xlnx,gen-f0-vsync-hstart = <0x500>; + xlnx,gen-f0-vsync-vend = <0x2d9>; + xlnx,gen-f0-vsync-vstart = <0x2d4>; + xlnx,gen-f1-vblank-hend = <0x500>; + xlnx,gen-f1-vblank-hstart = <0x500>; + xlnx,gen-f1-vframe-size = <0x2ee>; + xlnx,gen-f1-vsync-hend = <0x500>; + xlnx,gen-f1-vsync-hstart = <0x500>; + xlnx,gen-f1-vsync-vend = <0x2d9>; + xlnx,gen-f1-vsync-vstart = <0x2d4>; + xlnx,gen-fieldid-en = <0x0>; + xlnx,gen-fieldid-polarity = <0x1>; + xlnx,gen-hactive-size = <0x500>; + xlnx,gen-hblank-en = <0x1>; + xlnx,gen-hblank-polarity = <0x1>; + xlnx,gen-hframe-size = <0x672>; + xlnx,gen-hsync-en = <0x1>; + xlnx,gen-hsync-end = <0x596>; + xlnx,gen-hsync-polarity = <0x1>; + xlnx,gen-hsync-start = <0x56e>; + xlnx,gen-interlaced = <0x0>; + xlnx,gen-vactive-size = <0x2d0>; + xlnx,gen-vblank-en = <0x1>; + xlnx,gen-vblank-polarity = <0x1>; + xlnx,gen-video-format = <0x2>; + xlnx,gen-vsync-en = <0x1>; + xlnx,gen-vsync-polarity = <0x1>; + xlnx,generate-en = <0x1>; + xlnx,has-axi4-lite = <0x1>; + xlnx,has-intc-if = <0x0>; + xlnx,interlace-en = <0x0>; + xlnx,max-lines = <0x1000>; + xlnx,max-pixels = <0x1000>; + xlnx,num-fsyncs = <0x1>; + xlnx,sync-en = <0x0>; + }; + }; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts new file mode 100644 index 00000000..19654392 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts @@ -0,0 +1,184 @@ +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "zynq-7000.dtsi" +/include/ "zynq-7000-qspi-dummy.dtsi" +/include/ "pcw.dtsi" +/include/ "pl.dtsi" + +/ { + model = "Digilent-Zybo-Linux-BD-v2015.4"; + aliases { + serial0 = &uart1; + ethernet0 = &gem0; + spi0 = &qspi; + }; + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + btn4 { + label = "btn4"; + gpios = <&gpio0 50 0>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + btn5 { + label = "btn5"; + gpios = <&gpio0 51 0>; + linux,code = <103>; /* up */ + gpio-key,wakeup; + autorepeat; + }; + }; + + usb_phy0: usb_phy@0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + reset-gpios = <&gpio0 46 1>; + }; +}; + +&amba { + u-boot,dm-pre-reloc; +}; + +&amba_pl { + encoder_0: digilent_encoder { + compatible = "digilent,drm-encoder"; + dglnt,edid-i2c = <&i2c1>; + }; + + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,vtc = <&v_tc_0>; + xlnx,connector-type = "HDMIA"; + xlnx,encoder-slave = <&encoder_0>; + clocks = <&axi_dynclk_0>; + planes { + xlnx,pixel-format = "xrgb8888"; + plane0 { + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + }; + }; + }; + + i2s_clk: i2s_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + clock-output-names = "i2s_clk"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "ZYBO-Sound-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MICIN", "Microphone Jack", + "Headphone Jack", "LHPOUT", + "Headphone Jack", "RHPOUT", + "LLINEIN", "Line In Jack", + "RLINEIN", "Line In Jack"; + dailink0_master: simple-audio-card,cpu { + clocks = <&i2s_clk>; + sound-dai = <&axi_i2s_adi_0>; + }; + simple-audio-card,codec { + clocks = <&i2s_clk>; + sound-dai = <&ssm2603>; + }; + }; +}; + +&axi_dynclk_0 { + compatible = "digilent,axi-dynclk"; + #clock-cells = <0>; + clocks = <&clkc 15>; +}; + +&axi_i2s_adi_0 { + #sound-dai-cells = <0>; + compatible = "adi,axi-i2s-1.00.a"; + clocks = <&clkc 15>, <&i2s_clk>; + clock-names = "axi", "ref"; + dmas = <&dmac_s 0 &dmac_s 1>; + dma-names = "tx", "rx"; +}; + +&gem0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + local-mac-address = []; + phy0: phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +&i2c0 { + eeprom@50 { + /* Microchip 24AA02E48 */ + compatible = "microchip,24c02"; + reg = <0x50>; + }; + + ssm2603: ssm2603@1a{ + #sound-dai-cells = <0>; + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&qspi { + #address-cells = <1>; + #size-cells = <0>; + flash0: flash@0 { + compatible = "micron,m25p80", "s25fl128s"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + partition@0x00000000 { + label = "boot"; + reg = <0x00000000 0x00300000>; + }; + partition@0x00300000 { + label = "bootenv"; + reg = <0x00300000 0x00020000>; + }; + partition@0x00320000 { + label = "kernel"; + reg = <0x00320000 0x00a80000>; + }; + partition@0x00da0000 { + label = "spare"; + reg = <0x00da0000 0x00000000>; + }; + }; +}; + +&usb0 { + usb-phy = <&usb_phy0>; +}; + +&v_tc_0 { + compatible = "xlnx,v-tc-5.01.a"; +}; diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend new file mode 100644 index 00000000..fbe42821 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init.bbappend @@ -0,0 +1,4 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/platform-init:" + +COMPATIBLE_MACHINE:picozed-zynq7 = "picozed-zynq7" + diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c new file mode 100644 index 00000000..5587ab25 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c @@ -0,0 +1,13191 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x3 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF800014C[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000150[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000150[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x28 + // .. ==> 0XF8000154[13:8] = 0x00000028U + // .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000170[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000170[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x14 + // .. .. ==> 0XF8000180[13:8] = 0x00000014U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000180[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x3c + // .. .. ==> 0XF8000190[13:8] = 0x0000003CU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF8000190[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x28 + // .. .. ==> 0XF80001A0[13:8] = 0x00000028U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U + // .. .. DIVISOR1 = 0x1 + // .. .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa1 + // .. .. ==> 0XF800612C[19:10] = 0x000000A1U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa0 + // .. .. ==> 0XF8006130[19:10] = 0x000000A0U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006134[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006134[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF8006138[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0xad + // .. .. ==> 0XF8006138[19:10] = 0x000000ADU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006154[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c + // .. .. ==> 0XF8006158[9:0] = 0x0000007CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF800615C[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006160[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 + // .. .. ==> 0XF8006168[10:0] = 0x000000F6U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 + // .. .. ==> 0XF800616C[10:0] = 0x000000F5U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006170[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x102 + // .. .. ==> 0XF8006174[10:0] = 0x00000102U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF800617C[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xbc + // .. .. ==> 0XF8006180[9:0] = 0x000000BCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006184[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF8006188[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000700[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000704[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000724[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007A8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007AC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007B8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007BC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007BC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007CC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: TPIU WIDTH IN CASE OF EMIO + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0XC5ACCE55 + // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. .. START: TRACE CURRENT PORT SIZE + // .. .. a = 2 + // .. .. ==> 0XF8803004[31:0] = 0x00000002U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), + // .. .. FINISH: TRACE CURRENT PORT SIZE + // .. .. START: TRACE LOCK ACCESS REGISTER + // .. .. a = 0X0 + // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), + // .. .. FINISH: TRACE LOCK ACCESS REGISTER + // .. FINISH: TPIU WIDTH IN CASE OF EMIO + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h new file mode 100644 index 00000000..df5205e8 --- /dev/null +++ b/meta-xilinx-vendor/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h @@ -0,0 +1,130 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 33333336 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + + -- cgit v1.2.3-54-g00ecf