From 57b1213ff07b3f984a7b46f8552c516d5be37b14 Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Mon, 1 Jan 2024 12:41:06 +0530 Subject: embeddedsw : Updated SRCREV for 2024.1_1507 v_hdmirxss: Add support for SDT flow v_hdmirx: Add support for SDT flow vphy: Add SDT flow support for HDMI v_hdmiphy1: Add speedgrade variable in yaml v_hdmitxss1: Fix absolute for VTC and Tx core in SDT flow v_hdmirxss1: Fix absolute address for Rx core in SDT flow xilsem:Added additional check for Inplace PLM update in deferred start-up mode. xilpm: versal_common: server: Add CPPUTEST macro xilplmi: prints optimization xilloader: prints optimization BSP: riscv: Explicitly align trap vector base address to 4 bytes BSP: riscv: Disable relaxation of code sequence while setting up stack xilffs: Update YAML with Versal Net support --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-xilinx-standalone') diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 1d809d81..f78d15f8 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -12,7 +12,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[git] = "${AUTOREV}" ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" ESW_REV[2023.2] = "c9a0ee31b2a14cbcfcb56ca369037319b4ad4847" -ESW_REV[2024.1] = "6dc195e1d775ec6406a7ed4886e7809964b40cb0" +ESW_REV[2024.1] = "590fcce10751c97344a4d635f91d1685ce395f5e" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf