From 9f1a6d2a5d98b8b836c313aa1cde205a990db82a Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 20 Apr 2023 13:32:45 +0530 Subject: Updated SRCREV of embeddedsw for 2023.2_8743 rfdc: Enable workaround for a specific version of libidn.so needed by cmake XilinxProcessorIPLib: drivers: aiengine: Add support for system device-tree flow plm: versal: Remove xplm_modules from PPU1 RAM XilinxProcessorIPLib: drivers: CMakeLists.txt: Add required cmake meta-data for libxil xilpuf: Fix PUF auxiliary convergence error versal_psmfw: versal_net: reduce partition count xilpm: versal: server: Update BFR-B pre-config sequence Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'meta-xilinx-standalone') diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 8500c598..777eb31a 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "master-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[2023.1] = "2e9f85579e203d76b983ff21c4294a8c3d578942" -ESW_REV[2023.2] = "448abaa11ad5fc71a2910a7e30c38f09a277eca0" +ESW_REV[2023.2] = "0a86a22212eb3ade44ca71f513c4b3fa1d2d17ac" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf