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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6.inc3
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6/pr46934.patch392
2 files changed, 394 insertions, 1 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.inc b/meta/recipes-devtools/gcc/gcc-4.6.inc
index 0fb628771f..fbc90eaea1 100644
--- a/meta/recipes-devtools/gcc/gcc-4.6.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.6.inc
@@ -1,6 +1,6 @@
1require gcc-common.inc 1require gcc-common.inc
2 2
3PR = "r14" 3PR = "r15"
4 4
5# Third digit in PV should be incremented after a minor release 5# Third digit in PV should be incremented after a minor release
6# happens from this branch on gcc e.g. currently its 4.6.0 6# happens from this branch on gcc e.g. currently its 4.6.0
@@ -69,6 +69,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
69 file://powerpc-e5500.patch \ 69 file://powerpc-e5500.patch \
70 file://fix-for-ice-50099.patch \ 70 file://fix-for-ice-50099.patch \
71 file://gcc-with-linker-hash-style.patch \ 71 file://gcc-with-linker-hash-style.patch \
72 file://pr46934.patch \
72 " 73 "
73 74
74SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch " 75SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch "
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/pr46934.patch b/meta/recipes-devtools/gcc/gcc-4.6/pr46934.patch
new file mode 100644
index 0000000000..afd3eef8f0
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6/pr46934.patch
@@ -0,0 +1,392 @@
12011-09-19 chengbin <bin.cheng@arm.com>
2
3 Backport r174035 from mainline
4 2011-05-22 Tom de Vries <tom@codesourcery.com>
5
6 PR middle-end/48689
7 * fold-const.c (fold_checksum_tree): Guard TREE_CHAIN use with
8 CODE_CONTAINS_STRUCT (TS_COMMON).
9
10 Backport r172297 from mainline
11 2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
12 Richard Earnshaw <rearnsha@arm.com>
13
14 PR target/48250
15 * config/arm/arm.c (arm_legitimize_reload_address): Update cases
16 to use sign-magnitude offsets. Reject unsupported unaligned
17 cases. Add detailed description in comments.
18 * config/arm/arm.md (reload_outdf): Disable for ARM mode; change
19 condition from TARGET_32BIT to TARGET_ARM.
20
21 Backport r171978 from mainline
22 2011-04-05 Tom de Vries <tom@codesourcery.com>
23
24 PR target/43920
25 * config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing
26 for size.
27
28 Backport r171632 from mainline
29 2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
30
31 * builtins.c (expand_builtin_memset_args): Use gen_int_mode
32 instead of GEN_INT.
33
34 Backport r171379 from mainline
35 2011-03-23 Chung-Lin Tang <cltang@codesourcery.com>
36
37 PR target/46934
38 * config/arm/arm.md (casesi): Use the gen_int_mode() function
39 to subtract lower bound instead of GEN_INT().
40
41 Backport r171251 from mainline
42 2011-03-21 Daniel Jacobowitz <dan@codesourcery.com>
43
44 * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
45 for barrier handlers.
46
47 Backport r171096 from mainline
48 2011-03-17 Chung-Lin Tang <cltang@codesourcery.com>
49
50 PR target/43872
51 * config/arm/arm.c (arm_get_frame_offsets): Adjust early
52 return condition with !cfun->calls_alloca.
53
54Index: gcc-4_6-branch/gcc/builtins.c
55===================================================================
56--- gcc-4_6-branch.orig/gcc/builtins.c 2011-10-17 17:45:32.050502963 -0700
57+++ gcc-4_6-branch/gcc/builtins.c 2011-10-17 17:46:11.154696878 -0700
58@@ -3972,6 +3972,7 @@
59 {
60 tree fndecl, fn;
61 enum built_in_function fcode;
62+ enum machine_mode val_mode;
63 char c;
64 unsigned int dest_align;
65 rtx dest_mem, dest_addr, len_rtx;
66@@ -4006,14 +4007,14 @@
67
68 len_rtx = expand_normal (len);
69 dest_mem = get_memory_rtx (dest, len);
70+ val_mode = TYPE_MODE (unsigned_char_type_node);
71
72 if (TREE_CODE (val) != INTEGER_CST)
73 {
74 rtx val_rtx;
75
76 val_rtx = expand_normal (val);
77- val_rtx = convert_to_mode (TYPE_MODE (unsigned_char_type_node),
78- val_rtx, 0);
79+ val_rtx = convert_to_mode (val_mode, val_rtx, 0);
80
81 /* Assume that we can memset by pieces if we can store
82 * the coefficients by pieces (in the required modes).
83@@ -4024,8 +4025,7 @@
84 builtin_memset_read_str, &c, dest_align,
85 true))
86 {
87- val_rtx = force_reg (TYPE_MODE (unsigned_char_type_node),
88- val_rtx);
89+ val_rtx = force_reg (val_mode, val_rtx);
90 store_by_pieces (dest_mem, tree_low_cst (len, 1),
91 builtin_memset_gen_str, val_rtx, dest_align,
92 true, 0);
93@@ -4051,7 +4051,8 @@
94 true))
95 store_by_pieces (dest_mem, tree_low_cst (len, 1),
96 builtin_memset_read_str, &c, dest_align, true, 0);
97- else if (!set_storage_via_setmem (dest_mem, len_rtx, GEN_INT (c),
98+ else if (!set_storage_via_setmem (dest_mem, len_rtx,
99+ gen_int_mode (c, val_mode),
100 dest_align, expected_align,
101 expected_size))
102 goto do_libcall;
103Index: gcc-4_6-branch/gcc/config/arm/arm.c
104===================================================================
105--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-10-17 17:45:41.914551883 -0700
106+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-10-17 17:48:35.447412371 -0700
107@@ -6406,23 +6406,126 @@
108 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
109 HOST_WIDE_INT low, high;
110
111- if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
112- low = ((val & 0xf) ^ 0x8) - 0x8;
113- else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
114- /* Need to be careful, -256 is not a valid offset. */
115- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
116- else if (mode == SImode
117- || (mode == SFmode && TARGET_SOFT_FLOAT)
118- || ((mode == HImode || mode == QImode) && ! arm_arch4))
119- /* Need to be careful, -4096 is not a valid offset. */
120- low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
121- else if ((mode == HImode || mode == QImode) && arm_arch4)
122- /* Need to be careful, -256 is not a valid offset. */
123- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
124- else if (GET_MODE_CLASS (mode) == MODE_FLOAT
125- && TARGET_HARD_FLOAT && TARGET_FPA)
126- /* Need to be careful, -1024 is not a valid offset. */
127- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
128+ /* Detect coprocessor load/stores. */
129+ bool coproc_p = ((TARGET_HARD_FLOAT
130+ && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
131+ && (mode == SFmode || mode == DFmode
132+ || (mode == DImode && TARGET_MAVERICK)))
133+ || (TARGET_REALLY_IWMMXT
134+ && VALID_IWMMXT_REG_MODE (mode))
135+ || (TARGET_NEON
136+ && (VALID_NEON_DREG_MODE (mode)
137+ || VALID_NEON_QREG_MODE (mode))));
138+
139+ /* For some conditions, bail out when lower two bits are unaligned. */
140+ if ((val & 0x3) != 0
141+ /* Coprocessor load/store indexes are 8-bits + '00' appended. */
142+ && (coproc_p
143+ /* For DI, and DF under soft-float: */
144+ || ((mode == DImode || mode == DFmode)
145+ /* Without ldrd, we use stm/ldm, which does not
146+ fair well with unaligned bits. */
147+ && (! TARGET_LDRD
148+ /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
149+ || TARGET_THUMB2))))
150+ return false;
151+
152+ /* When breaking down a [reg+index] reload address into [(reg+high)+low],
153+ of which the (reg+high) gets turned into a reload add insn,
154+ we try to decompose the index into high/low values that can often
155+ also lead to better reload CSE.
156+ For example:
157+ ldr r0, [r2, #4100] // Offset too large
158+ ldr r1, [r2, #4104] // Offset too large
159+
160+ is best reloaded as:
161+ add t1, r2, #4096
162+ ldr r0, [t1, #4]
163+ add t2, r2, #4096
164+ ldr r1, [t2, #8]
165+
166+ which post-reload CSE can simplify in most cases to eliminate the
167+ second add instruction:
168+ add t1, r2, #4096
169+ ldr r0, [t1, #4]
170+ ldr r1, [t1, #8]
171+
172+ The idea here is that we want to split out the bits of the constant
173+ as a mask, rather than as subtracting the maximum offset that the
174+ respective type of load/store used can handle.
175+
176+ When encountering negative offsets, we can still utilize it even if
177+ the overall offset is positive; sometimes this may lead to an immediate
178+ that can be constructed with fewer instructions.
179+ For example:
180+ ldr r0, [r2, #0x3FFFFC]
181+
182+ This is best reloaded as:
183+ add t1, r2, #0x400000
184+ ldr r0, [t1, #-4]
185+
186+ The trick for spotting this for a load insn with N bits of offset
187+ (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
188+ negative offset that is going to make bit N and all the bits below
189+ it become zero in the remainder part.
190+
191+ The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
192+ to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
193+ used in most cases of ARM load/store instructions. */
194+
195+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
196+ (((VAL) & ((1 << (N)) - 1)) \
197+ ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
198+ : 0)
199+
200+ if (coproc_p)
201+ low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
202+ else if (GET_MODE_SIZE (mode) == 8)
203+ {
204+ if (TARGET_LDRD)
205+ low = (TARGET_THUMB2
206+ ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
207+ : SIGN_MAG_LOW_ADDR_BITS (val, 8));
208+ else
209+ /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
210+ to access doublewords. The supported load/store offsets are
211+ -8, -4, and 4, which we try to produce here. */
212+ low = ((val & 0xf) ^ 0x8) - 0x8;
213+ }
214+ else if (GET_MODE_SIZE (mode) < 8)
215+ {
216+ /* NEON element load/stores do not have an offset. */
217+ if (TARGET_NEON_FP16 && mode == HFmode)
218+ return false;
219+
220+ if (TARGET_THUMB2)
221+ {
222+ /* Thumb-2 has an asymmetrical index range of (-256,4096).
223+ Try the wider 12-bit range first, and re-try if the result
224+ is out of range. */
225+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
226+ if (low < -255)
227+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
228+ }
229+ else
230+ {
231+ if (mode == HImode || mode == HFmode)
232+ {
233+ if (arm_arch4)
234+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
235+ else
236+ {
237+ /* The storehi/movhi_bytes fallbacks can use only
238+ [-4094,+4094] of the full ldrb/strb index range. */
239+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
240+ if (low == 4095 || low == -4095)
241+ return false;
242+ }
243+ }
244+ else
245+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
246+ }
247+ }
248 else
249 return false;
250
251@@ -15415,7 +15518,10 @@
252 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
253 /* A leaf function does not need any stack alignment if it has nothing
254 on the stack. */
255- if (leaf && frame_size == 0)
256+ if (leaf && frame_size == 0
257+ /* However if it calls alloca(), we have a dynamically allocated
258+ block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
259+ && ! cfun->calls_alloca)
260 {
261 offsets->outgoing_args = offsets->soft_frame;
262 offsets->locals_base = offsets->soft_frame;
263Index: gcc-4_6-branch/gcc/config/arm/arm.h
264===================================================================
265--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-10-17 17:45:41.910551858 -0700
266+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-10-17 17:48:35.447412371 -0700
267@@ -2041,7 +2041,8 @@
268 /* Try to generate sequences that don't involve branches, we can then use
269 conditional instructions */
270 #define BRANCH_COST(speed_p, predictable_p) \
271- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
272+ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
273+ : (optimize > 0 ? 2 : 0))
274
275 /* Position Independent Code. */
276 /* We decide which register to use based on the compilation options and
277Index: gcc-4_6-branch/gcc/config/arm/arm.md
278===================================================================
279--- gcc-4_6-branch.orig/gcc/config/arm/arm.md 2011-10-17 17:46:11.002696119 -0700
280+++ gcc-4_6-branch/gcc/config/arm/arm.md 2011-10-17 17:46:11.202697111 -0700
281@@ -6187,7 +6187,7 @@
282 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
283 (match_operand:DF 1 "s_register_operand" "r")
284 (match_operand:SI 2 "s_register_operand" "=&r")]
285- "TARGET_32BIT"
286+ "TARGET_THUMB2"
287 "
288 {
289 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
290@@ -8359,7 +8359,8 @@
291 rtx reg = gen_reg_rtx (SImode);
292
293 emit_insn (gen_addsi3 (reg, operands[0],
294- GEN_INT (-INTVAL (operands[1]))));
295+ gen_int_mode (-INTVAL (operands[1]),
296+ SImode)));
297 operands[0] = reg;
298 }
299
300Index: gcc-4_6-branch/gcc/config/arm/unwind-arm.c
301===================================================================
302--- gcc-4_6-branch.orig/gcc/config/arm/unwind-arm.c 2011-10-17 17:45:41.390549278 -0700
303+++ gcc-4_6-branch/gcc/config/arm/unwind-arm.c 2011-10-17 17:46:11.000000000 -0700
304@@ -1196,8 +1196,6 @@
305 ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
306
307 if (data[0] & uint32_highbit)
308- phase2_call_unexpected_after_unwind = 1;
309- else
310 {
311 data += rtti_count + 1;
312 /* Setup for entry to the handler. */
313@@ -1207,6 +1205,8 @@
314 _Unwind_SetGR (context, 0, (_uw) ucbp);
315 return _URC_INSTALL_CONTEXT;
316 }
317+ else
318+ phase2_call_unexpected_after_unwind = 1;
319 }
320 if (data[0] & uint32_highbit)
321 data++;
322Index: gcc-4_6-branch/gcc/fold-const.c
323===================================================================
324--- gcc-4_6-branch.orig/gcc/fold-const.c 2011-10-17 17:45:32.050502963 -0700
325+++ gcc-4_6-branch/gcc/fold-const.c 2011-10-17 17:46:11.178696990 -0700
326@@ -13788,7 +13788,8 @@
327 if (TREE_CODE_CLASS (code) != tcc_type
328 && TREE_CODE_CLASS (code) != tcc_declaration
329 && code != TREE_LIST
330- && code != SSA_NAME)
331+ && code != SSA_NAME
332+ && CODE_CONTAINS_STRUCT (code, TS_COMMON))
333 fold_checksum_tree (TREE_CHAIN (expr), ctx, ht);
334 switch (TREE_CODE_CLASS (code))
335 {
336Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c
337===================================================================
338--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr40887.c 2011-06-24 08:13:47.000000000 -0700
339+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c 2011-10-17 17:46:11.182697014 -0700
340@@ -1,5 +1,6 @@
341 /* { dg-options "-O2 -march=armv5te" } */
342 /* { dg-final { scan-assembler "blx" } } */
343+/* { dg-prune-output "switch .* conflicts with" } */
344
345 int (*indirect_func)();
346
347Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c
348===================================================================
349--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr42575.c 2011-06-24 08:13:47.000000000 -0700
350+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c 2011-10-17 17:46:11.182697014 -0700
351@@ -1,4 +1,4 @@
352-/* { dg-options "-O2 -march=armv7-a" } */
353+/* { dg-options "-O2" } */
354 /* Make sure RA does good job allocating registers and avoids
355 unnecessary moves. */
356 /* { dg-final { scan-assembler-not "mov" } } */
357Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c
358===================================================================
359--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr43698.c 2011-06-24 08:13:47.000000000 -0700
360+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c 2011-10-17 17:46:11.182697014 -0700
361@@ -1,5 +1,5 @@
362 /* { dg-do run } */
363-/* { dg-options "-Os -march=armv7-a" } */
364+/* { dg-options "-Os" } */
365 #include <stdint.h>
366 #include <stdlib.h>
367
368Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c
369===================================================================
370--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr44788.c 2011-06-24 08:13:47.000000000 -0700
371+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c 2011-10-17 17:46:11.182697014 -0700
372@@ -1,6 +1,6 @@
373 /* { dg-do compile } */
374 /* { dg-require-effective-target arm_thumb2_ok } */
375-/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
376+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -mfpu=vfp3 -mfloat-abi=softfp" } */
377
378 void joint_decode(float* mlt_buffer1, int t) {
379 int i;
380Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c
381===================================================================
382--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/sync-1.c 2011-06-24 08:13:47.000000000 -0700
383+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c 2011-10-17 17:46:11.182697014 -0700
384@@ -1,5 +1,6 @@
385-/* { dg-do run } */
386-/* { dg-options "-O2 -march=armv7-a" } */
387+
388+/* { dg-do run { target sync_int_long } } */
389+/* { dg-options "-O2" } */
390
391 volatile int mem;
392
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-11-10 20:43:29 +0000