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-rw-r--r--meta/packages/drm/files/poulsbo.patch2647
-rw-r--r--meta/packages/drm/libdrm_2.4.4.bb4
2 files changed, 2650 insertions, 1 deletions
diff --git a/meta/packages/drm/files/poulsbo.patch b/meta/packages/drm/files/poulsbo.patch
new file mode 100644
index 0000000000..7dda90a2f5
--- /dev/null
+++ b/meta/packages/drm/files/poulsbo.patch
@@ -0,0 +1,2647 @@
1Index: libdrm-2.4.4/libdrm/xf86drm.c
2===================================================================
3--- libdrm-2.4.4.orig/libdrm/xf86drm.c 2009-01-10 01:08:29.000000000 +0000
4+++ libdrm-2.4.4/libdrm/xf86drm.c 2009-02-05 12:23:22.000000000 +0000
5@@ -2402,6 +2402,569 @@
6 return 0;
7 }
8
9+
10+/*
11+ * Valid flags are
12+ * DRM_FENCE_FLAG_EMIT
13+ * DRM_FENCE_FLAG_SHAREABLE
14+ * DRM_FENCE_MASK_DRIVER
15+ */
16+
17+int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
18+ drmFence *fence)
19+{
20+ drm_fence_arg_t arg;
21+
22+ memset(&arg, 0, sizeof(arg));
23+ arg.flags = flags;
24+ arg.type = type;
25+ arg.fence_class = fence_class;
26+
27+ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
28+ return -errno;
29+ fence->handle = arg.handle;
30+ fence->fence_class = arg.fence_class;
31+ fence->type = arg.type;
32+ fence->flags = arg.flags;
33+ fence->signaled = 0;
34+ return 0;
35+}
36+
37+/*
38+ * Valid flags are
39+ * DRM_FENCE_FLAG_SHAREABLE
40+ * DRM_FENCE_MASK_DRIVER
41+ */
42+
43+int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
44+{
45+ drm_fence_arg_t arg;
46+
47+ memset(&arg, 0, sizeof(arg));
48+ arg.flags = flags;
49+ arg.fence_class = fence_class;
50+
51+ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
52+ return -errno;
53+ fence->handle = arg.handle;
54+ fence->fence_class = arg.fence_class;
55+ fence->type = arg.type;
56+ fence->flags = arg.flags;
57+ fence->sequence = arg.sequence;
58+ fence->signaled = 0;
59+ return 0;
60+}
61+
62+int drmFenceReference(int fd, unsigned handle, drmFence *fence)
63+{
64+ drm_fence_arg_t arg;
65+
66+ memset(&arg, 0, sizeof(arg));
67+ arg.handle = handle;
68+
69+ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
70+ return -errno;
71+ fence->handle = arg.handle;
72+ fence->fence_class = arg.fence_class;
73+ fence->type = arg.type;
74+ fence->flags = arg.flags;
75+ fence->signaled = arg.signaled;
76+ return 0;
77+}
78+
79+int drmFenceUnreference(int fd, const drmFence *fence)
80+{
81+ drm_fence_arg_t arg;
82+
83+ memset(&arg, 0, sizeof(arg));
84+ arg.handle = fence->handle;
85+
86+ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
87+ return -errno;
88+ return 0;
89+}
90+
91+int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
92+{
93+ drm_fence_arg_t arg;
94+
95+ memset(&arg, 0, sizeof(arg));
96+ arg.handle = fence->handle;
97+ arg.type = flush_type;
98+
99+ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
100+ return -errno;
101+ fence->fence_class = arg.fence_class;
102+ fence->type = arg.type;
103+ fence->signaled = arg.signaled;
104+ return arg.error;
105+}
106+
107+int drmFenceUpdate(int fd, drmFence *fence)
108+{
109+ drm_fence_arg_t arg;
110+
111+ memset(&arg, 0, sizeof(arg));
112+ arg.handle = fence->handle;
113+
114+ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
115+ return -errno;
116+ fence->fence_class = arg.fence_class;
117+ fence->type = arg.type;
118+ fence->signaled = arg.signaled;
119+ return 0;
120+}
121+
122+int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
123+ int *signaled)
124+{
125+ if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
126+ ((fenceType & fence->signaled) != fenceType)) {
127+ int ret = drmFenceFlush(fd, fence, fenceType);
128+ if (ret)
129+ return ret;
130+ }
131+
132+ *signaled = ((fenceType & fence->signaled) == fenceType);
133+
134+ return 0;
135+}
136+
137+/*
138+ * Valid flags are
139+ * DRM_FENCE_FLAG_SHAREABLE
140+ * DRM_FENCE_MASK_DRIVER
141+ */
142+
143+
144+int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
145+{
146+ drm_fence_arg_t arg;
147+
148+ memset(&arg, 0, sizeof(arg));
149+ arg.fence_class = fence->fence_class;
150+ arg.flags = flags;
151+ arg.handle = fence->handle;
152+ arg.type = emit_type;
153+
154+ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
155+ return -errno;
156+ fence->fence_class = arg.fence_class;
157+ fence->type = arg.type;
158+ fence->signaled = arg.signaled;
159+ fence->sequence = arg.sequence;
160+ return 0;
161+}
162+
163+/*
164+ * Valid flags are
165+ * DRM_FENCE_FLAG_WAIT_LAZY
166+ * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
167+ */
168+
169+#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
170+
171+static unsigned long
172+drmTimeDiff(struct timeval *now, struct timeval *then)
173+{
174+ uint64_t val;
175+
176+ val = now->tv_sec - then->tv_sec;
177+ val *= 1000000LL;
178+ val += now->tv_usec;
179+ val -= then->tv_usec;
180+
181+ return (unsigned long) val;
182+}
183+
184+static int
185+drmIoctlTimeout(int fd, unsigned long request, void *argp)
186+{
187+ int haveThen = 0;
188+ struct timeval then, now;
189+ int ret;
190+
191+ do {
192+ ret = ioctl(fd, request, argp);
193+ if (ret != 0 && errno == EAGAIN) {
194+ if (!haveThen) {
195+ gettimeofday(&then, NULL);
196+ haveThen = 1;
197+ }
198+ gettimeofday(&now, NULL);
199+ }
200+ } while (ret != 0 && errno == EAGAIN &&
201+ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
202+
203+ if (ret != 0)
204+ return ((errno == EAGAIN) ? -EBUSY : -errno);
205+
206+ return 0;
207+}
208+
209+
210+
211+
212+int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
213+{
214+ drm_fence_arg_t arg;
215+ int ret;
216+
217+ if (flush_type == 0) {
218+ flush_type = fence->type;
219+ }
220+
221+ if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) {
222+ if ((flush_type & fence->signaled) == flush_type) {
223+ return 0;
224+ }
225+ }
226+
227+ memset(&arg, 0, sizeof(arg));
228+ arg.handle = fence->handle;
229+ arg.type = flush_type;
230+ arg.flags = flags;
231+
232+
233+ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
234+ if (ret)
235+ return ret;
236+
237+ fence->fence_class = arg.fence_class;
238+ fence->type = arg.type;
239+ fence->signaled = arg.signaled;
240+ return arg.error;
241+}
242+
243+static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
244+{
245+ buf->handle = rep->handle;
246+ buf->flags = rep->flags;
247+ buf->size = rep->size;
248+ buf->offset = rep->offset;
249+ buf->mapHandle = rep->arg_handle;
250+ buf->mask = rep->proposed_flags;
251+ buf->start = rep->buffer_start;
252+ buf->fenceFlags = rep->fence_flags;
253+ buf->replyFlags = rep->rep_flags;
254+ buf->pageAlignment = rep->page_alignment;
255+ buf->tileInfo = rep->tile_info;
256+ buf->hwTileStride = rep->hw_tile_stride;
257+ buf->desiredTileStride = rep->desired_tile_stride;
258+}
259+
260+
261+
262+int drmBOCreate(int fd, unsigned long size,
263+ unsigned pageAlignment, void *user_buffer,
264+ uint64_t mask,
265+ unsigned hint, drmBO *buf)
266+{
267+ struct drm_bo_create_arg arg;
268+ struct drm_bo_create_req *req = &arg.d.req;
269+ struct drm_bo_info_rep *rep = &arg.d.rep;
270+ int ret;
271+
272+ memset(buf, 0, sizeof(*buf));
273+ memset(&arg, 0, sizeof(arg));
274+ req->flags = mask;
275+ req->hint = hint;
276+ req->size = size;
277+ req->page_alignment = pageAlignment;
278+ req->buffer_start = (unsigned long) user_buffer;
279+
280+ buf->virtual = NULL;
281+
282+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
283+ if (ret)
284+ return ret;
285+
286+ drmBOCopyReply(rep, buf);
287+ buf->virtual = user_buffer;
288+ buf->mapCount = 0;
289+
290+ return 0;
291+}
292+
293+int drmBOReference(int fd, unsigned handle, drmBO *buf)
294+{
295+ struct drm_bo_reference_info_arg arg;
296+ struct drm_bo_handle_arg *req = &arg.d.req;
297+ struct drm_bo_info_rep *rep = &arg.d.rep;
298+
299+ memset(&arg, 0, sizeof(arg));
300+ req->handle = handle;
301+
302+ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
303+ return -errno;
304+
305+ drmBOCopyReply(rep, buf);
306+ buf->mapVirtual = NULL;
307+ buf->mapCount = 0;
308+ buf->virtual = NULL;
309+
310+ return 0;
311+}
312+
313+int drmBOUnreference(int fd, drmBO *buf)
314+{
315+ struct drm_bo_handle_arg arg;
316+
317+ if (buf->mapVirtual && buf->mapHandle) {
318+ (void) munmap(buf->mapVirtual, buf->start + buf->size);
319+ buf->mapVirtual = NULL;
320+ buf->virtual = NULL;
321+ }
322+
323+ memset(&arg, 0, sizeof(arg));
324+ arg.handle = buf->handle;
325+
326+ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
327+ return -errno;
328+
329+ buf->handle = 0;
330+ return 0;
331+}
332+
333+
334+/*
335+ * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
336+ * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
337+ * call return an -EBUSY if it can' immediately honor the mapping request.
338+ */
339+
340+int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
341+ void **address)
342+{
343+ struct drm_bo_map_wait_idle_arg arg;
344+ struct drm_bo_info_req *req = &arg.d.req;
345+ struct drm_bo_info_rep *rep = &arg.d.rep;
346+ int ret = 0;
347+
348+ /*
349+ * Make sure we have a virtual address of the buffer.
350+ */
351+
352+ if (!buf->virtual) {
353+ drmAddress virtual;
354+ virtual = mmap(0, buf->size + buf->start,
355+ PROT_READ | PROT_WRITE, MAP_SHARED,
356+ fd, buf->mapHandle);
357+ if (virtual == MAP_FAILED) {
358+ ret = -errno;
359+ }
360+ if (ret)
361+ return ret;
362+ buf->mapVirtual = virtual;
363+ buf->virtual = ((char *) virtual) + buf->start;
364+ }
365+
366+ memset(&arg, 0, sizeof(arg));
367+ req->handle = buf->handle;
368+ req->mask = mapFlags;
369+ req->hint = mapHint;
370+
371+ /*
372+ * May hang if the buffer object is busy.
373+ * This IOCTL synchronizes the buffer.
374+ */
375+
376+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
377+ if (ret)
378+ return ret;
379+
380+ drmBOCopyReply(rep, buf);
381+ buf->mapFlags = mapFlags;
382+ ++buf->mapCount;
383+ *address = buf->virtual;
384+
385+ return 0;
386+}
387+
388+
389+int drmBOUnmap(int fd, drmBO *buf)
390+{
391+ struct drm_bo_handle_arg arg;
392+
393+ memset(&arg, 0, sizeof(arg));
394+ arg.handle = buf->handle;
395+
396+ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
397+ return -errno;
398+ }
399+ buf->mapCount--;
400+ return 0;
401+}
402+
403+int drmBOSetStatus(int fd, drmBO *buf,
404+ uint64_t flags, uint64_t mask,
405+ unsigned int hint,
406+ unsigned int desired_tile_stride,
407+ unsigned int tile_info)
408+{
409+
410+ struct drm_bo_map_wait_idle_arg arg;
411+ struct drm_bo_info_req *req = &arg.d.req;
412+ struct drm_bo_info_rep *rep = &arg.d.rep;
413+ int ret = 0;
414+
415+ memset(&arg, 0, sizeof(arg));
416+ req->mask = mask;
417+ req->flags = flags;
418+ req->handle = buf->handle;
419+ req->hint = hint;
420+ req->desired_tile_stride = desired_tile_stride;
421+ req->tile_info = tile_info;
422+
423+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
424+ if (ret)
425+ return ret;
426+
427+ drmBOCopyReply(rep, buf);
428+ return 0;
429+}
430+
431+
432+int drmBOInfo(int fd, drmBO *buf)
433+{
434+ struct drm_bo_reference_info_arg arg;
435+ struct drm_bo_handle_arg *req = &arg.d.req;
436+ struct drm_bo_info_rep *rep = &arg.d.rep;
437+ int ret = 0;
438+
439+ memset(&arg, 0, sizeof(arg));
440+ req->handle = buf->handle;
441+
442+ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
443+ if (ret)
444+ return -errno;
445+
446+ drmBOCopyReply(rep, buf);
447+ return 0;
448+}
449+
450+int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
451+{
452+ struct drm_bo_map_wait_idle_arg arg;
453+ struct drm_bo_info_req *req = &arg.d.req;
454+ struct drm_bo_info_rep *rep = &arg.d.rep;
455+ int ret = 0;
456+
457+ if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
458+ (buf->replyFlags & DRM_BO_REP_BUSY)) {
459+ memset(&arg, 0, sizeof(arg));
460+ req->handle = buf->handle;
461+ req->hint = hint;
462+
463+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
464+ if (ret)
465+ return ret;
466+
467+ drmBOCopyReply(rep, buf);
468+ }
469+ return 0;
470+}
471+
472+int drmBOBusy(int fd, drmBO *buf, int *busy)
473+{
474+ if (!(buf->flags & DRM_BO_FLAG_SHAREABLE) &&
475+ !(buf->replyFlags & DRM_BO_REP_BUSY)) {
476+ *busy = 0;
477+ return 0;
478+ }
479+ else {
480+ int ret = drmBOInfo(fd, buf);
481+ if (ret)
482+ return ret;
483+ *busy = (buf->replyFlags & DRM_BO_REP_BUSY);
484+ return 0;
485+ }
486+}
487+
488+int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
489+ unsigned memType)
490+{
491+ struct drm_mm_init_arg arg;
492+
493+ memset(&arg, 0, sizeof(arg));
494+
495+ arg.magic = DRM_BO_INIT_MAGIC;
496+ arg.major = DRM_BO_INIT_MAJOR;
497+ arg.minor = DRM_BO_INIT_MINOR;
498+ arg.p_offset = pOffset;
499+ arg.p_size = pSize;
500+ arg.mem_type = memType;
501+
502+ if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
503+ return -errno;
504+ return 0;
505+}
506+
507+int drmMMTakedown(int fd, unsigned memType)
508+{
509+ struct drm_mm_type_arg arg;
510+
511+ memset(&arg, 0, sizeof(arg));
512+ arg.mem_type = memType;
513+
514+ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
515+ return -errno;
516+ return 0;
517+}
518+
519+/*
520+ * If this function returns an error, and lockBM was set to 1,
521+ * the buffer manager is NOT locked.
522+ */
523+
524+int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
525+{
526+ struct drm_mm_type_arg arg;
527+
528+ memset(&arg, 0, sizeof(arg));
529+ arg.mem_type = memType;
530+ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
531+ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
532+
533+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
534+}
535+
536+int drmMMUnlock(int fd, unsigned memType, int unlockBM)
537+{
538+ struct drm_mm_type_arg arg;
539+
540+ memset(&arg, 0, sizeof(arg));
541+
542+ arg.mem_type = memType;
543+ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
544+
545+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
546+}
547+
548+int drmBOVersion(int fd, unsigned int *major,
549+ unsigned int *minor,
550+ unsigned int *patchlevel)
551+{
552+ struct drm_bo_version_arg arg;
553+ int ret;
554+
555+ memset(&arg, 0, sizeof(arg));
556+ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
557+ if (ret)
558+ return -errno;
559+
560+ if (major)
561+ *major = arg.major;
562+ if (minor)
563+ *minor = arg.minor;
564+ if (patchlevel)
565+ *patchlevel = arg.patchlevel;
566+
567+ return 0;
568+}
569+
570+
571+
572 #define DRM_MAX_FDS 16
573 static struct {
574 char *BusID;
575Index: libdrm-2.4.4/libdrm/xf86drm.h
576===================================================================
577--- libdrm-2.4.4.orig/libdrm/xf86drm.h 2008-12-17 18:28:24.000000000 +0000
578+++ libdrm-2.4.4/libdrm/xf86drm.h 2009-02-04 16:39:55.000000000 +0000
579@@ -665,4 +665,6 @@
580 extern int drmSetMaster(int fd);
581 extern int drmDropMaster(int fd);
582
583+#include "xf86mm.h"
584+
585 #endif
586Index: libdrm-2.4.4/libdrm/xf86mm.h
587===================================================================
588--- /dev/null 1970-01-01 00:00:00.000000000 +0000
589+++ libdrm-2.4.4/libdrm/xf86mm.h 2009-02-04 16:39:55.000000000 +0000
590@@ -0,0 +1,140 @@
591+/**************************************************************************
592+ *
593+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA.
594+ * All Rights Reserved.
595+ *
596+ * Permission is hereby granted, free of charge, to any person obtaining a
597+ * copy of this software and associated documentation files (the
598+ * "Software"), to deal in the Software without restriction, including
599+ * without limitation the rights to use, copy, modify, merge, publish,
600+ * distribute, sub license, and/or sell copies of the Software, and to
601+ * permit persons to whom the Software is furnished to do so, subject to
602+ * the following conditions:
603+ *
604+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
605+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
606+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
607+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
608+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
609+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
610+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
611+ *
612+ * The above copyright notice and this permission notice (including the
613+ * next paragraph) shall be included in all copies or substantial portions
614+ * of the Software.
615+ *
616+ *
617+ **************************************************************************/
618+
619+#ifndef _XF86MM_H_
620+#define _XF86MM_H_
621+#include <stddef.h>
622+#include <stdint.h>
623+#include "drm.h"
624+
625+/*
626+ * Note on multithreaded applications using this interface.
627+ * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to
628+ * be protected using an external mutex.
629+ *
630+ * Note: Don't protect the following functions, as it may lead to deadlocks:
631+ * drmBOUnmap().
632+ * The kernel is synchronizing and refcounting buffer maps.
633+ * User space only needs to refcount object usage within the same application.
634+ */
635+
636+
637+/*
638+ * List macros heavily inspired by the Linux kernel
639+ * list handling. No list looping yet.
640+ */
641+
642+typedef struct _drmFence
643+{
644+ unsigned handle;
645+ int fence_class;
646+ unsigned type;
647+ unsigned flags;
648+ unsigned signaled;
649+ uint32_t sequence;
650+ unsigned pad[4]; /* for future expansion */
651+} drmFence;
652+
653+typedef struct _drmBO
654+{
655+ unsigned handle;
656+ uint64_t mapHandle;
657+ uint64_t flags;
658+ uint64_t mask;
659+ unsigned mapFlags;
660+ unsigned long size;
661+ unsigned long offset;
662+ unsigned long start;
663+ unsigned replyFlags;
664+ unsigned fenceFlags;
665+ unsigned pageAlignment;
666+ unsigned tileInfo;
667+ unsigned hwTileStride;
668+ unsigned desiredTileStride;
669+ void *virtual;
670+ void *mapVirtual;
671+ int mapCount;
672+ unsigned pad[8]; /* for future expansion */
673+} drmBO;
674+
675+/*
676+ * Fence functions.
677+ */
678+
679+extern int drmFenceCreate(int fd, unsigned flags, int fence_class,
680+ unsigned type, drmFence *fence);
681+extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
682+extern int drmFenceUnreference(int fd, const drmFence *fence);
683+extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
684+extern int drmFenceSignaled(int fd, drmFence *fence,
685+ unsigned fenceType, int *signaled);
686+extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
687+ unsigned flush_type);
688+extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
689+ unsigned emit_type);
690+extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence);
691+
692+
693+/*
694+ * Buffer object functions.
695+ */
696+
697+extern int drmBOCreate(int fd, unsigned long size,
698+ unsigned pageAlignment, void *user_buffer,
699+ uint64_t mask, unsigned hint, drmBO *buf);
700+extern int drmBOReference(int fd, unsigned handle, drmBO *buf);
701+extern int drmBOUnreference(int fd, drmBO *buf);
702+extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
703+ void **address);
704+extern int drmBOUnmap(int fd, drmBO *buf);
705+extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle);
706+extern int drmBOInfo(int fd, drmBO *buf);
707+extern int drmBOBusy(int fd, drmBO *buf, int *busy);
708+
709+extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint);
710+
711+/*
712+ * Initialization functions.
713+ */
714+
715+extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
716+ unsigned memType);
717+extern int drmMMTakedown(int fd, unsigned memType);
718+extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict);
719+extern int drmMMUnlock(int fd, unsigned memType, int unlockBM);
720+extern int drmBOSetStatus(int fd, drmBO *buf,
721+ uint64_t flags, uint64_t mask,
722+ unsigned int hint,
723+ unsigned int desired_tile_stride,
724+ unsigned int tile_info);
725+extern int drmBOVersion(int fd, unsigned int *major,
726+ unsigned int *minor,
727+ unsigned int *patchlevel);
728+
729+
730+#endif
731Index: libdrm-2.4.4/Makefile.am
732===================================================================
733--- libdrm-2.4.4.orig/Makefile.am 2008-10-09 20:02:10.000000000 +0100
734+++ libdrm-2.4.4/Makefile.am 2009-02-04 16:39:55.000000000 +0000
735@@ -22,7 +22,7 @@
736 # here too, but let's just do libdrm for now
737
738 AUTOMAKE_OPTIONS = foreign
739-SUBDIRS = libdrm shared-core tests
740+SUBDIRS = libdrm shared-core
741
742 pkgconfigdir = @pkgconfigdir@
743 pkgconfig_DATA = libdrm.pc
744Index: libdrm-2.4.4/shared-core/drm.h
745===================================================================
746--- libdrm-2.4.4.orig/shared-core/drm.h 2008-12-17 18:28:24.000000000 +0000
747+++ libdrm-2.4.4/shared-core/drm.h 2009-02-05 12:20:53.000000000 +0000
748@@ -632,6 +632,8 @@
749 unsigned long handle; /**< Used for mapping / unmapping */
750 };
751
752+
753+
754 /**
755 * DRM_IOCTL_SET_VERSION ioctl argument type.
756 */
757@@ -1109,6 +1111,32 @@
758 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t)
759 #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xB0, struct drm_mode_fb_cmd)
760
761+#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
762+#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
763+#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
764+#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
765+
766+#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
767+#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
768+#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
769+#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
770+#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
771+#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
772+#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
773+#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
774+
775+#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
776+#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
777+#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
778+#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
779+#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
780+#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
781+#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
782+#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
783+#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
784+
785+#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
786+#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
787 /*@}*/
788
789 /**
790Index: libdrm-2.4.4/shared-core/i915_drm.h
791===================================================================
792--- libdrm-2.4.4.orig/shared-core/i915_drm.h 2008-12-23 00:03:35.000000000 +0000
793+++ libdrm-2.4.4/shared-core/i915_drm.h 2009-02-04 16:39:55.000000000 +0000
794@@ -767,4 +767,22 @@
795 uint64_t aper_available_size;
796 };
797
798+/*
799+ * Relocation header is 4 uint32_ts
800+ * 0 - (16-bit relocation type << 16)| 16 bit reloc count
801+ * 1 - buffer handle for another list of relocs
802+ * 2-3 - spare.
803+ */
804+#define I915_RELOC_HEADER 4
805+
806+/*
807+ * type 0 relocation has 4-uint32_t stride
808+ * 0 - offset into buffer
809+ * 1 - delta to add in
810+ * 2 - index into buffer list
811+ * 3 - reserved (for optimisations later).
812+ */
813+#define I915_RELOC_TYPE_0 0
814+#define I915_RELOC0_STRIDE 4
815+
816 #endif /* _I915_DRM_H_ */
817Index: libdrm-2.4.4/shared-core/Makefile.am
818===================================================================
819--- libdrm-2.4.4.orig/shared-core/Makefile.am 2008-12-17 18:28:24.000000000 +0000
820+++ libdrm-2.4.4/shared-core/Makefile.am 2009-02-04 16:39:55.000000000 +0000
821@@ -31,6 +31,8 @@
822 mach64_drm.h \
823 mga_drm.h \
824 nouveau_drm.h \
825+ psb_drm.h \
826+ psb_reg.h \
827 r128_drm.h \
828 radeon_drm.h \
829 savage_drm.h \
830Index: libdrm-2.4.4/shared-core/nouveau_drm.h
831===================================================================
832--- libdrm-2.4.4.orig/shared-core/nouveau_drm.h 2008-10-09 20:02:11.000000000 +0100
833+++ libdrm-2.4.4/shared-core/nouveau_drm.h 2009-02-04 16:39:55.000000000 +0000
834@@ -144,9 +144,12 @@
835 NV_05 =5,
836 NV_10 =10,
837 NV_11 =11,
838+ NV_15 =11,
839 NV_17 =17,
840 NV_20 =20,
841+ NV_25 =20,
842 NV_30 =30,
843+ NV_34 =30,
844 NV_40 =40,
845 NV_44 =44,
846 NV_50 =50,
847Index: libdrm-2.4.4/shared-core/psb_drm.h
848===================================================================
849--- /dev/null 1970-01-01 00:00:00.000000000 +0000
850+++ libdrm-2.4.4/shared-core/psb_drm.h 2009-02-04 16:39:55.000000000 +0000
851@@ -0,0 +1,359 @@
852+/**************************************************************************
853+ * Copyright (c) 2007, Intel Corporation.
854+ * All Rights Reserved.
855+ *
856+ * This program is free software; you can redistribute it and/or modify it
857+ * under the terms and conditions of the GNU General Public License,
858+ * version 2, as published by the Free Software Foundation.
859+ *
860+ * This program is distributed in the hope it will be useful, but WITHOUT
861+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
862+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
863+ * more details.
864+ *
865+ * You should have received a copy of the GNU General Public License along with
866+ * this program; if not, write to the Free Software Foundation, Inc.,
867+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
868+ *
869+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
870+ * develop this driver.
871+ *
872+ **************************************************************************/
873+/*
874+ */
875+
876+#ifndef _PSB_DRM_H_
877+#define _PSB_DRM_H_
878+
879+#if defined(__linux__) && !defined(__KERNEL__)
880+#include<stdint.h>
881+#endif
882+
883+/*
884+ * Intel Poulsbo driver package version.
885+ *
886+ */
887+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
888+#define PSB_PACKAGE_VERSION "2.0.0.32L.0007"
889+
890+#define DRM_PSB_SAREA_MAJOR 0
891+#define DRM_PSB_SAREA_MINOR 1
892+#define PSB_FIXED_SHIFT 16
893+
894+/*
895+ * Public memory types.
896+ */
897+
898+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
899+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
900+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
901+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
902+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
903+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
904+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
905+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
906+#define PSB_MEM_RASTGEOM_START 0x30000000
907+
908+typedef int32_t psb_fixed;
909+typedef uint32_t psb_ufixed;
910+
911+static inline psb_fixed psb_int_to_fixed(int a)
912+{
913+ return a * (1 << PSB_FIXED_SHIFT);
914+}
915+
916+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
917+{
918+ return a << PSB_FIXED_SHIFT;
919+}
920+
921+/*Status of the command sent to the gfx device.*/
922+typedef enum {
923+ DRM_CMD_SUCCESS,
924+ DRM_CMD_FAILED,
925+ DRM_CMD_HANG
926+} drm_cmd_status_t;
927+
928+struct drm_psb_scanout {
929+ uint32_t buffer_id; /* DRM buffer object ID */
930+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
931+ uint32_t stride; /* Buffer stride in bytes */
932+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
933+ uint32_t width; /* Buffer width in pixels */
934+ uint32_t height; /* Buffer height in lines */
935+ psb_fixed transform[3][3]; /* Buffer composite transform */
936+ /* (scaling, rot, reflect) */
937+};
938+
939+#define DRM_PSB_SAREA_OWNERS 16
940+#define DRM_PSB_SAREA_OWNER_2D 0
941+#define DRM_PSB_SAREA_OWNER_3D 1
942+
943+#define DRM_PSB_SAREA_SCANOUTS 3
944+
945+struct drm_psb_sarea {
946+ /* Track changes of this data structure */
947+
948+ uint32_t major;
949+ uint32_t minor;
950+
951+ /* Last context to touch part of hw */
952+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
953+
954+ /* Definition of front- and rotated buffers */
955+ uint32_t num_scanouts;
956+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
957+
958+ int planeA_x;
959+ int planeA_y;
960+ int planeA_w;
961+ int planeA_h;
962+ int planeB_x;
963+ int planeB_y;
964+ int planeB_w;
965+ int planeB_h;
966+ uint32_t msvdx_state;
967+ uint32_t msvdx_context;
968+};
969+
970+#define PSB_RELOC_MAGIC 0x67676767
971+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
972+#define PSB_RELOC_SHIFT_SHIFT 0
973+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
974+#define PSB_RELOC_ALSHIFT_SHIFT 16
975+
976+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
977+ * buffer
978+ */
979+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
980+ * buffer, relative to 2D
981+ * base address
982+ */
983+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
984+ * relative to PDS base address
985+ */
986+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
987+ * buffer (for tiling)
988+ */
989+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
990+ * relative to base reg
991+ */
992+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
993+
994+struct drm_psb_reloc {
995+ uint32_t reloc_op;
996+ uint32_t where; /* offset in destination buffer */
997+ uint32_t buffer; /* Buffer reloc applies to */
998+ uint32_t mask; /* Destination format: */
999+ uint32_t shift; /* Destination format: */
1000+ uint32_t pre_add; /* Destination format: */
1001+ uint32_t background; /* Destination add */
1002+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
1003+ uint32_t arg0; /* Reloc-op dependant */
1004+ uint32_t arg1;
1005+};
1006+
1007+#define PSB_BO_FLAG_TA (1ULL << 48)
1008+#define PSB_BO_FLAG_SCENE (1ULL << 49)
1009+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
1010+#define PSB_BO_FLAG_USSE (1ULL << 51)
1011+
1012+#define PSB_ENGINE_2D 0
1013+#define PSB_ENGINE_VIDEO 1
1014+#define PSB_ENGINE_RASTERIZER 2
1015+#define PSB_ENGINE_TA 3
1016+#define PSB_ENGINE_HPRAST 4
1017+
1018+/*
1019+ * For this fence class we have a couple of
1020+ * fence types.
1021+ */
1022+
1023+#define _PSB_FENCE_EXE_SHIFT 0
1024+#define _PSB_FENCE_TA_DONE_SHIFT 1
1025+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
1026+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
1027+#define _PSB_FENCE_FEEDBACK_SHIFT 4
1028+
1029+#define _PSB_ENGINE_TA_FENCE_TYPES 5
1030+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
1031+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
1032+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
1033+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
1034+
1035+#define PSB_ENGINE_HPRAST 4
1036+#define PSB_NUM_ENGINES 5
1037+
1038+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
1039+#define PSB_TA_FLAG_LASTPASS (1 << 1)
1040+
1041+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
1042+
1043+struct drm_psb_scene {
1044+ int handle_valid;
1045+ uint32_t handle;
1046+ uint32_t w;
1047+ uint32_t h;
1048+ uint32_t num_buffers;
1049+};
1050+
1051+typedef struct drm_psb_cmdbuf_arg {
1052+ uint64_t buffer_list; /* List of buffers to validate */
1053+ uint64_t clip_rects; /* See i915 counterpart */
1054+ uint64_t scene_arg;
1055+ uint64_t fence_arg;
1056+
1057+ uint32_t ta_flags;
1058+
1059+ uint32_t ta_handle; /* TA reg-value pairs */
1060+ uint32_t ta_offset;
1061+ uint32_t ta_size;
1062+
1063+ uint32_t oom_handle;
1064+ uint32_t oom_offset;
1065+ uint32_t oom_size;
1066+
1067+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
1068+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
1069+ uint32_t cmdbuf_size;
1070+
1071+ uint32_t reloc_handle; /* Reloc buffer object */
1072+ uint32_t reloc_offset;
1073+ uint32_t num_relocs;
1074+
1075+ int32_t damage; /* Damage front buffer with cliprects */
1076+ /* Not implemented yet */
1077+ uint32_t fence_flags;
1078+ uint32_t engine;
1079+
1080+ /*
1081+ * Feedback;
1082+ */
1083+
1084+ uint32_t feedback_ops;
1085+ uint32_t feedback_handle;
1086+ uint32_t feedback_offset;
1087+ uint32_t feedback_breakpoints;
1088+ uint32_t feedback_size;
1089+} drm_psb_cmdbuf_arg_t;
1090+
1091+struct drm_psb_xhw_init_arg {
1092+ uint32_t operation;
1093+ uint32_t buffer_handle;
1094+};
1095+
1096+/*
1097+ * Feedback components:
1098+ */
1099+
1100+/*
1101+ * Vistest component. The number of these in the feedback buffer
1102+ * equals the number of vistest breakpoints + 1.
1103+ * This is currently the only feedback component.
1104+ */
1105+
1106+struct drm_psb_vistest {
1107+ uint32_t vt[8];
1108+};
1109+
1110+#define PSB_HW_COOKIE_SIZE 16
1111+#define PSB_HW_FEEDBACK_SIZE 8
1112+#define PSB_HW_OOM_CMD_SIZE 6
1113+
1114+struct drm_psb_xhw_arg {
1115+ uint32_t op;
1116+ int ret;
1117+ uint32_t irq_op;
1118+ uint32_t issue_irq;
1119+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
1120+ union {
1121+ struct {
1122+ uint32_t w;
1123+ uint32_t h;
1124+ uint32_t size;
1125+ uint32_t clear_p_start;
1126+ uint32_t clear_num_pages;
1127+ } si;
1128+ struct {
1129+ uint32_t fire_flags;
1130+ uint32_t hw_context;
1131+ uint32_t offset;
1132+ uint32_t engine;
1133+ uint32_t flags;
1134+ uint32_t rca;
1135+ uint32_t num_oom_cmds;
1136+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
1137+ } sb;
1138+ struct {
1139+ uint32_t pages;
1140+ uint32_t size;
1141+ } bi;
1142+ struct {
1143+ uint32_t bca;
1144+ uint32_t rca;
1145+ uint32_t flags;
1146+ } oom;
1147+ struct {
1148+ uint32_t pt_offset;
1149+ uint32_t param_offset;
1150+ uint32_t flags;
1151+ } bl;
1152+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
1153+ } arg;
1154+};
1155+
1156+#define DRM_PSB_CMDBUF 0x00
1157+#define DRM_PSB_XHW_INIT 0x01
1158+#define DRM_PSB_XHW 0x02
1159+#define DRM_PSB_SCENE_UNREF 0x03
1160+/* Controlling the kernel modesetting buffers */
1161+#define DRM_PSB_KMS_OFF 0x04
1162+#define DRM_PSB_KMS_ON 0x05
1163+
1164+#define PSB_XHW_INIT 0x00
1165+#define PSB_XHW_TAKEDOWN 0x01
1166+
1167+#define PSB_XHW_FIRE_RASTER 0x00
1168+#define PSB_XHW_SCENE_INFO 0x01
1169+#define PSB_XHW_SCENE_BIND_FIRE 0x02
1170+#define PSB_XHW_TA_MEM_INFO 0x03
1171+#define PSB_XHW_RESET_DPM 0x04
1172+#define PSB_XHW_OOM 0x05
1173+#define PSB_XHW_TERMINATE 0x06
1174+#define PSB_XHW_VISTEST 0x07
1175+#define PSB_XHW_RESUME 0x08
1176+#define PSB_XHW_TA_MEM_LOAD 0x09
1177+
1178+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
1179+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
1180+#define PSB_SCENE_FLAG_SETUP (1 << 2)
1181+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
1182+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
1183+
1184+#define PSB_TA_MEM_FLAG_TA (1 << 0)
1185+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
1186+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
1187+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
1188+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
1189+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
1190+
1191+/*Raster fire will deallocate memory */
1192+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
1193+/*Isp reset needed due to change in ZLS format */
1194+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
1195+/*These are set by Xpsb. */
1196+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
1197+/*The task has had at least one OOM and Xpsb will
1198+ send back messages on each fire. */
1199+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
1200+
1201+#define PSB_SCENE_ENGINE_TA 0
1202+#define PSB_SCENE_ENGINE_RASTER 1
1203+#define PSB_SCENE_NUM_ENGINES 2
1204+
1205+struct drm_psb_dev_info_arg {
1206+ uint32_t num_use_attribute_registers;
1207+};
1208+#define DRM_PSB_DEVINFO 0x01
1209+
1210+#endif
1211Index: libdrm-2.4.4/shared-core/psb_drv.h
1212===================================================================
1213--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1214+++ libdrm-2.4.4/shared-core/psb_drv.h 2009-02-04 16:39:55.000000000 +0000
1215@@ -0,0 +1,786 @@
1216+/**************************************************************************
1217+ * Copyright (c) 2007, Intel Corporation.
1218+ * All Rights Reserved.
1219+ *
1220+ * This program is free software; you can redistribute it and/or modify it
1221+ * under the terms and conditions of the GNU General Public License,
1222+ * version 2, as published by the Free Software Foundation.
1223+ *
1224+ * This program is distributed in the hope it will be useful, but WITHOUT
1225+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1226+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1227+ * more details.
1228+ *
1229+ * You should have received a copy of the GNU General Public License along with
1230+ * this program; if not, write to the Free Software Foundation, Inc.,
1231+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1232+ *
1233+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
1234+ * develop this driver.
1235+ *
1236+ **************************************************************************/
1237+/*
1238+ */
1239+#ifndef _PSB_DRV_H_
1240+#define _PSB_DRV_H_
1241+
1242+#include "drmP.h"
1243+#include "psb_drm.h"
1244+#include "psb_reg.h"
1245+#include "psb_schedule.h"
1246+#include "intel_drv.h"
1247+
1248+enum {
1249+ CHIP_PSB_8108 = 0,
1250+ CHIP_PSB_8109 = 1
1251+};
1252+
1253+#define DRIVER_NAME "psb"
1254+#define DRIVER_DESC "drm driver for the Intel GMA500"
1255+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
1256+
1257+#define PSB_DRM_DRIVER_DATE "20080107"
1258+#define PSB_DRM_DRIVER_MAJOR 4
1259+#define PSB_DRM_DRIVER_MINOR 1
1260+#define PSB_DRM_DRIVER_PATCHLEVEL 0
1261+
1262+#define PSB_VDC_OFFSET 0x00000000
1263+#define PSB_VDC_SIZE 0x000080000
1264+#define PSB_SGX_SIZE 0x8000
1265+#define PSB_SGX_OFFSET 0x00040000
1266+#define PSB_MMIO_RESOURCE 0
1267+#define PSB_GATT_RESOURCE 2
1268+#define PSB_GTT_RESOURCE 3
1269+#define PSB_GMCH_CTRL 0x52
1270+#define PSB_BSM 0x5C
1271+#define _PSB_GMCH_ENABLED 0x4
1272+#define PSB_PGETBL_CTL 0x2020
1273+#define _PSB_PGETBL_ENABLED 0x00000001
1274+#define PSB_SGX_2D_SLAVE_PORT 0x4000
1275+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
1276+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
1277+#define PSB_NUM_VALIDATE_BUFFERS 640
1278+#define PSB_MEM_KERNEL_START 0x10000000
1279+#define PSB_MEM_PDS_START 0x20000000
1280+#define PSB_MEM_MMU_START 0x40000000
1281+
1282+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
1283+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
1284+
1285+/*
1286+ * Flags for external memory type field.
1287+ */
1288+
1289+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
1290+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
1291+
1292+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
1293+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
1294+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
1295+
1296+/*
1297+ * PTE's and PDE's
1298+ */
1299+
1300+#define PSB_PDE_MASK 0x003FFFFF
1301+#define PSB_PDE_SHIFT 22
1302+#define PSB_PTE_SHIFT 12
1303+
1304+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
1305+#define PSB_PTE_WO 0x0002 /* Write only */
1306+#define PSB_PTE_RO 0x0004 /* Read only */
1307+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
1308+
1309+/*
1310+ * VDC registers and bits
1311+ */
1312+#define PSB_HWSTAM 0x2098
1313+#define PSB_INSTPM 0x20C0
1314+#define PSB_INT_IDENTITY_R 0x20A4
1315+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
1316+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
1317+#define _PSB_IRQ_SGX_FLAG (1<<18)
1318+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
1319+#define PSB_INT_MASK_R 0x20A8
1320+#define PSB_INT_ENABLE_R 0x20A0
1321+#define PSB_PIPEASTAT 0x70024
1322+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
1323+#define _PSB_VBLANK_CLEAR (1 << 1)
1324+#define PSB_PIPEBSTAT 0x71024
1325+
1326+#define _PSB_MMU_ER_MASK 0x0001FF00
1327+#define _PSB_MMU_ER_HOST (1 << 16)
1328+#define GPIOA 0x5010
1329+#define GPIOB 0x5014
1330+#define GPIOC 0x5018
1331+#define GPIOD 0x501c
1332+#define GPIOE 0x5020
1333+#define GPIOF 0x5024
1334+#define GPIOG 0x5028
1335+#define GPIOH 0x502c
1336+#define GPIO_CLOCK_DIR_MASK (1 << 0)
1337+#define GPIO_CLOCK_DIR_IN (0 << 1)
1338+#define GPIO_CLOCK_DIR_OUT (1 << 1)
1339+#define GPIO_CLOCK_VAL_MASK (1 << 2)
1340+#define GPIO_CLOCK_VAL_OUT (1 << 3)
1341+#define GPIO_CLOCK_VAL_IN (1 << 4)
1342+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1343+#define GPIO_DATA_DIR_MASK (1 << 8)
1344+#define GPIO_DATA_DIR_IN (0 << 9)
1345+#define GPIO_DATA_DIR_OUT (1 << 9)
1346+#define GPIO_DATA_VAL_MASK (1 << 10)
1347+#define GPIO_DATA_VAL_OUT (1 << 11)
1348+#define GPIO_DATA_VAL_IN (1 << 12)
1349+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1350+
1351+#define VCLK_DIVISOR_VGA0 0x6000
1352+#define VCLK_DIVISOR_VGA1 0x6004
1353+#define VCLK_POST_DIV 0x6010
1354+
1355+#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
1356+#define I915_WRITE(_offs, _val) \
1357+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
1358+#define I915_READ(_offs) \
1359+ ioread32(dev_priv->vdc_reg + (_offs))
1360+
1361+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
1362+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
1363+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
1364+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
1365+#define PSB_COMM_USER_IRQ (1024 >> 2)
1366+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
1367+#define PSB_COMM_FW (2048 >> 2)
1368+
1369+#define PSB_UIRQ_VISTEST 1
1370+#define PSB_UIRQ_OOM_REPLY 2
1371+#define PSB_UIRQ_FIRE_TA_REPLY 3
1372+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
1373+
1374+#define PSB_2D_SIZE (256*1024*1024)
1375+#define PSB_MAX_RELOC_PAGES 1024
1376+
1377+#define PSB_LOW_REG_OFFS 0x0204
1378+#define PSB_HIGH_REG_OFFS 0x0600
1379+
1380+#define PSB_NUM_VBLANKS 2
1381+
1382+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
1383+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
1384+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
1385+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
1386+#define PSB_COMM_FW (2048 >> 2)
1387+
1388+#define PSB_2D_SIZE (256*1024*1024)
1389+#define PSB_MAX_RELOC_PAGES 1024
1390+
1391+#define PSB_LOW_REG_OFFS 0x0204
1392+#define PSB_HIGH_REG_OFFS 0x0600
1393+
1394+#define PSB_NUM_VBLANKS 2
1395+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
1396+
1397+/*
1398+ * User options.
1399+ */
1400+
1401+struct drm_psb_uopt {
1402+ int disable_clock_gating;
1403+};
1404+
1405+struct psb_gtt {
1406+ struct drm_device *dev;
1407+ int initialized;
1408+ uint32_t gatt_start;
1409+ uint32_t gtt_start;
1410+ uint32_t gtt_phys_start;
1411+ unsigned gtt_pages;
1412+ unsigned gatt_pages;
1413+ uint32_t stolen_base;
1414+ uint32_t pge_ctl;
1415+ u16 gmch_ctrl;
1416+ unsigned long stolen_size;
1417+ uint32_t *gtt_map;
1418+ struct rw_semaphore sem;
1419+};
1420+
1421+struct psb_use_base {
1422+ struct list_head head;
1423+ struct drm_fence_object *fence;
1424+ unsigned int reg;
1425+ unsigned long offset;
1426+ unsigned int dm;
1427+};
1428+
1429+struct psb_buflist_item {
1430+ struct drm_buffer_object *bo;
1431+ void __user *data;
1432+ struct drm_bo_info_rep rep;
1433+ int ret;
1434+};
1435+
1436+struct psb_msvdx_cmd_queue {
1437+ struct list_head head;
1438+ void *cmd;
1439+ unsigned long cmd_size;
1440+ uint32_t sequence;
1441+};
1442+
1443+struct drm_psb_private {
1444+ unsigned long chipset;
1445+
1446+ struct psb_xhw_buf resume_buf;
1447+ struct drm_psb_dev_info_arg dev_info;
1448+ struct drm_psb_uopt uopt;
1449+
1450+ struct psb_gtt *pg;
1451+
1452+ struct page *scratch_page;
1453+ struct page *comm_page;
1454+
1455+ volatile uint32_t *comm;
1456+ uint32_t comm_mmu_offset;
1457+ uint32_t mmu_2d_offset;
1458+ uint32_t sequence[PSB_NUM_ENGINES];
1459+ uint32_t last_sequence[PSB_NUM_ENGINES];
1460+ int idle[PSB_NUM_ENGINES];
1461+ uint32_t last_submitted_seq[PSB_NUM_ENGINES];
1462+ int engine_lockup_2d;
1463+
1464+ struct psb_mmu_driver *mmu;
1465+ struct psb_mmu_pd *pf_pd;
1466+
1467+ uint8_t *sgx_reg;
1468+ uint8_t *vdc_reg;
1469+ uint8_t *msvdx_reg;
1470+ /*MSVDX*/ int msvdx_needs_reset;
1471+ int has_msvdx;
1472+ uint32_t gatt_free_offset;
1473+
1474+ /*
1475+ * Fencing / irq.
1476+ */
1477+
1478+ uint32_t sgx_irq_mask;
1479+ uint32_t vdc_irq_mask;
1480+
1481+ spinlock_t irqmask_lock;
1482+ spinlock_t sequence_lock;
1483+ int fence0_irq_on;
1484+ int irq_enabled;
1485+ unsigned int irqen_count_2d;
1486+ wait_queue_head_t event_2d_queue;
1487+
1488+ uint32_t msvdx_current_sequence;
1489+ uint32_t msvdx_last_sequence;
1490+ int fence2_irq_on;
1491+ struct mutex mutex_2d;
1492+
1493+ /*
1494+ * MSVDX Rendec Memory
1495+ */
1496+ struct drm_buffer_object *ccb0;
1497+ uint32_t base_addr0;
1498+ struct drm_buffer_object *ccb1;
1499+ uint32_t base_addr1;
1500+
1501+ /*
1502+ * Memory managers
1503+ */
1504+
1505+ int have_vram;
1506+ int have_tt;
1507+ int have_mem_mmu;
1508+ int have_mem_aper;
1509+ int have_mem_kernel;
1510+ int have_mem_pds;
1511+ int have_mem_rastgeom;
1512+ struct mutex temp_mem;
1513+
1514+ /*
1515+ * Relocation buffer mapping.
1516+ */
1517+
1518+ spinlock_t reloc_lock;
1519+ unsigned int rel_mapped_pages;
1520+ wait_queue_head_t rel_mapped_queue;
1521+
1522+ /*
1523+ * SAREA
1524+ */
1525+ struct drm_psb_sarea *sarea_priv;
1526+
1527+ /*
1528+ * LVDS info
1529+ */
1530+ uint8_t blc_type;
1531+ uint8_t blc_pol;
1532+ uint8_t blc_freq;
1533+ uint8_t blc_minbrightness;
1534+ uint8_t blc_i2caddr;
1535+ uint8_t blc_brightnesscmd;
1536+ int backlight; /* restore backlight to this value */
1537+
1538+ struct intel_i2c_chan *i2c_bus;
1539+ u32 CoreClock;
1540+ u32 PWMControlRegFreq;
1541+
1542+ unsigned char * OpRegion;
1543+ unsigned int OpRegionSize;
1544+
1545+ int backlight_duty_cycle; /* restore backlight to this value */
1546+ bool panel_wants_dither;
1547+ struct drm_display_mode *panel_fixed_mode;
1548+
1549+ /*
1550+ * Register state
1551+ */
1552+ uint32_t saveDSPACNTR;
1553+ uint32_t saveDSPBCNTR;
1554+ uint32_t savePIPEACONF;
1555+ uint32_t savePIPEBCONF;
1556+ uint32_t savePIPEASRC;
1557+ uint32_t savePIPEBSRC;
1558+ uint32_t saveFPA0;
1559+ uint32_t saveFPA1;
1560+ uint32_t saveDPLL_A;
1561+ uint32_t saveDPLL_A_MD;
1562+ uint32_t saveHTOTAL_A;
1563+ uint32_t saveHBLANK_A;
1564+ uint32_t saveHSYNC_A;
1565+ uint32_t saveVTOTAL_A;
1566+ uint32_t saveVBLANK_A;
1567+ uint32_t saveVSYNC_A;
1568+ uint32_t saveDSPASTRIDE;
1569+ uint32_t saveDSPASIZE;
1570+ uint32_t saveDSPAPOS;
1571+ uint32_t saveDSPABASE;
1572+ uint32_t saveDSPASURF;
1573+ uint32_t saveFPB0;
1574+ uint32_t saveFPB1;
1575+ uint32_t saveDPLL_B;
1576+ uint32_t saveDPLL_B_MD;
1577+ uint32_t saveHTOTAL_B;
1578+ uint32_t saveHBLANK_B;
1579+ uint32_t saveHSYNC_B;
1580+ uint32_t saveVTOTAL_B;
1581+ uint32_t saveVBLANK_B;
1582+ uint32_t saveVSYNC_B;
1583+ uint32_t saveDSPBSTRIDE;
1584+ uint32_t saveDSPBSIZE;
1585+ uint32_t saveDSPBPOS;
1586+ uint32_t saveDSPBBASE;
1587+ uint32_t saveDSPBSURF;
1588+ uint32_t saveVCLK_DIVISOR_VGA0;
1589+ uint32_t saveVCLK_DIVISOR_VGA1;
1590+ uint32_t saveVCLK_POST_DIV;
1591+ uint32_t saveVGACNTRL;
1592+ uint32_t saveADPA;
1593+ uint32_t saveLVDS;
1594+ uint32_t saveDVOA;
1595+ uint32_t saveDVOB;
1596+ uint32_t saveDVOC;
1597+ uint32_t savePP_ON;
1598+ uint32_t savePP_OFF;
1599+ uint32_t savePP_CONTROL;
1600+ uint32_t savePP_CYCLE;
1601+ uint32_t savePFIT_CONTROL;
1602+ uint32_t savePaletteA[256];
1603+ uint32_t savePaletteB[256];
1604+ uint32_t saveBLC_PWM_CTL;
1605+
1606+ /*
1607+ * USE code base register management.
1608+ */
1609+
1610+ struct drm_reg_manager use_manager;
1611+
1612+ /*
1613+ * Xhw
1614+ */
1615+
1616+ uint32_t *xhw;
1617+ struct drm_buffer_object *xhw_bo;
1618+ struct drm_bo_kmap_obj xhw_kmap;
1619+ struct list_head xhw_in;
1620+ spinlock_t xhw_lock;
1621+ atomic_t xhw_client;
1622+ struct drm_file *xhw_file;
1623+ wait_queue_head_t xhw_queue;
1624+ wait_queue_head_t xhw_caller_queue;
1625+ struct mutex xhw_mutex;
1626+ struct psb_xhw_buf *xhw_cur_buf;
1627+ int xhw_submit_ok;
1628+ int xhw_on;
1629+
1630+ /*
1631+ * Scheduling.
1632+ */
1633+
1634+ struct mutex reset_mutex;
1635+ struct mutex cmdbuf_mutex;
1636+ struct psb_scheduler scheduler;
1637+ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS];
1638+ uint32_t ta_mem_pages;
1639+ struct psb_ta_mem *ta_mem;
1640+ int force_ta_mem_load;
1641+
1642+ /*
1643+ * Watchdog
1644+ */
1645+
1646+ spinlock_t watchdog_lock;
1647+ struct timer_list watchdog_timer;
1648+ struct work_struct watchdog_wq;
1649+ struct work_struct msvdx_watchdog_wq;
1650+ int timer_available;
1651+
1652+ /*
1653+ * msvdx command queue
1654+ */
1655+ spinlock_t msvdx_lock;
1656+ struct mutex msvdx_mutex;
1657+ struct list_head msvdx_queue;
1658+ int msvdx_busy;
1659+};
1660+
1661+struct psb_mmu_driver;
1662+
1663+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
1664+ int trap_pagefaults,
1665+ int invalid_type);
1666+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
1667+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
1668+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
1669+ uint32_t gtt_start, uint32_t gtt_pages);
1670+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
1671+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
1672+ int trap_pagefaults,
1673+ int invalid_type);
1674+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
1675+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
1676+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
1677+ unsigned long address,
1678+ uint32_t num_pages);
1679+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
1680+ uint32_t start_pfn,
1681+ unsigned long address,
1682+ uint32_t num_pages, int type);
1683+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
1684+ unsigned long *pfn);
1685+
1686+/*
1687+ * Enable / disable MMU for different requestors.
1688+ */
1689+
1690+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
1691+ uint32_t mask);
1692+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
1693+ uint32_t mask);
1694+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
1695+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
1696+ unsigned long address, uint32_t num_pages,
1697+ uint32_t desired_tile_stride,
1698+ uint32_t hw_tile_stride, int type);
1699+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
1700+ uint32_t num_pages,
1701+ uint32_t desired_tile_stride,
1702+ uint32_t hw_tile_stride);
1703+/*
1704+ * psb_sgx.c
1705+ */
1706+
1707+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
1708+ uint32_t sequence);
1709+extern void psb_init_2d(struct drm_psb_private *dev_priv);
1710+extern int drm_psb_idle(struct drm_device *dev);
1711+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
1712+ uint32_t src_offset,
1713+ uint32_t dst_offset, uint32_t pages,
1714+ int direction);
1715+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
1716+ struct drm_file *file_priv);
1717+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
1718+ unsigned int cmds);
1719+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
1720+ struct drm_buffer_object *cmd_buffer,
1721+ unsigned long cmd_offset,
1722+ unsigned long cmd_size, int engine,
1723+ uint32_t * copy_buffer);
1724+
1725+extern int psb_fence_for_errors(struct drm_file *priv,
1726+ struct drm_psb_cmdbuf_arg *arg,
1727+ struct drm_fence_arg *fence_arg,
1728+ struct drm_fence_object **fence_p);
1729+
1730+/*
1731+ * psb_irq.c
1732+ */
1733+
1734+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
1735+extern void psb_irq_preinstall(struct drm_device *dev);
1736+extern void psb_irq_postinstall(struct drm_device *dev);
1737+extern void psb_irq_uninstall(struct drm_device *dev);
1738+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
1739+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
1740+
1741+/*
1742+ * psb_fence.c
1743+ */
1744+
1745+extern void psb_poke_flush(struct drm_device *dev, uint32_t class);
1746+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class,
1747+ uint32_t flags, uint32_t * sequence,
1748+ uint32_t * native_type);
1749+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
1750+extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class,
1751+ uint32_t flags);
1752+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
1753+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
1754+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
1755+ uint32_t class);
1756+extern void psb_fence_error(struct drm_device *dev,
1757+ uint32_t class,
1758+ uint32_t sequence, uint32_t type, int error);
1759+
1760+/*MSVDX stuff*/
1761+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
1762+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
1763+
1764+/*
1765+ * psb_buffer.c
1766+ */
1767+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
1768+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
1769+ uint32_t * type);
1770+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
1771+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
1772+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
1773+ struct drm_mem_type_manager *man);
1774+extern int psb_move(struct drm_buffer_object *bo,
1775+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
1776+
1777+/*
1778+ * psb_gtt.c
1779+ */
1780+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
1781+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
1782+ unsigned offset_pages, unsigned num_pages,
1783+ unsigned desired_tile_stride,
1784+ unsigned hw_tile_stride, int type);
1785+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
1786+ unsigned num_pages,
1787+ unsigned desired_tile_stride,
1788+ unsigned hw_tile_stride);
1789+
1790+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
1791+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
1792+
1793+/*
1794+ * psb_fb.c
1795+ */
1796+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
1797+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
1798+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
1799+ struct drm_file *file_priv);
1800+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
1801+ struct drm_file *file_priv);
1802+
1803+/*
1804+ * psb_reset.c
1805+ */
1806+
1807+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
1808+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
1809+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
1810+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
1811+
1812+/*
1813+ * psb_regman.c
1814+ */
1815+
1816+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
1817+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
1818+ unsigned long dev_virtual,
1819+ unsigned long size,
1820+ unsigned int data_master,
1821+ uint32_t fence_class,
1822+ uint32_t fence_type,
1823+ int no_wait,
1824+ int ignore_signals,
1825+ int *r_reg, uint32_t * r_offset);
1826+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
1827+ unsigned int reg_start, unsigned int reg_num);
1828+
1829+/*
1830+ * psb_xhw.c
1831+ */
1832+
1833+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
1834+ struct drm_file *file_priv);
1835+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
1836+ struct drm_file *file_priv);
1837+extern int psb_xhw_init(struct drm_device *dev);
1838+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
1839+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
1840+ struct drm_file *file_priv, int closing);
1841+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
1842+ struct psb_xhw_buf *buf,
1843+ uint32_t fire_flags,
1844+ uint32_t hw_context,
1845+ uint32_t * cookie,
1846+ uint32_t * oom_cmds,
1847+ uint32_t num_oom_cmds,
1848+ uint32_t offset,
1849+ uint32_t engine, uint32_t flags);
1850+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
1851+ struct psb_xhw_buf *buf, uint32_t fire_flags);
1852+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
1853+ struct psb_xhw_buf *buf,
1854+ uint32_t w,
1855+ uint32_t h,
1856+ uint32_t * hw_cookie,
1857+ uint32_t * bo_size,
1858+ uint32_t * clear_p_start,
1859+ uint32_t * clear_num_pages);
1860+
1861+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
1862+ struct psb_xhw_buf *buf);
1863+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
1864+ struct psb_xhw_buf *buf,
1865+ uint32_t pages,
1866+ uint32_t * hw_cookie, uint32_t * size);
1867+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
1868+ struct psb_xhw_buf *buf, uint32_t * cookie);
1869+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
1870+ struct psb_xhw_buf *buf,
1871+ uint32_t * cookie,
1872+ uint32_t * bca,
1873+ uint32_t * rca, uint32_t * flags);
1874+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
1875+ struct psb_xhw_buf *buf);
1876+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
1877+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
1878+ struct psb_xhw_buf *buf);
1879+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
1880+ struct psb_xhw_buf *buf, uint32_t * cookie);
1881+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
1882+ struct psb_xhw_buf *buf,
1883+ uint32_t flags,
1884+ uint32_t param_offset,
1885+ uint32_t pt_offset,
1886+ uint32_t *hw_cookie);
1887+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
1888+ struct psb_xhw_buf *buf);
1889+
1890+/*
1891+ * Utilities
1892+ */
1893+
1894+#define PSB_ALIGN_TO(_val, _align) \
1895+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
1896+#define PSB_WVDC32(_val, _offs) \
1897+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
1898+#define PSB_RVDC32(_offs) \
1899+ ioread32(dev_priv->vdc_reg + (_offs))
1900+#define PSB_WSGX32(_val, _offs) \
1901+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
1902+#define PSB_RSGX32(_offs) \
1903+ ioread32(dev_priv->sgx_reg + (_offs))
1904+#define PSB_WMSVDX32(_val, _offs) \
1905+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1906+#define PSB_RMSVDX32(_offs) \
1907+ ioread32(dev_priv->msvdx_reg + (_offs))
1908+
1909+#define PSB_ALPL(_val, _base) \
1910+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
1911+#define PSB_ALPLM(_val, _base) \
1912+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
1913+
1914+static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b)
1915+{
1916+ s64 tmp;
1917+ s64 a64 = (s64) a;
1918+ s64 b64 = (s64) b;
1919+
1920+ tmp = a64 * b64;
1921+ return tmp / (1ULL << PSB_FIXED_SHIFT) +
1922+ ((tmp & 0x80000000ULL) ? 1 : 0);
1923+}
1924+
1925+static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b)
1926+{
1927+ u64 tmp;
1928+ u64 a64 = (u64) a;
1929+ u64 b64 = (u64) b;
1930+
1931+ tmp = a64 * b64;
1932+ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0);
1933+}
1934+
1935+static inline uint32_t psb_ufixed_to_float32(psb_ufixed a)
1936+{
1937+ uint32_t exp = 0x7f + 7;
1938+ uint32_t mantissa = (uint32_t) a;
1939+
1940+ if (a == 0)
1941+ return 0;
1942+ while ((mantissa & 0xff800000) == 0) {
1943+ exp -= 1;
1944+ mantissa <<= 1;
1945+ }
1946+ while ((mantissa & 0xff800000) > 0x00800000) {
1947+ exp += 1;
1948+ mantissa >>= 1;
1949+ }
1950+ return (mantissa & ~0xff800000) | (exp << 23);
1951+}
1952+
1953+static inline uint32_t psb_fixed_to_float32(psb_fixed a)
1954+{
1955+ if (a < 0)
1956+ return psb_ufixed_to_float32(-a) | 0x80000000;
1957+ else
1958+ return psb_ufixed_to_float32(a);
1959+}
1960+
1961+#define PSB_D_RENDER (1 << 16)
1962+
1963+#define PSB_D_GENERAL (1 << 0)
1964+#define PSB_D_INIT (1 << 1)
1965+#define PSB_D_IRQ (1 << 2)
1966+#define PSB_D_FW (1 << 3)
1967+#define PSB_D_PERF (1 << 4)
1968+#define PSB_D_TMP (1 << 5)
1969+
1970+extern int drm_psb_debug;
1971+extern int drm_psb_no_fb;
1972+extern int drm_psb_disable_vsync;
1973+
1974+#define PSB_DEBUG_FW(_fmt, _arg...) \
1975+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
1976+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
1977+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
1978+#define PSB_DEBUG_INIT(_fmt, _arg...) \
1979+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
1980+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
1981+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
1982+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
1983+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
1984+#define PSB_DEBUG_PERF(_fmt, _arg...) \
1985+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
1986+#define PSB_DEBUG_TMP(_fmt, _arg...) \
1987+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
1988+
1989+#if DRM_DEBUG_CODE
1990+#define PSB_DEBUG(_flag, _fmt, _arg...) \
1991+ do { \
1992+ if ((_flag) & drm_psb_debug) \
1993+ printk(KERN_DEBUG \
1994+ "[psb:0x%02x:%s] " _fmt , _flag, \
1995+ __FUNCTION__ , ##_arg); \
1996+ } while (0)
1997+#else
1998+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
1999+#endif
2000+
2001+#endif
2002Index: libdrm-2.4.4/shared-core/psb_reg.h
2003===================================================================
2004--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2005+++ libdrm-2.4.4/shared-core/psb_reg.h 2009-02-04 16:39:55.000000000 +0000
2006@@ -0,0 +1,555 @@
2007+/**************************************************************************
2008+ *
2009+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
2010+ * Copyright (c) 2007, Intel Corporation.
2011+ * All Rights Reserved.
2012+ *
2013+ * This program is free software; you can redistribute it and/or modify it
2014+ * under the terms and conditions of the GNU General Public License,
2015+ * version 2, as published by the Free Software Foundation.
2016+ *
2017+ * This program is distributed in the hope it will be useful, but WITHOUT
2018+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2019+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2020+ * more details.
2021+ *
2022+ * You should have received a copy of the GNU General Public License along with
2023+ * this program; if not, write to the Free Software Foundation, Inc.,
2024+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2025+ *
2026+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
2027+ * develop this driver.
2028+ *
2029+ **************************************************************************/
2030+/*
2031+ */
2032+#ifndef _PSB_REG_H_
2033+#define _PSB_REG_H_
2034+
2035+#define PSB_CR_CLKGATECTL 0x0000
2036+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
2037+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
2038+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
2039+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
2040+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
2041+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
2042+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
2043+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
2044+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
2045+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
2046+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
2047+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
2048+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
2049+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
2050+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
2051+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
2052+
2053+#define PSB_CR_CORE_ID 0x0010
2054+#define _PSB_CC_ID_ID_SHIFT (16)
2055+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
2056+#define _PSB_CC_ID_CONFIG_SHIFT (0)
2057+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
2058+
2059+#define PSB_CR_CORE_REVISION 0x0014
2060+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
2061+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
2062+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
2063+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
2064+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
2065+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
2066+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
2067+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
2068+
2069+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
2070+
2071+#define PSB_CR_SOFT_RESET 0x0080
2072+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
2073+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
2074+#define _PSB_CS_RESET_USE_RESET (1 << 4)
2075+#define _PSB_CS_RESET_TA_RESET (1 << 3)
2076+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
2077+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
2078+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
2079+
2080+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
2081+
2082+#define PSB_CR_EVENT_STATUS 0x012C
2083+
2084+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
2085+
2086+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
2087+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
2088+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
2089+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
2090+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
2091+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
2092+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
2093+#define _PSB_CE_SW_EVENT (1 << 14)
2094+#define _PSB_CE_TA_FINISHED (1 << 13)
2095+#define _PSB_CE_TA_TERMINATE (1 << 12)
2096+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
2097+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
2098+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
2099+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
2100+
2101+
2102+#define PSB_USE_OFFSET_MASK 0x0007FFFF
2103+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
2104+#define PSB_CR_USE_CODE_BASE0 0x0A0C
2105+#define PSB_CR_USE_CODE_BASE1 0x0A10
2106+#define PSB_CR_USE_CODE_BASE2 0x0A14
2107+#define PSB_CR_USE_CODE_BASE3 0x0A18
2108+#define PSB_CR_USE_CODE_BASE4 0x0A1C
2109+#define PSB_CR_USE_CODE_BASE5 0x0A20
2110+#define PSB_CR_USE_CODE_BASE6 0x0A24
2111+#define PSB_CR_USE_CODE_BASE7 0x0A28
2112+#define PSB_CR_USE_CODE_BASE8 0x0A2C
2113+#define PSB_CR_USE_CODE_BASE9 0x0A30
2114+#define PSB_CR_USE_CODE_BASE10 0x0A34
2115+#define PSB_CR_USE_CODE_BASE11 0x0A38
2116+#define PSB_CR_USE_CODE_BASE12 0x0A3C
2117+#define PSB_CR_USE_CODE_BASE13 0x0A40
2118+#define PSB_CR_USE_CODE_BASE14 0x0A44
2119+#define PSB_CR_USE_CODE_BASE15 0x0A48
2120+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
2121+#define _PSB_CUC_BASE_DM_SHIFT (25)
2122+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
2123+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
2124+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
2125+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
2126+#define _PSB_CUC_DM_VERTEX (0)
2127+#define _PSB_CUC_DM_PIXEL (1)
2128+#define _PSB_CUC_DM_RESERVED (2)
2129+#define _PSB_CUC_DM_EDM (3)
2130+
2131+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
2132+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
2133+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
2134+
2135+#define PSB_CR_EVENT_KICKER 0x0AC4
2136+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
2137+
2138+#define PSB_CR_EVENT_KICK 0x0AC8
2139+#define _PSB_CE_KICK_NOW (1 << 0)
2140+
2141+
2142+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
2143+
2144+#define PSB_CR_BIF_CTRL 0x0C00
2145+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
2146+#define _PSB_CB_CTRL_INVALDC (1 << 3)
2147+#define _PSB_CB_CTRL_FLUSH (1 << 2)
2148+
2149+#define PSB_CR_BIF_INT_STAT 0x0C04
2150+
2151+#define PSB_CR_BIF_FAULT 0x0C08
2152+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
2153+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
2154+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
2155+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
2156+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
2157+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
2158+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
2159+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
2160+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
2161+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
2162+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
2163+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
2164+
2165+#define PSB_CR_BIF_BANK0 0x0C78
2166+
2167+#define PSB_CR_BIF_BANK1 0x0C7C
2168+
2169+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
2170+
2171+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
2172+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
2173+
2174+#define PSB_CR_2D_SOCIF 0x0E18
2175+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
2176+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
2177+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
2178+
2179+#define PSB_CR_2D_BLIT_STATUS 0x0E04
2180+#define _PSB_C2B_STATUS_BUSY (1 << 24)
2181+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
2182+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
2183+
2184+/*
2185+ * 2D defs.
2186+ */
2187+
2188+/*
2189+ * 2D Slave Port Data : Block Header's Object Type
2190+ */
2191+
2192+#define PSB_2D_CLIP_BH (0x00000000)
2193+#define PSB_2D_PAT_BH (0x10000000)
2194+#define PSB_2D_CTRL_BH (0x20000000)
2195+#define PSB_2D_SRC_OFF_BH (0x30000000)
2196+#define PSB_2D_MASK_OFF_BH (0x40000000)
2197+#define PSB_2D_RESERVED1_BH (0x50000000)
2198+#define PSB_2D_RESERVED2_BH (0x60000000)
2199+#define PSB_2D_FENCE_BH (0x70000000)
2200+#define PSB_2D_BLIT_BH (0x80000000)
2201+#define PSB_2D_SRC_SURF_BH (0x90000000)
2202+#define PSB_2D_DST_SURF_BH (0xA0000000)
2203+#define PSB_2D_PAT_SURF_BH (0xB0000000)
2204+#define PSB_2D_SRC_PAL_BH (0xC0000000)
2205+#define PSB_2D_PAT_PAL_BH (0xD0000000)
2206+#define PSB_2D_MASK_SURF_BH (0xE0000000)
2207+#define PSB_2D_FLUSH_BH (0xF0000000)
2208+
2209+/*
2210+ * Clip Definition block (PSB_2D_CLIP_BH)
2211+ */
2212+#define PSB_2D_CLIPCOUNT_MAX (1)
2213+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
2214+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
2215+#define PSB_2D_CLIPCOUNT_SHIFT (0)
2216+// clip rectangle min & max
2217+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
2218+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
2219+#define PSB_2D_CLIP_XMAX_SHIFT (12)
2220+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
2221+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
2222+#define PSB_2D_CLIP_XMIN_SHIFT (0)
2223+// clip rectangle offset
2224+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
2225+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
2226+#define PSB_2D_CLIP_YMAX_SHIFT (12)
2227+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
2228+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
2229+#define PSB_2D_CLIP_YMIN_SHIFT (0)
2230+
2231+/*
2232+ * Pattern Control (PSB_2D_PAT_BH)
2233+ */
2234+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
2235+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
2236+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
2237+#define PSB_2D_PAT_WIDTH_SHIFT (5)
2238+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
2239+#define PSB_2D_PAT_YSTART_SHIFT (10)
2240+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
2241+#define PSB_2D_PAT_XSTART_SHIFT (15)
2242+
2243+/*
2244+ * 2D Control block (PSB_2D_CTRL_BH)
2245+ */
2246+// Present Flags
2247+#define PSB_2D_SRCCK_CTRL (0x00000001)
2248+#define PSB_2D_DSTCK_CTRL (0x00000002)
2249+#define PSB_2D_ALPHA_CTRL (0x00000004)
2250+// Colour Key Colour (SRC/DST)
2251+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
2252+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
2253+#define PSB_2D_CK_COL_SHIFT (0)
2254+// Colour Key Mask (SRC/DST)
2255+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
2256+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
2257+#define PSB_2D_CK_MASK_SHIFT (0)
2258+// Alpha Control (Alpha/RGB)
2259+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
2260+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
2261+#define PSB_2D_GBLALPHA_SHIFT (12)
2262+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
2263+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
2264+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
2265+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
2266+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
2267+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
2268+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
2269+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
2270+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
2271+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
2272+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
2273+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
2274+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
2275+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
2276+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
2277+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
2278+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
2279+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
2280+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
2281+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
2282+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
2283+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
2284+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
2285+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
2286+
2287+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
2288+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
2289+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
2290+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
2291+
2292+/*
2293+ *Source Offset (PSB_2D_SRC_OFF_BH)
2294+ */
2295+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
2296+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
2297+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
2298+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
2299+
2300+/*
2301+ * Mask Offset (PSB_2D_MASK_OFF_BH)
2302+ */
2303+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
2304+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
2305+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
2306+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
2307+
2308+/*
2309+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
2310+ */
2311+
2312+/*
2313+ *Blit Rectangle (PSB_2D_BLIT_BH)
2314+ */
2315+
2316+#define PSB_2D_ROT_MASK (3<<25)
2317+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
2318+#define PSB_2D_ROT_NONE (0<<25)
2319+#define PSB_2D_ROT_90DEGS (1<<25)
2320+#define PSB_2D_ROT_180DEGS (2<<25)
2321+#define PSB_2D_ROT_270DEGS (3<<25)
2322+
2323+#define PSB_2D_COPYORDER_MASK (3<<23)
2324+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
2325+#define PSB_2D_COPYORDER_TL2BR (0<<23)
2326+#define PSB_2D_COPYORDER_BR2TL (1<<23)
2327+#define PSB_2D_COPYORDER_TR2BL (2<<23)
2328+#define PSB_2D_COPYORDER_BL2TR (3<<23)
2329+
2330+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
2331+#define PSB_2D_DSTCK_DISABLE (0x00000000)
2332+#define PSB_2D_DSTCK_PASS (0x00200000)
2333+#define PSB_2D_DSTCK_REJECT (0x00400000)
2334+
2335+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
2336+#define PSB_2D_SRCCK_DISABLE (0x00000000)
2337+#define PSB_2D_SRCCK_PASS (0x00080000)
2338+#define PSB_2D_SRCCK_REJECT (0x00100000)
2339+
2340+#define PSB_2D_CLIP_ENABLE (0x00040000)
2341+
2342+#define PSB_2D_ALPHA_ENABLE (0x00020000)
2343+
2344+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
2345+#define PSB_2D_PAT_MASK (0x00010000)
2346+#define PSB_2D_USE_PAT (0x00010000)
2347+#define PSB_2D_USE_FILL (0x00000000)
2348+/*
2349+ * Tungsten Graphics note on rop codes: If rop A and rop B are
2350+ * identical, the mask surface will not be read and need not be
2351+ * set up.
2352+ */
2353+
2354+#define PSB_2D_ROP3B_MASK (0x0000FF00)
2355+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
2356+#define PSB_2D_ROP3B_SHIFT (8)
2357+// rop code A
2358+#define PSB_2D_ROP3A_MASK (0x000000FF)
2359+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
2360+#define PSB_2D_ROP3A_SHIFT (0)
2361+
2362+#define PSB_2D_ROP4_MASK (0x0000FFFF)
2363+/*
2364+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
2365+ * Fill Colour RGBA8888
2366+ */
2367+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
2368+#define PSB_2D_FILLCOLOUR_SHIFT (0)
2369+/*
2370+ * DWORD1: (Always Present)
2371+ * X Start (Dest)
2372+ * Y Start (Dest)
2373+ */
2374+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
2375+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
2376+#define PSB_2D_DST_XSTART_SHIFT (12)
2377+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
2378+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
2379+#define PSB_2D_DST_YSTART_SHIFT (0)
2380+/*
2381+ * DWORD2: (Always Present)
2382+ * X Size (Dest)
2383+ * Y Size (Dest)
2384+ */
2385+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
2386+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
2387+#define PSB_2D_DST_XSIZE_SHIFT (12)
2388+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
2389+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
2390+#define PSB_2D_DST_YSIZE_SHIFT (0)
2391+
2392+/*
2393+ * Source Surface (PSB_2D_SRC_SURF_BH)
2394+ */
2395+/*
2396+ * WORD 0
2397+ */
2398+
2399+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
2400+#define PSB_2D_SRC_1_PAL (0x00000000)
2401+#define PSB_2D_SRC_2_PAL (0x00008000)
2402+#define PSB_2D_SRC_4_PAL (0x00010000)
2403+#define PSB_2D_SRC_8_PAL (0x00018000)
2404+#define PSB_2D_SRC_8_ALPHA (0x00020000)
2405+#define PSB_2D_SRC_4_ALPHA (0x00028000)
2406+#define PSB_2D_SRC_332RGB (0x00030000)
2407+#define PSB_2D_SRC_4444ARGB (0x00038000)
2408+#define PSB_2D_SRC_555RGB (0x00040000)
2409+#define PSB_2D_SRC_1555ARGB (0x00048000)
2410+#define PSB_2D_SRC_565RGB (0x00050000)
2411+#define PSB_2D_SRC_0888ARGB (0x00058000)
2412+#define PSB_2D_SRC_8888ARGB (0x00060000)
2413+#define PSB_2D_SRC_8888UYVY (0x00068000)
2414+#define PSB_2D_SRC_RESERVED (0x00070000)
2415+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
2416+
2417+
2418+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
2419+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
2420+#define PSB_2D_SRC_STRIDE_SHIFT (0)
2421+/*
2422+ * WORD 1 - Base Address
2423+ */
2424+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
2425+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
2426+#define PSB_2D_SRC_ADDR_SHIFT (2)
2427+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
2428+
2429+/*
2430+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
2431+ */
2432+/*
2433+ * WORD 0
2434+ */
2435+
2436+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
2437+#define PSB_2D_PAT_1_PAL (0x00000000)
2438+#define PSB_2D_PAT_2_PAL (0x00008000)
2439+#define PSB_2D_PAT_4_PAL (0x00010000)
2440+#define PSB_2D_PAT_8_PAL (0x00018000)
2441+#define PSB_2D_PAT_8_ALPHA (0x00020000)
2442+#define PSB_2D_PAT_4_ALPHA (0x00028000)
2443+#define PSB_2D_PAT_332RGB (0x00030000)
2444+#define PSB_2D_PAT_4444ARGB (0x00038000)
2445+#define PSB_2D_PAT_555RGB (0x00040000)
2446+#define PSB_2D_PAT_1555ARGB (0x00048000)
2447+#define PSB_2D_PAT_565RGB (0x00050000)
2448+#define PSB_2D_PAT_0888ARGB (0x00058000)
2449+#define PSB_2D_PAT_8888ARGB (0x00060000)
2450+
2451+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
2452+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
2453+#define PSB_2D_PAT_STRIDE_SHIFT (0)
2454+/*
2455+ * WORD 1 - Base Address
2456+ */
2457+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
2458+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
2459+#define PSB_2D_PAT_ADDR_SHIFT (2)
2460+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
2461+
2462+/*
2463+ * Destination Surface (PSB_2D_DST_SURF_BH)
2464+ */
2465+/*
2466+ * WORD 0
2467+ */
2468+
2469+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
2470+#define PSB_2D_DST_332RGB (0x00030000)
2471+#define PSB_2D_DST_4444ARGB (0x00038000)
2472+#define PSB_2D_DST_555RGB (0x00040000)
2473+#define PSB_2D_DST_1555ARGB (0x00048000)
2474+#define PSB_2D_DST_565RGB (0x00050000)
2475+#define PSB_2D_DST_0888ARGB (0x00058000)
2476+#define PSB_2D_DST_8888ARGB (0x00060000)
2477+#define PSB_2D_DST_8888AYUV (0x00070000)
2478+
2479+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
2480+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
2481+#define PSB_2D_DST_STRIDE_SHIFT (0)
2482+/*
2483+ * WORD 1 - Base Address
2484+ */
2485+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
2486+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
2487+#define PSB_2D_DST_ADDR_SHIFT (2)
2488+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
2489+
2490+/*
2491+ * Mask Surface (PSB_2D_MASK_SURF_BH)
2492+ */
2493+/*
2494+ * WORD 0
2495+ */
2496+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
2497+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
2498+#define PSB_2D_MASK_STRIDE_SHIFT (0)
2499+/*
2500+ * WORD 1 - Base Address
2501+ */
2502+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
2503+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
2504+#define PSB_2D_MASK_ADDR_SHIFT (2)
2505+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
2506+
2507+/*
2508+ * Source Palette (PSB_2D_SRC_PAL_BH)
2509+ */
2510+
2511+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
2512+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
2513+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
2514+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
2515+
2516+/*
2517+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
2518+ */
2519+
2520+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
2521+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
2522+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
2523+#define PSB_2D_PATPAL_BYTEALIGN (1024)
2524+
2525+/*
2526+ * Rop3 Codes (2 LS bytes)
2527+ */
2528+
2529+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
2530+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
2531+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
2532+#define PSB_2D_ROP3_BLACKNESS (0x0000)
2533+#define PSB_2D_ROP3_SRC (0xCC)
2534+#define PSB_2D_ROP3_PAT (0xF0)
2535+#define PSB_2D_ROP3_DST (0xAA)
2536+
2537+
2538+/*
2539+ * Sizes.
2540+ */
2541+
2542+#define PSB_SCENE_HW_COOKIE_SIZE 16
2543+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
2544+
2545+/*
2546+ * Scene stuff.
2547+ */
2548+
2549+#define PSB_NUM_HW_SCENES 2
2550+
2551+/*
2552+ * Scheduler completion actions.
2553+ */
2554+
2555+#define PSB_RASTER_BLOCK 0
2556+#define PSB_RASTER 1
2557+#define PSB_RETURN 2
2558+#define PSB_TA 3
2559+
2560+
2561+#endif
2562Index: libdrm-2.4.4/shared-core/radeon_drm.h
2563===================================================================
2564--- libdrm-2.4.4.orig/shared-core/radeon_drm.h 2008-10-09 20:02:11.000000000 +0100
2565+++ libdrm-2.4.4/shared-core/radeon_drm.h 2009-02-04 16:39:55.000000000 +0000
2566@@ -453,8 +453,17 @@
2567 int pfCurrentPage; /* which buffer is being displayed? */
2568 int crtc2_base; /* CRTC2 frame offset */
2569 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
2570+
2571+ unsigned int last_fence;
2572 } drm_radeon_sarea_t;
2573
2574+/* The only fence class we support */
2575+#define DRM_RADEON_FENCE_CLASS_ACCEL 0
2576+/* Fence type that guarantees read-write flush */
2577+#define DRM_RADEON_FENCE_TYPE_RW 2
2578+/* cache flushes programmed just before the fence */
2579+#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000
2580+
2581 /* WARNING: If you change any of these defines, make sure to change the
2582 * defines in the Xserver file (xf86drmRadeon.h)
2583 *
2584Index: libdrm-2.4.4/shared-core/tdfx_drv.h
2585===================================================================
2586--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2587+++ libdrm-2.4.4/shared-core/tdfx_drv.h 2009-02-04 16:39:55.000000000 +0000
2588@@ -0,0 +1,47 @@
2589+/* tdfx.h -- 3dfx DRM template customization -*- linux-c -*-
2590+ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
2591+ */
2592+/*
2593+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
2594+ * All Rights Reserved.
2595+ *
2596+ * Permission is hereby granted, free of charge, to any person obtaining a
2597+ * copy of this software and associated documentation files (the "Software"),
2598+ * to deal in the Software without restriction, including without limitation
2599+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
2600+ * and/or sell copies of the Software, and to permit persons to whom the
2601+ * Software is furnished to do so, subject to the following conditions:
2602+ *
2603+ * The above copyright notice and this permission notice (including the next
2604+ * paragraph) shall be included in all copies or substantial portions of the
2605+ * Software.
2606+ *
2607+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2608+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2609+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
2610+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2611+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2612+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2613+ * OTHER DEALINGS IN THE SOFTWARE.
2614+ *
2615+ * Authors:
2616+ * Gareth Hughes <gareth@valinux.com>
2617+ */
2618+
2619+#ifndef __TDFX_H__
2620+#define __TDFX_H__
2621+
2622+/* General customization:
2623+ */
2624+
2625+#define DRIVER_AUTHOR "VA Linux Systems Inc."
2626+
2627+#define DRIVER_NAME "tdfx"
2628+#define DRIVER_DESC "3dfx Banshee/Voodoo3+"
2629+#define DRIVER_DATE "20010216"
2630+
2631+#define DRIVER_MAJOR 1
2632+#define DRIVER_MINOR 0
2633+#define DRIVER_PATCHLEVEL 0
2634+
2635+#endif
2636Index: libdrm-2.4.4/libdrm/Makefile.am
2637===================================================================
2638--- libdrm-2.4.4.orig/libdrm/Makefile.am 2009-02-04 16:42:01.000000000 +0000
2639+++ libdrm-2.4.4/libdrm/Makefile.am 2009-02-04 16:45:06.000000000 +0000
2640@@ -31,6 +31,6 @@
2641 libdrm_lists.h
2642
2643 libdrmincludedir = ${includedir}
2644-libdrminclude_HEADERS = xf86drm.h xf86drmMode.h
2645+libdrminclude_HEADERS = xf86drm.h xf86drmMode.h xf86mm.h libdrm_lists.h
2646
2647 EXTRA_DIST = ChangeLog TODO
diff --git a/meta/packages/drm/libdrm_2.4.4.bb b/meta/packages/drm/libdrm_2.4.4.bb
index 29b3c4cbf8..ddb3776adb 100644
--- a/meta/packages/drm/libdrm_2.4.4.bb
+++ b/meta/packages/drm/libdrm_2.4.4.bb
@@ -1,6 +1,8 @@
1SECTION = "x11/base" 1SECTION = "x11/base"
2LICENSE = "MIT" 2LICENSE = "MIT"
3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2" 3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2 \
4 file://poulsbo.patch;patch=1"
5PR = "r2"
4PROVIDES = "drm" 6PROVIDES = "drm"
5DEPENDS = "libpthread-stubs" 7DEPENDS = "libpthread-stubs"
6 8
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-11-08 01:36:37 +0000