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authorAdrian Dudau <adrian.dudau@enea.com>2013-12-12 17:36:38 +0100
committerAdrian Dudau <adrian.dudau@enea.com>2013-12-12 17:36:38 +0100
commit2a7348129a42f21095fcd62e47a035f78d254130 (patch)
tree544dc8019a8f8cb684ace8674193605e607f9964 /recipes-append/oprofile/files
downloadmeta-enea-master.tar.gz
initial commit of Enea Linux 3.1HEADmaster
Migrated from the internal git server on the dora-enea branch Signed-off-by: Adrian Dudau <adrian.dudau@enea.com>
Diffstat (limited to 'recipes-append/oprofile/files')
-rw-r--r--recipes-append/oprofile/files/oprofile-e500mc.patch2095
1 files changed, 2095 insertions, 0 deletions
diff --git a/recipes-append/oprofile/files/oprofile-e500mc.patch b/recipes-append/oprofile/files/oprofile-e500mc.patch
new file mode 100644
index 0000000..f784ae6
--- /dev/null
+++ b/recipes-append/oprofile/files/oprofile-e500mc.patch
@@ -0,0 +1,2095 @@
1diff -uNr a/events/Makefile.am b/events/Makefile.am
2--- a/events/Makefile.am 2012-08-27 20:59:13.000000000 +0200
3+++ b/events/Makefile.am 2013-02-07 07:06:04.168567619 +0100
4@@ -72,6 +72,7 @@
5 ppc/7450/events ppc/7450/unit_masks \
6 ppc/e500/events ppc/e500/unit_masks \
7 ppc/e500v2/events ppc/e500v2/unit_masks \
8+ ppc/e500mc/events ppc/e500mc/unit_masks \
9 ppc/e300/events ppc/e300/unit_masks \
10 tile/tile64/events tile/tile64/unit_masks \
11 tile/tilepro/events tile/tilepro/unit_masks \
12diff -uNr a/events/ppc/e500mc/events b/events/ppc/e500mc/events
13--- a/events/ppc/e500mc/events 1970-01-01 01:00:00.000000000 +0100
14+++ b/events/ppc/e500mc/events 2013-02-07 07:03:57.990063725 +0100
15@@ -0,0 +1,83 @@
16+# e500 Events
17+#
18+event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles
19+event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
20+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
21+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
22+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
23+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
24+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
25+event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
26+event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
27+event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
28+event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
29+event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished
30+event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
31+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction
32+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken
33+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
34+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
35+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
36+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
37+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
38+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
39+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
40+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
41+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated.
42+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.)
43+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.)
44+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.)
45+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)
46+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
47+event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated
48+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated
49+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated.
50+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB
51+event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.)
52+event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.)
53+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.)
54+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.)
55+event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.)
56+event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.
57+event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF.
58+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full.
59+event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full.
60+event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer.
61+event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full.
62+event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision.
63+event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss.
64+event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy.
65+event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache.
66+event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full.
67+event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full.
68+event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer.
69+event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full.
70+event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision.
71+event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss.
72+event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy.
73+event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache.
74+event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.)
75+event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.
76+event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
77+event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads
78+event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads
79+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads
80+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads
81+event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt
82+event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.)
83+event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.)
84+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.)
85+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.)
86+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_RETRIES : Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)
87+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.)
88+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared)
89+event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)
90+event:0x4b counters:0,1,2,3 um:zero minimum:500 name:SNOOP_RETRIES : Number of snoop requests retried. (Counts snoop ARTRYs.)
91+event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
92+event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
93+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
94+event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
95+event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
96+event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
97+event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
98+event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
99diff -uNr a/events/ppc/e500mc/unit_masks b/events/ppc/e500mc/unit_masks
100--- a/events/ppc/e500mc/unit_masks 1970-01-01 01:00:00.000000000 +0100
101+++ b/events/ppc/e500mc/unit_masks 2013-02-07 07:03:57.994063551 +0100
102@@ -0,0 +1,4 @@
103+# e500 possible unit masks
104+#
105+name:zero type:mandatory default:0x0
106+ 0x0 No unit mask
107diff -uNr a/libop/op_cpu_type.c b/libop/op_cpu_type.c
108--- a/libop/op_cpu_type.c 2012-08-27 20:59:14.000000000 +0200
109+++ b/libop/op_cpu_type.c 2013-02-07 07:03:57.994063551 +0100
110@@ -66,6 +66,7 @@
111 { "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2 },
112 { "e500", "ppc/e500", CPU_PPC_E500, 4 },
113 { "e500v2", "ppc/e500v2", CPU_PPC_E500_2, 4 },
114+ { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 },
115 { "Core Solo / Duo", "i386/core", CPU_CORE, 2 },
116 { "PowerPC G4", "ppc/7450", CPU_PPC_7450, 6 },
117 { "Core 2", "i386/core_2", CPU_CORE_2, 2 },
118diff -uNr a/libop/op_cpu_type.c.orig b/libop/op_cpu_type.c.orig
119--- a/libop/op_cpu_type.c.orig 1970-01-01 01:00:00.000000000 +0100
120+++ b/libop/op_cpu_type.c.orig 2013-02-07 07:01:39.408100801 +0100
121@@ -0,0 +1,621 @@
122+/**
123+ * @file op_cpu_type.c
124+ * CPU type determination
125+ *
126+ * @remark Copyright 2002 OProfile authors
127+ * @remark Read the file COPYING
128+ *
129+ * @author John Levon
130+ * @author Philippe Elie
131+ */
132+
133+#include <stdio.h>
134+#include <stdlib.h>
135+#include <string.h>
136+#include <sys/utsname.h>
137+#include <ctype.h>
138+#include <errno.h>
139+#include <fnmatch.h>
140+
141+#include "op_cpu_type.h"
142+#include "op_hw_specific.h"
143+
144+struct cpu_descr {
145+ char const * pretty;
146+ char const * name;
147+ op_cpu cpu;
148+ unsigned int nr_counters;
149+};
150+
151+static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
152+ { "Pentium Pro", "i386/ppro", CPU_PPRO, 2 },
153+ { "PII", "i386/pii", CPU_PII, 2 },
154+ { "PIII", "i386/piii", CPU_PIII, 2 },
155+ { "Athlon", "i386/athlon", CPU_ATHLON, 4 },
156+ { "CPU with timer interrupt", "timer", CPU_TIMER_INT, 1 },
157+ { "CPU with RTC device", "rtc", CPU_RTC, 1 },
158+ { "P4 / Xeon", "i386/p4", CPU_P4, 8 },
159+ { "IA64", "ia64/ia64", CPU_IA64, 4 },
160+ { "Itanium", "ia64/itanium", CPU_IA64_1, 4 },
161+ { "Itanium 2", "ia64/itanium2", CPU_IA64_2, 4 },
162+ { "AMD64 processors", "x86-64/hammer", CPU_HAMMER, 4 },
163+ { "P4 / Xeon with 2 hyper-threads", "i386/p4-ht", CPU_P4_HT2, 4 },
164+ { "Alpha EV4", "alpha/ev4", CPU_AXP_EV4, 2 },
165+ { "Alpha EV5", "alpha/ev5", CPU_AXP_EV5, 3 },
166+ { "Alpha PCA56", "alpha/pca56", CPU_AXP_PCA56, 3 },
167+ { "Alpha EV6", "alpha/ev6", CPU_AXP_EV6, 2 },
168+ { "Alpha EV67", "alpha/ev67", CPU_AXP_EV67, 20 },
169+ { "Pentium M (P6 core)", "i386/p6_mobile", CPU_P6_MOBILE, 2 },
170+ { "ARM/XScale PMU1", "arm/xscale1", CPU_ARM_XSCALE1, 3 },
171+ { "ARM/XScale PMU2", "arm/xscale2", CPU_ARM_XSCALE2, 5 },
172+ { "ppc64 POWER4", "ppc64/power4", CPU_PPC64_POWER4, 8 },
173+ { "ppc64 POWER5", "ppc64/power5", CPU_PPC64_POWER5, 6 },
174+ { "ppc64 POWER5+", "ppc64/power5+", CPU_PPC64_POWER5p, 6 },
175+ { "ppc64 970", "ppc64/970", CPU_PPC64_970, 8 },
176+ { "MIPS 20K", "mips/20K", CPU_MIPS_20K, 1},
177+ { "MIPS 24K", "mips/24K", CPU_MIPS_24K, 2},
178+ { "MIPS 25K", "mips/25K", CPU_MIPS_25K, 2},
179+ { "MIPS 34K", "mips/34K", CPU_MIPS_34K, 2},
180+ { "MIPS 5K", "mips/5K", CPU_MIPS_5K, 2},
181+ { "MIPS R10000", "mips/r10000", CPU_MIPS_R10000, 2 },
182+ { "MIPS R12000", "mips/r12000", CPU_MIPS_R12000, 4 },
183+ { "QED RM7000", "mips/rm7000", CPU_MIPS_RM7000, 1 },
184+ { "PMC-Sierra RM9000", "mips/rm9000", CPU_MIPS_RM9000, 2 },
185+ { "Sibyte SB1", "mips/sb1", CPU_MIPS_SB1, 4 },
186+ { "NEC VR5432", "mips/vr5432", CPU_MIPS_VR5432, 2 },
187+ { "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2 },
188+ { "e500", "ppc/e500", CPU_PPC_E500, 4 },
189+ { "e500v2", "ppc/e500v2", CPU_PPC_E500_2, 4 },
190+ { "Core Solo / Duo", "i386/core", CPU_CORE, 2 },
191+ { "PowerPC G4", "ppc/7450", CPU_PPC_7450, 6 },
192+ { "Core 2", "i386/core_2", CPU_CORE_2, 2 },
193+ { "ppc64 POWER6", "ppc64/power6", CPU_PPC64_POWER6, 4 },
194+ { "ppc64 970MP", "ppc64/970MP", CPU_PPC64_970MP, 8 },
195+ { "ppc64 Cell Broadband Engine", "ppc64/cell-be", CPU_PPC64_CELL, 8 },
196+ { "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 },
197+ { "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 },
198+ { "ARM 11MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 },
199+ { "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 },
200+ { "ppc64 POWER5++", "ppc64/power5++", CPU_PPC64_POWER5pp, 6 },
201+ { "e300", "ppc/e300", CPU_PPC_E300, 4 },
202+ { "AVR32", "avr32", CPU_AVR32, 3 },
203+ { "ARM Cortex-A8", "arm/armv7", CPU_ARM_V7, 5 },
204+ { "Intel Architectural Perfmon", "i386/arch_perfmon", CPU_ARCH_PERFMON, 0},
205+ { "AMD64 family11h", "x86-64/family11h", CPU_FAMILY11H, 4 },
206+ { "ppc64 POWER7", "ppc64/power7", CPU_PPC64_POWER7, 6 },
207+ { "ppc64 compat version 1", "ppc64/ibm-compat-v1", CPU_PPC64_IBM_COMPAT_V1, 4 },
208+ { "Intel Core/i7", "i386/core_i7", CPU_CORE_I7, 4 },
209+ { "Intel Atom", "i386/atom", CPU_ATOM, 2 },
210+ { "Loongson2", "mips/loongson2", CPU_MIPS_LOONGSON2, 2 },
211+ { "Intel Nehalem microarchitecture", "i386/nehalem", CPU_NEHALEM, 4 },
212+ { "ARM Cortex-A9", "arm/armv7-ca9", CPU_ARM_V7_CA9, 7 },
213+ { "MIPS 74K", "mips/74K", CPU_MIPS_74K, 4},
214+ { "MIPS 1004K", "mips/1004K", CPU_MIPS_1004K, 2},
215+ { "AMD64 family12h", "x86-64/family12h", CPU_FAMILY12H, 4 },
216+ { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 },
217+ { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 },
218+ { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 },
219+ { "ARMv7 Scorpion", "arm/armv7-scorpion", CPU_ARM_SCORPION, 5 },
220+ { "ARMv7 ScorpionMP", "arm/armv7-scorpionmp", CPU_ARM_SCORPIONMP, 5 },
221+ { "Intel Sandy Bridge microarchitecture", "i386/sandybridge", CPU_SANDYBRIDGE, 8 },
222+ { "TILE64", "tile/tile64", CPU_TILE_TILE64, 2 },
223+ { "TILEPro", "tile/tilepro", CPU_TILE_TILEPRO, 4 },
224+ { "TILE-GX", "tile/tilegx", CPU_TILE_TILEGX, 4 },
225+ { "IBM System z10", "s390/z10", CPU_S390_Z10, 1 },
226+ { "IBM zEnterprise z196", "s390/z196", CPU_S390_Z196, 1 },
227+ { "Intel Ivy Bridge microarchitecture", "i386/ivybridge", CPU_IVYBRIDGE, 8 },
228+ { "ARM Cortex-A5", "arm/armv7-ca5", CPU_ARM_V7_CA5, 3 },
229+ { "ARM Cortex-A7", "arm/armv7-ca7", CPU_ARM_V7_CA7, 5 },
230+ { "ARM Cortex-A15", "arm/armv7-ca15", CPU_ARM_V7_CA15, 7 },
231+};
232+
233+static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
234+
235+static char * _get_cpuinfo_cpu_type_line(char * buf, int len, const char * prefix, int token)
236+{
237+ char * ret = NULL;
238+ char * end = NULL;
239+ int prefix_len = strlen(prefix);
240+ FILE * fp = fopen("/proc/cpuinfo", "r");
241+
242+ if (!fp) {
243+ perror("Unable to open /proc/cpuinfo\n");
244+ return ret;
245+ }
246+
247+ memset(buf, 0, len);
248+
249+ while (!ret) {
250+ if (fgets(buf, len, fp) == NULL) {
251+ fprintf(stderr, "Did not find processor type in /proc/cpuinfo.\n");
252+ break;
253+ }
254+ if (!strncmp(buf, prefix, prefix_len)) {
255+ ret = buf + prefix_len;
256+ /* Strip leading whitespace and ':' delimiter */
257+ while (*ret && (*ret == ':' || isspace(*ret)))
258+ ++ret;
259+ buf = ret;
260+ /* if token param 0 then read the whole line else
261+ * first token only. */
262+ if (token == 0) {
263+ /* Trim trailing whitespace */
264+ end = buf + strlen(buf) - 1;
265+ while (isspace(*end))
266+ --end;
267+ *(++end) = '\0';
268+ break;
269+ } else {
270+ /* Scan ahead to the end of the token */
271+ while (*buf && !isspace(*buf))
272+ ++buf;
273+ /* Trim trailing whitespace */
274+ *buf = '\0';
275+ break;
276+ }
277+ }
278+ }
279+
280+ fclose(fp);
281+ return ret;
282+}
283+
284+static char * _get_cpuinfo_cpu_type(char * buf, int len, const char * prefix)
285+{
286+ return _get_cpuinfo_cpu_type_line(buf, len, prefix, 1);
287+}
288+
289+static op_cpu _get_ppc64_cpu_type(void)
290+{
291+ int i;
292+ size_t len;
293+ char line[100], cpu_type_str[64], cpu_name_lowercase[64], * cpu_name;
294+
295+ cpu_name = _get_cpuinfo_cpu_type(line, 100, "cpu");
296+ if (!cpu_name)
297+ return CPU_NO_GOOD;
298+
299+ len = strlen(cpu_name);
300+ for (i = 0; i < (int)len ; i++)
301+ cpu_name_lowercase[i] = tolower(cpu_name[i]);
302+
303+ cpu_type_str[0] = '\0';
304+ strcat(cpu_type_str, "ppc64/");
305+ strncat(cpu_type_str, cpu_name_lowercase, len);
306+ return op_get_cpu_number(cpu_type_str);
307+}
308+
309+static op_cpu _get_arm_cpu_type(void)
310+{
311+ unsigned long cpuid, vendorid;
312+ char line[100];
313+ char * cpu_part, * cpu_implementer;
314+
315+ cpu_implementer = _get_cpuinfo_cpu_type(line, 100, "CPU implementer");
316+ if (!cpu_implementer)
317+ return CPU_NO_GOOD;
318+
319+ errno = 0;
320+ vendorid = strtoul(cpu_implementer, NULL, 16);
321+ if (errno) {
322+ fprintf(stderr, "Unable to parse CPU implementer %s\n", cpu_implementer);
323+ return CPU_NO_GOOD;
324+ }
325+
326+ cpu_part = _get_cpuinfo_cpu_type(line, 100, "CPU part");
327+ if (!cpu_part)
328+ return CPU_NO_GOOD;
329+
330+ errno = 0;
331+ cpuid = strtoul(cpu_part, NULL, 16);
332+ if (errno) {
333+ fprintf(stderr, "Unable to parse CPU part %s\n", cpu_part);
334+ return CPU_NO_GOOD;
335+ }
336+
337+ if (vendorid == 0x41) { /* ARM Ltd. */
338+ switch (cpuid) {
339+ case 0xb36:
340+ case 0xb56:
341+ case 0xb76:
342+ return op_get_cpu_number("arm/armv6");
343+ case 0xb02:
344+ return op_get_cpu_number("arm/mpcore");
345+ case 0xc05:
346+ return op_get_cpu_number("arm/armv7-ca5");
347+ case 0xc07:
348+ return op_get_cpu_number("arm/armv7-ca7");
349+ case 0xc08:
350+ return op_get_cpu_number("arm/armv7");
351+ case 0xc09:
352+ return op_get_cpu_number("arm/armv7-ca9");
353+ case 0xc0f:
354+ return op_get_cpu_number("arm/armv7-ca15");
355+ }
356+ } else if (vendorid == 0x69) { /* Intel xscale */
357+ switch (cpuid >> 9) {
358+ case 1:
359+ return op_get_cpu_number("arm/xscale1");
360+ case 2:
361+ return op_get_cpu_number("arm/xscale2");
362+ }
363+ }
364+
365+ return CPU_NO_GOOD;
366+}
367+
368+static op_cpu _get_tile_cpu_type(void)
369+{
370+ int i;
371+ size_t len;
372+ char line[100], cpu_type_str[64], cpu_name_lowercase[64], * cpu_name;
373+
374+ cpu_name = _get_cpuinfo_cpu_type(line, 100, "model name");
375+ if (!cpu_name)
376+ return CPU_NO_GOOD;
377+
378+ len = strlen(cpu_name);
379+ for (i = 0; i < (int)len ; i++)
380+ cpu_name_lowercase[i] = tolower(cpu_name[i]);
381+
382+ cpu_type_str[0] = '\0';
383+ strcat(cpu_type_str, "tile/");
384+ strncat(cpu_type_str, cpu_name_lowercase, len);
385+ return op_get_cpu_number(cpu_type_str);
386+}
387+
388+#if defined(__x86_64__) || defined(__i386__)
389+int op_is_cpu_vendor(char * vendor)
390+{
391+ return cpuid_vendor(vendor);
392+}
393+
394+static unsigned cpuid_eax(unsigned func)
395+{
396+ cpuid_data d;
397+
398+ cpuid(func, &d);
399+ return d.eax;
400+}
401+
402+static inline int perfmon_available(void)
403+{
404+ unsigned eax;
405+ if (cpuid_eax(0) < 10)
406+ return 0;
407+ eax = cpuid_eax(10);
408+ if ((eax & 0xff) == 0)
409+ return 0;
410+ return (eax >> 8) & 0xff;
411+}
412+
413+static int cpu_info_number(char *name, unsigned long *number)
414+{
415+ char buf[100];
416+ char *end;
417+
418+ if (!_get_cpuinfo_cpu_type(buf, sizeof buf, name))
419+ return 0;
420+ *number = strtoul(buf, &end, 0);
421+ return end > buf;
422+}
423+
424+static op_cpu _get_intel_cpu_type(void)
425+{
426+ unsigned eax, family, model;
427+
428+ if (perfmon_available())
429+ return op_cpu_specific_type(CPU_ARCH_PERFMON);
430+
431+ /* Handle old non arch perfmon CPUs */
432+ eax = cpuid_signature();
433+ family = cpu_family(eax);
434+ model = cpu_model(eax);
435+
436+ if (family == 6) {
437+ /* Reproduce kernel p6_init logic. Only for non arch perfmon cpus */
438+ switch (model) {
439+ case 0 ... 2:
440+ return op_get_cpu_number("i386/ppro");
441+ case 3 ... 5:
442+ return op_get_cpu_number("i386/pii");
443+ case 6 ... 8:
444+ case 10 ... 11:
445+ return op_get_cpu_number("i386/piii");
446+ case 9:
447+ case 13:
448+ return op_get_cpu_number("i386/p6_mobile");
449+ }
450+ } else if (family == 15) {
451+ unsigned long siblings;
452+
453+ /* Reproduce kernel p4_init() logic */
454+ if (model > 6 || model == 5)
455+ return CPU_NO_GOOD;
456+ if (!cpu_info_number("siblings", &siblings) ||
457+ siblings == 1)
458+ return op_get_cpu_number("i386/p4");
459+ if (siblings == 2)
460+ return op_get_cpu_number("i386/p4-ht");
461+ }
462+ return CPU_NO_GOOD;
463+}
464+
465+static op_cpu _get_amd_cpu_type(void)
466+{
467+ unsigned eax, family, model;
468+ op_cpu ret = CPU_NO_GOOD;
469+
470+ eax = cpuid_signature();
471+ family = cpu_family(eax);
472+ model = cpu_model(eax);
473+
474+ switch (family) {
475+ case 0x0f:
476+ ret = op_get_cpu_number("x86-64/hammer");
477+ break;
478+ case 0x10:
479+ ret = op_get_cpu_number("x86-64/family10");
480+ break;
481+ case 0x11:
482+ ret = op_get_cpu_number("x86-64/family11h");
483+ break;
484+ case 0x12:
485+ ret = op_get_cpu_number("x86-64/family12h");
486+ break;
487+ case 0x14:
488+ ret = op_get_cpu_number("x86-64/family14h");
489+ break;
490+ case 0x15:
491+ switch (model) {
492+ case 0x00 ... 0x0f:
493+ ret = op_get_cpu_number("x86-64/family15h");
494+ break;
495+ default:
496+ break;
497+ }
498+ break;
499+ default:
500+ break;
501+ }
502+
503+ return ret;
504+}
505+
506+static op_cpu _get_x86_64_cpu_type(void)
507+{
508+ op_cpu ret = CPU_NO_GOOD;
509+
510+ if (cpuid_vendor("GenuineIntel")) {
511+ ret = _get_intel_cpu_type();
512+ } else if (cpuid_vendor("AuthenticAMD")) {
513+ ret = _get_amd_cpu_type();
514+ }
515+
516+ return ret;
517+}
518+
519+#else
520+static op_cpu _get_x86_64_cpu_type(void)
521+{
522+ return CPU_NO_GOOD;
523+}
524+#endif
525+
526+struct mips_cpu_descr
527+{
528+ const char * key;
529+ const char * value;
530+};
531+
532+static struct mips_cpu_descr mips_cpu_descrs[] = {
533+ { .key = "MIPS 5Kc", .value = "mips/5K" }, /* CPU_5KC */
534+ { .key = "MIPS 20Kc", .value = "mips/20K" }, /* CPU_20KC */
535+ { .key = "MIPS 24Kc", .value = "mips/24K" }, /* CPU_24K */
536+ { .key = "MIPS 25Kc", .value = "mips/25K" }, /* CPU_25KF */
537+ { .key = "MIPS 34Kc", .value = "mips/34K" }, /* CPU_34K */
538+ { .key = "MIPS 74Kc", .value = "mips/74K" }, /* CPU_74K */
539+ { .key = "MIPS M14Kc", .value = "mips/M14Kc" }, /* CPU_M14KC */
540+ { .key = "RM9000", .value = "mips/rm9000" }, /* CPU_RM9000 */
541+ { .key = "R10000", .value = "mips/r10000" }, /* CPU_R10000 */
542+ { .key = "R12000", .value = "mips/r12000" }, /* CPU_R12000 */
543+ { .key = "R14000", .value = "mips/r12000" }, /* CPU_R14000 */
544+ { .key = "ICT Loongson-2", .value = "mips/loongson2" }, /* CPU_LOONGSON2 */
545+ { .key = NULL, .value = NULL }
546+};
547+
548+static const char * _get_mips_op_name(const char * key)
549+{
550+ struct mips_cpu_descr * p_it = mips_cpu_descrs;
551+ size_t len;
552+
553+
554+ while (p_it->key != NULL) {
555+ len = strlen(p_it->key);
556+ if (0 == strncmp(key, p_it->key, len))
557+ return p_it->value;
558+ ++p_it;
559+ }
560+ return NULL;
561+}
562+
563+static op_cpu _get_mips_cpu_type(void)
564+{
565+ char line[100];
566+ char * cpu_model;
567+ const char * op_name = NULL;
568+
569+ cpu_model = _get_cpuinfo_cpu_type_line(line, 100, "cpu model", 0);
570+ if (!cpu_model)
571+ return CPU_NO_GOOD;
572+
573+ op_name = _get_mips_op_name(cpu_model);
574+
575+ if (op_name)
576+ return op_get_cpu_number(op_name);
577+ return CPU_NO_GOOD;
578+}
579+
580+static op_cpu __get_cpu_type_alt_method(void)
581+{
582+ struct utsname uname_info;
583+ if (uname(&uname_info) < 0) {
584+ perror("uname failed");
585+ return CPU_NO_GOOD;
586+ }
587+ if (strncmp(uname_info.machine, "x86_64", 6) == 0 ||
588+ fnmatch("i?86", uname_info.machine, 0) == 0) {
589+ return _get_x86_64_cpu_type();
590+ }
591+ if (strncmp(uname_info.machine, "ppc64", 5) == 0) {
592+ return _get_ppc64_cpu_type();
593+ }
594+ if (strncmp(uname_info.machine, "arm", 3) == 0) {
595+ return _get_arm_cpu_type();
596+ }
597+ if (strncmp(uname_info.machine, "tile", 4) == 0) {
598+ return _get_tile_cpu_type();
599+ }
600+ if (strncmp(uname_info.machine, "mips", 4) == 0) {
601+ return _get_mips_cpu_type();
602+ }
603+ return CPU_NO_GOOD;
604+}
605+
606+int op_cpu_variations(op_cpu cpu_type)
607+{
608+ switch (cpu_type) {
609+ case CPU_ARCH_PERFMON:
610+ return 1;
611+ default:
612+ return 0;
613+ }
614+}
615+
616+
617+op_cpu op_cpu_base_type(op_cpu cpu_type)
618+{
619+ /* All the processors that support CPU_ARCH_PERFMON */
620+ switch (cpu_type) {
621+ case CPU_CORE_2:
622+ case CPU_CORE_I7:
623+ case CPU_ATOM:
624+ case CPU_NEHALEM:
625+ case CPU_WESTMERE:
626+ case CPU_SANDYBRIDGE:
627+ case CPU_IVYBRIDGE:
628+ return CPU_ARCH_PERFMON;
629+ default:
630+ /* assume processor in a class by itself */
631+ return cpu_type;
632+ }
633+}
634+
635+op_cpu op_get_cpu_type(void)
636+{
637+ int cpu_type = CPU_NO_GOOD;
638+ char str[100];
639+ FILE * fp;
640+
641+ fp = fopen("/proc/sys/dev/oprofile/cpu_type", "r");
642+ if (!fp) {
643+ /* Try 2.6's oprofilefs one instead. */
644+ fp = fopen("/dev/oprofile/cpu_type", "r");
645+ if (!fp) {
646+ if ((cpu_type = __get_cpu_type_alt_method()) == CPU_NO_GOOD) {
647+ fprintf(stderr, "Unable to open cpu_type file for reading\n");
648+ fprintf(stderr, "Make sure you have done opcontrol --init\n");
649+ }
650+ return cpu_type;
651+ }
652+ }
653+
654+ if (!fgets(str, 99, fp)) {
655+ fprintf(stderr, "Could not read cpu type.\n");
656+ fclose(fp);
657+ return cpu_type;
658+ }
659+
660+ cpu_type = op_get_cpu_number(str);
661+
662+ if (op_cpu_variations(cpu_type))
663+ cpu_type = op_cpu_specific_type(cpu_type);
664+
665+ fclose(fp);
666+
667+ return cpu_type;
668+}
669+
670+
671+op_cpu op_get_cpu_number(char const * cpu_string)
672+{
673+ int cpu_type = CPU_NO_GOOD;
674+ size_t i;
675+
676+ for (i = 0; i < nr_cpu_descrs; ++i) {
677+ if (!strcmp(cpu_descrs[i].name, cpu_string)) {
678+ cpu_type = cpu_descrs[i].cpu;
679+ break;
680+ }
681+ }
682+
683+ /* Attempt to convert into a number */
684+ if (cpu_type == CPU_NO_GOOD)
685+ sscanf(cpu_string, "%d\n", &cpu_type);
686+
687+ if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE)
688+ cpu_type = CPU_NO_GOOD;
689+
690+ return cpu_type;
691+}
692+
693+
694+char const * op_get_cpu_type_str(op_cpu cpu_type)
695+{
696+ if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE)
697+ return "invalid cpu type";
698+
699+ return cpu_descrs[cpu_type].pretty;
700+}
701+
702+
703+char const * op_get_cpu_name(op_cpu cpu_type)
704+{
705+ if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE)
706+ return "invalid cpu type";
707+
708+ return cpu_descrs[cpu_type].name;
709+}
710+
711+
712+int op_get_nr_counters(op_cpu cpu_type)
713+{
714+ int cnt;
715+
716+ if (cpu_type <= CPU_NO_GOOD || cpu_type >= MAX_CPU_TYPE)
717+ return 0;
718+
719+ cnt = arch_num_counters(cpu_type);
720+ if (cnt >= 0)
721+ return cnt;
722+
723+ return op_cpu_has_timer_fs()
724+ ? cpu_descrs[cpu_type].nr_counters + 1
725+ : cpu_descrs[cpu_type].nr_counters;
726+}
727+
728+int op_cpu_has_timer_fs(void)
729+{
730+ static int cached_has_timer_fs_p = -1;
731+ FILE * fp;
732+
733+ if (cached_has_timer_fs_p != -1)
734+ return cached_has_timer_fs_p;
735+
736+ fp = fopen("/dev/oprofile/timer", "r");
737+ cached_has_timer_fs_p = !!fp;
738+ if (fp)
739+ fclose(fp);
740+
741+ return cached_has_timer_fs_p;
742+}
743diff -uNr a/libop/op_cpu_type.h b/libop/op_cpu_type.h
744--- a/libop/op_cpu_type.h 2012-08-27 20:59:14.000000000 +0200
745+++ b/libop/op_cpu_type.h 2013-02-07 07:03:57.994063551 +0100
746@@ -59,6 +59,7 @@
747 CPU_MIPS_VR5500, /**< MIPS VR5500, VR5532 and VR7701 */
748 CPU_PPC_E500, /**< e500 */
749 CPU_PPC_E500_2, /**< e500v2 */
750+ CPU_PPC_E500MC, /**< e500mc */
751 CPU_CORE, /**< Core Solo / Duo series */
752 CPU_PPC_7450, /**< PowerPC G4 */
753 CPU_CORE_2, /**< Intel Core 2 */
754diff -uNr a/libop/op_events.c b/libop/op_events.c
755--- a/libop/op_events.c 2012-08-27 20:59:14.000000000 +0200
756+++ b/libop/op_events.c 2013-02-07 07:03:57.994063551 +0100
757@@ -1182,6 +1182,7 @@
758
759 case CPU_PPC_E500:
760 case CPU_PPC_E500_2:
761+ case CPU_PPC_E500MC:
762 case CPU_PPC_E300:
763 descr->name = "CPU_CLK";
764 break;
765diff -uNr a/libop/op_events.c.orig b/libop/op_events.c.orig
766--- a/libop/op_events.c.orig 1970-01-01 01:00:00.000000000 +0100
767+++ b/libop/op_events.c.orig 2013-02-07 07:01:39.408100801 +0100
768@@ -0,0 +1,1327 @@
769+/**
770+ * @file op_events.c
771+ * Details of PMC profiling events
772+ *
773+ * You can have silliness here.
774+ *
775+ * @remark Copyright 2002 OProfile authors
776+ * @remark Read the file COPYING
777+ *
778+ * @author John Levon
779+ * @author Philippe Elie
780+ */
781+
782+#include "op_events.h"
783+#include "op_libiberty.h"
784+#include "op_fileio.h"
785+#include "op_string.h"
786+#include "op_cpufreq.h"
787+#include "op_hw_specific.h"
788+#include "op_parse_event.h"
789+
790+#include <string.h>
791+#include <stdlib.h>
792+#include <stdio.h>
793+#include <ctype.h>
794+
795+static LIST_HEAD(events_list);
796+static LIST_HEAD(um_list);
797+
798+static char const * filename;
799+static unsigned int line_nr;
800+
801+static void delete_event(struct op_event * event);
802+static void read_events(char const * file);
803+static void read_unit_masks(char const * file);
804+static void free_unit_mask(struct op_unit_mask * um);
805+
806+static char *build_fn(const char *cpu_name, const char *fn)
807+{
808+ char *s;
809+ static const char *dir;
810+ if (dir == NULL)
811+ dir = getenv("OPROFILE_EVENTS_DIR");
812+ if (dir == NULL)
813+ dir = OP_DATADIR;
814+ s = xmalloc(strlen(dir) + strlen(cpu_name) + strlen(fn) + 5);
815+ sprintf(s, "%s/%s/%s", dir, cpu_name, fn);
816+ return s;
817+}
818+
819+static void parse_error(char const * context)
820+{
821+ fprintf(stderr, "oprofile: parse error in %s, line %u\n",
822+ filename, line_nr);
823+ fprintf(stderr, "%s\n", context);
824+ exit(EXIT_FAILURE);
825+}
826+
827+
828+static int parse_int(char const * str)
829+{
830+ int value;
831+ if (sscanf(str, "%d", &value) != 1)
832+ parse_error("expected decimal value");
833+
834+ return value;
835+}
836+
837+
838+static int parse_hex(char const * str)
839+{
840+ int value;
841+ /* 0x/0X to force the use of hexa notation for field intended to
842+ be in hexadecimal */
843+ if (sscanf(str, "0x%x", &value) != 1 &&
844+ sscanf(str, "0X%x", &value) != 1)
845+ parse_error("expected hexadecimal value");
846+
847+ return value;
848+}
849+
850+
851+static u64 parse_long_hex(char const * str)
852+{
853+ u64 value;
854+ if (sscanf(str, "%Lx", &value) != 1)
855+ parse_error("expected long hexadecimal value");
856+
857+ fflush(stderr);
858+ return value;
859+}
860+
861+static void include_um(const char *start, const char *end)
862+{
863+ char *s;
864+ char cpu[end - start + 1];
865+ int old_line_nr;
866+ const char *old_filename;
867+
868+ strncpy(cpu, start, end - start);
869+ cpu[end - start] = 0;
870+ s = build_fn(cpu, "unit_masks");
871+ old_line_nr = line_nr;
872+ old_filename = filename;
873+ read_unit_masks(s);
874+ line_nr = old_line_nr;
875+ filename = old_filename;
876+ free(s);
877+}
878+
879+/* extra:cmask=12,inv,edge */
880+unsigned parse_extra(const char *s)
881+{
882+ unsigned v, w;
883+ int o;
884+
885+ v = 0;
886+ while (*s) {
887+ if (isspace(*s))
888+ break;
889+ if (strisprefix(s, "edge")) {
890+ v |= EXTRA_EDGE;
891+ s += 4;
892+ } else if (strisprefix(s, "inv")) {
893+ v |= EXTRA_INV;
894+ s += 3;
895+ } else if (sscanf(s, "cmask=%x%n", &w, &o) >= 1) {
896+ v |= (w & EXTRA_CMASK_MASK) << EXTRA_CMASK_SHIFT;
897+ s += o;
898+ } else if (strisprefix(s, "any")) {
899+ v |= EXTRA_ANY;
900+ s += 3;
901+ } else {
902+ parse_error("Illegal extra field modifier");
903+ }
904+ if (*s == ',')
905+ ++s;
906+ }
907+ return v;
908+}
909+
910+/* name:MESI type:bitmask default:0x0f */
911+static void parse_um(struct op_unit_mask * um, char const * line)
912+{
913+ int seen_name = 0;
914+ int seen_type = 0;
915+ int seen_default = 0;
916+ char const * valueend = line + 1;
917+ char const * tagend = line + 1;
918+ char const * start = line;
919+
920+ while (*valueend) {
921+ valueend = skip_nonws(valueend);
922+
923+ while (*tagend != ':' && *tagend)
924+ ++tagend;
925+
926+ if (valueend == tagend)
927+ break;
928+
929+ if (!*tagend)
930+ parse_error("parse_um() expected :value");
931+
932+ ++tagend;
933+
934+ if (strisprefix(start, "include")) {
935+ if (seen_name + seen_type + seen_default > 0)
936+ parse_error("include must be on its own");
937+ free_unit_mask(um);
938+ include_um(tagend, valueend);
939+ return;
940+ }
941+
942+ if (strisprefix(start, "name")) {
943+ if (seen_name)
944+ parse_error("duplicate name: tag");
945+ seen_name = 1;
946+ um->name = op_xstrndup(tagend, valueend - tagend);
947+ } else if (strisprefix(start, "type")) {
948+ if (seen_type)
949+ parse_error("duplicate type: tag");
950+ seen_type = 1;
951+ if (strisprefix(tagend, "mandatory")) {
952+ um->unit_type_mask = utm_mandatory;
953+ } else if (strisprefix(tagend, "bitmask")) {
954+ um->unit_type_mask = utm_bitmask;
955+ } else if (strisprefix(tagend, "exclusive")) {
956+ um->unit_type_mask = utm_exclusive;
957+ } else {
958+ parse_error("invalid unit mask type");
959+ }
960+ } else if (strisprefix(start, "default")) {
961+ if (seen_default)
962+ parse_error("duplicate default: tag");
963+ seen_default = 1;
964+ um->default_mask = parse_hex(tagend);
965+ } else {
966+ parse_error("invalid unit mask tag");
967+ }
968+
969+ valueend = skip_ws(valueend);
970+ tagend = valueend;
971+ start = valueend;
972+ }
973+
974+ if (!um->name)
975+ parse_error("Missing name for unit mask");
976+ if (!seen_type)
977+ parse_error("Missing type for unit mask");
978+}
979+
980+
981+/* \t0x08 (M)odified cache state */
982+/* \t0x08 extra:inv,cmask=... (M)odified cache state */
983+static void parse_um_entry(struct op_described_um * entry, char const * line)
984+{
985+ char const * c = line;
986+
987+ c = skip_ws(c);
988+ entry->value = parse_hex(c);
989+ c = skip_nonws(c);
990+
991+ c = skip_ws(c);
992+ if (strisprefix(c, "extra:")) {
993+ c += 6;
994+ entry->extra = parse_extra(c);
995+ c = skip_nonws(c);
996+ } else
997+ entry->extra = 0;
998+
999+ if (!*c)
1000+ parse_error("invalid unit mask entry");
1001+
1002+ c = skip_ws(c);
1003+
1004+ if (!*c)
1005+ parse_error("invalid unit mask entry");
1006+
1007+ entry->desc = xstrdup(c);
1008+}
1009+
1010+
1011+static struct op_unit_mask * new_unit_mask(void)
1012+{
1013+ struct op_unit_mask * um = xmalloc(sizeof(struct op_unit_mask));
1014+ memset(um, '\0', sizeof(struct op_unit_mask));
1015+ list_add_tail(&um->um_next, &um_list);
1016+
1017+ return um;
1018+}
1019+
1020+static void free_unit_mask(struct op_unit_mask * um)
1021+{
1022+ list_del(&um->um_next);
1023+ free(um);
1024+}
1025+
1026+/*
1027+ * name:zero type:mandatory default:0x0
1028+ * \t0x0 No unit mask
1029+ */
1030+static void read_unit_masks(char const * file)
1031+{
1032+ struct op_unit_mask * um = NULL;
1033+ char * line;
1034+ FILE * fp = fopen(file, "r");
1035+
1036+ if (!fp) {
1037+ fprintf(stderr,
1038+ "oprofile: could not open unit mask description file %s\n", file);
1039+ exit(EXIT_FAILURE);
1040+ }
1041+
1042+ filename = file;
1043+ line_nr = 1;
1044+
1045+ line = op_get_line(fp);
1046+
1047+ while (line) {
1048+ if (empty_line(line) || comment_line(line))
1049+ goto next;
1050+
1051+ if (line[0] != '\t') {
1052+ um = new_unit_mask();
1053+ parse_um(um, line);
1054+ } else {
1055+ if (!um)
1056+ parse_error("no unit mask name line");
1057+ if (um->num >= MAX_UNIT_MASK)
1058+ parse_error("oprofile: maximum unit mask entries exceeded");
1059+
1060+ parse_um_entry(&um->um[um->num], line);
1061+ ++(um->num);
1062+ }
1063+
1064+next:
1065+ free(line);
1066+ line = op_get_line(fp);
1067+ ++line_nr;
1068+ }
1069+
1070+ fclose(fp);
1071+}
1072+
1073+
1074+static u32 parse_counter_mask(char const * str)
1075+{
1076+ u32 mask = 0;
1077+ char const * numstart = str;
1078+
1079+ while (*numstart) {
1080+ mask |= 1 << parse_int(numstart);
1081+
1082+ while (*numstart && *numstart != ',')
1083+ ++numstart;
1084+ /* skip , unless we reach eos */
1085+ if (*numstart)
1086+ ++numstart;
1087+
1088+ numstart = skip_ws(numstart);
1089+ }
1090+
1091+ return mask;
1092+}
1093+
1094+static struct op_unit_mask * try_find_um(char const * value)
1095+{
1096+ struct list_head * pos;
1097+
1098+ list_for_each(pos, &um_list) {
1099+ struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next);
1100+ if (strcmp(value, um->name) == 0) {
1101+ um->used = 1;
1102+ return um;
1103+ }
1104+ }
1105+ return NULL;
1106+}
1107+
1108+static struct op_unit_mask * find_um(char const * value)
1109+{
1110+ struct op_unit_mask * um = try_find_um(value);
1111+ if (um)
1112+ return um;
1113+ fprintf(stderr, "oprofile: could not find unit mask %s\n", value);
1114+ exit(EXIT_FAILURE);
1115+}
1116+
1117+/* um:a,b,c,d merge multiple unit masks */
1118+static struct op_unit_mask * merge_um(char * value)
1119+{
1120+ int num;
1121+ char *s;
1122+ struct op_unit_mask *new, *um;
1123+ enum unit_mask_type type = -1U;
1124+
1125+ um = try_find_um(value);
1126+ if (um)
1127+ return um;
1128+
1129+ new = new_unit_mask();
1130+ new->name = xstrdup(value);
1131+ new->used = 1;
1132+ num = 0;
1133+ while ((s = strsep(&value, ",")) != NULL) {
1134+ unsigned c;
1135+ um = find_um(s);
1136+ if (type == -1U)
1137+ type = um->unit_type_mask;
1138+ if (um->unit_type_mask != type)
1139+ parse_error("combined unit mask must be all the same types");
1140+ if (type != utm_bitmask && type != utm_exclusive)
1141+ parse_error("combined unit mask must be all bitmasks or exclusive");
1142+ new->default_mask |= um->default_mask;
1143+ new->num += um->num;
1144+ if (new->num > MAX_UNIT_MASK)
1145+ parse_error("too many members in combined unit mask");
1146+ for (c = 0; c < um->num; c++, num++) {
1147+ new->um[num] = um->um[c];
1148+ new->um[num].desc = xstrdup(new->um[num].desc);
1149+ }
1150+ }
1151+ if (type == -1U)
1152+ parse_error("Empty unit mask");
1153+ new->unit_type_mask = type;
1154+ return new;
1155+}
1156+
1157+/* parse either a "tag:value" or a ": trailing description string" */
1158+static int next_token(char const ** cp, char ** name, char ** value)
1159+{
1160+ size_t tag_len;
1161+ size_t val_len;
1162+ char const * c = *cp;
1163+ char const * end;
1164+ char const * colon;
1165+
1166+ c = skip_ws(c);
1167+ end = colon = c;
1168+ end = skip_nonws(end);
1169+
1170+ colon = strchr(colon, ':');
1171+
1172+ if (!colon) {
1173+ if (*c)
1174+ parse_error("next_token(): garbage at end of line");
1175+ return 0;
1176+ }
1177+
1178+ if (colon >= end)
1179+ parse_error("next_token() expected ':'");
1180+
1181+ tag_len = colon - c;
1182+ val_len = end - (colon + 1);
1183+
1184+ if (!tag_len) {
1185+ /* : trailing description */
1186+ end = skip_ws(end);
1187+ *name = xstrdup("desc");
1188+ *value = xstrdup(end);
1189+ end += strlen(end);
1190+ } else {
1191+ /* tag:value */
1192+ *name = op_xstrndup(c, tag_len);
1193+ *value = op_xstrndup(colon + 1, val_len);
1194+ end = skip_ws(end);
1195+ }
1196+
1197+ *cp = end;
1198+ return 1;
1199+}
1200+
1201+static void include_events (char *value)
1202+{
1203+ char * event_file;
1204+ const char *old_filename;
1205+ int old_line_nr;
1206+
1207+ event_file = build_fn(value, "events");
1208+ old_line_nr = line_nr;
1209+ old_filename = filename;
1210+ read_events(event_file);
1211+ line_nr = old_line_nr;
1212+ filename = old_filename;
1213+ free(event_file);
1214+}
1215+
1216+static struct op_event * new_event(void)
1217+{
1218+ struct op_event * event = xmalloc(sizeof(struct op_event));
1219+ memset(event, '\0', sizeof(struct op_event));
1220+ list_add_tail(&event->event_next, &events_list);
1221+
1222+ return event;
1223+}
1224+
1225+static void free_event(struct op_event * event)
1226+{
1227+ list_del(&event->event_next);
1228+ free(event);
1229+}
1230+
1231+/* event:0x00 counters:0 um:zero minimum:4096 name:ISSUES : Total issues */
1232+/* event:0x00 ext:xxxxxx um:zero minimum:4096 name:ISSUES : Total issues */
1233+static void read_events(char const * file)
1234+{
1235+ struct op_event * event = NULL;
1236+ char * line;
1237+ char * name;
1238+ char * value;
1239+ char const * c;
1240+ int seen_event, seen_counters, seen_um, seen_minimum, seen_name, seen_ext;
1241+ FILE * fp = fopen(file, "r");
1242+ int tags;
1243+
1244+ if (!fp) {
1245+ fprintf(stderr, "oprofile: could not open event description file %s\n", file);
1246+ exit(EXIT_FAILURE);
1247+ }
1248+
1249+ filename = file;
1250+ line_nr = 1;
1251+
1252+ line = op_get_line(fp);
1253+
1254+ while (line) {
1255+ if (empty_line(line) || comment_line(line))
1256+ goto next;
1257+
1258+ tags = 0;
1259+ seen_name = 0;
1260+ seen_event = 0;
1261+ seen_counters = 0;
1262+ seen_ext = 0;
1263+ seen_um = 0;
1264+ seen_minimum = 0;
1265+ event = new_event();
1266+ event->filter = -1;
1267+ event->ext = NULL;
1268+
1269+ c = line;
1270+ while (next_token(&c, &name, &value)) {
1271+ if (strcmp(name, "name") == 0) {
1272+ if (seen_name)
1273+ parse_error("duplicate name: tag");
1274+ seen_name = 1;
1275+ if (strchr(value, '/') != NULL)
1276+ parse_error("invalid event name");
1277+ if (strchr(value, '.') != NULL)
1278+ parse_error("invalid event name");
1279+ event->name = value;
1280+ } else if (strcmp(name, "event") == 0) {
1281+ if (seen_event)
1282+ parse_error("duplicate event: tag");
1283+ seen_event = 1;
1284+ event->val = parse_hex(value);
1285+ free(value);
1286+ } else if (strcmp(name, "counters") == 0) {
1287+ if (seen_counters)
1288+ parse_error("duplicate counters: tag");
1289+ seen_counters = 1;
1290+ if (!strcmp(value, "cpuid"))
1291+ event->counter_mask = arch_get_counter_mask();
1292+ else
1293+ event->counter_mask = parse_counter_mask(value);
1294+ free(value);
1295+ } else if (strcmp(name, "ext") == 0) {
1296+ if (seen_ext)
1297+ parse_error("duplicate ext: tag");
1298+ seen_ext = 1;
1299+ event->ext = value;
1300+ } else if (strcmp(name, "um") == 0) {
1301+ if (seen_um)
1302+ parse_error("duplicate um: tag");
1303+ seen_um = 1;
1304+ if (strchr(value, ','))
1305+ event->unit = merge_um(value);
1306+ else
1307+ event->unit = find_um(value);
1308+ free(value);
1309+ } else if (strcmp(name, "minimum") == 0) {
1310+ if (seen_minimum)
1311+ parse_error("duplicate minimum: tag");
1312+ seen_minimum = 1;
1313+ event->min_count = parse_int(value);
1314+ free(value);
1315+ } else if (strcmp(name, "desc") == 0) {
1316+ event->desc = value;
1317+ } else if (strcmp(name, "filter") == 0) {
1318+ event->filter = parse_int(value);
1319+ free(value);
1320+ } else if (strcmp(name, "include") == 0) {
1321+ if (tags > 0)
1322+ parse_error("tags before include:");
1323+ free_event(event);
1324+ include_events(value);
1325+ free(value);
1326+ c = skip_ws(c);
1327+ if (*c != '\0' && *c != '#')
1328+ parse_error("non whitespace after include:");
1329+ } else {
1330+ parse_error("unknown tag");
1331+ }
1332+ tags++;
1333+
1334+ free(name);
1335+ }
1336+next:
1337+ free(line);
1338+ line = op_get_line(fp);
1339+ ++line_nr;
1340+ }
1341+
1342+ fclose(fp);
1343+}
1344+
1345+
1346+/* usefull for make check */
1347+static int check_unit_mask(struct op_unit_mask const * um,
1348+ char const * cpu_name)
1349+{
1350+ u32 i;
1351+ int err = 0;
1352+
1353+ if (!um->used) {
1354+ fprintf(stderr, "um %s is not used\n", um->name);
1355+ err = EXIT_FAILURE;
1356+ }
1357+
1358+ if (um->unit_type_mask == utm_mandatory && um->num != 1) {
1359+ fprintf(stderr, "mandatory um %s doesn't contain exactly one "
1360+ "entry (%s)\n", um->name, cpu_name);
1361+ err = EXIT_FAILURE;
1362+ } else if (um->unit_type_mask == utm_bitmask) {
1363+ u32 default_mask = um->default_mask;
1364+ for (i = 0; i < um->num; ++i)
1365+ default_mask &= ~um->um[i].value;
1366+
1367+ if (default_mask) {
1368+ fprintf(stderr, "um %s default mask is not valid "
1369+ "(%s)\n", um->name, cpu_name);
1370+ err = EXIT_FAILURE;
1371+ }
1372+ } else {
1373+ for (i = 0; i < um->num; ++i) {
1374+ if (um->default_mask == um->um[i].value)
1375+ break;
1376+ }
1377+
1378+ if (i == um->num) {
1379+ fprintf(stderr, "exclusive um %s default value is not "
1380+ "valid (%s)\n", um->name, cpu_name);
1381+ err = EXIT_FAILURE;
1382+ }
1383+ }
1384+ return err;
1385+}
1386+
1387+static void arch_filter_events(op_cpu cpu_type)
1388+{
1389+ struct list_head * pos, * pos2;
1390+ unsigned filter = arch_get_filter(cpu_type);
1391+ if (!filter)
1392+ return;
1393+ list_for_each_safe (pos, pos2, &events_list) {
1394+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1395+ if (event->filter >= 0 && ((1U << event->filter) & filter))
1396+ delete_event(event);
1397+ }
1398+}
1399+
1400+static void load_events_name(const char *cpu_name)
1401+{
1402+ char * event_file;
1403+ char * um_file;
1404+
1405+ event_file = build_fn(cpu_name, "events");
1406+ um_file = build_fn(cpu_name, "unit_masks");
1407+
1408+ read_unit_masks(um_file);
1409+ read_events(event_file);
1410+
1411+ free(um_file);
1412+ free(event_file);
1413+}
1414+
1415+static void load_events(op_cpu cpu_type)
1416+{
1417+ const char * cpu_name = op_get_cpu_name(cpu_type);
1418+ struct list_head * pos;
1419+ struct op_event *event;
1420+ struct op_unit_mask *unit_mask;
1421+ int err = 0;
1422+
1423+ if (!list_empty(&events_list))
1424+ return;
1425+
1426+ load_events_name(cpu_name);
1427+
1428+ arch_filter_events(cpu_type);
1429+
1430+ /* sanity check: all unit mask must be used */
1431+ list_for_each(pos, &um_list) {
1432+ struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next);
1433+ err |= check_unit_mask(um, cpu_name);
1434+ }
1435+ if (err)
1436+ exit(err);
1437+
1438+ if (!op_cpu_has_timer_fs())
1439+ return;
1440+
1441+ /* sanity check: Don't use event `TIMER' since it is predefined. */
1442+ list_for_each(pos, &events_list) {
1443+ struct op_event * event = list_entry(pos, struct op_event,
1444+ event_next);
1445+
1446+ if (strcmp(event->name, TIMER_EVENT_NAME) == 0) {
1447+ fprintf(stderr, "Error: " TIMER_EVENT_NAME
1448+ " event cannot be redefined.\n");
1449+ exit(EXIT_FAILURE);
1450+ }
1451+ if (event->val == TIMER_EVENT_VALUE) {
1452+ fprintf(stderr, "Error: Event %s uses " TIMER_EVENT_NAME
1453+ " which is reserverd for timer based sampling.\n",
1454+ event->name);
1455+ exit(EXIT_FAILURE);
1456+ }
1457+ }
1458+
1459+ list_for_each(pos, &um_list) {
1460+ struct op_unit_mask * um = list_entry(pos, struct op_unit_mask,
1461+ um_next);
1462+ if (strcmp(um->name, TIMER_EVENT_UNIT_MASK_NAME) == 0) {
1463+ fprintf(stderr, "Error: " TIMER_EVENT_UNIT_MASK_NAME
1464+ " unit mask cannot be redefined.\n");
1465+ exit(EXIT_FAILURE);
1466+ }
1467+ }
1468+
1469+ unit_mask = new_unit_mask();
1470+ unit_mask->name = xstrdup(TIMER_EVENT_UNIT_MASK_NAME);
1471+ unit_mask->num = 1;
1472+ unit_mask->unit_type_mask = utm_mandatory;
1473+ unit_mask->um[0].extra = 0;
1474+ unit_mask->um[0].value = 0;
1475+ unit_mask->um[0].desc = xstrdup("No unit mask");
1476+ unit_mask->used = 1;
1477+
1478+ event = new_event();
1479+ event->name = xstrdup(TIMER_EVENT_NAME);
1480+ event->desc = xstrdup(TIMER_EVENT_DESC);
1481+ event->val = TIMER_EVENT_VALUE;
1482+ event->unit = unit_mask;
1483+ event->min_count = 0;
1484+ event->filter = 0;
1485+ event->counter_mask = 1 << (op_get_nr_counters(cpu_type) - 1);
1486+ event->ext = NULL;
1487+ event->filter = -1;
1488+}
1489+
1490+struct list_head * op_events(op_cpu cpu_type)
1491+{
1492+ load_events(cpu_type);
1493+ arch_filter_events(cpu_type);
1494+ return &events_list;
1495+}
1496+
1497+
1498+static void delete_unit_mask(struct op_unit_mask * unit)
1499+{
1500+ u32 cur;
1501+ for (cur = 0 ; cur < unit->num ; ++cur) {
1502+ if (unit->um[cur].desc)
1503+ free(unit->um[cur].desc);
1504+ }
1505+
1506+ if (unit->name)
1507+ free(unit->name);
1508+
1509+ list_del(&unit->um_next);
1510+ free(unit);
1511+}
1512+
1513+
1514+static void delete_event(struct op_event * event)
1515+{
1516+ if (event->name)
1517+ free(event->name);
1518+ if (event->desc)
1519+ free(event->desc);
1520+
1521+ list_del(&event->event_next);
1522+ free(event);
1523+}
1524+
1525+
1526+void op_free_events(void)
1527+{
1528+ struct list_head * pos, * pos2;
1529+ list_for_each_safe(pos, pos2, &events_list) {
1530+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1531+ delete_event(event);
1532+ }
1533+
1534+ list_for_each_safe(pos, pos2, &um_list) {
1535+ struct op_unit_mask * unit = list_entry(pos, struct op_unit_mask, um_next);
1536+ delete_unit_mask(unit);
1537+ }
1538+}
1539+
1540+/* There can be actually multiple events here, so this is not quite correct */
1541+static struct op_event * find_event_any(u32 nr)
1542+{
1543+ struct list_head * pos;
1544+
1545+ list_for_each(pos, &events_list) {
1546+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1547+ if (event->val == nr)
1548+ return event;
1549+ }
1550+
1551+ return NULL;
1552+}
1553+
1554+static struct op_event * find_event_um(u32 nr, u32 um)
1555+{
1556+ struct list_head * pos;
1557+ unsigned int i;
1558+
1559+ list_for_each(pos, &events_list) {
1560+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1561+ if (event->val == nr) {
1562+ for (i = 0; i < event->unit->num; i++) {
1563+ if (event->unit->um[i].value == um)
1564+ return event;
1565+ }
1566+ }
1567+ }
1568+
1569+ return NULL;
1570+}
1571+
1572+static FILE * open_event_mapping_file(char const * cpu_name)
1573+{
1574+ char * ev_map_file;
1575+ char * dir;
1576+ dir = getenv("OPROFILE_EVENTS_DIR");
1577+ if (dir == NULL)
1578+ dir = OP_DATADIR;
1579+
1580+ ev_map_file = xmalloc(strlen(dir) + strlen("/") + strlen(cpu_name) +
1581+ strlen("/") + + strlen("event_mappings") + 1);
1582+ strcpy(ev_map_file, dir);
1583+ strcat(ev_map_file, "/");
1584+
1585+ strcat(ev_map_file, cpu_name);
1586+ strcat(ev_map_file, "/");
1587+ strcat(ev_map_file, "event_mappings");
1588+ filename = ev_map_file;
1589+ return (fopen(ev_map_file, "r"));
1590+}
1591+
1592+
1593+/**
1594+ * This function is PPC64-specific.
1595+ */
1596+static char const * get_mapping(u32 nr, FILE * fp)
1597+{
1598+ char * line;
1599+ char * name;
1600+ char * value;
1601+ char const * c;
1602+ char * map = NULL;
1603+ int seen_event = 0, seen_mmcr0 = 0, seen_mmcr1 = 0, seen_mmcra = 0;
1604+ u32 mmcr0 = 0;
1605+ u64 mmcr1 = 0;
1606+ u32 mmcra = 0;
1607+ int event_found = 0;
1608+
1609+ line_nr = 1;
1610+ line = op_get_line(fp);
1611+ while (line && !event_found) {
1612+ if (empty_line(line) || comment_line(line))
1613+ goto next;
1614+
1615+ seen_event = 0;
1616+ seen_mmcr0 = 0;
1617+ seen_mmcr1 = 0;
1618+ seen_mmcra = 0;
1619+ mmcr0 = 0;
1620+ mmcr1 = 0;
1621+ mmcra = 0;
1622+
1623+ c = line;
1624+ while (next_token(&c, &name, &value)) {
1625+ if (strcmp(name, "event") == 0) {
1626+ u32 evt;
1627+ if (seen_event)
1628+ parse_error("duplicate event tag");
1629+ seen_event = 1;
1630+ evt = parse_hex(value);
1631+ if (evt == nr)
1632+ event_found = 1;
1633+ free(value);
1634+ } else if (strcmp(name, "mmcr0") == 0) {
1635+ if (seen_mmcr0)
1636+ parse_error("duplicate mmcr0 tag");
1637+ seen_mmcr0 = 1;
1638+ mmcr0 = parse_hex(value);
1639+ free(value);
1640+ } else if (strcmp(name, "mmcr1") == 0) {
1641+ if (seen_mmcr1)
1642+ parse_error("duplicate mmcr1: tag");
1643+ seen_mmcr1 = 1;
1644+ mmcr1 = parse_long_hex(value);
1645+ free(value);
1646+ } else if (strcmp(name, "mmcra") == 0) {
1647+ if (seen_mmcra)
1648+ parse_error("duplicate mmcra: tag");
1649+ seen_mmcra = 1;
1650+ mmcra = parse_hex(value);
1651+ free(value);
1652+ } else {
1653+ parse_error("unknown tag");
1654+ }
1655+
1656+ free(name);
1657+ }
1658+next:
1659+ free(line);
1660+ line = op_get_line(fp);
1661+ ++line_nr;
1662+ }
1663+ if (event_found) {
1664+ if (!seen_mmcr0 || !seen_mmcr1 || !seen_mmcra) {
1665+ fprintf(stderr, "Error: Missing information in line %d of event mapping file %s\n", line_nr, filename);
1666+ exit(EXIT_FAILURE);
1667+ }
1668+ map = xmalloc(70);
1669+ snprintf(map, 70, "mmcr0:%u mmcr1:%Lu mmcra:%u",
1670+ mmcr0, mmcr1, mmcra);
1671+ }
1672+
1673+ return map;
1674+}
1675+
1676+
1677+char const * find_mapping_for_event(u32 nr, op_cpu cpu_type)
1678+{
1679+ char const * cpu_name = op_get_cpu_name(cpu_type);
1680+ FILE * fp = open_event_mapping_file(cpu_name);
1681+ char const * map = NULL;
1682+ switch (cpu_type) {
1683+ case CPU_PPC64_PA6T:
1684+ case CPU_PPC64_970:
1685+ case CPU_PPC64_970MP:
1686+ case CPU_PPC64_POWER4:
1687+ case CPU_PPC64_POWER5:
1688+ case CPU_PPC64_POWER5p:
1689+ case CPU_PPC64_POWER5pp:
1690+ case CPU_PPC64_POWER6:
1691+ case CPU_PPC64_POWER7:
1692+ case CPU_PPC64_IBM_COMPAT_V1:
1693+ if (!fp) {
1694+ fprintf(stderr, "oprofile: could not open event mapping file %s\n", filename);
1695+ exit(EXIT_FAILURE);
1696+ } else {
1697+ map = get_mapping(nr, fp);
1698+ }
1699+ break;
1700+ default:
1701+ break;
1702+ }
1703+
1704+ if (fp)
1705+ fclose(fp);
1706+
1707+ return map;
1708+}
1709+
1710+static int match_event(int i, struct op_event *event, unsigned um)
1711+{
1712+ unsigned v = event->unit->um[i].value;
1713+
1714+ switch (event->unit->unit_type_mask) {
1715+ case utm_exclusive:
1716+ case utm_mandatory:
1717+ return v == um;
1718+
1719+ case utm_bitmask:
1720+ return (v & um) || (!v && v == 0);
1721+ }
1722+
1723+ abort();
1724+}
1725+
1726+struct op_event * find_event_by_name(char const * name, unsigned um, int um_valid)
1727+{
1728+ struct list_head * pos;
1729+
1730+ list_for_each(pos, &events_list) {
1731+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1732+ if (strcmp(event->name, name) == 0) {
1733+ if (um_valid) {
1734+ unsigned i;
1735+
1736+ for (i = 0; i < event->unit->num; i++)
1737+ if (match_event(i, event, um))
1738+ return event;
1739+ continue;
1740+ }
1741+ return event;
1742+ }
1743+ }
1744+
1745+ return NULL;
1746+}
1747+
1748+
1749+static struct op_event * find_next_event(struct op_event * e)
1750+{
1751+ struct list_head * n;
1752+
1753+ for (n = e->event_next.next; n != &events_list; n = n->next) {
1754+ struct op_event * ne = list_entry(n, struct op_event, event_next);
1755+ if (!strcmp(e->name, ne->name))
1756+ return ne;
1757+ }
1758+ return NULL;
1759+}
1760+
1761+struct op_event * op_find_event(op_cpu cpu_type, u32 nr, u32 um)
1762+{
1763+ struct op_event * event;
1764+
1765+ load_events(cpu_type);
1766+
1767+ event = find_event_um(nr, um);
1768+
1769+ return event;
1770+}
1771+
1772+struct op_event * op_find_event_any(op_cpu cpu_type, u32 nr)
1773+{
1774+ load_events(cpu_type);
1775+
1776+ return find_event_any(nr);
1777+}
1778+
1779+int op_check_events(int ctr, u32 nr, u32 um, op_cpu cpu_type)
1780+{
1781+ int ret = OP_INVALID_EVENT;
1782+ size_t i;
1783+ u32 ctr_mask = 1 << ctr;
1784+ struct list_head * pos;
1785+
1786+ load_events(cpu_type);
1787+
1788+ list_for_each(pos, &events_list) {
1789+ struct op_event * event = list_entry(pos, struct op_event, event_next);
1790+ if (event->val != nr)
1791+ continue;
1792+
1793+ ret = OP_OK_EVENT;
1794+
1795+ if ((event->counter_mask & ctr_mask) == 0)
1796+ ret |= OP_INVALID_COUNTER;
1797+
1798+ if (event->unit->unit_type_mask == utm_bitmask) {
1799+ for (i = 0; i < event->unit->num; ++i)
1800+ um &= ~(event->unit->um[i].value);
1801+
1802+ if (um)
1803+ ret |= OP_INVALID_UM;
1804+
1805+ } else {
1806+ for (i = 0; i < event->unit->num; ++i) {
1807+ if (event->unit->um[i].value == um)
1808+ break;
1809+ }
1810+
1811+ if (i == event->unit->num)
1812+ ret |= OP_INVALID_UM;
1813+
1814+ }
1815+
1816+ if (ret == OP_OK_EVENT)
1817+ return ret;
1818+ }
1819+
1820+ return ret;
1821+}
1822+
1823+
1824+void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
1825+{
1826+ descr->name = "";
1827+ descr->um = 0x0;
1828+ /* A fixed value of CPU cycles; this should ensure good
1829+ * granulity even on faster CPUs, though it will generate more
1830+ * interrupts.
1831+ */
1832+ descr->count = 100000;
1833+
1834+ switch (cpu_type) {
1835+ case CPU_PPRO:
1836+ case CPU_PII:
1837+ case CPU_PIII:
1838+ case CPU_P6_MOBILE:
1839+ case CPU_CORE:
1840+ case CPU_CORE_2:
1841+ case CPU_ATHLON:
1842+ case CPU_HAMMER:
1843+ case CPU_FAMILY10:
1844+ case CPU_ARCH_PERFMON:
1845+ case CPU_FAMILY11H:
1846+ case CPU_ATOM:
1847+ case CPU_CORE_I7:
1848+ case CPU_NEHALEM:
1849+ case CPU_WESTMERE:
1850+ case CPU_SANDYBRIDGE:
1851+ case CPU_IVYBRIDGE:
1852+ case CPU_MIPS_LOONGSON2:
1853+ case CPU_FAMILY12H:
1854+ case CPU_FAMILY14H:
1855+ case CPU_FAMILY15H:
1856+ descr->name = "CPU_CLK_UNHALTED";
1857+ break;
1858+
1859+ case CPU_RTC:
1860+ descr->name = "RTC_INTERRUPTS";
1861+ descr->count = 1024;
1862+ break;
1863+
1864+ case CPU_P4:
1865+ case CPU_P4_HT2:
1866+ descr->name = "GLOBAL_POWER_EVENTS";
1867+ descr->um = 0x1;
1868+ break;
1869+
1870+ case CPU_IA64:
1871+ case CPU_IA64_1:
1872+ case CPU_IA64_2:
1873+ descr->count = 1000000;
1874+ descr->name = "CPU_CYCLES";
1875+ break;
1876+
1877+ case CPU_AXP_EV4:
1878+ case CPU_AXP_EV5:
1879+ case CPU_AXP_PCA56:
1880+ case CPU_AXP_EV6:
1881+ case CPU_AXP_EV67:
1882+ descr->name = "CYCLES";
1883+ break;
1884+
1885+ // we could possibly use the CCNT
1886+ case CPU_ARM_XSCALE1:
1887+ case CPU_ARM_XSCALE2:
1888+ case CPU_ARM_MPCORE:
1889+ case CPU_ARM_V6:
1890+ case CPU_ARM_V7:
1891+ case CPU_ARM_V7_CA5:
1892+ case CPU_ARM_V7_CA7:
1893+ case CPU_ARM_V7_CA9:
1894+ case CPU_ARM_V7_CA15:
1895+ case CPU_AVR32:
1896+ case CPU_ARM_SCORPION:
1897+ case CPU_ARM_SCORPIONMP:
1898+ descr->name = "CPU_CYCLES";
1899+ break;
1900+
1901+ case CPU_PPC64_PA6T:
1902+ case CPU_PPC64_970:
1903+ case CPU_PPC64_970MP:
1904+ case CPU_PPC_7450:
1905+ case CPU_PPC64_POWER4:
1906+ case CPU_PPC64_POWER5:
1907+ case CPU_PPC64_POWER6:
1908+ case CPU_PPC64_POWER5p:
1909+ case CPU_PPC64_POWER5pp:
1910+ case CPU_PPC64_CELL:
1911+ case CPU_PPC64_POWER7:
1912+ case CPU_PPC64_IBM_COMPAT_V1:
1913+ descr->name = "CYCLES";
1914+ break;
1915+
1916+ case CPU_MIPS_20K:
1917+ descr->name = "CYCLES";
1918+ break;
1919+
1920+ case CPU_MIPS_24K:
1921+ case CPU_MIPS_34K:
1922+ case CPU_MIPS_74K:
1923+ case CPU_MIPS_1004K:
1924+ descr->name = "INSTRUCTIONS";
1925+ break;
1926+
1927+ case CPU_MIPS_5K:
1928+ case CPU_MIPS_25K:
1929+ descr->name = "CYCLES";
1930+ break;
1931+
1932+ case CPU_MIPS_R10000:
1933+ case CPU_MIPS_R12000:
1934+ descr->name = "INSTRUCTIONS_GRADUATED";
1935+ break;
1936+
1937+ case CPU_MIPS_RM7000:
1938+ case CPU_MIPS_RM9000:
1939+ descr->name = "INSTRUCTIONS_ISSUED";
1940+ break;
1941+
1942+ case CPU_MIPS_SB1:
1943+ descr->name = "INSN_SURVIVED_STAGE7";
1944+ break;
1945+
1946+ case CPU_MIPS_VR5432:
1947+ case CPU_MIPS_VR5500:
1948+ descr->name = "INSTRUCTIONS_EXECUTED";
1949+ break;
1950+
1951+ case CPU_PPC_E500:
1952+ case CPU_PPC_E500_2:
1953+ case CPU_PPC_E300:
1954+ descr->name = "CPU_CLK";
1955+ break;
1956+ case CPU_S390_Z10:
1957+ case CPU_S390_Z196:
1958+ if (op_get_nr_counters(cpu_type) > 1) {
1959+ descr->name = "HWSAMPLING";
1960+ descr->count = 4127518;
1961+ } else {
1962+ descr->name = TIMER_EVENT_NAME;
1963+ descr->count = 10000;
1964+ }
1965+ break;
1966+
1967+ case CPU_TILE_TILE64:
1968+ case CPU_TILE_TILEPRO:
1969+ case CPU_TILE_TILEGX:
1970+ descr->name = "ONE";
1971+ break;
1972+
1973+ // don't use default, if someone add a cpu he wants a compiler
1974+ // warning if he forgets to handle it here.
1975+ case CPU_TIMER_INT:
1976+ case CPU_NO_GOOD:
1977+ case MAX_CPU_TYPE:
1978+ break;
1979+ }
1980+}
1981+
1982+static void extra_check(struct op_event *e, u32 unit_mask)
1983+{
1984+ unsigned i;
1985+ int found = 0;
1986+
1987+ for (i = 0; i < e->unit->num; i++)
1988+ if (e->unit->um[i].value == unit_mask)
1989+ found++;
1990+ if (found > 1) {
1991+ fprintf(stderr,
1992+"Named unit masks not allowed for events without 'extra:' values.\n"
1993+"Please specify the numerical value for the unit mask. See 'opcontrol'"
1994+" man page for more info.\n");
1995+ exit(EXIT_FAILURE);
1996+ }
1997+}
1998+
1999+static void another_extra_check(struct op_event *e, char *name, unsigned w)
2000+{
2001+ int found;
2002+ unsigned i;
2003+
2004+ if (!e->unit->um[w].extra) {
2005+ fprintf(stderr,
2006+"Named unit mask (%s) not allowed for event without 'extra:' values.\n"
2007+"Please specify the numerical value for the unit mask. See 'opcontrol'"
2008+" man page for more info.\n", name);
2009+ exit(EXIT_FAILURE);
2010+ }
2011+
2012+ found = 0;
2013+ for (i = 0; i < e->unit->num; i++) {
2014+ int len = strcspn(e->unit->um[i].desc, " \t");
2015+ if (!strncmp(name, e->unit->um[i].desc, len) &&
2016+ name[len] == '\0')
2017+ found++;
2018+ }
2019+ if (found > 1) {
2020+ fprintf(stderr,
2021+ "Unit mask name `%s' not unique. Sorry please use a numerical unit mask\n", name);
2022+ exit(EXIT_FAILURE);
2023+ }
2024+}
2025+
2026+static void do_resolve_unit_mask(struct op_event *e, struct parsed_event *pe,
2027+ u32 *extra)
2028+{
2029+ unsigned i;
2030+ int found;
2031+
2032+ for (;;) {
2033+ if (pe->unit_mask_name == NULL) {
2034+ int had_unit_mask = pe->unit_mask_valid;
2035+
2036+ found = 0;
2037+ for (i = 0; i < e->unit->num; i++) {
2038+ if (!pe->unit_mask_valid &&
2039+ e->unit->um[i].value == e->unit->default_mask) {
2040+ pe->unit_mask_valid = 1;
2041+ pe->unit_mask = e->unit->default_mask;
2042+ break;
2043+ }
2044+ }
2045+ if (found > 1 && had_unit_mask) {
2046+ fprintf(stderr,
2047+ "Non unique numerical unit mask.\n"
2048+ "Please specify the unit mask using the first word of the description\n");
2049+ exit(EXIT_FAILURE);
2050+ }
2051+ extra_check(e, pe->unit_mask);
2052+ if (i == e->unit->num) {
2053+ e = find_next_event(e);
2054+ if (e != NULL)
2055+ continue;
2056+ } else {
2057+ if (extra)
2058+ *extra = e->unit->um[i].extra;
2059+ }
2060+ return;
2061+ }
2062+ for (i = 0; i < e->unit->num; i++) {
2063+ int len = strcspn(e->unit->um[i].desc, " \t");
2064+ if (!strncmp(pe->unit_mask_name, e->unit->um[i].desc,
2065+ len) && pe->unit_mask_name[len] == '\0')
2066+ break;
2067+ }
2068+ if (i == e->unit->num) {
2069+ e = find_next_event(e);
2070+ if (e != NULL)
2071+ continue;
2072+ fprintf(stderr, "Cannot find unit mask %s for %s\n",
2073+ pe->unit_mask_name, pe->name);
2074+ exit(EXIT_FAILURE);
2075+ }
2076+ another_extra_check(e, pe->unit_mask_name, i);
2077+ pe->unit_mask_valid = 1;
2078+ pe->unit_mask = e->unit->um[i].value;
2079+ if (extra)
2080+ *extra = e->unit->um[i].extra;
2081+ return;
2082+ }
2083+}
2084+
2085+void op_resolve_unit_mask(struct parsed_event *pe, u32 *extra)
2086+{
2087+ struct op_event *e;
2088+
2089+ e = find_event_by_name(pe->name, 0, 0);
2090+ if (!e) {
2091+ fprintf(stderr, "Cannot find event %s\n", pe->name);
2092+ exit(EXIT_FAILURE);
2093+ }
2094+ return do_resolve_unit_mask(e, pe, extra);
2095+}
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-05-13 17:07:29 +0000